| 1 |
/*************************************************************************** |
| 2 |
|
| 3 |
cpuintrf.h |
| 4 |
|
| 5 |
Core CPU interface functions and definitions. |
| 6 |
|
| 7 |
***************************************************************************/ |
| 8 |
|
| 9 |
#ifndef CPUINTRF_H |
| 10 |
#define CPUINTRF_H |
| 11 |
|
| 12 |
#include "osd_cpu.h" |
| 13 |
#include "memory.h" |
| 14 |
#include "timer.h" |
| 15 |
|
| 16 |
#ifdef __cplusplus |
| 17 |
extern "C" { |
| 18 |
#endif |
| 19 |
|
| 20 |
|
| 21 |
/************************************* |
| 22 |
* |
| 23 |
* Enum listing all the CPUs |
| 24 |
* |
| 25 |
*************************************/ |
| 26 |
|
| 27 |
/* the following list is automatically generated by makelist.pl - don't edit manually! */ |
| 28 |
enum |
| 29 |
{ |
| 30 |
CPU_DUMMY, |
| 31 |
#if (HAS_Z80) |
| 32 |
CPU_Z80, |
| 33 |
#endif |
| 34 |
#if (HAS_Z180) |
| 35 |
CPU_Z180, |
| 36 |
#endif |
| 37 |
#if (HAS_8080) |
| 38 |
CPU_8080, |
| 39 |
#endif |
| 40 |
#if (HAS_8085A) |
| 41 |
CPU_8085A, |
| 42 |
#endif |
| 43 |
#if (HAS_M6502) |
| 44 |
CPU_M6502, |
| 45 |
#endif |
| 46 |
#if (HAS_M65C02) |
| 47 |
CPU_M65C02, |
| 48 |
#endif |
| 49 |
#if (HAS_M65SC02) |
| 50 |
CPU_M65SC02, |
| 51 |
#endif |
| 52 |
#if (HAS_M65CE02) |
| 53 |
CPU_M65CE02, |
| 54 |
#endif |
| 55 |
#if (HAS_M6509) |
| 56 |
CPU_M6509, |
| 57 |
#endif |
| 58 |
#if (HAS_M6510) |
| 59 |
CPU_M6510, |
| 60 |
#endif |
| 61 |
#if (HAS_M6510T) |
| 62 |
CPU_M6510T, |
| 63 |
#endif |
| 64 |
#if (HAS_M7501) |
| 65 |
CPU_M7501, |
| 66 |
#endif |
| 67 |
#if (HAS_M8502) |
| 68 |
CPU_M8502, |
| 69 |
#endif |
| 70 |
#if (HAS_N2A03) |
| 71 |
CPU_N2A03, |
| 72 |
#endif |
| 73 |
#if (HAS_M4510) |
| 74 |
CPU_M4510, |
| 75 |
#endif |
| 76 |
#if (HAS_H6280) |
| 77 |
CPU_H6280, |
| 78 |
#endif |
| 79 |
#if (HAS_I86) |
| 80 |
CPU_I86, |
| 81 |
#endif |
| 82 |
#if (HAS_I88) |
| 83 |
CPU_I88, |
| 84 |
#endif |
| 85 |
#if (HAS_I186) |
| 86 |
CPU_I186, |
| 87 |
#endif |
| 88 |
#if (HAS_I188) |
| 89 |
CPU_I188, |
| 90 |
#endif |
| 91 |
#if (HAS_I286) |
| 92 |
CPU_I286, |
| 93 |
#endif |
| 94 |
#if (HAS_V20) |
| 95 |
CPU_V20, |
| 96 |
#endif |
| 97 |
#if (HAS_V30) |
| 98 |
CPU_V30, |
| 99 |
#endif |
| 100 |
#if (HAS_V33) |
| 101 |
CPU_V33, |
| 102 |
#endif |
| 103 |
#if (HAS_V60) |
| 104 |
CPU_V60, |
| 105 |
#endif |
| 106 |
#if (HAS_I8035) |
| 107 |
CPU_I8035, |
| 108 |
#endif |
| 109 |
#if (HAS_I8039) |
| 110 |
CPU_I8039, |
| 111 |
#endif |
| 112 |
#if (HAS_I8048) |
| 113 |
CPU_I8048, |
| 114 |
#endif |
| 115 |
#if (HAS_N7751) |
| 116 |
CPU_N7751, |
| 117 |
#endif |
| 118 |
#if (HAS_I8X41) |
| 119 |
CPU_I8X41, |
| 120 |
#endif |
| 121 |
#if (HAS_M6800) |
| 122 |
CPU_M6800, |
| 123 |
#endif |
| 124 |
#if (HAS_M6801) |
| 125 |
CPU_M6801, |
| 126 |
#endif |
| 127 |
#if (HAS_M6802) |
| 128 |
CPU_M6802, |
| 129 |
#endif |
| 130 |
#if (HAS_M6803) |
| 131 |
CPU_M6803, |
| 132 |
#endif |
| 133 |
#if (HAS_M6808) |
| 134 |
CPU_M6808, |
| 135 |
#endif |
| 136 |
#if (HAS_HD63701) |
| 137 |
CPU_HD63701, |
| 138 |
#endif |
| 139 |
#if (HAS_NSC8105) |
| 140 |
CPU_NSC8105, |
| 141 |
#endif |
| 142 |
#if (HAS_M6805) |
| 143 |
CPU_M6805, |
| 144 |
#endif |
| 145 |
#if (HAS_M68705) |
| 146 |
CPU_M68705, |
| 147 |
#endif |
| 148 |
#if (HAS_HD63705) |
| 149 |
CPU_HD63705, |
| 150 |
#endif |
| 151 |
#if (HAS_HD6309) |
| 152 |
CPU_HD6309, |
| 153 |
#endif |
| 154 |
#if (HAS_M6809) |
| 155 |
CPU_M6809, |
| 156 |
#endif |
| 157 |
#if (HAS_KONAMI) |
| 158 |
CPU_KONAMI, |
| 159 |
#endif |
| 160 |
#if (HAS_M68000) |
| 161 |
CPU_M68000, |
| 162 |
#endif |
| 163 |
#if (HAS_M68010) |
| 164 |
CPU_M68010, |
| 165 |
#endif |
| 166 |
#if (HAS_M68EC020) |
| 167 |
CPU_M68EC020, |
| 168 |
#endif |
| 169 |
#if (HAS_M68020) |
| 170 |
CPU_M68020, |
| 171 |
#endif |
| 172 |
#if (HAS_T11) |
| 173 |
CPU_T11, |
| 174 |
#endif |
| 175 |
#if (HAS_S2650) |
| 176 |
CPU_S2650, |
| 177 |
#endif |
| 178 |
#if (HAS_TMS34010) |
| 179 |
CPU_TMS34010, |
| 180 |
#endif |
| 181 |
#if (HAS_TMS34020) |
| 182 |
CPU_TMS34020, |
| 183 |
#endif |
| 184 |
#if (HAS_TMS9900) |
| 185 |
CPU_TMS9900, |
| 186 |
#endif |
| 187 |
#if (HAS_TMS9940) |
| 188 |
CPU_TMS9940, |
| 189 |
#endif |
| 190 |
#if (HAS_TMS9980) |
| 191 |
CPU_TMS9980, |
| 192 |
#endif |
| 193 |
#if (HAS_TMS9985) |
| 194 |
CPU_TMS9985, |
| 195 |
#endif |
| 196 |
#if (HAS_TMS9989) |
| 197 |
CPU_TMS9989, |
| 198 |
#endif |
| 199 |
#if (HAS_TMS9995) |
| 200 |
CPU_TMS9995, |
| 201 |
#endif |
| 202 |
#if (HAS_TMS99105A) |
| 203 |
CPU_TMS99105A, |
| 204 |
#endif |
| 205 |
#if (HAS_TMS99110A) |
| 206 |
CPU_TMS99110A, |
| 207 |
#endif |
| 208 |
#if (HAS_Z8000) |
| 209 |
CPU_Z8000, |
| 210 |
#endif |
| 211 |
#if (HAS_TMS320C10) |
| 212 |
CPU_TMS320C10, |
| 213 |
#endif |
| 214 |
#if (HAS_CCPU) |
| 215 |
CPU_CCPU, |
| 216 |
#endif |
| 217 |
#if (HAS_ADSP2100) |
| 218 |
CPU_ADSP2100, |
| 219 |
#endif |
| 220 |
#if (HAS_ADSP2105) |
| 221 |
CPU_ADSP2105, |
| 222 |
#endif |
| 223 |
#if (HAS_PSXCPU) |
| 224 |
CPU_PSXCPU, |
| 225 |
#endif |
| 226 |
#if (HAS_ASAP) |
| 227 |
CPU_ASAP, |
| 228 |
#endif |
| 229 |
#if (HAS_UPD7810) |
| 230 |
CPU_UPD7810, |
| 231 |
#endif |
| 232 |
#if (HAS_JAGUAR) |
| 233 |
CPU_JAGUARGPU, |
| 234 |
CPU_JAGUARDSP, |
| 235 |
#endif |
| 236 |
#if (HAS_R3000) |
| 237 |
CPU_R3000BE, |
| 238 |
CPU_R3000LE, |
| 239 |
#endif |
| 240 |
#if (HAS_TMS320C31) |
| 241 |
CPU_TMS320C31, |
| 242 |
#endif |
| 243 |
#if (HAS_ARM) |
| 244 |
CPU_ARM, |
| 245 |
#endif |
| 246 |
#if (HAS_SH2) |
| 247 |
CPU_SH2, |
| 248 |
#endif |
| 249 |
|
| 250 |
#ifdef MESS |
| 251 |
#if (HAS_APEXC) |
| 252 |
CPU_APEXC, |
| 253 |
#endif |
| 254 |
#if (HAS_CDP1802) |
| 255 |
CPU_CDP1802, |
| 256 |
#endif |
| 257 |
#if (HAS_CP1600) |
| 258 |
CPU_CP1600, |
| 259 |
#endif |
| 260 |
#if (HAS_F8) |
| 261 |
CPU_F8, |
| 262 |
#endif |
| 263 |
#if (HAS_G65816) |
| 264 |
CPU_G65816, |
| 265 |
#endif |
| 266 |
#if (HAS_LH5801) |
| 267 |
CPU_LH5801, |
| 268 |
#endif |
| 269 |
#if (HAS_PDP1) |
| 270 |
CPU_PDP1, |
| 271 |
#endif |
| 272 |
#if (HAS_SATURN) |
| 273 |
CPU_SATURN, |
| 274 |
#endif |
| 275 |
#if (HAS_SC61860) |
| 276 |
CPU_SC61860, |
| 277 |
#endif |
| 278 |
#if (HAS_SPC700) |
| 279 |
CPU_SPC700, |
| 280 |
#endif |
| 281 |
#if (HAS_Z80GB) |
| 282 |
CPU_Z80GB, |
| 283 |
#endif |
| 284 |
#if (HAS_Z80_MSX) |
| 285 |
CPU_Z80_MSX, |
| 286 |
#endif |
| 287 |
#endif |
| 288 |
CPU_COUNT |
| 289 |
}; |
| 290 |
|
| 291 |
|
| 292 |
|
| 293 |
/************************************* |
| 294 |
* |
| 295 |
* Interrupt line constants |
| 296 |
* |
| 297 |
*************************************/ |
| 298 |
|
| 299 |
enum |
| 300 |
{ |
| 301 |
/* line states */ |
| 302 |
CLEAR_LINE = 0, /* clear (a fired, held or pulsed) line */ |
| 303 |
ASSERT_LINE, /* assert an interrupt immediately */ |
| 304 |
HOLD_LINE, /* hold interrupt line until acknowledged */ |
| 305 |
PULSE_LINE, /* pulse interrupt line for one instruction */ |
| 306 |
|
| 307 |
/* internal flags (not for use by drivers!) */ |
| 308 |
INTERNAL_CLEAR_LINE = 100 + CLEAR_LINE, |
| 309 |
INTERNAL_ASSERT_LINE = 100 + ASSERT_LINE, |
| 310 |
|
| 311 |
/* interrupt parameters */ |
| 312 |
MAX_IRQ_LINES = 16, /* maximum number of IRQ lines per CPU */ |
| 313 |
IRQ_LINE_NMI = 127 /* IRQ line for NMIs */ |
| 314 |
}; |
| 315 |
|
| 316 |
|
| 317 |
|
| 318 |
/************************************* |
| 319 |
* |
| 320 |
* CPU information constants |
| 321 |
* |
| 322 |
*************************************/ |
| 323 |
|
| 324 |
/* get_reg/set_reg constants */ |
| 325 |
enum |
| 326 |
{ |
| 327 |
MAX_REGS = 128, /* maximum number of register of any CPU */ |
| 328 |
|
| 329 |
/* This value is passed to activecpu_get_reg to retrieve the previous |
| 330 |
* program counter value, ie. before a CPU emulation started |
| 331 |
* to fetch opcodes and arguments for the current instrution. */ |
| 332 |
REG_PREVIOUSPC = -1, |
| 333 |
|
| 334 |
/* This value is passed to activecpu_get_reg to retrieve the current |
| 335 |
* program counter value. */ |
| 336 |
REG_PC = -2, |
| 337 |
|
| 338 |
/* This value is passed to activecpu_get_reg to retrieve the current |
| 339 |
* stack pointer value. */ |
| 340 |
REG_SP = -3, |
| 341 |
|
| 342 |
/* This value is passed to activecpu_get_reg/activecpu_set_reg, instead of one of |
| 343 |
* the names from the enum a CPU core defines for it's registers, |
| 344 |
* to get or set the contents of the memory pointed to by a stack pointer. |
| 345 |
* You can specify the n'th element on the stack by (REG_SP_CONTENTS-n), |
| 346 |
* ie. lower negative values. The actual element size (UINT16 or UINT32) |
| 347 |
* depends on the CPU core. */ |
| 348 |
REG_SP_CONTENTS = -4 |
| 349 |
}; |
| 350 |
|
| 351 |
|
| 352 |
/* endianness constants */ |
| 353 |
enum |
| 354 |
{ |
| 355 |
CPU_IS_LE = 0, /* emulated CPU is little endian */ |
| 356 |
CPU_IS_BE /* emulated CPU is big endian */ |
| 357 |
}; |
| 358 |
|
| 359 |
|
| 360 |
/* Values passed to the cpu_info function of a core to retrieve information */ |
| 361 |
enum |
| 362 |
{ |
| 363 |
CPU_INFO_REG, |
| 364 |
CPU_INFO_FLAGS = MAX_REGS, |
| 365 |
CPU_INFO_NAME, |
| 366 |
CPU_INFO_FAMILY, |
| 367 |
CPU_INFO_VERSION, |
| 368 |
CPU_INFO_FILE, |
| 369 |
CPU_INFO_CREDITS, |
| 370 |
CPU_INFO_REG_LAYOUT, |
| 371 |
CPU_INFO_WIN_LAYOUT |
| 372 |
}; |
| 373 |
|
| 374 |
|
| 375 |
|
| 376 |
/************************************* |
| 377 |
* |
| 378 |
* Core CPU interface structure |
| 379 |
* |
| 380 |
*************************************/ |
| 381 |
|
| 382 |
struct cpu_interface |
| 383 |
{ |
| 384 |
/* index (used to make sure we mach the enum above */ |
| 385 |
unsigned cpu_num; |
| 386 |
|
| 387 |
/* table of core functions */ |
| 388 |
void (*init)(void); |
| 389 |
void (*reset)(void *param); |
| 390 |
void (*exit)(void); |
| 391 |
int (*execute)(int cycles); |
| 392 |
void (*burn)(int cycles); |
| 393 |
unsigned (*get_context)(void *reg); |
| 394 |
void (*set_context)(void *reg); |
| 395 |
const void *(*get_cycle_table)(int which); |
| 396 |
void (*set_cycle_table)(int which, void *new_table); |
| 397 |
unsigned (*get_reg)(int regnum); |
| 398 |
void (*set_reg)(int regnum, unsigned val); |
| 399 |
void (*set_irq_line)(int irqline, int linestate); |
| 400 |
void (*set_irq_callback)(int(*callback)(int irqline)); |
| 401 |
const char *(*cpu_info)(void *context,int regnum); |
| 402 |
unsigned (*cpu_dasm)(char *buffer,unsigned pc); |
| 403 |
|
| 404 |
/* IRQ and clock information */ |
| 405 |
unsigned num_irqs; |
| 406 |
int default_vector; |
| 407 |
int * icount; |
| 408 |
double overclock; |
| 409 |
|
| 410 |
/* memory information */ |
| 411 |
int databus_width; |
| 412 |
mem_read_handler memory_read; |
| 413 |
mem_write_handler memory_write; |
| 414 |
mem_read_handler internal_read; |
| 415 |
mem_write_handler internal_write; |
| 416 |
offs_t pgm_memory_base; |
| 417 |
void (*set_op_base)(offs_t pc); |
| 418 |
int address_shift; |
| 419 |
unsigned address_bits; |
| 420 |
unsigned endianess; |
| 421 |
unsigned align_unit; |
| 422 |
unsigned max_inst_len; |
| 423 |
}; |
| 424 |
|
| 425 |
|
| 426 |
|
| 427 |
/************************************* |
| 428 |
* |
| 429 |
* Core CPU interface functions |
| 430 |
* |
| 431 |
*************************************/ |
| 432 |
|
| 433 |
/* reset the internal CPU tracking */ |
| 434 |
int cpuintrf_init(void); |
| 435 |
|
| 436 |
/* set up the interface for one CPU of a given type */ |
| 437 |
int cpuintrf_init_cpu(int cpunum, int cputype); |
| 438 |
|
| 439 |
/* clean up the interface for one CPU */ |
| 440 |
void cpuintrf_exit_cpu(int cpunum); |
| 441 |
|
| 442 |
/* remember the previous context and set a new one */ |
| 443 |
void cpuintrf_push_context(int cpunum); |
| 444 |
|
| 445 |
/* restore the previous context */ |
| 446 |
void cpuintrf_pop_context(void); |
| 447 |
|
| 448 |
|
| 449 |
|
| 450 |
/************************************* |
| 451 |
* |
| 452 |
* Active CPU acccessors |
| 453 |
* |
| 454 |
*************************************/ |
| 455 |
|
| 456 |
/* apply a +/- to the current icount */ |
| 457 |
void activecpu_adjust_icount(int delta); |
| 458 |
|
| 459 |
/* return the current icount */ |
| 460 |
int activecpu_get_icount(void); |
| 461 |
|
| 462 |
/* ensure banking is reset properly */ |
| 463 |
void activecpu_reset_banking(void); |
| 464 |
|
| 465 |
/* set the IRQ line on a CPU -- drivers use cpu_set_irq_line() */ |
| 466 |
void activecpu_set_irq_line(int irqline, int state); |
| 467 |
|
| 468 |
/* return a pointer to the active cycle count table for the active CPU */ |
| 469 |
const void *activecpu_get_cycle_table(int which); |
| 470 |
|
| 471 |
/* set a pointer to the active cycle count table for the active CPU */ |
| 472 |
void activecpu_set_cycle_tbl(int which, void *new_table); |
| 473 |
|
| 474 |
/* return the value of a register on the active CPU */ |
| 475 |
unsigned activecpu_get_reg(int regnum); |
| 476 |
|
| 477 |
/* set the value of a register on the active CPU */ |
| 478 |
void activecpu_set_reg(int regnum, unsigned val); |
| 479 |
|
| 480 |
/* return the PC, corrected to a byte offset, on the active CPU */ |
| 481 |
offs_t activecpu_get_pc_byte(void); |
| 482 |
|
| 483 |
/* update the banking on the active CPU */ |
| 484 |
void activecpu_set_op_base(unsigned val); |
| 485 |
|
| 486 |
/* disassemble a line at a given PC on the active CPU */ |
| 487 |
unsigned activecpu_dasm(char *buffer, unsigned pc); |
| 488 |
|
| 489 |
/* return a string containing the state of the flags on the active CPU */ |
| 490 |
const char *activecpu_flags(void); |
| 491 |
|
| 492 |
/* return a string containing the value of a register on the active CPU */ |
| 493 |
const char *activecpu_dump_reg(int regnum); |
| 494 |
|
| 495 |
/* return a string containing the state of the active CPU */ |
| 496 |
const char *activecpu_dump_state(void); |
| 497 |
|
| 498 |
/* return the default IRQ vector for the active CPU */ |
| 499 |
int activecpu_default_irq_vector(void); |
| 500 |
|
| 501 |
/* return the width of the address bus on the active CPU */ |
| 502 |
unsigned activecpu_address_bits(void); |
| 503 |
|
| 504 |
/* return the active address mask on the active CPU */ |
| 505 |
unsigned activecpu_address_mask(void); |
| 506 |
|
| 507 |
/* return the shift value to convert from address to bytes on the active CPU */ |
| 508 |
int activecpu_address_shift(void); |
| 509 |
|
| 510 |
/* return the endianess of the active CPU */ |
| 511 |
unsigned activecpu_endianess(void); |
| 512 |
|
| 513 |
/* return the width of the data bus on the active CPU */ |
| 514 |
unsigned activecpu_databus_width(void); |
| 515 |
|
| 516 |
/* return the required alignment of data accesses on the active CPU */ |
| 517 |
unsigned activecpu_align_unit(void); |
| 518 |
|
| 519 |
/* return the maximum length of one instruction on the active CPU */ |
| 520 |
unsigned activecpu_max_inst_len(void); |
| 521 |
|
| 522 |
/* return a string containing the name of the active CPU */ |
| 523 |
const char *activecpu_name(void); |
| 524 |
|
| 525 |
/* return a string containing the family of the active CPU */ |
| 526 |
const char *activecpu_core_family(void); |
| 527 |
|
| 528 |
/* return a string containing the version of the active CPU */ |
| 529 |
const char *activecpu_core_version(void); |
| 530 |
|
| 531 |
/* return a string containing the filename for the emulator of the active CPU */ |
| 532 |
const char *activecpu_core_file(void); |
| 533 |
|
| 534 |
/* return a string containing the emulation credits for the active CPU */ |
| 535 |
const char *activecpu_core_credits(void); |
| 536 |
|
| 537 |
/* return a string containing the registers of the active CPU */ |
| 538 |
const char *activecpu_reg_layout(void); |
| 539 |
|
| 540 |
/* return a string containing the debugger layout of the active CPU */ |
| 541 |
const char *activecpu_win_layout(void); |
| 542 |
|
| 543 |
|
| 544 |
|
| 545 |
/************************************* |
| 546 |
* |
| 547 |
* Specific CPU acccessors |
| 548 |
* |
| 549 |
*************************************/ |
| 550 |
|
| 551 |
/* execute the requested cycles on a given CPU */ |
| 552 |
int cpunum_execute(int cpunum, int cycles); |
| 553 |
|
| 554 |
/* signal a reset and set the IRQ ack callback for a given CPU */ |
| 555 |
void cpunum_reset(int cpunum, void *param, int (*irqack)(int)); |
| 556 |
|
| 557 |
/* read a byte from another CPU's memory space */ |
| 558 |
data8_t cpunum_read_byte(int cpunum, offs_t address); |
| 559 |
|
| 560 |
/* write a byte from another CPU's memory space */ |
| 561 |
void cpunum_write_byte(int cpunum, offs_t address, data8_t data); |
| 562 |
|
| 563 |
/* return a pointer to the saved context of a given CPU, or NULL if the |
| 564 |
context is active (and contained within the CPU core */ |
| 565 |
void *cpunum_get_context_ptr(int cpunum); |
| 566 |
|
| 567 |
/* return a pointer to the active cycle count table for a given CPU */ |
| 568 |
const void *cpunum_get_cycle_table(int cpunum, int which); |
| 569 |
|
| 570 |
/* set a pointer to the active cycle count table for a given CPU */ |
| 571 |
void cpunum_set_cycle_tbl(int cpunum, int which, void *new_table); |
| 572 |
|
| 573 |
/* return the value of a register on a given CPU */ |
| 574 |
unsigned cpunum_get_reg(int cpunum, int regnum); |
| 575 |
|
| 576 |
/* set the value of a register on a given CPU */ |
| 577 |
void cpunum_set_reg(int cpunum, int regnum, unsigned val); |
| 578 |
|
| 579 |
/* return the PC, corrected to a byte offset, on a given CPU */ |
| 580 |
offs_t cpunum_get_pc_byte(int cpunum); |
| 581 |
|
| 582 |
/* update the banking on a given CPU */ |
| 583 |
void cpunum_set_op_base(int cpunum, unsigned val); |
| 584 |
|
| 585 |
/* disassemble a line at a given PC on a given CPU */ |
| 586 |
unsigned cpunum_dasm(int cpunum, char *buffer, unsigned pc); |
| 587 |
|
| 588 |
/* return a string containing the state of the flags on a given CPU */ |
| 589 |
const char *cpunum_flags(int cpunum); |
| 590 |
|
| 591 |
/* return a string containing the value of a register on a given CPU */ |
| 592 |
const char *cpunum_dump_reg(int cpunum, int regnum); |
| 593 |
|
| 594 |
/* return a string containing the state of a given CPU */ |
| 595 |
const char *cpunum_dump_state(int cpunum); |
| 596 |
|
| 597 |
/* return the default IRQ vector for a given CPU */ |
| 598 |
int cpunum_default_irq_vector(int cpunum); |
| 599 |
|
| 600 |
/* return the width of the address bus on a given CPU */ |
| 601 |
unsigned cpunum_address_bits(int cpunum); |
| 602 |
|
| 603 |
/* return the active address mask on a given CPU */ |
| 604 |
unsigned cpunum_address_mask(int cpunum); |
| 605 |
|
| 606 |
/* return the shift value to convert from address to bytes on a given CPU */ |
| 607 |
int cpunum_address_shift(int cpunum); |
| 608 |
|
| 609 |
/* return the endianess of a given CPU */ |
| 610 |
unsigned cpunum_endianess(int cpunum); |
| 611 |
|
| 612 |
/* return the width of the data bus on a given CPU */ |
| 613 |
unsigned cpunum_databus_width(int cpunum); |
| 614 |
|
| 615 |
/* return the required alignment of data accesses on a given CPU */ |
| 616 |
unsigned cpunum_align_unit(int cpunum); |
| 617 |
|
| 618 |
/* return the maximum length of one instruction on a given CPU */ |
| 619 |
unsigned cpunum_max_inst_len(int cpunum); |
| 620 |
|
| 621 |
/* return a string containing the name of a given CPU */ |
| 622 |
const char *cpunum_name(int cpunum); |
| 623 |
|
| 624 |
/* return a string containing the family of a given CPU */ |
| 625 |
const char *cpunum_core_family(int cpunum); |
| 626 |
|
| 627 |
/* return a string containing the version of a given CPU */ |
| 628 |
const char *cpunum_core_version(int cpunum); |
| 629 |
|
| 630 |
/* return a string containing the filename for the emulator of a given CPU */ |
| 631 |
const char *cpunum_core_file(int cpunum); |
| 632 |
|
| 633 |
/* return a string containing the emulation credits for a given CPU */ |
| 634 |
const char *cpunum_core_credits(int cpunum); |
| 635 |
|
| 636 |
/* return a string containing the registers of a given CPU */ |
| 637 |
const char *cpunum_reg_layout(int cpunum); |
| 638 |
|
| 639 |
/* return a string containing the debugger layout of a given CPU */ |
| 640 |
const char *cpunum_win_layout(int cpunum); |
| 641 |
|
| 642 |
|
| 643 |
|
| 644 |
/************************************* |
| 645 |
* |
| 646 |
* CPU type acccessors |
| 647 |
* |
| 648 |
*************************************/ |
| 649 |
|
| 650 |
/* return the default IRQ vector for a given CPU type */ |
| 651 |
int cputype_default_irq_vector(int cputype); |
| 652 |
|
| 653 |
/* return the width of the address bus on a given CPU type */ |
| 654 |
unsigned cputype_address_bits(int cputype); |
| 655 |
|
| 656 |
/* return the active address mask on a given CPU type */ |
| 657 |
unsigned cputype_address_mask(int cputype); |
| 658 |
|
| 659 |
/* return the shift value to convert from address to bytes on a given CPU type */ |
| 660 |
int cputype_address_shift(int cputype); |
| 661 |
|
| 662 |
/* return the endianess of a given CPU type */ |
| 663 |
unsigned cputype_endianess(int cputype); |
| 664 |
|
| 665 |
/* return the width of the data bus on a given CPU type */ |
| 666 |
unsigned cputype_databus_width(int cputype); |
| 667 |
|
| 668 |
/* return the required alignment of data accesses on a given CPU type */ |
| 669 |
unsigned cputype_align_unit(int cputype); |
| 670 |
|
| 671 |
/* return the maximum length of one instruction on a given CPU type */ |
| 672 |
unsigned cputype_max_inst_len(int cputype); |
| 673 |
|
| 674 |
/* return a string containing the name of a given CPU type */ |
| 675 |
const char *cputype_name(int cputype); |
| 676 |
|
| 677 |
/* return a string containing the family of a given CPU type */ |
| 678 |
const char *cputype_core_family(int cputype); |
| 679 |
|
| 680 |
/* return a string containing the version of a given CPU type */ |
| 681 |
const char *cputype_core_version(int cputype); |
| 682 |
|
| 683 |
/* return a string containing the filename for the emulator of a given CPU type */ |
| 684 |
const char *cputype_core_file(int cputype); |
| 685 |
|
| 686 |
/* return a string containing the emulation credits for a given CPU type */ |
| 687 |
const char *cputype_core_credits(int cputype); |
| 688 |
|
| 689 |
/* return a string containing the registers of a given CPU type */ |
| 690 |
const char *cputype_reg_layout(int cputype); |
| 691 |
|
| 692 |
/* return a string containing the debugger layout of a given CPU type */ |
| 693 |
const char *cputype_win_layout(int cputype); |
| 694 |
|
| 695 |
|
| 696 |
|
| 697 |
/************************************* |
| 698 |
* |
| 699 |
* Miscellaneous functions |
| 700 |
* |
| 701 |
*************************************/ |
| 702 |
|
| 703 |
/* dump the states of all CPUs */ |
| 704 |
void cpu_dump_states(void); |
| 705 |
|
| 706 |
/* set a callback function for reset on the 68k */ |
| 707 |
void cpu_set_m68k_reset(int cpunum, void (*resetfn)(void)); |
| 708 |
|
| 709 |
|
| 710 |
|
| 711 |
/************************************* |
| 712 |
* |
| 713 |
* Macros |
| 714 |
* |
| 715 |
*************************************/ |
| 716 |
|
| 717 |
#define activecpu_get_previouspc() activecpu_get_reg(REG_PREVIOUSPC) |
| 718 |
#define activecpu_get_pc() activecpu_get_reg(REG_PC) |
| 719 |
#define activecpu_get_sp() activecpu_get_reg(REG_SP) |
| 720 |
#define activecpu_set_pc(val) activecpu_set_reg(REG_PC, val) |
| 721 |
#define activecpu_set_sp(val) activecpu_set_reg(REG_SP, val) |
| 722 |
|
| 723 |
#define cpunum_get_previouspc(cpu) cpunum_get_reg(cpu, REG_PREVIOUSPC) |
| 724 |
#define cpunum_get_pc(cpu) cpunum_get_reg(cpu, REG_PC) |
| 725 |
#define cpunum_get_sp(cpu) cpunum_get_reg(cpu, REG_SP) |
| 726 |
#define cpunum_set_pc(cpu, val) cpunum_set_reg(cpu, REG_PC, val) |
| 727 |
#define cpunum_set_sp(cpu, val) cpunum_set_reg(cpu, REG_SP, val) |
| 728 |
|
| 729 |
/* this is kind of gross - is it necessary */ |
| 730 |
#define cpu_geturnpc() activecpu_get_reg(REG_SP_CONTENTS) |
| 731 |
|
| 732 |
|
| 733 |
|
| 734 |
/************************************* |
| 735 |
* |
| 736 |
* CPU interface accessors |
| 737 |
* |
| 738 |
*************************************/ |
| 739 |
|
| 740 |
/* return a pointer to the interface struct for a given CPU type */ |
| 741 |
INLINE const struct cpu_interface *cputype_get_interface(int cputype) |
| 742 |
{ |
| 743 |
extern const struct cpu_interface cpuintrf[]; |
| 744 |
return &cpuintrf[cputype]; |
| 745 |
} |
| 746 |
|
| 747 |
|
| 748 |
/* return a the index of the active CPU */ |
| 749 |
INLINE int cpu_getactivecpu(void) |
| 750 |
{ |
| 751 |
extern int activecpu; |
| 752 |
return activecpu; |
| 753 |
} |
| 754 |
|
| 755 |
|
| 756 |
/* return a the total number of registered CPUs */ |
| 757 |
INLINE int cpu_gettotalcpu(void) |
| 758 |
{ |
| 759 |
extern int totalcpu; |
| 760 |
return totalcpu; |
| 761 |
} |
| 762 |
|
| 763 |
|
| 764 |
|
| 765 |
#ifdef __cplusplus |
| 766 |
} |
| 767 |
#endif |
| 768 |
|
| 769 |
#endif /* CPUINTRF_H */ |
| 770 |
|
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