OSDN -- Develop and Download Open Source Software

Android-x86
Fork
Donation

  • R/O
  • HTTP
  • SSH
  • HTTPS
Fork

external-mesa: Commit

external/mesa


Commit MetaInfo

Revisiona3ddc7a0baaa011963e4904433f9c8fc4329096d (tree)
Time2021-07-08 21:42:26
AuthorChih-Wei Huang <cwhuang@linu...>
CommiterChih-Wei Huang

Log Message

Merge remote-tracking branch 'mesa/21.1' into pie-x86

Change Summary

Incremental Difference

--- a/.gitlab-ci/windows/mesa_build.ps1
+++ b/.gitlab-ci/windows/mesa_build.ps1
@@ -2,6 +2,8 @@
22 Write-Host "Refreshing Windows TLS CA cache"
33 (New-Object System.Net.WebClient).DownloadString("https://github.com") >$null
44
5+$env:PYTHONUTF8=1
6+
57 Get-Date
68 Write-Host "Compiling Mesa"
79 $builddir = New-Item -ItemType Directory -Name "_build"
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -1,5 +1,5054 @@
11 [
22 {
3+ "sha": "40b67a292297606f0a7576e3ef4087028d5edd17",
4+ "description": "anv: allocate bigger batches as we grow command buffers",
5+ "nominated": true,
6+ "nomination_type": 0,
7+ "resolution": 1,
8+ "main_sha": null,
9+ "because_sha": null
10+ },
11+ {
12+ "sha": "5853f17c304d9f9acb2c4ad826f447d19405ec15",
13+ "description": "anv: Advertise VK_KHR_shader_subgroup_uniform_control_flow",
14+ "nominated": false,
15+ "nomination_type": null,
16+ "resolution": 4,
17+ "main_sha": null,
18+ "because_sha": null
19+ },
20+ {
21+ "sha": "6ad88a8f086da55916b567a328b981b14ddfdcf8",
22+ "description": "spirv: Support SPV_KHR_subgroup_uniform_control_flow",
23+ "nominated": false,
24+ "nomination_type": null,
25+ "resolution": 4,
26+ "main_sha": null,
27+ "because_sha": null
28+ },
29+ {
30+ "sha": "a219073e9b4384d785b467660230c5eb41e6c549",
31+ "description": "spirv: Update headers and metadata from latest Khronos commit",
32+ "nominated": false,
33+ "nomination_type": null,
34+ "resolution": 4,
35+ "main_sha": null,
36+ "because_sha": null
37+ },
38+ {
39+ "sha": "3a9289eaedc1fe7b92783a94dbe3a5fc308471c5",
40+ "description": "nir: Add test to check edge case in Split ALU optimization",
41+ "nominated": false,
42+ "nomination_type": null,
43+ "resolution": 4,
44+ "main_sha": null,
45+ "because_sha": null
46+ },
47+ {
48+ "sha": "b9519297955c3a75095f986b0e29afaf3a8c923a",
49+ "description": "nir/opt_if: Don't split ALU for single block infinite loops",
50+ "nominated": true,
51+ "nomination_type": 1,
52+ "resolution": 1,
53+ "main_sha": null,
54+ "because_sha": "0881e90c09965818b02e359474a6f7446b41d647"
55+ },
56+ {
57+ "sha": "7b89e4d1048d6104f07930d3717ee543253dad50",
58+ "description": "i965: Prevent invalid framebuffer usage",
59+ "nominated": false,
60+ "nomination_type": null,
61+ "resolution": 4,
62+ "main_sha": null,
63+ "because_sha": null
64+ },
65+ {
66+ "sha": "6a0c0d0da9b27d2868f993dcd71220bf2bd7e18f",
67+ "description": "i915: Prevent invalid framebuffer usage",
68+ "nominated": false,
69+ "nomination_type": null,
70+ "resolution": 4,
71+ "main_sha": null,
72+ "because_sha": null
73+ },
74+ {
75+ "sha": "40b1668ebdc47d5a816f62cf59cf77993b3933a6",
76+ "description": "amd/ci: Use MESA_VK_IGNORE_CONFORMANCE_WARNING to reduce warnings",
77+ "nominated": false,
78+ "nomination_type": null,
79+ "resolution": 4,
80+ "main_sha": null,
81+ "because_sha": null
82+ },
83+ {
84+ "sha": "ed77bf3c4ecfc1837eb868cb435f7632d2240ab7",
85+ "description": "ci: Unify on MESA_VK_IGNORE_CONFORMANCE_WARNING",
86+ "nominated": false,
87+ "nomination_type": null,
88+ "resolution": 4,
89+ "main_sha": null,
90+ "because_sha": null
91+ },
92+ {
93+ "sha": "6a79ee97f48ee99718b97bb8870a74faeecd56d9",
94+ "description": "anv: VK_EXT_multi_draw implementation",
95+ "nominated": false,
96+ "nomination_type": null,
97+ "resolution": 4,
98+ "main_sha": null,
99+ "because_sha": null
100+ },
101+ {
102+ "sha": "1e39f2c1994abb7183ebc05de29e11561c388eb5",
103+ "description": "anv: unify some draw state vertex constant emission",
104+ "nominated": false,
105+ "nomination_type": null,
106+ "resolution": 4,
107+ "main_sha": null,
108+ "because_sha": null
109+ },
110+ {
111+ "sha": "15a2e5dcdb9317a090915e89fae44467296a4512",
112+ "description": "zink: repack zink_context struct a bit",
113+ "nominated": false,
114+ "nomination_type": null,
115+ "resolution": 4,
116+ "main_sha": null,
117+ "because_sha": null
118+ },
119+ {
120+ "sha": "d01e7b50b88ae6a12df5a5772ad817d8e9f58bb3",
121+ "description": "freedreno, tu: Set SP_XS_PVT_MEM_HW_STACK_OFFSET",
122+ "nominated": false,
123+ "nomination_type": null,
124+ "resolution": 4,
125+ "main_sha": null,
126+ "because_sha": null
127+ },
128+ {
129+ "sha": "02b8f8704cfa7d4514795c9e5b8444e4a5c2fb25",
130+ "description": "freedreno/a6xx: Make SP_XS_PVT_MEM_HW_STACK_OFFSET non-inline",
131+ "nominated": false,
132+ "nomination_type": null,
133+ "resolution": 4,
134+ "main_sha": null,
135+ "because_sha": null
136+ },
137+ {
138+ "sha": "fdc0f489e098d320593a1c6837a19726c84d90e9",
139+ "description": "ir3: add ldg.a,stg.a which allow complex in-place offset calculation",
140+ "nominated": false,
141+ "nomination_type": null,
142+ "resolution": 4,
143+ "main_sha": null,
144+ "because_sha": null
145+ },
146+ {
147+ "sha": "4b06db0548603a719c836070b7b8959bce45a2c2",
148+ "description": "freedreno/isa: add uoffset type to print positive-only offsets",
149+ "nominated": false,
150+ "nomination_type": null,
151+ "resolution": 4,
152+ "main_sha": null,
153+ "because_sha": null
154+ },
155+ {
156+ "sha": "ba1c989348de066b35678fb1e6151dccd26831eb",
157+ "description": "freedreno/computerator: pass iova of buffer to const register",
158+ "nominated": false,
159+ "nomination_type": null,
160+ "resolution": 4,
161+ "main_sha": null,
162+ "because_sha": null
163+ },
164+ {
165+ "sha": "e791b2045a47e95b4d63910add3ecdbcacf52d1f",
166+ "description": "anv: do not dereference VkPipelineMultisampleStateCreateInfo always",
167+ "nominated": false,
168+ "nomination_type": null,
169+ "resolution": 4,
170+ "main_sha": null,
171+ "because_sha": null
172+ },
173+ {
174+ "sha": "a9fd4fa26c64275168946fa4d29ad066c0da7bc4",
175+ "description": "turnip: early exit in tu6_draw_common to save cpu cycles",
176+ "nominated": false,
177+ "nomination_type": null,
178+ "resolution": 4,
179+ "main_sha": null,
180+ "because_sha": null
181+ },
182+ {
183+ "sha": "815a85dd7c44f4be4cbf5b351836c921a7a923fd",
184+ "description": "turnip: do not re-emit same vs params",
185+ "nominated": false,
186+ "nomination_type": null,
187+ "resolution": 4,
188+ "main_sha": null,
189+ "because_sha": null
190+ },
191+ {
192+ "sha": "63e80d441a741202cf8190fbc56dccd3bd5b4c3f",
193+ "description": "intel/genxml: Remove old scratch fields on GFX version 12.5",
194+ "nominated": false,
195+ "nomination_type": null,
196+ "resolution": 4,
197+ "main_sha": null,
198+ "because_sha": null
199+ },
200+ {
201+ "sha": "eeeea5cb873b40418c738e25e4032fb1fd9b7ac9",
202+ "description": "anv: Add support for scratch on XeHP",
203+ "nominated": false,
204+ "nomination_type": null,
205+ "resolution": 4,
206+ "main_sha": null,
207+ "because_sha": null
208+ },
209+ {
210+ "sha": "ae18e1e707c4be005256305a30b747ab1bdf55d8",
211+ "description": "iris: Add support for scratch on XeHP",
212+ "nominated": false,
213+ "nomination_type": null,
214+ "resolution": 4,
215+ "main_sha": null,
216+ "because_sha": null
217+ },
218+ {
219+ "sha": "545011b445b31279e9c6b837b71f2953fa42f1f5",
220+ "description": "iris: Add a MEMZONE_BINDLESS and uploader",
221+ "nominated": false,
222+ "nomination_type": null,
223+ "resolution": 4,
224+ "main_sha": null,
225+ "because_sha": null
226+ },
227+ {
228+ "sha": "8ca0513ecaef6b3f70f9a6c2550ad75baf202052",
229+ "description": "intel/genxml: Add new ScratchSpaceBuffer fields on GFX version 12.5",
230+ "nominated": false,
231+ "nomination_type": null,
232+ "resolution": 4,
233+ "main_sha": null,
234+ "because_sha": null
235+ },
236+ {
237+ "sha": "1e242785c3155e71fec2ffcc7a814392ef9c90fe",
238+ "description": "intel/fs: Implement load/store_scratch on XeHP",
239+ "nominated": false,
240+ "nomination_type": null,
241+ "resolution": 4,
242+ "main_sha": null,
243+ "because_sha": null
244+ },
245+ {
246+ "sha": "c38812be1df41469b8995dbbcf3b327a3aeae5c3",
247+ "description": "intel/fs: Implement spilling on XeHP",
248+ "nominated": false,
249+ "nomination_type": null,
250+ "resolution": 4,
251+ "main_sha": null,
252+ "because_sha": null
253+ },
254+ {
255+ "sha": "96ee78778b515d5b71038c6ac16ad6f627c5062e",
256+ "description": "intel/isl: Add support for scratch buffers",
257+ "nominated": false,
258+ "nomination_type": null,
259+ "resolution": 4,
260+ "main_sha": null,
261+ "because_sha": null
262+ },
263+ {
264+ "sha": "443627fcc0e95ccce36521f4e6bbb48b7b6152a5",
265+ "description": "intel/genxml: Add SURFTYPE_SCRATCH on GFX version 12.5",
266+ "nominated": false,
267+ "nomination_type": null,
268+ "resolution": 4,
269+ "main_sha": null,
270+ "because_sha": null
271+ },
272+ {
273+ "sha": "ea43465dbfc856f114491deb605393f7ac9b6101",
274+ "description": "Revert \"freedreno: Cooperate with tc to stop checking the BC for resource_busy().\"",
275+ "nominated": false,
276+ "nomination_type": 2,
277+ "resolution": 4,
278+ "main_sha": null,
279+ "because_sha": "5cb043cf82af4af88dbfe83ce1eff4cc41e2a766"
280+ },
281+ {
282+ "sha": "be94bad12606c98ae3a06579b6740d20b11dca98",
283+ "description": "zink: flush pending clears if a resource is bound as a descriptor",
284+ "nominated": false,
285+ "nomination_type": null,
286+ "resolution": 4,
287+ "main_sha": null,
288+ "because_sha": null
289+ },
290+ {
291+ "sha": "9a027bebb5e1d66cff9e29b7c4d423443afc1de0",
292+ "description": "zink: only queue deferred descriptor layout change on first bind or change",
293+ "nominated": false,
294+ "nomination_type": null,
295+ "resolution": 4,
296+ "main_sha": null,
297+ "because_sha": null
298+ },
299+ {
300+ "sha": "8f897ae7c168b64de699776eaf7701dada1a0b6c",
301+ "description": "zink: improve automatic layout transitions for sampler+image descriptors",
302+ "nominated": false,
303+ "nomination_type": null,
304+ "resolution": 4,
305+ "main_sha": null,
306+ "because_sha": null
307+ },
308+ {
309+ "sha": "8a345adf208c46c3a551500015a432f11358ef44",
310+ "description": "zink: use bind counts to more accurately determine image descriptor's exact layout",
311+ "nominated": false,
312+ "nomination_type": null,
313+ "resolution": 4,
314+ "main_sha": null,
315+ "because_sha": null
316+ },
317+ {
318+ "sha": "e8a188a86e463c2eab41fc7e813663c9952e8a93",
319+ "description": "zink: only do deferred image barriers if layout changes",
320+ "nominated": false,
321+ "nomination_type": null,
322+ "resolution": 4,
323+ "main_sha": null,
324+ "because_sha": null
325+ },
326+ {
327+ "sha": "d3b7b355840531db9e122530504664d319c01c39",
328+ "description": "zink: split deferring of barriers to image and buffer functions",
329+ "nominated": false,
330+ "nomination_type": null,
331+ "resolution": 4,
332+ "main_sha": null,
333+ "because_sha": null
334+ },
335+ {
336+ "sha": "0e390d2f835c24ebb59b4a3373668ddce6228cdf",
337+ "description": "zink: break out image descriptor layout into util function",
338+ "nominated": false,
339+ "nomination_type": null,
340+ "resolution": 4,
341+ "main_sha": null,
342+ "because_sha": null
343+ },
344+ {
345+ "sha": "04578badc9e8dd1d76c5440964f3493b5afecc08",
346+ "description": "ci/windows: fix zink msvc build-rules",
347+ "nominated": false,
348+ "nomination_type": 1,
349+ "resolution": 4,
350+ "main_sha": null,
351+ "because_sha": "a426d7c2643eaa472fc01b5cc5f0bc89e7ac917b"
352+ },
353+ {
354+ "sha": "d0cbd39a5cf2645734b95fdc1cc6debfd4578646",
355+ "description": "microsoft/spirv_to_dxil: Add drive_location assignment",
356+ "nominated": false,
357+ "nomination_type": null,
358+ "resolution": 4,
359+ "main_sha": null,
360+ "because_sha": null
361+ },
362+ {
363+ "sha": "aa7aa7c78fca41a09af7693aa69571602ccb694c",
364+ "description": "microsoft/compiler: Switch io sort to use nir_sort_variables_with_modes",
365+ "nominated": false,
366+ "nomination_type": null,
367+ "resolution": 4,
368+ "main_sha": null,
369+ "because_sha": null
370+ },
371+ {
372+ "sha": "8a5333c105f4d99c139c866af1074366dcd7adb4",
373+ "description": "nir: Add modes filter to nir_sort_variables",
374+ "nominated": false,
375+ "nomination_type": null,
376+ "resolution": 4,
377+ "main_sha": null,
378+ "because_sha": null
379+ },
380+ {
381+ "sha": "81cb20bd17c7ad0ac94f41462685635df25fd16e",
382+ "description": "nir: Add a function for sorting variables",
383+ "nominated": false,
384+ "nomination_type": null,
385+ "resolution": 4,
386+ "main_sha": null,
387+ "because_sha": null
388+ },
389+ {
390+ "sha": "cf385cf68c542c2391052d692582bdc0f723dc65",
391+ "description": "util: Add qsort_r/s args adapter for MSVC and BSD/macOS",
392+ "nominated": false,
393+ "nomination_type": null,
394+ "resolution": 4,
395+ "main_sha": null,
396+ "because_sha": null
397+ },
398+ {
399+ "sha": "1df2acfbb81f37e4c3d2a49f570ccfc96b32eb8c",
400+ "description": "util: Add simple test for util_qsort_r",
401+ "nominated": false,
402+ "nomination_type": null,
403+ "resolution": 4,
404+ "main_sha": null,
405+ "because_sha": null
406+ },
407+ {
408+ "sha": "bdd460fdcbfd45aa7d48a53feb753d0c5529b392",
409+ "description": "util: Add an implementation of qsort_r for non-GNU platforms",
410+ "nominated": false,
411+ "nomination_type": null,
412+ "resolution": 4,
413+ "main_sha": null,
414+ "because_sha": null
415+ },
416+ {
417+ "sha": "e2e22720dcaeb73a2236d4d8d776ece64e137d04",
418+ "description": "d3d12, microsoft/compiler: Moving driver_location allocation to compiler",
419+ "nominated": false,
420+ "nomination_type": null,
421+ "resolution": 4,
422+ "main_sha": null,
423+ "because_sha": null
424+ },
425+ {
426+ "sha": "d0f1698a733c0d642ed7bf0391fe9ea796197043",
427+ "description": "d3d12, microsoft/compiler: Switching semantic names to TEXCOORD",
428+ "nominated": false,
429+ "nomination_type": null,
430+ "resolution": 4,
431+ "main_sha": null,
432+ "because_sha": null
433+ },
434+ {
435+ "sha": "b8e2374950345f2b7b9a899d5a4c1ba40997f033",
436+ "description": "microsoft/compiler: Remove de-duplication of arbitrary semantic names",
437+ "nominated": false,
438+ "nomination_type": null,
439+ "resolution": 4,
440+ "main_sha": null,
441+ "because_sha": null
442+ },
443+ {
444+ "sha": "83f8b19f9b72eb618fe6f8504978f5d6133675ec",
445+ "description": "vulkan/wsi/wayland: implement the full format table",
446+ "nominated": false,
447+ "nomination_type": null,
448+ "resolution": 4,
449+ "main_sha": null,
450+ "because_sha": null
451+ },
452+ {
453+ "sha": "8d0d2e82e7506d15a98b7889dd1478d472fdef0b",
454+ "description": "tu/kgsl: Fix file descriptor double close",
455+ "nominated": false,
456+ "nomination_type": null,
457+ "resolution": 4,
458+ "main_sha": null,
459+ "because_sha": null
460+ },
461+ {
462+ "sha": "a426d7c2643eaa472fc01b5cc5f0bc89e7ac917b",
463+ "description": "ci/windows: enable msvc builds of zink",
464+ "nominated": false,
465+ "nomination_type": null,
466+ "resolution": 4,
467+ "main_sha": null,
468+ "because_sha": null
469+ },
470+ {
471+ "sha": "b437fb810a83382cfae9aa2f38875a9a47e011a1",
472+ "description": "ci/windows: work around meson encoding issues",
473+ "nominated": true,
474+ "nomination_type": 0,
475+ "resolution": 1,
476+ "main_sha": null,
477+ "because_sha": null
478+ },
479+ {
480+ "sha": "f815026d36f32a83326b09113ed28ff3263bb7a0",
481+ "description": "zink: cast pointers to uintptr_t",
482+ "nominated": false,
483+ "nomination_type": 1,
484+ "resolution": 4,
485+ "main_sha": null,
486+ "because_sha": "d80d9e1c9354135f3b4a5788e94ba2a09aeec2fe"
487+ },
488+ {
489+ "sha": "bae4dca8e461640d8bed57dc77875afb4d5087ce",
490+ "description": "aux/trace: fix bool argument",
491+ "nominated": true,
492+ "nomination_type": 1,
493+ "resolution": 1,
494+ "main_sha": null,
495+ "because_sha": "c1270d4845d39939d6a7d3b1b81e0d2f9e33133d"
496+ },
497+ {
498+ "sha": "ea5707c52f5e45f16ef554ee3d9fe2d3f318dae5",
499+ "description": "turnip: Disable buffer texturing on 422 formats.",
500+ "nominated": false,
501+ "nomination_type": null,
502+ "resolution": 4,
503+ "main_sha": null,
504+ "because_sha": null
505+ },
506+ {
507+ "sha": "6bc88c26b69d53c0f60e5348ad87cd35e59f16d4",
508+ "description": "ci/turnip: Document create_instance_device_intentional_alloc_fail's fail.",
509+ "nominated": false,
510+ "nomination_type": null,
511+ "resolution": 4,
512+ "main_sha": null,
513+ "because_sha": null
514+ },
515+ {
516+ "sha": "55000408f9ff7d3fb82e0746c0182e69d27139db",
517+ "description": "turnip: Use vk_startup_errorf() in more startup paths.",
518+ "nominated": false,
519+ "nomination_type": null,
520+ "resolution": 4,
521+ "main_sha": null,
522+ "because_sha": null
523+ },
524+ {
525+ "sha": "31f8b704816d191936962a66e9afe18a878221a5",
526+ "description": "turnip: Link more MRs and issues related to our xfails.",
527+ "nominated": false,
528+ "nomination_type": null,
529+ "resolution": 4,
530+ "main_sha": null,
531+ "because_sha": null
532+ },
533+ {
534+ "sha": "4b44e28526dcc6a8d4cb59d4b904a71fc2a40590",
535+ "description": "freedreno/ir3: Report RA failure with mesa_loge().",
536+ "nominated": false,
537+ "nomination_type": null,
538+ "resolution": 4,
539+ "main_sha": null,
540+ "because_sha": null
541+ },
542+ {
543+ "sha": "45b7b57a838b5f91e993e5b8b42fdc3fe3d8b9ac",
544+ "description": "iris/ci: disable amly jobs",
545+ "nominated": false,
546+ "nomination_type": null,
547+ "resolution": 4,
548+ "main_sha": null,
549+ "because_sha": null
550+ },
551+ {
552+ "sha": "b14bd285f8f48bdb495f9902282ffc0c178fcb70",
553+ "description": "aco/ra: handle copies of copies better",
554+ "nominated": false,
555+ "nomination_type": null,
556+ "resolution": 4,
557+ "main_sha": null,
558+ "because_sha": null
559+ },
560+ {
561+ "sha": "995e218993767651c128cd89c5f90b6684fb4b50",
562+ "description": "aco/ra: handle copies of definition registers",
563+ "nominated": false,
564+ "nomination_type": null,
565+ "resolution": 4,
566+ "main_sha": null,
567+ "because_sha": null
568+ },
569+ {
570+ "sha": "d31dd812925150adc4e137d5915455ad894eaa0e",
571+ "description": "anv: Claim to be a discrete GPU if has_lmem",
572+ "nominated": false,
573+ "nomination_type": null,
574+ "resolution": 4,
575+ "main_sha": null,
576+ "because_sha": null
577+ },
578+ {
579+ "sha": "b6a1063c2ece41c3bb7e212f09a51884bc56ab51",
580+ "description": "intel/dev: Set has_local_mem for DG1",
581+ "nominated": false,
582+ "nomination_type": null,
583+ "resolution": 4,
584+ "main_sha": null,
585+ "because_sha": null
586+ },
587+ {
588+ "sha": "e505c221fa79a36445aa23c63238ec6d8998c599",
589+ "description": "anv: Allocate scratch and workaround BO in local memory",
590+ "nominated": false,
591+ "nomination_type": null,
592+ "resolution": 4,
593+ "main_sha": null,
594+ "because_sha": null
595+ },
596+ {
597+ "sha": "6352371ff64d9e1c5c456dbcbf31092f39609418",
598+ "description": "anv: Allocate BO in appropriate region",
599+ "nominated": false,
600+ "nomination_type": null,
601+ "resolution": 4,
602+ "main_sha": null,
603+ "because_sha": null
604+ },
605+ {
606+ "sha": "3f8eca7f82bd0432c18887ac4334f51e240143b7",
607+ "description": "anv: Wrapper around I915_GEM_CREATE_EXT_MEMORY_REGIONS",
608+ "nominated": false,
609+ "nomination_type": null,
610+ "resolution": 4,
611+ "main_sha": null,
612+ "because_sha": null
613+ },
614+ {
615+ "sha": "65e8d72bc106b0cce62d2037aa0e7f1babf42d13",
616+ "description": "anv: Query memory region info",
617+ "nominated": false,
618+ "nomination_type": null,
619+ "resolution": 4,
620+ "main_sha": null,
621+ "because_sha": null
622+ },
623+ {
624+ "sha": "aa3775c8e4aa0bf063121eada45564e1d2c8bb14",
625+ "description": "iris: Map with WC on non-LLC platforms.",
626+ "nominated": false,
627+ "nomination_type": null,
628+ "resolution": 4,
629+ "main_sha": null,
630+ "because_sha": null
631+ },
632+ {
633+ "sha": "b6a7400dfdb4e41c3c3fb3e4afa93464635be423",
634+ "description": "iris/bufmgr: Add flag to allocate from local memory.",
635+ "nominated": false,
636+ "nomination_type": null,
637+ "resolution": 4,
638+ "main_sha": null,
639+ "because_sha": null
640+ },
641+ {
642+ "sha": "55be94dcab4eebd10ae11c3f982c4c91b67fb3a7",
643+ "description": "iris/bufmgr: Add new set of buckets for local memory.",
644+ "nominated": false,
645+ "nomination_type": null,
646+ "resolution": 4,
647+ "main_sha": null,
648+ "because_sha": null
649+ },
650+ {
651+ "sha": "e60114b2ae117b0f9cc55de57ab397804c8d6bf8",
652+ "description": "iris/bufmgr: Query memory region info.",
653+ "nominated": false,
654+ "nomination_type": null,
655+ "resolution": 4,
656+ "main_sha": null,
657+ "because_sha": null
658+ },
659+ {
660+ "sha": "84069acfd4129956e3fdb0076e1b3f79b8f9386b",
661+ "description": "iris/bufmgr: Align vma addresses to 64K for local memory",
662+ "nominated": false,
663+ "nomination_type": null,
664+ "resolution": 4,
665+ "main_sha": null,
666+ "because_sha": null
667+ },
668+ {
669+ "sha": "cb6feae0b5c83b36af6538f1d0dae51f76ead4cd",
670+ "description": "intel/devinfo: Add has_local_mem",
671+ "nominated": false,
672+ "nomination_type": null,
673+ "resolution": 4,
674+ "main_sha": null,
675+ "because_sha": null
676+ },
677+ {
678+ "sha": "8dc3c91a5ce118f358bf5aa36d2a4a6b0b4e3789",
679+ "description": "include/drm-uapi: bump headers",
680+ "nominated": false,
681+ "nomination_type": null,
682+ "resolution": 4,
683+ "main_sha": null,
684+ "because_sha": null
685+ },
686+ {
687+ "sha": "2fe2eb1911f4425f76a6f5f7b9d47f80bf0c5571",
688+ "description": "radv: Implement VK_EXT_acquire_drm_display",
689+ "nominated": false,
690+ "nomination_type": null,
691+ "resolution": 4,
692+ "main_sha": null,
693+ "because_sha": null
694+ },
695+ {
696+ "sha": "f9944899a7f80994661fb0e8b4a09e1d5f3c8caf",
697+ "description": "vulkan/wsi: Implement VK_EXT_acquire_drm_display",
698+ "nominated": false,
699+ "nomination_type": null,
700+ "resolution": 4,
701+ "main_sha": null,
702+ "because_sha": null
703+ },
704+ {
705+ "sha": "fdf22aad739fdb9575e6839646dc3e948c5b40fc",
706+ "description": "vulkan/wsi: add drm_fd param to wsi_display_get_connector",
707+ "nominated": false,
708+ "nomination_type": null,
709+ "resolution": 4,
710+ "main_sha": null,
711+ "because_sha": null
712+ },
713+ {
714+ "sha": "7fb70ee2d51bd4a309641edb331f16e87e059447",
715+ "description": "docs/isl: Improve the bit[6] swizzling section of the tiling chapter",
716+ "nominated": false,
717+ "nomination_type": null,
718+ "resolution": 4,
719+ "main_sha": null,
720+ "because_sha": null
721+ },
722+ {
723+ "sha": "b8030ab1ea91cf4ba9ebac80d8d5aebd41f3bf80",
724+ "description": "isl,docs: Add a chapter on AUX state tracking",
725+ "nominated": false,
726+ "nomination_type": null,
727+ "resolution": 4,
728+ "main_sha": null,
729+ "because_sha": null
730+ },
731+ {
732+ "sha": "94a52bc85cd1f75eae66c9b1c03272b1a68ff5fd",
733+ "description": "isl,iris: Move the extra_aux_surf logic into iris",
734+ "nominated": false,
735+ "nomination_type": null,
736+ "resolution": 4,
737+ "main_sha": null,
738+ "because_sha": null
739+ },
740+ {
741+ "sha": "37f76aab1c7b3c7aa7066ef8f2406e9e2fdf8057",
742+ "description": "isl: Take a hiz_or_mcs_surf in isl_surf_supports_ccs",
743+ "nominated": false,
744+ "nomination_type": null,
745+ "resolution": 4,
746+ "main_sha": null,
747+ "because_sha": null
748+ },
749+ {
750+ "sha": "2d2590a879b211b2ec290299467d1fc1b8e772b9",
751+ "description": "isl: Assert some iris invariants in isl_surf_get_ccs_surf",
752+ "nominated": false,
753+ "nomination_type": null,
754+ "resolution": 4,
755+ "main_sha": null,
756+ "because_sha": null
757+ },
758+ {
759+ "sha": "6fe82e6c1e36892d9c9625e233a9f250893630a2",
760+ "description": "asahi: Fix macOS macro.",
761+ "nominated": false,
762+ "nomination_type": 1,
763+ "resolution": 4,
764+ "main_sha": null,
765+ "because_sha": "26b19bda3068ecee3b10ff2eed6b5c4f027abcba"
766+ },
767+ {
768+ "sha": "9aff548ff4f6c2d52bfca972050324e0eba043ec",
769+ "description": "libgl-gdi: add missing include",
770+ "nominated": true,
771+ "nomination_type": 1,
772+ "resolution": 1,
773+ "main_sha": null,
774+ "because_sha": "fdfe4a4d307377f078a01d05a247c4f61d208be8"
775+ },
776+ {
777+ "sha": "fa784acbdfed22be75e4184cd3599a98a4e76de4",
778+ "description": "zink: remove some needless moltenvk details",
779+ "nominated": false,
780+ "nomination_type": null,
781+ "resolution": 4,
782+ "main_sha": null,
783+ "because_sha": null
784+ },
785+ {
786+ "sha": "ccb9f8670e7d8c0e33d3fcb9857a2b3eac5a47ec",
787+ "description": "zink: do not store moltenvk functions in screen",
788+ "nominated": false,
789+ "nomination_type": null,
790+ "resolution": 4,
791+ "main_sha": null,
792+ "because_sha": null
793+ },
794+ {
795+ "sha": "95cbb560cf73ba60086b3c91d35ebcf577a95320",
796+ "description": "zink: remove unused moltenvk functions",
797+ "nominated": true,
798+ "nomination_type": 1,
799+ "resolution": 1,
800+ "main_sha": null,
801+ "because_sha": "c2cb2dd3bc68d0d61fa483a3927563bab08c93e9"
802+ },
803+ {
804+ "sha": "7b220f8694d1e2934b6ed7fc702f0a4a441d2031",
805+ "description": "zink: unbreak moltenvk code",
806+ "nominated": false,
807+ "nomination_type": 1,
808+ "resolution": 4,
809+ "main_sha": null,
810+ "because_sha": "55748681032b41bf09b92111064807a8c46216bf"
811+ },
812+ {
813+ "sha": "e979ecbd45670590d6b46de51215d5bc757da4ce",
814+ "description": "zink: remove unused function-pointers",
815+ "nominated": false,
816+ "nomination_type": 1,
817+ "resolution": 4,
818+ "main_sha": null,
819+ "because_sha": "55748681032b41bf09b92111064807a8c46216bf"
820+ },
821+ {
822+ "sha": "efa863990a264cbafeadbe04f7f486da000c7983",
823+ "description": "zink: drop unused macros",
824+ "nominated": false,
825+ "nomination_type": 1,
826+ "resolution": 4,
827+ "main_sha": null,
828+ "because_sha": "55748681032b41bf09b92111064807a8c46216bf"
829+ },
830+ {
831+ "sha": "d2114bf413a75fc40159cb037c0a773517f93c8c",
832+ "description": "crocus: fix another printf specifier.",
833+ "nominated": false,
834+ "nomination_type": null,
835+ "resolution": 4,
836+ "main_sha": null,
837+ "because_sha": null
838+ },
839+ {
840+ "sha": "78c979dc9311e7bb3d4180db4a9b366c532921e2",
841+ "description": "crocus/gfx6: always be dirtying gs attachments for xfb",
842+ "nominated": false,
843+ "nomination_type": null,
844+ "resolution": 4,
845+ "main_sha": null,
846+ "because_sha": null
847+ },
848+ {
849+ "sha": "7399d6028f5363d9b90e57b95a539ce2476d8792",
850+ "description": "crocus: Avoid replacing backing storage for buffers with no contents",
851+ "nominated": false,
852+ "nomination_type": null,
853+ "resolution": 4,
854+ "main_sha": null,
855+ "because_sha": null
856+ },
857+ {
858+ "sha": "0fa4b64f6c349da91bde6bcadda307b249705862",
859+ "description": "crocus: dirty blend state more often.",
860+ "nominated": false,
861+ "nomination_type": null,
862+ "resolution": 4,
863+ "main_sha": null,
864+ "because_sha": null
865+ },
866+ {
867+ "sha": "a74c16e5f8bd0647f8d5bf199eccd1551b0949e3",
868+ "description": "crocus/gfx6: fix sampler view first level.",
869+ "nominated": false,
870+ "nomination_type": null,
871+ "resolution": 4,
872+ "main_sha": null,
873+ "because_sha": null
874+ },
875+ {
876+ "sha": "0acd202858aae3774fdd0b1d92af4485a4e464f2",
877+ "description": "intel/genxml: fix gfx6 GS SVB_INDEX encoding",
878+ "nominated": false,
879+ "nomination_type": null,
880+ "resolution": 4,
881+ "main_sha": null,
882+ "because_sha": null
883+ },
884+ {
885+ "sha": "c282a082bef05d21aebf7f9a6c95d80f4b01cd23",
886+ "description": "crocus/query: poll the syncobj in the no wait situation",
887+ "nominated": false,
888+ "nomination_type": null,
889+ "resolution": 4,
890+ "main_sha": null,
891+ "because_sha": null
892+ },
893+ {
894+ "sha": "9ca6abd424c7f1a3c24dc5f4c021eed75613a3ae",
895+ "description": "vl/dri3: Don't leak regions on the X server",
896+ "nominated": false,
897+ "nomination_type": null,
898+ "resolution": 4,
899+ "main_sha": null,
900+ "because_sha": null
901+ },
902+ {
903+ "sha": "7e9424d91b06aca12d258959f68f7f7c7a2f12a8",
904+ "description": "loader/dri3: Don't churn through xfixes regions in SwapBuffers",
905+ "nominated": false,
906+ "nomination_type": null,
907+ "resolution": 4,
908+ "main_sha": null,
909+ "because_sha": null
910+ },
911+ {
912+ "sha": "34e4622983b70baf8e565502de1d63df71b066a7",
913+ "description": "loader/dri3: Properly initialize the XFIXES extension",
914+ "nominated": false,
915+ "nomination_type": null,
916+ "resolution": 4,
917+ "main_sha": null,
918+ "because_sha": null
919+ },
920+ {
921+ "sha": "888b7ba33822dafea1ec19bda6d9ea06c8c5adad",
922+ "description": "radeonsi: optimize set_inlinable_constants when they don't change",
923+ "nominated": false,
924+ "nomination_type": null,
925+ "resolution": 4,
926+ "main_sha": null,
927+ "because_sha": null
928+ },
929+ {
930+ "sha": "86355b5984da9ac54f3ab99ab8da879af4cfc262",
931+ "description": "ac/gpu_info: adjust the condition for use_late_alloc",
932+ "nominated": false,
933+ "nomination_type": null,
934+ "resolution": 4,
935+ "main_sha": null,
936+ "because_sha": null
937+ },
938+ {
939+ "sha": "ff42fd1fdfc6f8935f105d95acf92bc505483e4e",
940+ "description": "radeonsi: don't use NGG culling on 1 RB chips",
941+ "nominated": false,
942+ "nomination_type": null,
943+ "resolution": 4,
944+ "main_sha": null,
945+ "because_sha": null
946+ },
947+ {
948+ "sha": "f7afcc3d11d170a4820a1e5defc9f3e26b2c7f7d",
949+ "description": "radeonsi: remove incorrect comment about hangs in gfx10_ngg_gs_emit_epilogue",
950+ "nominated": false,
951+ "nomination_type": null,
952+ "resolution": 4,
953+ "main_sha": null,
954+ "because_sha": null
955+ },
956+ {
957+ "sha": "593f3b3a5a35426ea0d24c1a33ffa980429c68f2",
958+ "description": "radeonsi: if shader culling culls all vertices, cull the primitive exports too",
959+ "nominated": false,
960+ "nomination_type": null,
961+ "resolution": 4,
962+ "main_sha": null,
963+ "because_sha": null
964+ },
965+ {
966+ "sha": "defc7c92d90728ec66bea736a18bb8180ab60228",
967+ "description": "radeonsi: document why VBO descriptors in user SGPRs are beneficial",
968+ "nominated": false,
969+ "nomination_type": null,
970+ "resolution": 4,
971+ "main_sha": null,
972+ "because_sha": null
973+ },
974+ {
975+ "sha": "f99f7c06e71d6194d4206bde58a8acb5a42d90ed",
976+ "description": "lavapipe: implement multidraw ext",
977+ "nominated": false,
978+ "nomination_type": null,
979+ "resolution": 4,
980+ "main_sha": null,
981+ "because_sha": null
982+ },
983+ {
984+ "sha": "be0e34450b4202975792806c88a381cae597491f",
985+ "description": "zink: use depth/stencil-only layouts for depth/stencil-only formats",
986+ "nominated": false,
987+ "nomination_type": null,
988+ "resolution": 4,
989+ "main_sha": null,
990+ "because_sha": null
991+ },
992+ {
993+ "sha": "d22cdcd33a4ee2e47b07235f986273b9b69d5804",
994+ "description": "util: add work around for the game We Happy Few",
995+ "nominated": true,
996+ "nomination_type": 0,
997+ "resolution": 1,
998+ "main_sha": null,
999+ "because_sha": null
1000+ },
1001+ {
1002+ "sha": "a067f54f3e1606c916da57f61d692a859d4a58fb",
1003+ "description": "ci/i915g: Skip the piglit glx tests since we're not running X.",
1004+ "nominated": false,
1005+ "nomination_type": null,
1006+ "resolution": 4,
1007+ "main_sha": null,
1008+ "because_sha": null
1009+ },
1010+ {
1011+ "sha": "1ccb8ab8011da054c27962e18bc63aabf90c1375",
1012+ "description": "i915g: Finish out blend factor overrides for both RGBx and A8.",
1013+ "nominated": false,
1014+ "nomination_type": null,
1015+ "resolution": 4,
1016+ "main_sha": null,
1017+ "because_sha": null
1018+ },
1019+ {
1020+ "sha": "2683c7bf9ada52f92163cd6b27fb588ea80c47b4",
1021+ "description": "i915g: Fix bad naming of depth texture formats.",
1022+ "nominated": false,
1023+ "nomination_type": null,
1024+ "resolution": 4,
1025+ "main_sha": null,
1026+ "because_sha": null
1027+ },
1028+ {
1029+ "sha": "078030973bfe8164b529f77d2d68ebbe602e6a2a",
1030+ "description": "ir3/ra: Fix corner case in collect handling",
1031+ "nominated": false,
1032+ "nomination_type": 1,
1033+ "resolution": 4,
1034+ "main_sha": null,
1035+ "because_sha": "0ffcb19b9d9fbe902224542047c389a661fbf816"
1036+ },
1037+ {
1038+ "sha": "3dc8c5985858db451ca4a2465ccd2b85ffd8f90f",
1039+ "description": "ir3: Remove IR3_REG_DEST",
1040+ "nominated": false,
1041+ "nomination_type": null,
1042+ "resolution": 4,
1043+ "main_sha": null,
1044+ "because_sha": null
1045+ },
1046+ {
1047+ "sha": "def96adaee49bed7473cb21488c19f6ab60ed6d3",
1048+ "description": "ir3: Remove regs array",
1049+ "nominated": false,
1050+ "nomination_type": null,
1051+ "resolution": 4,
1052+ "main_sha": null,
1053+ "because_sha": null
1054+ },
1055+ {
1056+ "sha": "57aeef5c13538b78ad4fa88cfdc812442b64fb77",
1057+ "description": "ir3/frontend: Switch to srcs/dsts arrays",
1058+ "nominated": false,
1059+ "nomination_type": null,
1060+ "resolution": 4,
1061+ "main_sha": null,
1062+ "because_sha": null
1063+ },
1064+ {
1065+ "sha": "5785abb9ed305167f9eb617bd0880413a74cf08f",
1066+ "description": "ir3/opts: Switch to srcs/dsts arrays",
1067+ "nominated": false,
1068+ "nomination_type": null,
1069+ "resolution": 4,
1070+ "main_sha": null,
1071+ "because_sha": null
1072+ },
1073+ {
1074+ "sha": "58fb0a01e17bfbadbe1ebe1acd5b05e6f50a1e91",
1075+ "description": "ir3/validate: Switch to srcs/dsts arrays",
1076+ "nominated": false,
1077+ "nomination_type": null,
1078+ "resolution": 4,
1079+ "main_sha": null,
1080+ "because_sha": null
1081+ },
1082+ {
1083+ "sha": "050ec77d1bcd091b8f588d1e14f151398576b8fe",
1084+ "description": "ir3/print: Switch to srcs/dsts arrays",
1085+ "nominated": false,
1086+ "nomination_type": null,
1087+ "resolution": 4,
1088+ "main_sha": null,
1089+ "because_sha": null
1090+ },
1091+ {
1092+ "sha": "1b4990eea65c6d81aa486d88b36dd0641f349ad4",
1093+ "description": "ir3/legalize: Switch to srcs/dsts arrays",
1094+ "nominated": false,
1095+ "nomination_type": null,
1096+ "resolution": 4,
1097+ "main_sha": null,
1098+ "because_sha": null
1099+ },
1100+ {
1101+ "sha": "abebc1f53ffd1e8e57de06e4884b7178def2f7f7",
1102+ "description": "ir3/array_to_ssa: Switch to srcs/dsts arrays",
1103+ "nominated": false,
1104+ "nomination_type": null,
1105+ "resolution": 4,
1106+ "main_sha": null,
1107+ "because_sha": null
1108+ },
1109+ {
1110+ "sha": "dd13081e03545664c46de763e0fc4aef787a3c6b",
1111+ "description": "ir3/parser: Switch to srcs/dsts arrays",
1112+ "nominated": false,
1113+ "nomination_type": null,
1114+ "resolution": 4,
1115+ "main_sha": null,
1116+ "because_sha": null
1117+ },
1118+ {
1119+ "sha": "af48cfc06b69e1d322a533a8b467deebf6630484",
1120+ "description": "ir3/ra: Switch to srcs/dsts arrays",
1121+ "nominated": false,
1122+ "nomination_type": null,
1123+ "resolution": 4,
1124+ "main_sha": null,
1125+ "because_sha": null
1126+ },
1127+ {
1128+ "sha": "d3e08327cf85ef0b07c8e4920c168329cf66ec41",
1129+ "description": "ir3/core: Switch to srcs/dsts arrays",
1130+ "nominated": false,
1131+ "nomination_type": null,
1132+ "resolution": 4,
1133+ "main_sha": null,
1134+ "because_sha": null
1135+ },
1136+ {
1137+ "sha": "50994eeabff270a1aeccf7c104104d13a2018dfd",
1138+ "description": "ir3/sched: Convert to srcs/dsts arrays",
1139+ "nominated": false,
1140+ "nomination_type": null,
1141+ "resolution": 4,
1142+ "main_sha": null,
1143+ "because_sha": null
1144+ },
1145+ {
1146+ "sha": "132dfacdcbefdfa7094dee2ec36e6770edb1c8e9",
1147+ "description": "freedreno/tests: Convert to srcs/dsts",
1148+ "nominated": false,
1149+ "nomination_type": null,
1150+ "resolution": 4,
1151+ "main_sha": null,
1152+ "because_sha": null
1153+ },
1154+ {
1155+ "sha": "bff83fc42b2fbae6a9a96b1eab9936ce6bcb3a21",
1156+ "description": "freedreno/isa: Convert to srcs/dsts",
1157+ "nominated": false,
1158+ "nomination_type": null,
1159+ "resolution": 4,
1160+ "main_sha": null,
1161+ "because_sha": null
1162+ },
1163+ {
1164+ "sha": "db7814ad56468b7fd5ffb6e8469ade10ae64a4c6",
1165+ "description": "ir3: Add srcs/dsts arrays to ir3_instruction",
1166+ "nominated": false,
1167+ "nomination_type": null,
1168+ "resolution": 4,
1169+ "main_sha": null,
1170+ "because_sha": null
1171+ },
1172+ {
1173+ "sha": "59b9935877ee29a4ad7f83ac6f0753781530f08b",
1174+ "description": "ir3/legalize: Construct branch properly",
1175+ "nominated": false,
1176+ "nomination_type": null,
1177+ "resolution": 4,
1178+ "main_sha": null,
1179+ "because_sha": null
1180+ },
1181+ {
1182+ "sha": "e93f15d4bc346dd56bdf93d81513768872d8d1fb",
1183+ "description": "ir3: Add separate src/dst count in ir3_instr",
1184+ "nominated": false,
1185+ "nomination_type": null,
1186+ "resolution": 4,
1187+ "main_sha": null,
1188+ "because_sha": null
1189+ },
1190+ {
1191+ "sha": "3071e2e93395efeba14204564eac56ce38adfa37",
1192+ "description": "ir3: Split ir3_reg_create() into ir3_{src,dst}_create()",
1193+ "nominated": false,
1194+ "nomination_type": null,
1195+ "resolution": 4,
1196+ "main_sha": null,
1197+ "because_sha": null
1198+ },
1199+ {
1200+ "sha": "9af795d9b984055042ef4ed33c6d3f2021be778a",
1201+ "description": "ir3: Make ir3_instruction::address a normal register",
1202+ "nominated": false,
1203+ "nomination_type": null,
1204+ "resolution": 4,
1205+ "main_sha": null,
1206+ "because_sha": null
1207+ },
1208+ {
1209+ "sha": "2522f387a3d640b091b5ae2ca69a5e1d23edce99",
1210+ "description": "ir3: Add is_reg_special()",
1211+ "nominated": false,
1212+ "nomination_type": null,
1213+ "resolution": 4,
1214+ "main_sha": null,
1215+ "because_sha": null
1216+ },
1217+ {
1218+ "sha": "dce680737ddb200c59c55a8c696114f793757398",
1219+ "description": "ir3: Validate that ir3_register::instr is correct",
1220+ "nominated": false,
1221+ "nomination_type": null,
1222+ "resolution": 4,
1223+ "main_sha": null,
1224+ "because_sha": null
1225+ },
1226+ {
1227+ "sha": "ef7bc4a2aa6b0a0063a478499f74a85cf3ef1dd1",
1228+ "description": "ir3: Update ir3_register::instr when cloning instructions",
1229+ "nominated": false,
1230+ "nomination_type": null,
1231+ "resolution": 4,
1232+ "main_sha": null,
1233+ "because_sha": null
1234+ },
1235+ {
1236+ "sha": "0f329ba10ae64a6c58d7945d8b1b3f19959878e2",
1237+ "description": "ir3: Split read-modify-write array dests in two",
1238+ "nominated": false,
1239+ "nomination_type": null,
1240+ "resolution": 4,
1241+ "main_sha": null,
1242+ "because_sha": null
1243+ },
1244+ {
1245+ "sha": "cc649453364dd1ea3a8efff8f3bc4290ba80e34b",
1246+ "description": "ir3: Make tied sources/destinations part of the IR",
1247+ "nominated": false,
1248+ "nomination_type": null,
1249+ "resolution": 4,
1250+ "main_sha": null,
1251+ "because_sha": null
1252+ },
1253+ {
1254+ "sha": "f953dc2cedaa412ecf56ee804ac19d4dee3b47db",
1255+ "description": "amd/ci: add hawaii-specific skip and fail lists",
1256+ "nominated": false,
1257+ "nomination_type": null,
1258+ "resolution": 4,
1259+ "main_sha": null,
1260+ "because_sha": null
1261+ },
1262+ {
1263+ "sha": "08495a948e16ac4fe54e282b77e8265551606219",
1264+ "description": "pan/mdg: Add 16 bytes of padding to the end of shaders",
1265+ "nominated": true,
1266+ "nomination_type": 0,
1267+ "resolution": 1,
1268+ "main_sha": null,
1269+ "because_sha": null
1270+ },
1271+ {
1272+ "sha": "55951ac28e7a30c2fae762990962a4410669c989",
1273+ "description": "anv: fix emitting dynamic primitive topology",
1274+ "nominated": true,
1275+ "nomination_type": 1,
1276+ "resolution": 0,
1277+ "main_sha": null,
1278+ "because_sha": "f6fa4a8000053fc6e9a25a30f482c59466390898"
1279+ },
1280+ {
1281+ "sha": "43b99e48b13f462ff2325e35ba3df930ab0ee06c",
1282+ "description": "Revert \"ci: disable panfrost t760 jobs\"",
1283+ "nominated": false,
1284+ "nomination_type": 2,
1285+ "resolution": 4,
1286+ "main_sha": null,
1287+ "because_sha": "854d93f73d6064a13ddc13dddf74c8c760cda1d4"
1288+ },
1289+ {
1290+ "sha": "2d87ea3166596a07259c96d33f3e4880417117cd",
1291+ "description": "iris: take a reference to memobj bo in iris_resource_from_memobj",
1292+ "nominated": false,
1293+ "nomination_type": 1,
1294+ "resolution": 4,
1295+ "main_sha": null,
1296+ "because_sha": "772dc50d162f6ac99676ef5134607f0d0e6db21e"
1297+ },
1298+ {
1299+ "sha": "52547cfbd0dac490ddff6bd8e4f25539fb994d80",
1300+ "description": "radeonsi: disable ngg culling on llvm < 12",
1301+ "nominated": true,
1302+ "nomination_type": 0,
1303+ "resolution": 1,
1304+ "main_sha": null,
1305+ "because_sha": null
1306+ },
1307+ {
1308+ "sha": "9b7cba7724f5cc407a889a1feeccf7c9fb105f50",
1309+ "description": "anv: bound checks buffer memory binding in debug builds",
1310+ "nominated": false,
1311+ "nomination_type": null,
1312+ "resolution": 4,
1313+ "main_sha": null,
1314+ "because_sha": null
1315+ },
1316+ {
1317+ "sha": "4dc42843423aa6b0771f863c3359c44810424d63",
1318+ "description": "intel/fs: Implement Wa_14013745556 on TGL+.",
1319+ "nominated": false,
1320+ "nomination_type": null,
1321+ "resolution": 4,
1322+ "main_sha": null,
1323+ "because_sha": null
1324+ },
1325+ {
1326+ "sha": "c19cfa9dc22b805581ac5ed3ad835fed3c8506c2",
1327+ "description": "intel/fs: Fix synchronization of accumulator-clearing W/A move on TGL+.",
1328+ "nominated": true,
1329+ "nomination_type": 1,
1330+ "resolution": 1,
1331+ "main_sha": null,
1332+ "because_sha": "a27542c5ddec8dd6a64a9c236cf6bea1db1b9e48"
1333+ },
1334+ {
1335+ "sha": "63abc083ce5e03843d72465a76fdb93064bc3eb9",
1336+ "description": "intel/fs: Teach IR about EOT instruction writing the accumulator implicitly on TGL+.",
1337+ "nominated": true,
1338+ "nomination_type": 1,
1339+ "resolution": 1,
1340+ "main_sha": null,
1341+ "because_sha": "a27542c5ddec8dd6a64a9c236cf6bea1db1b9e48"
1342+ },
1343+ {
1344+ "sha": "5e7f443de05f7865654b280ffab298172b33b863",
1345+ "description": "intel/fs: Add SWSB dependency annotations for cross-pipeline WaR data hazards on XeHP+.",
1346+ "nominated": false,
1347+ "nomination_type": null,
1348+ "resolution": 4,
1349+ "main_sha": null,
1350+ "because_sha": null
1351+ },
1352+ {
1353+ "sha": "d46bb14d140079b78d9d1478d13ac5e0864fe403",
1354+ "description": "intel/fs: Implement Wa_22012725308 for cross-pipe accumulator data hazard.",
1355+ "nominated": false,
1356+ "nomination_type": null,
1357+ "resolution": 4,
1358+ "main_sha": null,
1359+ "because_sha": null
1360+ },
1361+ {
1362+ "sha": "385da1fe36ca231fc0ad3634b1aa3be4ef679959",
1363+ "description": "intel/fs: Track single accumulator in scoreboard lowering pass.",
1364+ "nominated": false,
1365+ "nomination_type": null,
1366+ "resolution": 4,
1367+ "main_sha": null,
1368+ "because_sha": null
1369+ },
1370+ {
1371+ "sha": "231337a13af03f5579f5401cff16aa96ec796746",
1372+ "description": "intel/fs/xehp: Assert that the compiler is sending all 3 coords for cubemaps.",
1373+ "nominated": false,
1374+ "nomination_type": null,
1375+ "resolution": 4,
1376+ "main_sha": null,
1377+ "because_sha": null
1378+ },
1379+ {
1380+ "sha": "85315f5fb1b17b7e289c22da317bc3f37666d043",
1381+ "description": "freedreno/ci: Use TU_IGNORE_CONFORMANCE_WARNING to reduce warnings",
1382+ "nominated": false,
1383+ "nomination_type": null,
1384+ "resolution": 4,
1385+ "main_sha": null,
1386+ "because_sha": null
1387+ },
1388+ {
1389+ "sha": "205d6e582c08285fd1cd55cead8f8fd2becbb211",
1390+ "description": "tu: Provide a toggle to avoid warnings about unsupported devices",
1391+ "nominated": false,
1392+ "nomination_type": null,
1393+ "resolution": 4,
1394+ "main_sha": null,
1395+ "because_sha": null
1396+ },
1397+ {
1398+ "sha": "17a1cc616371d5239498386fa6850df536ad1fe4",
1399+ "description": "meson/crocus: add prefer-crocus option.",
1400+ "nominated": false,
1401+ "nomination_type": null,
1402+ "resolution": 4,
1403+ "main_sha": null,
1404+ "because_sha": null
1405+ },
1406+ {
1407+ "sha": "ec7e26234901359a694b54f72e7ac78f00b6ab60",
1408+ "description": "mesa: unreference zombie buffers when creating buffers to lower memory usage",
1409+ "nominated": true,
1410+ "nomination_type": 1,
1411+ "resolution": 1,
1412+ "main_sha": null,
1413+ "because_sha": "e014e3b6be638f4192d6eddd3d1033fd571f3a76"
1414+ },
1415+ {
1416+ "sha": "29d272f144ba800933af656717ed57adaa5e6510",
1417+ "description": "crocus: fix batch state bo leak",
1418+ "nominated": false,
1419+ "nomination_type": null,
1420+ "resolution": 4,
1421+ "main_sha": null,
1422+ "because_sha": null
1423+ },
1424+ {
1425+ "sha": "9027aae546d0674aee704b24bf4e78271c25cc06",
1426+ "description": "crocus: fix vertex buffer leak on screen end.",
1427+ "nominated": false,
1428+ "nomination_type": null,
1429+ "resolution": 4,
1430+ "main_sha": null,
1431+ "because_sha": null
1432+ },
1433+ {
1434+ "sha": "6036121a559473bea48729002d94822791c888a1",
1435+ "description": "crocus: free context state properly.",
1436+ "nominated": false,
1437+ "nomination_type": null,
1438+ "resolution": 4,
1439+ "main_sha": null,
1440+ "because_sha": null
1441+ },
1442+ {
1443+ "sha": "c9bc5e3a86d9f8468b9fec3d4736d8e0d7880f52",
1444+ "description": "zink: ci updates",
1445+ "nominated": false,
1446+ "nomination_type": null,
1447+ "resolution": 4,
1448+ "main_sha": null,
1449+ "because_sha": null
1450+ },
1451+ {
1452+ "sha": "a7847130804d47ba1f54da76dcdf8cff3a3ee706",
1453+ "description": "zink: remove primconvert",
1454+ "nominated": false,
1455+ "nomination_type": null,
1456+ "resolution": 4,
1457+ "main_sha": null,
1458+ "because_sha": null
1459+ },
1460+ {
1461+ "sha": "c032c9e32d55bb4a413876c71f537b5bdd655487",
1462+ "description": "zink: export supported primitive restart types",
1463+ "nominated": false,
1464+ "nomination_type": null,
1465+ "resolution": 4,
1466+ "main_sha": null,
1467+ "because_sha": null
1468+ },
1469+ {
1470+ "sha": "2953d709942031db91edeaa8940c63cc5517bd65",
1471+ "description": "zink: export supported prim types",
1472+ "nominated": false,
1473+ "nomination_type": null,
1474+ "resolution": 4,
1475+ "main_sha": null,
1476+ "because_sha": null
1477+ },
1478+ {
1479+ "sha": "8ac4be916ef731b830822f85879e4527fc7b5056",
1480+ "description": "zink: export 8bit index buffer support based on extension presence",
1481+ "nominated": false,
1482+ "nomination_type": null,
1483+ "resolution": 4,
1484+ "main_sha": null,
1485+ "because_sha": null
1486+ },
1487+ {
1488+ "sha": "09c28a35a5a392587b32d4ffaf1bcc8980c7ff07",
1489+ "description": "zink: export PIPE_CAP_EMULATE_NONFIXED_PRIMITIVE_RESTART",
1490+ "nominated": false,
1491+ "nomination_type": null,
1492+ "resolution": 4,
1493+ "main_sha": null,
1494+ "because_sha": null
1495+ },
1496+ {
1497+ "sha": "3fc651110c8c45d72e2cfabb80f61c68503106e2",
1498+ "description": "gallium: add a pipe cap for determining driver support for prim type in restarts",
1499+ "nominated": false,
1500+ "nomination_type": null,
1501+ "resolution": 4,
1502+ "main_sha": null,
1503+ "because_sha": null
1504+ },
1505+ {
1506+ "sha": "f8ff6eb78b749fa3f0e8492232193d8843187dfe",
1507+ "description": "gallium: add a pipe cap for performing automatic prim type conversion",
1508+ "nominated": false,
1509+ "nomination_type": null,
1510+ "resolution": 4,
1511+ "main_sha": null,
1512+ "because_sha": null
1513+ },
1514+ {
1515+ "sha": "c8e674d4e391a517103b0da6480f1fe0a7c36a11",
1516+ "description": "gallium: handle automatic 8bit -> 16bit index buffer rewrites",
1517+ "nominated": false,
1518+ "nomination_type": null,
1519+ "resolution": 4,
1520+ "main_sha": null,
1521+ "because_sha": null
1522+ },
1523+ {
1524+ "sha": "c9a65e5f77ef7c4ff72591ef1a8a57678eb8dda4",
1525+ "description": "gallium: add a pipe cap to rewrite index buffers for draws using a non-fixed restart index",
1526+ "nominated": false,
1527+ "nomination_type": null,
1528+ "resolution": 4,
1529+ "main_sha": null,
1530+ "because_sha": null
1531+ },
1532+ {
1533+ "sha": "99a60ed3786a3224e7ca0930d2c19d5f2fd3727b",
1534+ "description": "util/primconvert: handle multidraws in primconvert",
1535+ "nominated": false,
1536+ "nomination_type": null,
1537+ "resolution": 4,
1538+ "main_sha": null,
1539+ "because_sha": null
1540+ },
1541+ {
1542+ "sha": "583070748cb103560b173b5789998302d517b587",
1543+ "description": "util/primconvert: handle rewriting of prim-restart draws with unsupported primtype",
1544+ "nominated": false,
1545+ "nomination_type": null,
1546+ "resolution": 4,
1547+ "main_sha": null,
1548+ "because_sha": null
1549+ },
1550+ {
1551+ "sha": "f3fe70f10e5000e704ca010555140ef82a5af281",
1552+ "description": "util/primconvert: map index buffer before getting index translator function",
1553+ "nominated": false,
1554+ "nomination_type": null,
1555+ "resolution": 4,
1556+ "main_sha": null,
1557+ "because_sha": null
1558+ },
1559+ {
1560+ "sha": "26e718fb37a99adf13ae503155de6a144a323ec1",
1561+ "description": "util/primconvert: handle indirect draws",
1562+ "nominated": false,
1563+ "nomination_type": null,
1564+ "resolution": 4,
1565+ "main_sha": null,
1566+ "because_sha": null
1567+ },
1568+ {
1569+ "sha": "4673febf919014cb72266b7d978ef6bc6e3aba82",
1570+ "description": "util/prim_restart: break out draw rewriting into separate function",
1571+ "nominated": false,
1572+ "nomination_type": null,
1573+ "resolution": 4,
1574+ "main_sha": null,
1575+ "because_sha": null
1576+ },
1577+ {
1578+ "sha": "3eb99323172902d34c80782aaa2d110567749cd9",
1579+ "description": "aux/draw: add a util function for reading back indirect draw params",
1580+ "nominated": false,
1581+ "nomination_type": null,
1582+ "resolution": 4,
1583+ "main_sha": null,
1584+ "because_sha": null
1585+ },
1586+ {
1587+ "sha": "854d93f73d6064a13ddc13dddf74c8c760cda1d4",
1588+ "description": "ci: disable panfrost t760 jobs",
1589+ "nominated": false,
1590+ "nomination_type": null,
1591+ "resolution": 4,
1592+ "main_sha": null,
1593+ "because_sha": null
1594+ },
1595+ {
1596+ "sha": "fd09727a7d93c4669aa0adfced63fcd4972984bb",
1597+ "description": "crocus: Explicitly cast value to uint64_t",
1598+ "nominated": false,
1599+ "nomination_type": null,
1600+ "resolution": 4,
1601+ "main_sha": null,
1602+ "because_sha": null
1603+ },
1604+ {
1605+ "sha": "17f0d7ef83d753f26957359b471d2471f52a4523",
1606+ "description": "amd/addrlib: remove Meson debug message()",
1607+ "nominated": true,
1608+ "nomination_type": 1,
1609+ "resolution": 1,
1610+ "main_sha": null,
1611+ "because_sha": "d0767fc045a1210f9fff464b96dd68cf36fe57f9"
1612+ },
1613+ {
1614+ "sha": "d977e7fbe107898480506fdd7bca9b177718587a",
1615+ "description": "radeon/vcn/enc: Add missing line to HEVC SPS header code",
1616+ "nominated": true,
1617+ "nomination_type": 1,
1618+ "resolution": 1,
1619+ "main_sha": null,
1620+ "because_sha": "e62c7e7c6caa6c9531afb694e7952a7fc3ac4401"
1621+ },
1622+ {
1623+ "sha": "d3fddf63ec9e3a70f3d8c5a98794d70a234417f7",
1624+ "description": "ac/llvm: don't set skip-uniform-regions to fix atomic.cmpswap",
1625+ "nominated": true,
1626+ "nomination_type": 1,
1627+ "resolution": 0,
1628+ "main_sha": null,
1629+ "because_sha": "3bb65c06706a58b124e4a600eeb35a7b3c5c3a23"
1630+ },
1631+ {
1632+ "sha": "bdd8646306b0dad87747425812039e24da808b62",
1633+ "description": "util: add force_gl_names_reuse for SWKOTOR.",
1634+ "nominated": false,
1635+ "nomination_type": null,
1636+ "resolution": 4,
1637+ "main_sha": null,
1638+ "because_sha": null
1639+ },
1640+ {
1641+ "sha": "a9e3ddfc63209a1b401e9de4a9de791789040f71",
1642+ "description": "i915g: Fix GL_ARB_copy_buffer assertion fails.",
1643+ "nominated": false,
1644+ "nomination_type": null,
1645+ "resolution": 4,
1646+ "main_sha": null,
1647+ "because_sha": null
1648+ },
1649+ {
1650+ "sha": "7ed0aaced7604b9ac3f5a3b5c24b2cc9509a7385",
1651+ "description": "nir: use a more fitting index for btd_stack_push_intel",
1652+ "nominated": false,
1653+ "nomination_type": null,
1654+ "resolution": 4,
1655+ "main_sha": null,
1656+ "because_sha": null
1657+ },
1658+ {
1659+ "sha": "423c47de991643269a7c76ea37efe59b237fa6e7",
1660+ "description": "nir: drop the btd_resume_intel intrinsic",
1661+ "nominated": false,
1662+ "nomination_type": null,
1663+ "resolution": 4,
1664+ "main_sha": null,
1665+ "because_sha": null
1666+ },
1667+ {
1668+ "sha": "4d9fcf2799e57fccb168027a1bb8c245236eca98",
1669+ "description": "intel/rt: switch to common pass for shader calls lowering",
1670+ "nominated": false,
1671+ "nomination_type": null,
1672+ "resolution": 4,
1673+ "main_sha": null,
1674+ "because_sha": null
1675+ },
1676+ {
1677+ "sha": "1dacea10f35983833dabcad220317fe6e61db31b",
1678+ "description": "anv: implement caching for ray tracing pipelines",
1679+ "nominated": false,
1680+ "nomination_type": null,
1681+ "resolution": 4,
1682+ "main_sha": null,
1683+ "because_sha": null
1684+ },
1685+ {
1686+ "sha": "fed7ac932f38ba3daebc4f2c937cb12d8c34b14d",
1687+ "description": "anv: move trivial return shader to device",
1688+ "nominated": false,
1689+ "nomination_type": null,
1690+ "resolution": 4,
1691+ "main_sha": null,
1692+ "because_sha": null
1693+ },
1694+ {
1695+ "sha": "7c852f78c41f608aaa940f17b81deb6191937777",
1696+ "description": "anv: store more RT shader data in pipeline_stage object",
1697+ "nominated": false,
1698+ "nomination_type": null,
1699+ "resolution": 4,
1700+ "main_sha": null,
1701+ "because_sha": null
1702+ },
1703+ {
1704+ "sha": "045f4600b1cd3096ecd12cda9c28de09b7919679",
1705+ "description": "anv: cache raytracing trampoline shader",
1706+ "nominated": false,
1707+ "nomination_type": null,
1708+ "resolution": 4,
1709+ "main_sha": null,
1710+ "because_sha": null
1711+ },
1712+ {
1713+ "sha": "ab77aeb48884b611f76c9be78a610a529c01221a",
1714+ "description": "blorp: add blorp string in shader keys",
1715+ "nominated": false,
1716+ "nomination_type": null,
1717+ "resolution": 4,
1718+ "main_sha": null,
1719+ "because_sha": null
1720+ },
1721+ {
1722+ "sha": "7479fe6ae0935fb8f9e3c64c16c7e6855481d1da",
1723+ "description": "anv: Implement vkCmdTraceRays and vkCmdTraceRaysIndirect",
1724+ "nominated": false,
1725+ "nomination_type": null,
1726+ "resolution": 4,
1727+ "main_sha": null,
1728+ "because_sha": null
1729+ },
1730+ {
1731+ "sha": "ac6d7a1758cbee91caf6812333bb3416d22ad7e4",
1732+ "description": "anv: Make anv_address::offset 64-bit",
1733+ "nominated": false,
1734+ "nomination_type": null,
1735+ "resolution": 4,
1736+ "main_sha": null,
1737+ "because_sha": null
1738+ },
1739+ {
1740+ "sha": "a67d7c9dee1a74c8aa861b0b848c455686d9a09b",
1741+ "description": "anv: Allow _anv_combine_address with a NULL batch",
1742+ "nominated": false,
1743+ "nomination_type": null,
1744+ "resolution": 4,
1745+ "main_sha": null,
1746+ "because_sha": null
1747+ },
1748+ {
1749+ "sha": "f68d64dac01505560a53aabe2b8616685cace0c2",
1750+ "description": "anv: Add support for vkCmdSetRayTracingPipelineStackSizeKHR",
1751+ "nominated": false,
1752+ "nomination_type": null,
1753+ "resolution": 4,
1754+ "main_sha": null,
1755+ "because_sha": null
1756+ },
1757+ {
1758+ "sha": "02f7964a134dffe2b904d0c3dec2e058d201cdc5",
1759+ "description": "anv: Compute scratch sizes for ray-tracing pipelines and shader groups",
1760+ "nominated": false,
1761+ "nomination_type": null,
1762+ "resolution": 4,
1763+ "main_sha": null,
1764+ "because_sha": null
1765+ },
1766+ {
1767+ "sha": "c3ac9afca3890be4aed7ebcdd0e3499556964da2",
1768+ "description": "anv: Create and return ray-tracing pipeline SBT handles",
1769+ "nominated": false,
1770+ "nomination_type": null,
1771+ "resolution": 4,
1772+ "main_sha": null,
1773+ "because_sha": null
1774+ },
1775+ {
1776+ "sha": "b66d3e627a81c6b89171972c32ba2bf61665b7c5",
1777+ "description": "intel/fs: Don't pull CS push constants if uses_inline_data",
1778+ "nominated": false,
1779+ "nomination_type": null,
1780+ "resolution": 4,
1781+ "main_sha": null,
1782+ "because_sha": null
1783+ },
1784+ {
1785+ "sha": "79dc25d8679ac6ab03c43ea51255ef046883d39f",
1786+ "description": "anv: Compile trivial return and trampoline shaders",
1787+ "nominated": false,
1788+ "nomination_type": null,
1789+ "resolution": 4,
1790+ "main_sha": null,
1791+ "because_sha": null
1792+ },
1793+ {
1794+ "sha": "e10455585115d502702a3f642dfd386d0c7a0c69",
1795+ "description": "anv: Compile ray-tracing shaders",
1796+ "nominated": false,
1797+ "nomination_type": null,
1798+ "resolution": 4,
1799+ "main_sha": null,
1800+ "because_sha": null
1801+ },
1802+ {
1803+ "sha": "379b9bb7b04dc87797e49933bbfac786b7ef38fb",
1804+ "description": "anv: Support fetching descriptor addresses from push constants",
1805+ "nominated": false,
1806+ "nomination_type": null,
1807+ "resolution": 4,
1808+ "main_sha": null,
1809+ "because_sha": null
1810+ },
1811+ {
1812+ "sha": "937ffb1af0201fbb11c939ca67f7c5b6a31035fa",
1813+ "description": "nir/apply_pipeline_layout: Handle bindless shaders",
1814+ "nominated": false,
1815+ "nomination_type": null,
1816+ "resolution": 4,
1817+ "main_sha": null,
1818+ "because_sha": null
1819+ },
1820+ {
1821+ "sha": "770d3312857a2ce2130dd949f3149d14068eb760",
1822+ "description": "anv: Disallow UBO pushing for bindless shaders",
1823+ "nominated": false,
1824+ "nomination_type": null,
1825+ "resolution": 4,
1826+ "main_sha": null,
1827+ "because_sha": null
1828+ },
1829+ {
1830+ "sha": "c92fd3584835b48fe745ef3c10ac1d71c5c6c6ae",
1831+ "description": "intel/rt: Use reloc constants for the resume SBT",
1832+ "nominated": false,
1833+ "nomination_type": null,
1834+ "resolution": 4,
1835+ "main_sha": null,
1836+ "because_sha": null
1837+ },
1838+ {
1839+ "sha": "705395344d2541d038326a6f64fbff838b52a71e",
1840+ "description": "intel/fs: Add support for compiling bindless shaders with resume shaders",
1841+ "nominated": false,
1842+ "nomination_type": null,
1843+ "resolution": 4,
1844+ "main_sha": null,
1845+ "because_sha": null
1846+ },
1847+ {
1848+ "sha": "d055ac9bdf6a07f14b405d2ed1d6400e9b7c638f",
1849+ "description": "intel/compiler: Add a U32 reloc type",
1850+ "nominated": false,
1851+ "nomination_type": null,
1852+ "resolution": 4,
1853+ "main_sha": null,
1854+ "because_sha": null
1855+ },
1856+ {
1857+ "sha": "55508bbe66cdae22cc8ae74f27829fba13f393c7",
1858+ "description": "intel/compiler: Generalize shader relocations a bit",
1859+ "nominated": false,
1860+ "nomination_type": null,
1861+ "resolution": 4,
1862+ "main_sha": null,
1863+ "because_sha": null
1864+ },
1865+ {
1866+ "sha": "f7668d6fe5aed6706e7ee1c42d4053ed2c61adfb",
1867+ "description": "anv,iris: Move the SHADER_RELOC enums to brw_compiler.h",
1868+ "nominated": false,
1869+ "nomination_type": null,
1870+ "resolution": 4,
1871+ "main_sha": null,
1872+ "because_sha": null
1873+ },
1874+ {
1875+ "sha": "d95d5b146511447294f3d593d6701b6ab389e711",
1876+ "description": "anv: Add support for binding ray-tracing pipelines",
1877+ "nominated": false,
1878+ "nomination_type": null,
1879+ "resolution": 4,
1880+ "main_sha": null,
1881+ "because_sha": null
1882+ },
1883+ {
1884+ "sha": "8cc5080580b2c858097184dd662441bd61ebde0c",
1885+ "description": "anv: Add a ray-tracing pipeline object",
1886+ "nominated": false,
1887+ "nomination_type": null,
1888+ "resolution": 4,
1889+ "main_sha": null,
1890+ "because_sha": null
1891+ },
1892+ {
1893+ "sha": "dc05daf0e51b1e9fd99b9624d657cdca98d1d02e",
1894+ "description": "anv: Get ready for more pipeline stages",
1895+ "nominated": false,
1896+ "nomination_type": null,
1897+ "resolution": 4,
1898+ "main_sha": null,
1899+ "because_sha": null
1900+ },
1901+ {
1902+ "sha": "f366f6a07163d757dcd881dfe353951bbfd25710",
1903+ "description": "anv: Add minimal boilerplate for VK_KHR_ray_tracing_pipeline",
1904+ "nominated": false,
1905+ "nomination_type": null,
1906+ "resolution": 4,
1907+ "main_sha": null,
1908+ "because_sha": null
1909+ },
1910+ {
1911+ "sha": "d258b0bf0e072438fc9eb921c5335734e6794459",
1912+ "description": "anv: Add support for binding acceleration structures",
1913+ "nominated": false,
1914+ "nomination_type": null,
1915+ "resolution": 4,
1916+ "main_sha": null,
1917+ "because_sha": null
1918+ },
1919+ {
1920+ "sha": "4664c9247833924d5f4a38342fc11c3e6e251fc4",
1921+ "description": "anv: Add stub support for acceleration structures",
1922+ "nominated": false,
1923+ "nomination_type": null,
1924+ "resolution": 4,
1925+ "main_sha": null,
1926+ "because_sha": null
1927+ },
1928+ {
1929+ "sha": "e97002ebcf983ee6a8586a1564b41588a7109a6a",
1930+ "description": "anv: Add minimal boilerplate for VK_KHR_acceleration_structure",
1931+ "nominated": false,
1932+ "nomination_type": null,
1933+ "resolution": 4,
1934+ "main_sha": null,
1935+ "because_sha": null
1936+ },
1937+ {
1938+ "sha": "72437f6d540d77e7bcfcfd46938accd996684b51",
1939+ "description": "spirv: Create acceleration structure and shader record variables",
1940+ "nominated": true,
1941+ "nomination_type": 1,
1942+ "resolution": 1,
1943+ "main_sha": null,
1944+ "because_sha": "10b3eecd361af465e0e207fb18553ae37b924c45"
1945+ },
1946+ {
1947+ "sha": "5cecf826d3b4ed4282a6979e0c00713d0a5f8909",
1948+ "description": "zink: don't clear batch resources on fence finish",
1949+ "nominated": false,
1950+ "nomination_type": null,
1951+ "resolution": 4,
1952+ "main_sha": null,
1953+ "because_sha": null
1954+ },
1955+ {
1956+ "sha": "b315aa43f1c2d2f17bdd6a78cf402daae060d31c",
1957+ "description": "zink: move some end-of-batch stuff to submit thread",
1958+ "nominated": false,
1959+ "nomination_type": null,
1960+ "resolution": 4,
1961+ "main_sha": null,
1962+ "because_sha": null
1963+ },
1964+ {
1965+ "sha": "d8dc03c2131701a9e803dba43a040bbc0b980fc3",
1966+ "description": "zink: flag scanout updates to batch state, not resource",
1967+ "nominated": false,
1968+ "nomination_type": null,
1969+ "resolution": 4,
1970+ "main_sha": null,
1971+ "because_sha": null
1972+ },
1973+ {
1974+ "sha": "c1d06c402aa21745740933de79dddbdbdd38486a",
1975+ "description": "zink: move fence reset to submit thread",
1976+ "nominated": false,
1977+ "nomination_type": null,
1978+ "resolution": 4,
1979+ "main_sha": null,
1980+ "because_sha": null
1981+ },
1982+ {
1983+ "sha": "97f82493367004c6c73747000b331f8140095bfe",
1984+ "description": "zink: move sparse buffer commit to screen queue",
1985+ "nominated": false,
1986+ "nomination_type": null,
1987+ "resolution": 4,
1988+ "main_sha": null,
1989+ "because_sha": null
1990+ },
1991+ {
1992+ "sha": "478f129ee720229a2a3f5093a9f579c97951118b",
1993+ "description": "zink: move queue submit thread to screen",
1994+ "nominated": false,
1995+ "nomination_type": null,
1996+ "resolution": 4,
1997+ "main_sha": null,
1998+ "because_sha": null
1999+ },
2000+ {
2001+ "sha": "d4159963e3d3bb7f40cd506515e1ec189800abbf",
2002+ "description": "zink: enforce multi-context waiting for unflushed resources on foreign batches",
2003+ "nominated": false,
2004+ "nomination_type": null,
2005+ "resolution": 4,
2006+ "main_sha": null,
2007+ "because_sha": null
2008+ },
2009+ {
2010+ "sha": "ef418cfc5913dbd0830bb2b42d6d27d8ce4a0639",
2011+ "description": "zink: make init_mem_range() a public function",
2012+ "nominated": false,
2013+ "nomination_type": null,
2014+ "resolution": 4,
2015+ "main_sha": null,
2016+ "because_sha": null
2017+ },
2018+ {
2019+ "sha": "18c22f502439ff3d3be6738ca86a0ffc19961670",
2020+ "description": "zink: break out offset alignment calculation into helper",
2021+ "nominated": false,
2022+ "nomination_type": null,
2023+ "resolution": 4,
2024+ "main_sha": null,
2025+ "because_sha": null
2026+ },
2027+ {
2028+ "sha": "d574b0a51e8af26037a3df21981d4535b4d6117c",
2029+ "description": "zink: apply zink_resource_object::offset for memory flush/invalidates",
2030+ "nominated": false,
2031+ "nomination_type": null,
2032+ "resolution": 4,
2033+ "main_sha": null,
2034+ "because_sha": null
2035+ },
2036+ {
2037+ "sha": "d80d9e1c9354135f3b4a5788e94ba2a09aeec2fe",
2038+ "description": "zink: queue v3.0",
2039+ "nominated": false,
2040+ "nomination_type": null,
2041+ "resolution": 4,
2042+ "main_sha": null,
2043+ "because_sha": null
2044+ },
2045+ {
2046+ "sha": "28496f6ff21584766012a696b885dd4a1b4da73f",
2047+ "description": "zink: remove no-longer-used resource helper functions",
2048+ "nominated": false,
2049+ "nomination_type": null,
2050+ "resolution": 4,
2051+ "main_sha": null,
2052+ "because_sha": null
2053+ },
2054+ {
2055+ "sha": "59ec1794f63ebc977e5d8006825c8f284746f023",
2056+ "description": "zink: use batch usage api for resource helper function",
2057+ "nominated": false,
2058+ "nomination_type": null,
2059+ "resolution": 4,
2060+ "main_sha": null,
2061+ "because_sha": null
2062+ },
2063+ {
2064+ "sha": "1226628eb652171943cee3e79b61a0bdf1b9c2d1",
2065+ "description": "zink: add and use fencing functions which take batch usage structs",
2066+ "nominated": false,
2067+ "nomination_type": null,
2068+ "resolution": 4,
2069+ "main_sha": null,
2070+ "because_sha": null
2071+ },
2072+ {
2073+ "sha": "982a2dfbd4a45cfed50e4f7f77702eb27b4f866f",
2074+ "description": "zink: improve tc fence disambiguation",
2075+ "nominated": false,
2076+ "nomination_type": null,
2077+ "resolution": 4,
2078+ "main_sha": null,
2079+ "because_sha": null
2080+ },
2081+ {
2082+ "sha": "618784732a227e5aa4970b303b1e34541c5f400a",
2083+ "description": "zink: only update last_finished during batch reset if the batch was used",
2084+ "nominated": false,
2085+ "nomination_type": null,
2086+ "resolution": 4,
2087+ "main_sha": null,
2088+ "because_sha": null
2089+ },
2090+ {
2091+ "sha": "56c7e69c4d9dca0e4e0f4c56dcfe97e8b8b4aa5e",
2092+ "description": "freedreno: Fix leak of the screen hash table.",
2093+ "nominated": false,
2094+ "nomination_type": null,
2095+ "resolution": 4,
2096+ "main_sha": null,
2097+ "because_sha": null
2098+ },
2099+ {
2100+ "sha": "b76f2299544c73c831edf4b1e212427a41ccdd23",
2101+ "description": "crocus/bufmgr: fix userptr left over fail",
2102+ "nominated": false,
2103+ "nomination_type": null,
2104+ "resolution": 4,
2105+ "main_sha": null,
2106+ "because_sha": null
2107+ },
2108+ {
2109+ "sha": "45c12da2119a4808afde9f9b1c7bbd40ca58cefa",
2110+ "description": "croucs: limit stencil swizzle change to older generations",
2111+ "nominated": false,
2112+ "nomination_type": null,
2113+ "resolution": 4,
2114+ "main_sha": null,
2115+ "because_sha": null
2116+ },
2117+ {
2118+ "sha": "7eb3728e4b50fba5cbfc6e5bd1b8cffb807ba50b",
2119+ "description": "zink: clear textures directly when possible",
2120+ "nominated": false,
2121+ "nomination_type": null,
2122+ "resolution": 4,
2123+ "main_sha": null,
2124+ "because_sha": null
2125+ },
2126+ {
2127+ "sha": "a0608b3efcf82944a951a2bdc816f062dcdba64c",
2128+ "description": "crocus/gen8: add support for cherryview (env var for bdw)",
2129+ "nominated": false,
2130+ "nomination_type": null,
2131+ "resolution": 4,
2132+ "main_sha": null,
2133+ "because_sha": null
2134+ },
2135+ {
2136+ "sha": "c63030419692b433570a08d33a86e36adc16bc3a",
2137+ "description": "crocus/gen8: hookup gen8 state generators",
2138+ "nominated": false,
2139+ "nomination_type": null,
2140+ "resolution": 4,
2141+ "main_sha": null,
2142+ "because_sha": null
2143+ },
2144+ {
2145+ "sha": "edf05076a45eb8d30c8481e58dd0cea518b3b10b",
2146+ "description": "crocus/gen8: handle sampler differences",
2147+ "nominated": false,
2148+ "nomination_type": null,
2149+ "resolution": 4,
2150+ "main_sha": null,
2151+ "because_sha": null
2152+ },
2153+ {
2154+ "sha": "661f108d808e5378eba779d4af758d6f4228fb6c",
2155+ "description": "croucs/gen8: handle gfx8 surface aux addr reloc.",
2156+ "nominated": false,
2157+ "nomination_type": null,
2158+ "resolution": 4,
2159+ "main_sha": null,
2160+ "because_sha": null
2161+ },
2162+ {
2163+ "sha": "12e4da8053f6dee84774053eec4242762de3eeec",
2164+ "description": "crocus/gen8: port over VFE/compute state changes",
2165+ "nominated": false,
2166+ "nomination_type": null,
2167+ "resolution": 4,
2168+ "main_sha": null,
2169+ "because_sha": null
2170+ },
2171+ {
2172+ "sha": "612c30bff7db91645b12246bd1f12ae46c6a040c",
2173+ "description": "crocus/gen8: port over ps/wm state changes from iris.",
2174+ "nominated": false,
2175+ "nomination_type": null,
2176+ "resolution": 4,
2177+ "main_sha": null,
2178+ "because_sha": null
2179+ },
2180+ {
2181+ "sha": "5888b718472274da042bb7916b550ee227a4f019",
2182+ "description": "crocus/gen8: port over vs/gs/ds state changes.",
2183+ "nominated": false,
2184+ "nomination_type": null,
2185+ "resolution": 4,
2186+ "main_sha": null,
2187+ "because_sha": null
2188+ },
2189+ {
2190+ "sha": "457f21aa91c27b04b921dd2d49c3db4365ac68cc",
2191+ "description": "crocus/gen8: add depth stencil state support",
2192+ "nominated": false,
2193+ "nomination_type": null,
2194+ "resolution": 4,
2195+ "main_sha": null,
2196+ "because_sha": null
2197+ },
2198+ {
2199+ "sha": "524eae8b7876e7684b1d63c07cde4a941c015fba",
2200+ "description": "crocus/gen8: add viewport support",
2201+ "nominated": false,
2202+ "nomination_type": null,
2203+ "resolution": 4,
2204+ "main_sha": null,
2205+ "because_sha": null
2206+ },
2207+ {
2208+ "sha": "d12a9eda72409168ddafedee46e602f3499ffb84",
2209+ "description": "crocus/gen8: add rasterizer state changes.",
2210+ "nominated": false,
2211+ "nomination_type": null,
2212+ "resolution": 4,
2213+ "main_sha": null,
2214+ "because_sha": null
2215+ },
2216+ {
2217+ "sha": "6613c0ac374d379924add8df8ae4c627cbc3159e",
2218+ "description": "crocus/gen8: refactor blend state for gen8",
2219+ "nominated": false,
2220+ "nomination_type": null,
2221+ "resolution": 4,
2222+ "main_sha": null,
2223+ "because_sha": null
2224+ },
2225+ {
2226+ "sha": "4025c9d34096687de9c59b549fde4117e35256b0",
2227+ "description": "crocus/gen8: add PS blend command support.",
2228+ "nominated": false,
2229+ "nomination_type": null,
2230+ "resolution": 4,
2231+ "main_sha": null,
2232+ "because_sha": null
2233+ },
2234+ {
2235+ "sha": "22b9063aeecdc4dbefa6a9931aa84aa098c8fb08",
2236+ "description": "crocus/gen8: add VF SGVS support.",
2237+ "nominated": false,
2238+ "nomination_type": null,
2239+ "resolution": 4,
2240+ "main_sha": null,
2241+ "because_sha": null
2242+ },
2243+ {
2244+ "sha": "5b32fccd3f1635bef04b1621caa32a1f59e75041",
2245+ "description": "crocus/gen8: add SBE swiz support",
2246+ "nominated": false,
2247+ "nomination_type": null,
2248+ "resolution": 4,
2249+ "main_sha": null,
2250+ "because_sha": null
2251+ },
2252+ {
2253+ "sha": "88bba6a49eb50cb2f312bc0a38edc524ccd6c385",
2254+ "description": "crocus/gen8: add streamout support",
2255+ "nominated": false,
2256+ "nomination_type": null,
2257+ "resolution": 4,
2258+ "main_sha": null,
2259+ "because_sha": null
2260+ },
2261+ {
2262+ "sha": "750e0c1ff3ce467ef7107cbc8b338a8afcdcad92",
2263+ "description": "crocus/gen8: add PMA fix from iris",
2264+ "nominated": false,
2265+ "nomination_type": null,
2266+ "resolution": 4,
2267+ "main_sha": null,
2268+ "because_sha": null
2269+ },
2270+ {
2271+ "sha": "786cf437dbe806cf952fe0a6582370bfda06b339",
2272+ "description": "crocus/gen8: add VF topology support",
2273+ "nominated": false,
2274+ "nomination_type": null,
2275+ "resolution": 4,
2276+ "main_sha": null,
2277+ "because_sha": null
2278+ },
2279+ {
2280+ "sha": "961ee7e72b98fd46b245c609968bc0aabaf2f48b",
2281+ "description": "crocus/gen8: state base address + misc setup state.",
2282+ "nominated": false,
2283+ "nomination_type": null,
2284+ "resolution": 4,
2285+ "main_sha": null,
2286+ "because_sha": null
2287+ },
2288+ {
2289+ "sha": "515f9f5e401507223692ccd6b2cf64ee22fc69e1",
2290+ "description": "crocus/gen8: add support for vertex instancing and index buffers.",
2291+ "nominated": false,
2292+ "nomination_type": null,
2293+ "resolution": 4,
2294+ "main_sha": null,
2295+ "because_sha": null
2296+ },
2297+ {
2298+ "sha": "abc990df9b98302e58100783862557e574a00ba3",
2299+ "description": "crocus/gen8: add raw pipe control support for gen8 workarounds",
2300+ "nominated": false,
2301+ "nomination_type": null,
2302+ "resolution": 4,
2303+ "main_sha": null,
2304+ "because_sha": null
2305+ },
2306+ {
2307+ "sha": "117fdacc2b3d73beb92fd799b350c0481039454f",
2308+ "description": "crocus/gen8: limit vertex buffer workarounds to ivb",
2309+ "nominated": false,
2310+ "nomination_type": null,
2311+ "resolution": 4,
2312+ "main_sha": null,
2313+ "because_sha": null
2314+ },
2315+ {
2316+ "sha": "36fd6152f6b7eb9f510b2ef71f7bfda237636068",
2317+ "description": "crocus/gen8: extending gen7 binding table pointers",
2318+ "nominated": false,
2319+ "nomination_type": null,
2320+ "resolution": 4,
2321+ "main_sha": null,
2322+ "because_sha": null
2323+ },
2324+ {
2325+ "sha": "643475bad378206d296f9307430739235cbad5a6",
2326+ "description": "crocus/gen8: add l3 config support",
2327+ "nominated": false,
2328+ "nomination_type": null,
2329+ "resolution": 4,
2330+ "main_sha": null,
2331+ "because_sha": null
2332+ },
2333+ {
2334+ "sha": "d0a96d681703ed32abb1b1a0db279c96b9982167",
2335+ "description": "crocus/gen8: add sampler / border color support for gen8",
2336+ "nominated": false,
2337+ "nomination_type": null,
2338+ "resolution": 4,
2339+ "main_sha": null,
2340+ "because_sha": null
2341+ },
2342+ {
2343+ "sha": "0cec8eed70b869a80793f92fe17d6a499ed142e0",
2344+ "description": "crocus/gen8: extend predicate handling to gen8.",
2345+ "nominated": false,
2346+ "nomination_type": null,
2347+ "resolution": 4,
2348+ "main_sha": null,
2349+ "because_sha": null
2350+ },
2351+ {
2352+ "sha": "aac830ec65a3cab30e4cc44f18dfab3473ae0ba0",
2353+ "description": "crocus: extend hsw cut index to gen8",
2354+ "nominated": false,
2355+ "nomination_type": null,
2356+ "resolution": 4,
2357+ "main_sha": null,
2358+ "because_sha": null
2359+ },
2360+ {
2361+ "sha": "a422823a611109fdf7a537668876879cdf4062b1",
2362+ "description": "crocus/gen8: extend image support to gen8",
2363+ "nominated": false,
2364+ "nomination_type": null,
2365+ "resolution": 4,
2366+ "main_sha": null,
2367+ "because_sha": null
2368+ },
2369+ {
2370+ "sha": "60c03d003af992a19c724c880781a8f14a442c88",
2371+ "description": "crocus/gen8: extend some compute + state functions to gen8",
2372+ "nominated": false,
2373+ "nomination_type": null,
2374+ "resolution": 4,
2375+ "main_sha": null,
2376+ "because_sha": null
2377+ },
2378+ {
2379+ "sha": "27b86a8b5c45461e7e0bb095d169c3863a739aa6",
2380+ "description": "crocus/gen8: add push constant support (extend hsw)",
2381+ "nominated": false,
2382+ "nomination_type": null,
2383+ "resolution": 4,
2384+ "main_sha": null,
2385+ "because_sha": null
2386+ },
2387+ {
2388+ "sha": "72e5778579d04975c9a9c8f35d1e01a1f356f9e6",
2389+ "description": "crocus: extend l3 config setup to gen8",
2390+ "nominated": false,
2391+ "nomination_type": null,
2392+ "resolution": 4,
2393+ "main_sha": null,
2394+ "because_sha": null
2395+ },
2396+ {
2397+ "sha": "7210e98c003e3cca6b5e2b0740a2ec69df71467e",
2398+ "description": "crocus/query: add gen8 support to queries by extending hsw checks",
2399+ "nominated": false,
2400+ "nomination_type": null,
2401+ "resolution": 4,
2402+ "main_sha": null,
2403+ "because_sha": null
2404+ },
2405+ {
2406+ "sha": "6b5b2237a083e6b51766cd07243def9dca3ab0e4",
2407+ "description": "crocus/stencil: limit stencil workaround to gen7",
2408+ "nominated": false,
2409+ "nomination_type": null,
2410+ "resolution": 4,
2411+ "main_sha": null,
2412+ "because_sha": null
2413+ },
2414+ {
2415+ "sha": "fa52824f3d4f98a34571b24e2d367566344085aa",
2416+ "description": "crocus: limit texture gather workarounds to gen7/hsw",
2417+ "nominated": false,
2418+ "nomination_type": null,
2419+ "resolution": 4,
2420+ "main_sha": null,
2421+ "because_sha": null
2422+ },
2423+ {
2424+ "sha": "df0e131b43119be5433613f127edd1da9b738e92",
2425+ "description": "crocus/gen8: limit some pipe controls to gen7/hsw",
2426+ "nominated": false,
2427+ "nomination_type": null,
2428+ "resolution": 4,
2429+ "main_sha": null,
2430+ "because_sha": null
2431+ },
2432+ {
2433+ "sha": "22ee372eb31f6c9fc30d4a57b01abddbaec34708",
2434+ "description": "crocus: refactor blend state code.",
2435+ "nominated": false,
2436+ "nomination_type": null,
2437+ "resolution": 4,
2438+ "main_sha": null,
2439+ "because_sha": null
2440+ },
2441+ {
2442+ "sha": "a9c1c75e9ce3f6d06c5a0a1d6610a63184b5954f",
2443+ "description": "crocus: convert a bunch of is_haswell into verx10 checks.",
2444+ "nominated": false,
2445+ "nomination_type": null,
2446+ "resolution": 4,
2447+ "main_sha": null,
2448+ "because_sha": null
2449+ },
2450+ {
2451+ "sha": "ae17ffedb7fa45008a8f4264c51c6f09cbbde0f0",
2452+ "description": "crocus: fixup workaround_bo to match 965.",
2453+ "nominated": false,
2454+ "nomination_type": null,
2455+ "resolution": 4,
2456+ "main_sha": null,
2457+ "because_sha": null
2458+ },
2459+ {
2460+ "sha": "1ced4213309784151c25aee452ea13e2613895f9",
2461+ "description": "crocus: rename genX proto functions to avoid iris conflicts.",
2462+ "nominated": false,
2463+ "nomination_type": null,
2464+ "resolution": 4,
2465+ "main_sha": null,
2466+ "because_sha": null
2467+ },
2468+ {
2469+ "sha": "7cfc41aa6be77ca51b197c76b5f53b84d917747d",
2470+ "description": "crocus: fixup stray tab",
2471+ "nominated": false,
2472+ "nomination_type": null,
2473+ "resolution": 4,
2474+ "main_sha": null,
2475+ "because_sha": null
2476+ },
2477+ {
2478+ "sha": "f557d11f153cc1b92ce00fa6a7e35d56fdc5bcd4",
2479+ "description": "crocus: drop dead gen prototypes.",
2480+ "nominated": false,
2481+ "nomination_type": null,
2482+ "resolution": 4,
2483+ "main_sha": null,
2484+ "because_sha": null
2485+ },
2486+ {
2487+ "sha": "553743e04aab7abf8d9622771a15d94c40d7057d",
2488+ "description": "i915g: Clear xfails for vertex texturing.",
2489+ "nominated": false,
2490+ "nomination_type": 1,
2491+ "resolution": 4,
2492+ "main_sha": null,
2493+ "because_sha": "7378c6479278983de7f1f39902aade0567a53965"
2494+ },
2495+ {
2496+ "sha": "4ef8eebdc7cf244a999e754c070471cfc3e8425a",
2497+ "description": "i915g: Use the color swizzle to reshuffle the blend const color.",
2498+ "nominated": false,
2499+ "nomination_type": null,
2500+ "resolution": 4,
2501+ "main_sha": null,
2502+ "because_sha": null
2503+ },
2504+ {
2505+ "sha": "0fda53b57499e905ca67e7d97fbb1f224713d1aa",
2506+ "description": "i915g: Simplify color write mask setup.",
2507+ "nominated": false,
2508+ "nomination_type": null,
2509+ "resolution": 4,
2510+ "main_sha": null,
2511+ "because_sha": null
2512+ },
2513+ {
2514+ "sha": "bd4121fe0430e41d7c929fb843a27bc16e355ef5",
2515+ "description": "i915g: Move cbuf color swizzle lookup to CSO creation time.",
2516+ "nominated": false,
2517+ "nomination_type": null,
2518+ "resolution": 4,
2519+ "main_sha": null,
2520+ "because_sha": null
2521+ },
2522+ {
2523+ "sha": "5b3840d9613928b97beb26c18d2ca60471c9516f",
2524+ "description": "i915g: Compute 3DSTATE_BUF_INFO flags at surface create time.",
2525+ "nominated": false,
2526+ "nomination_type": null,
2527+ "resolution": 4,
2528+ "main_sha": null,
2529+ "because_sha": null
2530+ },
2531+ {
2532+ "sha": "f8867b3d989f3d338b0796c028aae7272b20f827",
2533+ "description": "i915g: Create an i915_surface for our pipe_surfaces.",
2534+ "nominated": false,
2535+ "nomination_type": null,
2536+ "resolution": 4,
2537+ "main_sha": null,
2538+ "because_sha": null
2539+ },
2540+ {
2541+ "sha": "51458ba9e9c7c8cc4e44b7ffb1e24ad88b25ffe3",
2542+ "description": "i915g: Remove nr_cbufs loop.",
2543+ "nominated": false,
2544+ "nomination_type": null,
2545+ "resolution": 4,
2546+ "main_sha": null,
2547+ "because_sha": null
2548+ },
2549+ {
2550+ "sha": "c6da3827d031bf4d345d3048a149bcddd52a9a11",
2551+ "description": "radeon/vcn: use st_rps_bits only when it's set",
2552+ "nominated": false,
2553+ "nomination_type": 1,
2554+ "resolution": 4,
2555+ "main_sha": null,
2556+ "because_sha": "c9baccb516b70469ec8dc3c64af423d35617cf04"
2557+ },
2558+ {
2559+ "sha": "806498eee8f0d39897c1727b82ab08cbc75f1ee5",
2560+ "description": "docs/isl: Consistently use 3-space tabs",
2561+ "nominated": false,
2562+ "nomination_type": null,
2563+ "resolution": 4,
2564+ "main_sha": null,
2565+ "because_sha": null
2566+ },
2567+ {
2568+ "sha": "105a51b16667699bcbbbaf24e5820e4a63774583",
2569+ "description": "docs/nir: Use 3-space tabs",
2570+ "nominated": false,
2571+ "nomination_type": null,
2572+ "resolution": 4,
2573+ "main_sha": null,
2574+ "because_sha": null
2575+ },
2576+ {
2577+ "sha": "2175cc3920e26e41ea980988ea465c7ad34bf24b",
2578+ "description": "editorconfig: Use 3-space tabs for .rst",
2579+ "nominated": false,
2580+ "nomination_type": null,
2581+ "resolution": 4,
2582+ "main_sha": null,
2583+ "because_sha": null
2584+ },
2585+ {
2586+ "sha": "7c6084634f8fb1af036f7649955deb48b3f90064",
2587+ "description": "ci/llvmpipe: Mark two more multithread program link flakes.",
2588+ "nominated": false,
2589+ "nomination_type": null,
2590+ "resolution": 4,
2591+ "main_sha": null,
2592+ "because_sha": null
2593+ },
2594+ {
2595+ "sha": "5cb043cf82af4af88dbfe83ce1eff4cc41e2a766",
2596+ "description": "freedreno: Cooperate with tc to stop checking the BC for resource_busy().",
2597+ "nominated": false,
2598+ "nomination_type": null,
2599+ "resolution": 4,
2600+ "main_sha": null,
2601+ "because_sha": null
2602+ },
2603+ {
2604+ "sha": "6d0aceae4db45542f8d9531ec6e9ff5bee6ed282",
2605+ "description": "vk/util: add macros for multidraw",
2606+ "nominated": false,
2607+ "nomination_type": null,
2608+ "resolution": 4,
2609+ "main_sha": null,
2610+ "because_sha": null
2611+ },
2612+ {
2613+ "sha": "8c968b8301bec54f4b7a61e4c4144ccd322ca92c",
2614+ "description": "radv: advertise extendedDynamicState2LogicOp",
2615+ "nominated": false,
2616+ "nomination_type": null,
2617+ "resolution": 4,
2618+ "main_sha": null,
2619+ "because_sha": null
2620+ },
2621+ {
2622+ "sha": "8efa8971683f50a3b9473a0be7d2027f0465a6dd",
2623+ "description": "radv: implement dynamic logic op",
2624+ "nominated": false,
2625+ "nomination_type": null,
2626+ "resolution": 4,
2627+ "main_sha": null,
2628+ "because_sha": null
2629+ },
2630+ {
2631+ "sha": "e6bf5cfe59bfc19124785d39ab25584bfbf07f5e",
2632+ "description": "aco/gfx10: Emit barrier at the start of NGG VS and TES.",
2633+ "nominated": true,
2634+ "nomination_type": 0,
2635+ "resolution": 1,
2636+ "main_sha": null,
2637+ "because_sha": null
2638+ },
2639+ {
2640+ "sha": "f9447abb365c0e33a1afeb2ed25a5f10cc4aa968",
2641+ "description": "aco/gfx10: NGG zero output workaround for conservative rasterization.",
2642+ "nominated": true,
2643+ "nomination_type": 0,
2644+ "resolution": 1,
2645+ "main_sha": null,
2646+ "because_sha": null
2647+ },
2648+ {
2649+ "sha": "25314996d058629ff9d669fe917741c29222b35b",
2650+ "description": "radv/llvm: Emit s_barrier at the beginning of NGG non-GS shaders.",
2651+ "nominated": true,
2652+ "nomination_type": 0,
2653+ "resolution": 1,
2654+ "main_sha": null,
2655+ "because_sha": null
2656+ },
2657+ {
2658+ "sha": "d970fe2e9d6a8e9997a0ce212146d62013b3b455",
2659+ "description": "panfrost: Add a Vulkan driver for Midgard/Bifrost GPUs",
2660+ "nominated": false,
2661+ "nomination_type": null,
2662+ "resolution": 4,
2663+ "main_sha": null,
2664+ "because_sha": null
2665+ },
2666+ {
2667+ "sha": "20b22efdcb72ddadb1a64e6f4dcf4f1fe4ec5b29",
2668+ "description": "pan/midg: Add a flag to dump internal shaders",
2669+ "nominated": false,
2670+ "nomination_type": null,
2671+ "resolution": 4,
2672+ "main_sha": null,
2673+ "because_sha": null
2674+ },
2675+ {
2676+ "sha": "773bc1188bcc62b5badd0f6191df079b51cc49ea",
2677+ "description": "panfrost: Make panfrost_scoreboard_initialize_tiler() return the job pointer",
2678+ "nominated": false,
2679+ "nomination_type": null,
2680+ "resolution": 4,
2681+ "main_sha": null,
2682+ "because_sha": null
2683+ },
2684+ {
2685+ "sha": "6d2ed635c349dd882b1c67d13c6d15e182ace222",
2686+ "description": "panfrost: Constify the constants pointers passed to pan_blend functions",
2687+ "nominated": false,
2688+ "nomination_type": null,
2689+ "resolution": 4,
2690+ "main_sha": null,
2691+ "because_sha": null
2692+ },
2693+ {
2694+ "sha": "aefa40886bbdfcb17848007d0b58ff34fc906c3a",
2695+ "description": "anv: adjust headers for non-GNU after e9e1e0362b6c",
2696+ "nominated": false,
2697+ "nomination_type": 1,
2698+ "resolution": 4,
2699+ "main_sha": null,
2700+ "because_sha": "e9e1e0362b6c2d06867e5c67b13e812f3a24c3d5"
2701+ },
2702+ {
2703+ "sha": "7aaa54feb53a9d0cf3277bef31547312ee56b277",
2704+ "description": "radv: implement VK_EXT_physical_device_drm",
2705+ "nominated": false,
2706+ "nomination_type": null,
2707+ "resolution": 4,
2708+ "main_sha": null,
2709+ "because_sha": null
2710+ },
2711+ {
2712+ "sha": "60ff9dea27dad8c54ac19e7586c6a45d737f8fa6",
2713+ "description": "zink: use multidraw",
2714+ "nominated": false,
2715+ "nomination_type": null,
2716+ "resolution": 4,
2717+ "main_sha": null,
2718+ "because_sha": null
2719+ },
2720+ {
2721+ "sha": "b6855b2e183e6738081fcf4a949d9d60796a205f",
2722+ "description": "zink: support multidraw",
2723+ "nominated": false,
2724+ "nomination_type": null,
2725+ "resolution": 4,
2726+ "main_sha": null,
2727+ "because_sha": null
2728+ },
2729+ {
2730+ "sha": "84199077d95f6c3022acc04e0f654b5476620aa8",
2731+ "description": "zink: clear the fb clears array instead of freeing it on reset",
2732+ "nominated": false,
2733+ "nomination_type": null,
2734+ "resolution": 4,
2735+ "main_sha": null,
2736+ "because_sha": null
2737+ },
2738+ {
2739+ "sha": "6cc2929e876204ba967e5857fb4fc35522d6f506",
2740+ "description": "zink: add more clear hooks",
2741+ "nominated": false,
2742+ "nomination_type": null,
2743+ "resolution": 4,
2744+ "main_sha": null,
2745+ "because_sha": null
2746+ },
2747+ {
2748+ "sha": "3f420b3f5521105c38cf9346238d1dbcae2030f8",
2749+ "description": "zink: add a flag for disabling conditional render during blit",
2750+ "nominated": false,
2751+ "nomination_type": null,
2752+ "resolution": 4,
2753+ "main_sha": null,
2754+ "because_sha": null
2755+ },
2756+ {
2757+ "sha": "786fa3435cd3ca884c65a432cf71a8c6fe818469",
2758+ "description": "spirv_to_nir: Add environment variable to change default log level",
2759+ "nominated": false,
2760+ "nomination_type": null,
2761+ "resolution": 4,
2762+ "main_sha": null,
2763+ "because_sha": null
2764+ },
2765+ {
2766+ "sha": "e9991d5ff1e8d471a75f2bab22b2776aef90cabd",
2767+ "description": "radv: Provide a toggle to avoid warnings about unsupported devices.",
2768+ "nominated": false,
2769+ "nomination_type": null,
2770+ "resolution": 4,
2771+ "main_sha": null,
2772+ "because_sha": null
2773+ },
2774+ {
2775+ "sha": "26af7ef67fd8d1b6bb22e9332984136ec61b358b",
2776+ "description": "v3dv/build: meson infrastructure for multi-hw-version support",
2777+ "nominated": false,
2778+ "nomination_type": null,
2779+ "resolution": 4,
2780+ "main_sha": null,
2781+ "because_sha": null
2782+ },
2783+ {
2784+ "sha": "f257c79ea4e5aebba33b37ccc7e59ebf3d0ac037",
2785+ "description": "v3dv: remove gen-dependant includes from v3dv_private",
2786+ "nominated": false,
2787+ "nomination_type": null,
2788+ "resolution": 4,
2789+ "main_sha": null,
2790+ "because_sha": null
2791+ },
2792+ {
2793+ "sha": "2e40f13f9a87d4cf73ce6aeb27925d8d0caab4dc",
2794+ "description": "v3dv: don't use cl_packet_length for prepacked data",
2795+ "nominated": false,
2796+ "nomination_type": null,
2797+ "resolution": 4,
2798+ "main_sha": null,
2799+ "because_sha": null
2800+ },
2801+ {
2802+ "sha": "1bea0d76b8ce9ecc2fa079a4e1ab98ec84442c3f",
2803+ "description": "v3dv: split v3dv_descriptor hw version dependant to a new source file.",
2804+ "nominated": false,
2805+ "nomination_type": null,
2806+ "resolution": 4,
2807+ "main_sha": null,
2808+ "because_sha": null
2809+ },
2810+ {
2811+ "sha": "67f4624c0c528d9d46dea03564817507e692ea5c",
2812+ "description": "v3dv: move several hw version dependant code to their own (v3dvx) source file",
2813+ "nominated": false,
2814+ "nomination_type": null,
2815+ "resolution": 4,
2816+ "main_sha": null,
2817+ "because_sha": null
2818+ },
2819+ {
2820+ "sha": "76634f9b8a6ff9d94566435ac9d4a34856c00e48",
2821+ "description": "v3dv: split v3dv_device hw version dependant code to a new source file",
2822+ "nominated": false,
2823+ "nomination_type": null,
2824+ "resolution": 4,
2825+ "main_sha": null,
2826+ "because_sha": null
2827+ },
2828+ {
2829+ "sha": "f526f92043adfb458e1140dde16463ae060f4901",
2830+ "description": "v3dv: split v3dv_format hw version dependant code to a new source file",
2831+ "nominated": false,
2832+ "nomination_type": null,
2833+ "resolution": 4,
2834+ "main_sha": null,
2835+ "because_sha": null
2836+ },
2837+ {
2838+ "sha": "a3793dbef3e7626dcb2b96a2757aefb2c4b05f48",
2839+ "description": "v3dv: split v3dv_image hw version dependant code to a new source file",
2840+ "nominated": false,
2841+ "nomination_type": null,
2842+ "resolution": 4,
2843+ "main_sha": null,
2844+ "because_sha": null
2845+ },
2846+ {
2847+ "sha": "ad805712edc5956cec4d73908ef35b0eb91b3827",
2848+ "description": "v3dv: split v3dv_pipeline hw version dependant code to a new source file",
2849+ "nominated": false,
2850+ "nomination_type": null,
2851+ "resolution": 4,
2852+ "main_sha": null,
2853+ "because_sha": null
2854+ },
2855+ {
2856+ "sha": "83ba3c1020da2ef04db3acf0d6a8fca26fe90e7d",
2857+ "description": "v3dv: start to move and wrap hw-version code with v3dv_queue",
2858+ "nominated": false,
2859+ "nomination_type": null,
2860+ "resolution": 4,
2861+ "main_sha": null,
2862+ "because_sha": null
2863+ },
2864+ {
2865+ "sha": "efc363a7ce667c7638c89e282cb4b365a71da894",
2866+ "description": "v3dv/cmd_buffer: move cl_emit calls for Draw methods to helpers",
2867+ "nominated": false,
2868+ "nomination_type": null,
2869+ "resolution": 4,
2870+ "main_sha": null,
2871+ "because_sha": null
2872+ },
2873+ {
2874+ "sha": "d39930fb9205bf6f3707171daa8f86a0a5a9a72f",
2875+ "description": "v3dv/cmd_buffer: add helper job_emit_binning_prolog",
2876+ "nominated": false,
2877+ "nomination_type": null,
2878+ "resolution": 4,
2879+ "main_sha": null,
2880+ "because_sha": null
2881+ },
2882+ {
2883+ "sha": "1dc8c2d9f61f58259185c05f0951fb2ffb128118",
2884+ "description": "v3dv: rename v3dv_pack for v3dvx_pack",
2885+ "nominated": false,
2886+ "nomination_type": null,
2887+ "resolution": 4,
2888+ "main_sha": null,
2889+ "because_sha": null
2890+ },
2891+ {
2892+ "sha": "7c4478f43bbb18f6c71cb85433139c1a0d2cb697",
2893+ "description": "i965: fix regression in pipe control on g45",
2894+ "nominated": true,
2895+ "nomination_type": 1,
2896+ "resolution": 1,
2897+ "main_sha": null,
2898+ "because_sha": "b505db3864b097fa3bbf2a35bd3184554eb449d7"
2899+ },
2900+ {
2901+ "sha": "91a1849ff04fc6b7b921a303823a111196ff8559",
2902+ "description": "wgl: remove hard limit on pixelformats",
2903+ "nominated": false,
2904+ "nomination_type": null,
2905+ "resolution": 4,
2906+ "main_sha": null,
2907+ "because_sha": null
2908+ },
2909+ {
2910+ "sha": "8f9368ddb7c1ae682a9943cd82bbf297151da2c3",
2911+ "description": "ac/perfcounters: add a GPU block ID to every block definitions",
2912+ "nominated": false,
2913+ "nomination_type": null,
2914+ "resolution": 4,
2915+ "main_sha": null,
2916+ "because_sha": null
2917+ },
2918+ {
2919+ "sha": "5a8776fd8c46ca257efb38cf13b02dafba9bc000",
2920+ "description": "ac/perfcounters: add more SPM configuration fields",
2921+ "nominated": false,
2922+ "nomination_type": null,
2923+ "resolution": 4,
2924+ "main_sha": null,
2925+ "because_sha": null
2926+ },
2927+ {
2928+ "sha": "3d8d6ebcb09f8506abc7c84267f97f31b55b0214",
2929+ "description": "ac/perfcounters: rename num_multi to num_spm_counters",
2930+ "nominated": false,
2931+ "nomination_type": null,
2932+ "resolution": 4,
2933+ "main_sha": null,
2934+ "because_sha": null
2935+ },
2936+ {
2937+ "sha": "da947725100249d671683d0e5ca7b9c2d5950e8c",
2938+ "description": "ac/perfcounters,radeonsi: rework performance counters layout",
2939+ "nominated": false,
2940+ "nomination_type": null,
2941+ "resolution": 4,
2942+ "main_sha": null,
2943+ "because_sha": null
2944+ },
2945+ {
2946+ "sha": "66a34be6ac37d3475c492a0c83fbe3aadb3aa016",
2947+ "description": "ac/perfcounters: remove ac_pc_block_base::num_prelude",
2948+ "nominated": false,
2949+ "nomination_type": null,
2950+ "resolution": 4,
2951+ "main_sha": null,
2952+ "because_sha": null
2953+ },
2954+ {
2955+ "sha": "100fc3020ade0a44f904d1e6a94e01c0d5a957a6",
2956+ "description": "anv: provide dummy vkCmdSetPatchControlPointsEXT",
2957+ "nominated": false,
2958+ "nomination_type": 1,
2959+ "resolution": 4,
2960+ "main_sha": null,
2961+ "because_sha": "0d031d1da34bd3a58d723397404c7998117abb18"
2962+ },
2963+ {
2964+ "sha": "91029211093c7ab9e32de101ac7499a958635ac6",
2965+ "description": "llvmpipe: Add handle export for resource_get_param",
2966+ "nominated": true,
2967+ "nomination_type": 1,
2968+ "resolution": 1,
2969+ "main_sha": null,
2970+ "because_sha": "2dcc9c7f54edbff075665ebe5d50f2499dc12163"
2971+ },
2972+ {
2973+ "sha": "d3ea8f519eab95f4911143814b412ffbbd05f2d8",
2974+ "description": "docs,isl: Document Sandy Bridge HiZ/stencil",
2975+ "nominated": false,
2976+ "nomination_type": null,
2977+ "resolution": 4,
2978+ "main_sha": null,
2979+ "because_sha": null
2980+ },
2981+ {
2982+ "sha": "8dfb240b1f063307aa5e53fb1bd0865105eef986",
2983+ "description": "nir: Add raytracing shader call lowering pass.",
2984+ "nominated": false,
2985+ "nomination_type": null,
2986+ "resolution": 4,
2987+ "main_sha": null,
2988+ "because_sha": null
2989+ },
2990+ {
2991+ "sha": "02c5dc8035b8b03d1abc74074767303951fd0a5b",
2992+ "description": "nir: Add lowered vendor independent raytracing intrinsics.",
2993+ "nominated": false,
2994+ "nomination_type": null,
2995+ "resolution": 4,
2996+ "main_sha": null,
2997+ "because_sha": null
2998+ },
2999+ {
3000+ "sha": "58f5605124a74eeac6a6156b093c9f098bb99c78",
3001+ "description": "freedreno: Handle full blit discards by invalidating the resource.",
3002+ "nominated": false,
3003+ "nomination_type": null,
3004+ "resolution": 4,
3005+ "main_sha": null,
3006+ "because_sha": null
3007+ },
3008+ {
3009+ "sha": "74ede4b353bcac7451a56c75712e25151f7c6b63",
3010+ "description": "freedreno: Move the rsc-based batch flushing to helper functions.",
3011+ "nominated": false,
3012+ "nomination_type": null,
3013+ "resolution": 4,
3014+ "main_sha": null,
3015+ "because_sha": null
3016+ },
3017+ {
3018+ "sha": "447b6f60a6902e07ca034e0ebf667e76cde93ec6",
3019+ "description": "gallium/util: Introduce a helper for finding whole-resource blits.",
3020+ "nominated": false,
3021+ "nomination_type": null,
3022+ "resolution": 4,
3023+ "main_sha": null,
3024+ "because_sha": null
3025+ },
3026+ {
3027+ "sha": "9ce44dc9bc6bfbd88639e4ebeb16680d35585088",
3028+ "description": "gallium/draw: Garbage collect draw_pt_fetch_emit.",
3029+ "nominated": false,
3030+ "nomination_type": null,
3031+ "resolution": 4,
3032+ "main_sha": null,
3033+ "because_sha": null
3034+ },
3035+ {
3036+ "sha": "5e019269d64f006ee870d47df9845d554a6851a5",
3037+ "description": "gallium/draw: Garbage collect draw_set_force_passthrough",
3038+ "nominated": false,
3039+ "nomination_type": null,
3040+ "resolution": 4,
3041+ "main_sha": null,
3042+ "because_sha": null
3043+ },
3044+ {
3045+ "sha": "ae2b7a29d20546e494d8d10dfcf5880b54e5b999",
3046+ "description": "docs/envvars: document MESA_VK_WSI_PRESENT_MODE",
3047+ "nominated": false,
3048+ "nomination_type": null,
3049+ "resolution": 4,
3050+ "main_sha": null,
3051+ "because_sha": null
3052+ },
3053+ {
3054+ "sha": "7369b1a21ee7425492eaa2e2fece0c5e0a34ba99",
3055+ "description": "vulkan/wsi/wayland: simplify wl_surface version check",
3056+ "nominated": false,
3057+ "nomination_type": null,
3058+ "resolution": 4,
3059+ "main_sha": null,
3060+ "because_sha": null
3061+ },
3062+ {
3063+ "sha": "eb98171252aeec2a165cecbac0ee0987769f1511",
3064+ "description": "intel/gen125.xml: Drop GPGPU_WALKER",
3065+ "nominated": false,
3066+ "nomination_type": null,
3067+ "resolution": 4,
3068+ "main_sha": null,
3069+ "because_sha": null
3070+ },
3071+ {
3072+ "sha": "e9e1e0362b6c2d06867e5c67b13e812f3a24c3d5",
3073+ "description": "anv: implement VK_EXT_physical_device_drm",
3074+ "nominated": false,
3075+ "nomination_type": null,
3076+ "resolution": 4,
3077+ "main_sha": null,
3078+ "because_sha": null
3079+ },
3080+ {
3081+ "sha": "6a2e3d27366c1269868de536da90d145e230dbc1",
3082+ "description": "radeonsi: cleanup some primitive discard CS TODOs regarding instancing, etc.",
3083+ "nominated": false,
3084+ "nomination_type": null,
3085+ "resolution": 4,
3086+ "main_sha": null,
3087+ "because_sha": null
3088+ },
3089+ {
3090+ "sha": "4b5eb336e18a8ccc8425e107e316a239a1f4f943",
3091+ "description": "radeonsi: skip buffer_atomic_add(ptr, n) when n=0 in the prim discard CS",
3092+ "nominated": false,
3093+ "nomination_type": null,
3094+ "resolution": 4,
3095+ "main_sha": null,
3096+ "because_sha": null
3097+ },
3098+ {
3099+ "sha": "df4de12af48b66578e5fe2fce557abd713f28980",
3100+ "description": "radeonsi: drop support for triangle fans from the prim discard CS",
3101+ "nominated": false,
3102+ "nomination_type": null,
3103+ "resolution": 4,
3104+ "main_sha": null,
3105+ "because_sha": null
3106+ },
3107+ {
3108+ "sha": "4fa58c04e4f01d39c4a95658c031f6e4437cbf7b",
3109+ "description": "radeonsi: drop gfx7 support from the prim discard CS to simplify code",
3110+ "nominated": false,
3111+ "nomination_type": null,
3112+ "resolution": 4,
3113+ "main_sha": null,
3114+ "because_sha": null
3115+ },
3116+ {
3117+ "sha": "fc95ba6c86f97876651b80150b424b179ba87d34",
3118+ "description": "radeonsi: remove the Z culling option from the primitive discard CS",
3119+ "nominated": false,
3120+ "nomination_type": null,
3121+ "resolution": 4,
3122+ "main_sha": null,
3123+ "because_sha": null
3124+ },
3125+ {
3126+ "sha": "a448074d0507e6a225f3ff97a291bac219486252",
3127+ "description": "radeonsi: don't compile TES and GS draw_vbo variants for the prim discard CS",
3128+ "nominated": false,
3129+ "nomination_type": null,
3130+ "resolution": 4,
3131+ "main_sha": null,
3132+ "because_sha": null
3133+ },
3134+ {
3135+ "sha": "b35b5926c9b077087bcfc614ecd4203b710a57aa",
3136+ "description": "radeonsi: try to keep all VS input loads together for better perf",
3137+ "nominated": false,
3138+ "nomination_type": null,
3139+ "resolution": 4,
3140+ "main_sha": null,
3141+ "because_sha": null
3142+ },
3143+ {
3144+ "sha": "901f4aa5d62f8a3e7b90233b6dd1b6e7c0dfde5a",
3145+ "description": "radeonsi: remove incorrect comment about PA",
3146+ "nominated": false,
3147+ "nomination_type": null,
3148+ "resolution": 4,
3149+ "main_sha": null,
3150+ "because_sha": null
3151+ },
3152+ {
3153+ "sha": "ce4f4a8d13c5b1b0816f6b3121131d7b63f746c2",
3154+ "description": "radeonsi: set more precise max_waves in NGG code",
3155+ "nominated": false,
3156+ "nomination_type": null,
3157+ "resolution": 4,
3158+ "main_sha": null,
3159+ "because_sha": null
3160+ },
3161+ {
3162+ "sha": "1e9cc86511f154896d0bd3beab8b96c9d62d00f6",
3163+ "description": "radeonsi: merge 2 conditional blocks with same condition into 1 in culling code",
3164+ "nominated": false,
3165+ "nomination_type": null,
3166+ "resolution": 4,
3167+ "main_sha": null,
3168+ "because_sha": null
3169+ },
3170+ {
3171+ "sha": "786678a017c5b488bd36fade440d9f5308c3d23c",
3172+ "description": "radeonsi: restructure si_get_vs_vgpr_comp_cnt for readability",
3173+ "nominated": false,
3174+ "nomination_type": null,
3175+ "resolution": 4,
3176+ "main_sha": null,
3177+ "because_sha": null
3178+ },
3179+ {
3180+ "sha": "06ff0ae4bbf7d328b64fb8f51aee791e08afdc05",
3181+ "description": "freedreno: Flush if at risk of overflowing bos table",
3182+ "nominated": false,
3183+ "nomination_type": null,
3184+ "resolution": 4,
3185+ "main_sha": null,
3186+ "because_sha": null
3187+ },
3188+ {
3189+ "sha": "5b4f670c1cf0361a7913d256e12544acf7536665",
3190+ "description": "freedreno/a6xx: Handle fb_read in sysmem path",
3191+ "nominated": false,
3192+ "nomination_type": null,
3193+ "resolution": 4,
3194+ "main_sha": null,
3195+ "because_sha": null
3196+ },
3197+ {
3198+ "sha": "1a1eabd7d8bb740a0d349bc29b35e7691ca3d0d1",
3199+ "description": "freedreno/ci: Garbage collect some a630 flakes",
3200+ "nominated": false,
3201+ "nomination_type": null,
3202+ "resolution": 4,
3203+ "main_sha": null,
3204+ "because_sha": null
3205+ },
3206+ {
3207+ "sha": "aeaeef661a8f2ba5a4f1a4ef271cd8415c81d98d",
3208+ "description": "gallium/tools: improve handling of pointer arrays",
3209+ "nominated": false,
3210+ "nomination_type": null,
3211+ "resolution": 4,
3212+ "main_sha": null,
3213+ "because_sha": null
3214+ },
3215+ {
3216+ "sha": "1e508777b453704fd6bc940345eba1ab0918a3d5",
3217+ "description": "radv: allow VK_FORMAT_R8G8_SRGB sampling",
3218+ "nominated": false,
3219+ "nomination_type": null,
3220+ "resolution": 4,
3221+ "main_sha": null,
3222+ "because_sha": null
3223+ },
3224+ {
3225+ "sha": "1a14d98fa247ef33c0787b07ff8d5f663cdc4408",
3226+ "description": "nir: Document all the ALU opcodes",
3227+ "nominated": false,
3228+ "nomination_type": null,
3229+ "resolution": 4,
3230+ "main_sha": null,
3231+ "because_sha": null
3232+ },
3233+ {
3234+ "sha": "73188c6954299d57c5b3eb30c514977895283b66",
3235+ "description": "nir,docs: Add docs for NIR ALU instructions",
3236+ "nominated": false,
3237+ "nomination_type": null,
3238+ "resolution": 4,
3239+ "main_sha": null,
3240+ "because_sha": null
3241+ },
3242+ {
3243+ "sha": "f00b5a30f5799b5072197ecb92bbcc16877109cd",
3244+ "description": "nir: Require vectorized ALU ops to be all-or-nothing",
3245+ "nominated": false,
3246+ "nomination_type": null,
3247+ "resolution": 4,
3248+ "main_sha": null,
3249+ "because_sha": null
3250+ },
3251+ {
3252+ "sha": "ea68d4a676260d9c45dfbe0cb8de8e40869b5523",
3253+ "description": "nir/propagate_invariant: add invariant_prim option",
3254+ "nominated": false,
3255+ "nomination_type": null,
3256+ "resolution": 4,
3257+ "main_sha": null,
3258+ "because_sha": null
3259+ },
3260+ {
3261+ "sha": "7144f338025e1f4db4d01cf79e1d9bda218fea0d",
3262+ "description": "zink: handle custom border color without matching wrap mode case",
3263+ "nominated": true,
3264+ "nomination_type": 1,
3265+ "resolution": 1,
3266+ "main_sha": null,
3267+ "because_sha": "36f4e61403a32081ffebfa3d178bfb7ba483559f"
3268+ },
3269+ {
3270+ "sha": "69d4fa3a1c1a376858230669569d9812a149cbc1",
3271+ "description": "vulkan: Update the XML and headers to 1.2.182",
3272+ "nominated": false,
3273+ "nomination_type": null,
3274+ "resolution": 4,
3275+ "main_sha": null,
3276+ "because_sha": null
3277+ },
3278+ {
3279+ "sha": "2e08bae9b38a241b505e882d681f6f68d346937e",
3280+ "description": "nir,vc4: Suffix a bunch of unorm 4x8 opcodes _vc4",
3281+ "nominated": false,
3282+ "nomination_type": null,
3283+ "resolution": 4,
3284+ "main_sha": null,
3285+ "because_sha": null
3286+ },
3287+ {
3288+ "sha": "0afbfee8da30d465f141d214ad6a307ed54b3b03",
3289+ "description": "nir,panfrost: Suffix fsat_signed and fclamp_pos with _mali",
3290+ "nominated": false,
3291+ "nomination_type": null,
3292+ "resolution": 4,
3293+ "main_sha": null,
3294+ "because_sha": null
3295+ },
3296+ {
3297+ "sha": "f0f713960b17328712c84dde539a76b22a8bf38b",
3298+ "description": "nir,amd: Suffix nir_op_cube_face_coord/index with _amd",
3299+ "nominated": false,
3300+ "nomination_type": null,
3301+ "resolution": 4,
3302+ "main_sha": null,
3303+ "because_sha": null
3304+ },
3305+ {
3306+ "sha": "e5510536e76e65e8a4f089a8d7acb093de853173",
3307+ "description": "aco: Fix checking if load_shared is used by cross lane instructions.",
3308+ "nominated": false,
3309+ "nomination_type": 1,
3310+ "resolution": 4,
3311+ "main_sha": null,
3312+ "because_sha": "b4e22eb4822d74a6e981c629ddff9bcd29b9a0ec"
3313+ },
3314+ {
3315+ "sha": "90c7ab08ea1325964e3c74f1f6b58f97845e3490",
3316+ "description": "ci: use bash with download-git-cache.sh",
3317+ "nominated": false,
3318+ "nomination_type": null,
3319+ "resolution": 4,
3320+ "main_sha": null,
3321+ "because_sha": null
3322+ },
3323+ {
3324+ "sha": "d074cc4af492950273960cef723c3813cff5231e",
3325+ "description": "util/fossilize_db: Only lock the db file, not the index.",
3326+ "nominated": false,
3327+ "nomination_type": null,
3328+ "resolution": 4,
3329+ "main_sha": null,
3330+ "because_sha": null
3331+ },
3332+ {
3333+ "sha": "4f0f8133a35ec2fec8d99936cd7425e40d092169",
3334+ "description": "util/fossilize_db: Do not lock the fossilize db permanently.",
3335+ "nominated": true,
3336+ "nomination_type": 1,
3337+ "resolution": 1,
3338+ "main_sha": null,
3339+ "because_sha": "eca6bb9540d8d1b260511cd0a71bdddb00ff4a3c"
3340+ },
3341+ {
3342+ "sha": "2ec1bff0f3a4450a9739d59421dc9c9fe72c94c6",
3343+ "description": "util/fossilize_db: Split out reading the index.",
3344+ "nominated": true,
3345+ "nomination_type": 1,
3346+ "resolution": 1,
3347+ "main_sha": null,
3348+ "because_sha": "eca6bb9540d8d1b260511cd0a71bdddb00ff4a3c"
3349+ },
3350+ {
3351+ "sha": "bd41c51c8f4d67d18d8a4407358ea4b71f153d2a",
3352+ "description": "util/fossilize_db: Pull seek into lock.",
3353+ "nominated": true,
3354+ "nomination_type": 1,
3355+ "resolution": 1,
3356+ "main_sha": null,
3357+ "because_sha": "eca6bb9540d8d1b260511cd0a71bdddb00ff4a3c"
3358+ },
3359+ {
3360+ "sha": "a99474fae52db73a23861c2ba961ee5424222da5",
3361+ "description": "radv: Add -Wpointer-arith.",
3362+ "nominated": false,
3363+ "nomination_type": null,
3364+ "resolution": 4,
3365+ "main_sha": null,
3366+ "because_sha": null
3367+ },
3368+ {
3369+ "sha": "72174a3eef230883444e7f7c77a89c4919bb38d5",
3370+ "description": "ac/nir: Update TCS output barriers with nir_var_mem_shared.",
3371+ "nominated": true,
3372+ "nomination_type": 1,
3373+ "resolution": 1,
3374+ "main_sha": null,
3375+ "because_sha": "bf966d1c1dd968116b8b547ca2739f5113caccb5"
3376+ },
3377+ {
3378+ "sha": "ed04cb62d898ade2670dbb486cfaebedce19bb6f",
3379+ "description": "docs: use rst captions",
3380+ "nominated": false,
3381+ "nomination_type": null,
3382+ "resolution": 4,
3383+ "main_sha": null,
3384+ "because_sha": null
3385+ },
3386+ {
3387+ "sha": "e41efc173b3c9c5e7061cab4656a2ba08731effb",
3388+ "description": "docs: use more file-roles",
3389+ "nominated": false,
3390+ "nomination_type": null,
3391+ "resolution": 4,
3392+ "main_sha": null,
3393+ "because_sha": null
3394+ },
3395+ {
3396+ "sha": "63c9d519812f48602d8d83b6c89dbcd33208f3c2",
3397+ "description": "docs: drop historic meson details",
3398+ "nominated": false,
3399+ "nomination_type": null,
3400+ "resolution": 4,
3401+ "main_sha": null,
3402+ "because_sha": null
3403+ },
3404+ {
3405+ "sha": "07cd8897fbdd8bbdb82fe93bc00a4fbf184d915e",
3406+ "description": "docs: remove outdated clarification",
3407+ "nominated": false,
3408+ "nomination_type": null,
3409+ "resolution": 4,
3410+ "main_sha": null,
3411+ "because_sha": null
3412+ },
3413+ {
3414+ "sha": "309b549f0eb8876af2af0f5599181a7ba7494f54",
3415+ "description": "docs: remove outdated meson-section",
3416+ "nominated": false,
3417+ "nomination_type": null,
3418+ "resolution": 4,
3419+ "main_sha": null,
3420+ "because_sha": null
3421+ },
3422+ {
3423+ "sha": "fa8868192b7c6b52bf7d7294b8b4525783026cb2",
3424+ "description": "v3dv: remove const qualifier for resource pointer in view objects",
3425+ "nominated": false,
3426+ "nomination_type": null,
3427+ "resolution": 4,
3428+ "main_sha": null,
3429+ "because_sha": null
3430+ },
3431+ {
3432+ "sha": "b8abedb97458470b5829f01d33663fc4d79ef976",
3433+ "description": "v3dv: expose VK_KHR_copy_commands2",
3434+ "nominated": false,
3435+ "nomination_type": null,
3436+ "resolution": 4,
3437+ "main_sha": null,
3438+ "because_sha": null
3439+ },
3440+ {
3441+ "sha": "aa61a653a5dcbebd8b5a0f32ea4dbba3cba77dd6",
3442+ "description": "v3dv: implement vkCmdResolveImage2KHR",
3443+ "nominated": false,
3444+ "nomination_type": null,
3445+ "resolution": 4,
3446+ "main_sha": null,
3447+ "because_sha": null
3448+ },
3449+ {
3450+ "sha": "8e358a74d0820e8f0735083b406b02741cf93822",
3451+ "description": "v3dv: implement vkCmdCopyImage2KHR",
3452+ "nominated": false,
3453+ "nomination_type": null,
3454+ "resolution": 4,
3455+ "main_sha": null,
3456+ "because_sha": null
3457+ },
3458+ {
3459+ "sha": "3bdc03fd28703b3c18fcc2e423fab43a9ddda4ec",
3460+ "description": "v3dv: implement vkCmdCopyBufferToImage2KHR and vkCmdCopyImageToBuffer2KHR",
3461+ "nominated": false,
3462+ "nomination_type": null,
3463+ "resolution": 4,
3464+ "main_sha": null,
3465+ "because_sha": null
3466+ },
3467+ {
3468+ "sha": "47390d6669ae57ad0594f028d8275029c3361c8e",
3469+ "description": "v3dv: implement vkCmdCopyBuffer2KHR",
3470+ "nominated": false,
3471+ "nomination_type": null,
3472+ "resolution": 4,
3473+ "main_sha": null,
3474+ "because_sha": null
3475+ },
3476+ {
3477+ "sha": "06a9a3ead56552f66139c08dc31cf312008ae0bd",
3478+ "description": "v3dv: implement vkCmdBlitImage2KHR",
3479+ "nominated": false,
3480+ "nomination_type": null,
3481+ "resolution": 4,
3482+ "main_sha": null,
3483+ "because_sha": null
3484+ },
3485+ {
3486+ "sha": "89b4f337d50c01c5782e19ee40b57a6c9e4b324b",
3487+ "description": "c_std=c11 in meson default_options",
3488+ "nominated": false,
3489+ "nomination_type": null,
3490+ "resolution": 4,
3491+ "main_sha": null,
3492+ "because_sha": null
3493+ },
3494+ {
3495+ "sha": "61a845ca19f7c1d236a7f517108c6ddb3b929c64",
3496+ "description": "ac/surface: don't set DCC_PIPE_ALIGN modifier bit for gfx10 with 1 RB",
3497+ "nominated": false,
3498+ "nomination_type": null,
3499+ "resolution": 4,
3500+ "main_sha": null,
3501+ "because_sha": null
3502+ },
3503+ {
3504+ "sha": "2acd34f2664e538836644c1a410d9ac0b937af22",
3505+ "description": "ac/surface/tests: fix RB counts",
3506+ "nominated": false,
3507+ "nomination_type": null,
3508+ "resolution": 4,
3509+ "main_sha": null,
3510+ "because_sha": null
3511+ },
3512+ {
3513+ "sha": "9c3225cb53bae8dacf6c5b1407b3c59f3de95c1c",
3514+ "description": "radeonsi: move the accepting code into the bbox cull branch in NGG cull code",
3515+ "nominated": false,
3516+ "nomination_type": null,
3517+ "resolution": 4,
3518+ "main_sha": null,
3519+ "because_sha": null
3520+ },
3521+ {
3522+ "sha": "12d2df15f178591d45193b6cc3e093281e2ea0aa",
3523+ "description": "ac/llvm: add a callback to ac_cull_triangle to generate code in inner-most block",
3524+ "nominated": false,
3525+ "nomination_type": null,
3526+ "resolution": 4,
3527+ "main_sha": null,
3528+ "because_sha": null
3529+ },
3530+ {
3531+ "sha": "18055726948f24670a31bb421cc9fa07140c1a5e",
3532+ "description": "radeonsi: fix multi draws for the prim discard CS",
3533+ "nominated": false,
3534+ "nomination_type": null,
3535+ "resolution": 4,
3536+ "main_sha": null,
3537+ "because_sha": null
3538+ },
3539+ {
3540+ "sha": "848dbe9ff7bb696250dfb2e79f7dfd661cba69b5",
3541+ "description": "radeonsi: fix incorrect counting of compute_num_verts_rejected",
3542+ "nominated": false,
3543+ "nomination_type": null,
3544+ "resolution": 4,
3545+ "main_sha": null,
3546+ "because_sha": null
3547+ },
3548+ {
3549+ "sha": "3cde2f96f9bc86de714795a7491d1cf7ede2268a",
3550+ "description": "radeonsi: use ac_build_bit_count instead of opencoding it",
3551+ "nominated": false,
3552+ "nomination_type": null,
3553+ "resolution": 4,
3554+ "main_sha": null,
3555+ "because_sha": null
3556+ },
3557+ {
3558+ "sha": "70b5a5cbbf6888bcf251b42d957529048d9e82d9",
3559+ "description": "radeonsi: fix compile failures with SI_PRIM_DISCARD_DEBUG enabled",
3560+ "nominated": false,
3561+ "nomination_type": null,
3562+ "resolution": 4,
3563+ "main_sha": null,
3564+ "because_sha": null
3565+ },
3566+ {
3567+ "sha": "b4d90b1182acb3365789755a618ef14cc7e53fa6",
3568+ "description": "egl: fix in expected type",
3569+ "nominated": false,
3570+ "nomination_type": null,
3571+ "resolution": 4,
3572+ "main_sha": null,
3573+ "because_sha": null
3574+ },
3575+ {
3576+ "sha": "7b8199e4a25b8aaca47d07c8236a9dca84f05b1f",
3577+ "description": "crocus: Drop extra_aux support",
3578+ "nominated": false,
3579+ "nomination_type": null,
3580+ "resolution": 4,
3581+ "main_sha": null,
3582+ "because_sha": null
3583+ },
3584+ {
3585+ "sha": "82de184c3a2c797eb010b982636dd34c04cd1b8e",
3586+ "description": "radv: Enable VK_KHR_acceleration_structure with RADV_PERFTEST=rt.",
3587+ "nominated": false,
3588+ "nomination_type": null,
3589+ "resolution": 4,
3590+ "main_sha": null,
3591+ "because_sha": null
3592+ },
3593+ {
3594+ "sha": "c27e3a6248c60ad094233c3ec783d9274fb9055d",
3595+ "description": "radv: Add rt perftest flag.",
3596+ "nominated": false,
3597+ "nomination_type": null,
3598+ "resolution": 4,
3599+ "main_sha": null,
3600+ "because_sha": null
3601+ },
3602+ {
3603+ "sha": "438cb7f9a31250d01984d2122b35d153c37bc1c6",
3604+ "description": "radv: Expose formats for acceleration structure.",
3605+ "nominated": false,
3606+ "nomination_type": null,
3607+ "resolution": 4,
3608+ "main_sha": null,
3609+ "because_sha": null
3610+ },
3611+ {
3612+ "sha": "9920eadf83b1c802b175b83b10beb717a75b63aa",
3613+ "description": "radv: Implement load_vulkan_descriptor for acceleration structures.",
3614+ "nominated": false,
3615+ "nomination_type": null,
3616+ "resolution": 4,
3617+ "main_sha": null,
3618+ "because_sha": null
3619+ },
3620+ {
3621+ "sha": "85e39cb325abfe09cb4d59e7a2de1976675ec94d",
3622+ "description": "radv: Convert lower_intrinsics to a switch statement",
3623+ "nominated": false,
3624+ "nomination_type": null,
3625+ "resolution": 4,
3626+ "main_sha": null,
3627+ "because_sha": null
3628+ },
3629+ {
3630+ "sha": "a4b3ce5d56e7eb22a7d0f97b4709bef6e16af16e",
3631+ "description": "radv: Add acceleration structure descriptor set support.",
3632+ "nominated": false,
3633+ "nomination_type": null,
3634+ "resolution": 4,
3635+ "main_sha": null,
3636+ "because_sha": null
3637+ },
3638+ {
3639+ "sha": "0dad88b4694cf82664f633187442ec65c14f3812",
3640+ "description": "radv: Implement device-side BVH building.",
3641+ "nominated": false,
3642+ "nomination_type": null,
3643+ "resolution": 4,
3644+ "main_sha": null,
3645+ "because_sha": null
3646+ },
3647+ {
3648+ "sha": "d51a4b4c4b0f1a6c4f73cab026d2f1b42ead547d",
3649+ "description": "radv: Add initial CPU BVH building.",
3650+ "nominated": false,
3651+ "nomination_type": null,
3652+ "resolution": 4,
3653+ "main_sha": null,
3654+ "because_sha": null
3655+ },
3656+ {
3657+ "sha": "67e949a8f80d1458a538b297e786823282bc76ee",
3658+ "description": "radv: Use the global BO list for acceleration structures.",
3659+ "nominated": false,
3660+ "nomination_type": null,
3661+ "resolution": 4,
3662+ "main_sha": null,
3663+ "because_sha": null
3664+ },
3665+ {
3666+ "sha": "f31bfda34abaf5fdd3c31497b476b11f23f728f3",
3667+ "description": "util: Move the 4x4 matrix inverse function to u_math",
3668+ "nominated": false,
3669+ "nomination_type": null,
3670+ "resolution": 4,
3671+ "main_sha": null,
3672+ "because_sha": null
3673+ },
3674+ {
3675+ "sha": "1727adfbc55dab76be75be72aad32d293774c992",
3676+ "description": "freedreno/ci: Increase # of jobs for CI runners",
3677+ "nominated": false,
3678+ "nomination_type": null,
3679+ "resolution": 4,
3680+ "main_sha": null,
3681+ "because_sha": null
3682+ },
3683+ {
3684+ "sha": "fc00abe46c2910449197be0c449f48446a43eefb",
3685+ "description": "freedreno/ci: Start longest traces first",
3686+ "nominated": false,
3687+ "nomination_type": null,
3688+ "resolution": 4,
3689+ "main_sha": null,
3690+ "because_sha": null
3691+ },
3692+ {
3693+ "sha": "714145f54c4dfc9bfcb7af10ee85bbb9e755efff",
3694+ "description": "crocus/gen6: fix depth blit blorp regression.",
3695+ "nominated": false,
3696+ "nomination_type": null,
3697+ "resolution": 4,
3698+ "main_sha": null,
3699+ "because_sha": null
3700+ },
3701+ {
3702+ "sha": "caa5c5b12e50ad85867ff06d4202c786b498ca8f",
3703+ "description": "freedreno/ir3: Move NIR printing to mesa_log.",
3704+ "nominated": false,
3705+ "nomination_type": null,
3706+ "resolution": 4,
3707+ "main_sha": null,
3708+ "because_sha": null
3709+ },
3710+ {
3711+ "sha": "990c23260319fa25f873038f776d8ab1f3f5628e",
3712+ "description": "nir: Add an interface for logging shaders with mesa_log*.",
3713+ "nominated": false,
3714+ "nomination_type": null,
3715+ "resolution": 4,
3716+ "main_sha": null,
3717+ "because_sha": null
3718+ },
3719+ {
3720+ "sha": "88fe7ab4fae7c86457f9473b67dafa6bdd8fe5da",
3721+ "description": "freedreno/ir3: Move the native code output to mesa_log as well.",
3722+ "nominated": false,
3723+ "nomination_type": null,
3724+ "resolution": 4,
3725+ "main_sha": null,
3726+ "because_sha": null
3727+ },
3728+ {
3729+ "sha": "9d458336c647a976dac2aa029fb099533fc7981d",
3730+ "description": "freedreno/ir3: Use mesa_log_stream() for ir3 disassembly.",
3731+ "nominated": false,
3732+ "nomination_type": null,
3733+ "resolution": 4,
3734+ "main_sha": null,
3735+ "because_sha": null
3736+ },
3737+ {
3738+ "sha": "250c127c200f6ccd5463c0af6bc5cd9eb607de94",
3739+ "description": "util/log: Add a streaming printf interface.",
3740+ "nominated": false,
3741+ "nomination_type": null,
3742+ "resolution": 4,
3743+ "main_sha": null,
3744+ "because_sha": null
3745+ },
3746+ {
3747+ "sha": "3863008c22375d9cc1ecfab2a816c49c8787b83f",
3748+ "description": "freedreno/ir3: Move the assert output to mesa_loge().",
3749+ "nominated": false,
3750+ "nomination_type": null,
3751+ "resolution": 4,
3752+ "main_sha": null,
3753+ "because_sha": null
3754+ },
3755+ {
3756+ "sha": "ecf807c900f0412627eb21db92bc30a43e4e46b4",
3757+ "description": "freedreno: Move some driver debug printfs to mesa_logd.",
3758+ "nominated": false,
3759+ "nomination_type": null,
3760+ "resolution": 4,
3761+ "main_sha": null,
3762+ "because_sha": null
3763+ },
3764+ {
3765+ "sha": "caf69b5b778667dbd5d777ac15cc1246ddb16c75",
3766+ "description": "i915g: Add triangle provoking vertex support.",
3767+ "nominated": false,
3768+ "nomination_type": null,
3769+ "resolution": 4,
3770+ "main_sha": null,
3771+ "because_sha": null
3772+ },
3773+ {
3774+ "sha": "ddf5c798d233940264ca3b8ecf7db285ac68958d",
3775+ "description": "docs: update calendar and link releases notes for 21.1.3",
3776+ "nominated": false,
3777+ "nomination_type": null,
3778+ "resolution": 4,
3779+ "main_sha": null,
3780+ "because_sha": null
3781+ },
3782+ {
3783+ "sha": "b8d54b7a713e1665c476a97123aae042e906d10b",
3784+ "description": "docs: add release notes for 21.1.3",
3785+ "nominated": false,
3786+ "nomination_type": null,
3787+ "resolution": 4,
3788+ "main_sha": null,
3789+ "because_sha": null
3790+ },
3791+ {
3792+ "sha": "4f86cd46eb2ae4d48886c4a68cf764fd3c31e9a3",
3793+ "description": "nine: add zink to the build target",
3794+ "nominated": false,
3795+ "nomination_type": null,
3796+ "resolution": 4,
3797+ "main_sha": null,
3798+ "because_sha": null
3799+ },
3800+ {
3801+ "sha": "f91ffe13490e33ad4e8e8c280297f0f56c0f6e6a",
3802+ "description": "nine: only enable tgsi disk cache if the driver supports it",
3803+ "nominated": false,
3804+ "nomination_type": null,
3805+ "resolution": 4,
3806+ "main_sha": null,
3807+ "because_sha": null
3808+ },
3809+ {
3810+ "sha": "977355c6e5efd781dde85d834172dd23cd4852f1",
3811+ "description": "radv: fix dynamic culling and depth/stencil related dynamic states",
3812+ "nominated": true,
3813+ "nomination_type": 0,
3814+ "resolution": 0,
3815+ "main_sha": null,
3816+ "because_sha": null
3817+ },
3818+ {
3819+ "sha": "651c6b16ff09745cb033566bc7910375868027df",
3820+ "description": "radv: move pipe_misaligned and l2_coherent image checks to flags set on init",
3821+ "nominated": false,
3822+ "nomination_type": null,
3823+ "resolution": 4,
3824+ "main_sha": null,
3825+ "because_sha": null
3826+ },
3827+ {
3828+ "sha": "e1af22d9dd7777739fbb5f1198a1dd5748d85964",
3829+ "description": "radeon/vcn: allocate non-tmz context buffer for VCN2+",
3830+ "nominated": false,
3831+ "nomination_type": null,
3832+ "resolution": 4,
3833+ "main_sha": null,
3834+ "because_sha": null
3835+ },
3836+ {
3837+ "sha": "796358e2f56b8444f2d422ea14639945be7c709e",
3838+ "description": "radeon/vcn: move calc_dpb_size into create_decoder",
3839+ "nominated": false,
3840+ "nomination_type": null,
3841+ "resolution": 4,
3842+ "main_sha": null,
3843+ "because_sha": null
3844+ },
3845+ {
3846+ "sha": "b97dedd365fbd8c2e62e0fecc89d01cfc38eb0e6",
3847+ "description": "docs/isl: Add detailed documentation about CCS compression",
3848+ "nominated": false,
3849+ "nomination_type": null,
3850+ "resolution": 4,
3851+ "main_sha": null,
3852+ "because_sha": null
3853+ },
3854+ {
3855+ "sha": "6b15ce9fa2dfcbf0a421a6846727cbce279492a7",
3856+ "description": "docs/isl: Add detailed documentation about tiling on Intel GPUs",
3857+ "nominated": false,
3858+ "nomination_type": null,
3859+ "resolution": 4,
3860+ "main_sha": null,
3861+ "because_sha": null
3862+ },
3863+ {
3864+ "sha": "0f6ebd2b73207845be0f01d49c22b0a48c7ff367",
3865+ "description": "docs/isl: Add detailed documentation about isl formats",
3866+ "nominated": false,
3867+ "nomination_type": null,
3868+ "resolution": 4,
3869+ "main_sha": null,
3870+ "because_sha": null
3871+ },
3872+ {
3873+ "sha": "3894e42590a79551541819185fbf0161990f7953",
3874+ "description": "docs/isl: Document ISL's units",
3875+ "nominated": false,
3876+ "nomination_type": null,
3877+ "resolution": 4,
3878+ "main_sha": null,
3879+ "because_sha": null
3880+ },
3881+ {
3882+ "sha": "d07ec294bb3e86a7a7f896f2d417ceffff093b1c",
3883+ "description": "isl: Document more members of isl_surf",
3884+ "nominated": false,
3885+ "nomination_type": null,
3886+ "resolution": 4,
3887+ "main_sha": null,
3888+ "because_sha": null
3889+ },
3890+ {
3891+ "sha": "831750b40b67ed07b7473d17531f70fb23b4e9b5",
3892+ "description": "docs: Begin documenting ISL",
3893+ "nominated": false,
3894+ "nomination_type": null,
3895+ "resolution": 4,
3896+ "main_sha": null,
3897+ "because_sha": null
3898+ },
3899+ {
3900+ "sha": "d3a63149dadcf9aa5b34a4cab884a233a6d6c75c",
3901+ "description": "zink: remove inlinable_uniforms_dirty_mask",
3902+ "nominated": false,
3903+ "nomination_type": null,
3904+ "resolution": 4,
3905+ "main_sha": null,
3906+ "because_sha": null
3907+ },
3908+ {
3909+ "sha": "78f820acd7d438f1864fbc76a93ac76a88042f37",
3910+ "description": "zink: remove duplicated bitflag filtering for inline uniforms",
3911+ "nominated": false,
3912+ "nomination_type": null,
3913+ "resolution": 4,
3914+ "main_sha": null,
3915+ "because_sha": null
3916+ },
3917+ {
3918+ "sha": "60348360a2dbecc27afe10fca36122976c7057d8",
3919+ "description": "radv: create only one pipeline for decompressing depth/stencil images",
3920+ "nominated": false,
3921+ "nomination_type": null,
3922+ "resolution": 4,
3923+ "main_sha": null,
3924+ "because_sha": null
3925+ },
3926+ {
3927+ "sha": "213c4c5f44f0f731a2c7538405612eea81f874fa",
3928+ "description": "radv: always decompress both aspects of a depth/stencil image",
3929+ "nominated": true,
3930+ "nomination_type": 0,
3931+ "resolution": 1,
3932+ "main_sha": null,
3933+ "because_sha": null
3934+ },
3935+ {
3936+ "sha": "50233d0daa3ca444a1f1caf6e9eab1144d28530d",
3937+ "description": "radv: reject binding buffer/image when the device memory is too small",
3938+ "nominated": true,
3939+ "nomination_type": 0,
3940+ "resolution": 1,
3941+ "main_sha": null,
3942+ "because_sha": null
3943+ },
3944+ {
3945+ "sha": "66dbd16f38e6acccb9ba3ba02d0f9bbb18e4e3b1",
3946+ "description": "radeonsi: skip instance_count==0 draws on <= GFX9",
3947+ "nominated": true,
3948+ "nomination_type": 0,
3949+ "resolution": 1,
3950+ "main_sha": null,
3951+ "because_sha": null
3952+ },
3953+ {
3954+ "sha": "2624765e66efbedd65841a11d68d3bd4a3baccbe",
3955+ "description": "nvc0/ir: Initialize Limits members in constructor.",
3956+ "nominated": false,
3957+ "nomination_type": null,
3958+ "resolution": 4,
3959+ "main_sha": null,
3960+ "because_sha": null
3961+ },
3962+ {
3963+ "sha": "5f771134ad07fc8c3755ba36b294cbf49259998e",
3964+ "description": "intel/vec4: Add missing break statement.",
3965+ "nominated": false,
3966+ "nomination_type": 1,
3967+ "resolution": 4,
3968+ "main_sha": null,
3969+ "because_sha": "89fd196f6b5e80fd4082ed5842e51b944907eff3"
3970+ },
3971+ {
3972+ "sha": "2b3fc26da8bed1f70f6631a3fc6c6cd43fe2acc2",
3973+ "description": "i915g: Switch to using nir-to-tgsi.",
3974+ "nominated": false,
3975+ "nomination_type": null,
3976+ "resolution": 4,
3977+ "main_sha": null,
3978+ "because_sha": null
3979+ },
3980+ {
3981+ "sha": "934d2c8f7f51d6e148e2b034e88a5eb6e1b9c98a",
3982+ "description": "i915g: Handle fragment depth being in OUT[1] not OUT[0].",
3983+ "nominated": false,
3984+ "nomination_type": null,
3985+ "resolution": 4,
3986+ "main_sha": null,
3987+ "because_sha": null
3988+ },
3989+ {
3990+ "sha": "026452fe466f2537ce2496efd008b16d1be5053b",
3991+ "description": "nir_to_tgsi: Support integer sysvals on !CAP_INTEGERS hardware.",
3992+ "nominated": false,
3993+ "nomination_type": null,
3994+ "resolution": 4,
3995+ "main_sha": null,
3996+ "because_sha": null
3997+ },
3998+ {
3999+ "sha": "baa8d33908cd640ef1e5c7efca931d43a46cd9f5",
4000+ "description": "nir_to_tgsi: Fix internal handling of NIR uints for !CAP_INTEGERS",
4001+ "nominated": false,
4002+ "nomination_type": null,
4003+ "resolution": 4,
4004+ "main_sha": null,
4005+ "because_sha": null
4006+ },
4007+ {
4008+ "sha": "47804f53f991c3467671e05421df437b0f34eb22",
4009+ "description": "nir: Do peephole select on other instructions if the limit is ~0.",
4010+ "nominated": false,
4011+ "nomination_type": null,
4012+ "resolution": 4,
4013+ "main_sha": null,
4014+ "because_sha": null
4015+ },
4016+ {
4017+ "sha": "aba8b6675ae3ddc136f4f48cbabb7d3e24c6d58b",
4018+ "description": "nir/lower_int_to_float: Make sure the cursor is in the right spot.",
4019+ "nominated": false,
4020+ "nomination_type": null,
4021+ "resolution": 4,
4022+ "main_sha": null,
4023+ "because_sha": null
4024+ },
4025+ {
4026+ "sha": "31ab2735dbc64c5d67b7db3ef75e9fd5969f4b2a",
4027+ "description": "i915g: Allow fragment coord conventions TGSI properties to be set.",
4028+ "nominated": false,
4029+ "nomination_type": null,
4030+ "resolution": 4,
4031+ "main_sha": null,
4032+ "because_sha": null
4033+ },
4034+ {
4035+ "sha": "942f62a9b28f9afc32185506b0a9bbf770287f84",
4036+ "description": "i915: Drop assertion failure about seeing each const decled once.",
4037+ "nominated": false,
4038+ "nomination_type": null,
4039+ "resolution": 4,
4040+ "main_sha": null,
4041+ "because_sha": null
4042+ },
4043+ {
4044+ "sha": "7378c6479278983de7f1f39902aade0567a53965",
4045+ "description": "i915: Disable vertex texturing and delete the code.",
4046+ "nominated": false,
4047+ "nomination_type": null,
4048+ "resolution": 4,
4049+ "main_sha": null,
4050+ "because_sha": null
4051+ },
4052+ {
4053+ "sha": "87f35032a664c6b93cde40777f5c587d3312d716",
4054+ "description": "anv: enable multi-planar support for drm format modifier",
4055+ "nominated": false,
4056+ "nomination_type": null,
4057+ "resolution": 4,
4058+ "main_sha": null,
4059+ "because_sha": null
4060+ },
4061+ {
4062+ "sha": "ec70092d55c913a9a24f21d184511bf65fc2ae65",
4063+ "description": "anv: support multi-planar format in add_all_surfaces_explicit_layout",
4064+ "nominated": false,
4065+ "nomination_type": null,
4066+ "resolution": 4,
4067+ "main_sha": null,
4068+ "because_sha": null
4069+ },
4070+ {
4071+ "sha": "345a4e987104406a6fb8145c841f92dadaf0b270",
4072+ "description": "anv: fix some log formats",
4073+ "nominated": false,
4074+ "nomination_type": null,
4075+ "resolution": 4,
4076+ "main_sha": null,
4077+ "because_sha": null
4078+ },
4079+ {
4080+ "sha": "6bce24e214050686c510beed5221c1259a498bb2",
4081+ "description": "freedreno: Add some cheza flakes from the last week.",
4082+ "nominated": false,
4083+ "nomination_type": null,
4084+ "resolution": 4,
4085+ "main_sha": null,
4086+ "because_sha": null
4087+ },
4088+ {
4089+ "sha": "df7fdae127a78f400f5827bd88c6db89dada6da6",
4090+ "description": "freedreno: Skip staging blits from uninitialized resources.",
4091+ "nominated": false,
4092+ "nomination_type": null,
4093+ "resolution": 4,
4094+ "main_sha": null,
4095+ "because_sha": null
4096+ },
4097+ {
4098+ "sha": "4018c5f928b01c1536a7361c0f04bbf314a1f598",
4099+ "description": "freedreno: Add more detailed blit debug in FD_MESA_DEBUG=msgs.",
4100+ "nominated": false,
4101+ "nomination_type": null,
4102+ "resolution": 4,
4103+ "main_sha": null,
4104+ "because_sha": null
4105+ },
4106+ {
4107+ "sha": "8effbeeea6f7b2de29bc9e9a85dc96fe15adf51c",
4108+ "description": "freedreno/fdl: Give the tiling mode a nice name in debug dumps.",
4109+ "nominated": false,
4110+ "nomination_type": null,
4111+ "resolution": 4,
4112+ "main_sha": null,
4113+ "because_sha": null
4114+ },
4115+ {
4116+ "sha": "57da290b52aeb411082ea1d594818b6662c23c38",
4117+ "description": "freedreno: Move FD_MESA_DEBUG=msgs output to mesa_logi.",
4118+ "nominated": false,
4119+ "nomination_type": null,
4120+ "resolution": 4,
4121+ "main_sha": null,
4122+ "because_sha": null
4123+ },
4124+ {
4125+ "sha": "d4203bf7abaa24ad20d76267a663668600b45f40",
4126+ "description": "freedreno: Add perf_debug() for our software conditional rendering.",
4127+ "nominated": false,
4128+ "nomination_type": null,
4129+ "resolution": 4,
4130+ "main_sha": null,
4131+ "because_sha": null
4132+ },
4133+ {
4134+ "sha": "6402dc17b3836dbe11dacad57a566b80c2d0db9c",
4135+ "description": "freedreno: Defer freeing batch->key",
4136+ "nominated": false,
4137+ "nomination_type": 1,
4138+ "resolution": 4,
4139+ "main_sha": null,
4140+ "because_sha": "507f701d9e89b891fdfa03ad23dc73acf3c5c6b4"
4141+ },
4142+ {
4143+ "sha": "64cb143b922b4c074a8404359e7ed9b790941744",
4144+ "description": "spirv: Fix handling of OpBranchConditional with same THEN and ELSE",
4145+ "nominated": true,
4146+ "nomination_type": 1,
4147+ "resolution": 1,
4148+ "main_sha": null,
4149+ "because_sha": "9c2a11430e101b820ce8d605f3cc5b0593bb4c5e"
4150+ },
4151+ {
4152+ "sha": "38e8d7afe30bb33218191ac681607de48753fbae",
4153+ "description": "pan/mdg: Fix reading a spilt register in the bundle it's written",
4154+ "nominated": true,
4155+ "nomination_type": 0,
4156+ "resolution": 1,
4157+ "main_sha": null,
4158+ "because_sha": null
4159+ },
4160+ {
4161+ "sha": "31d26ebf1b9d0f819c894aec10c29a44052a995a",
4162+ "description": "pan/mdg: Fill from TLS before spilling non-SSA nodes",
4163+ "nominated": true,
4164+ "nomination_type": 0,
4165+ "resolution": 1,
4166+ "main_sha": null,
4167+ "because_sha": null
4168+ },
4169+ {
4170+ "sha": "ed9a9a09f2899baadbcf700352a70df677f658ef",
4171+ "description": "pan/mdg: Reorder some code in mir_spill_register",
4172+ "nominated": true,
4173+ "nomination_type": 0,
4174+ "resolution": 1,
4175+ "main_sha": null,
4176+ "because_sha": null
4177+ },
4178+ {
4179+ "sha": "1490e7e622d1b3ffe35ad9f577f13744497c0169",
4180+ "description": "pan/mdg: Add a bundle ID to instructions",
4181+ "nominated": true,
4182+ "nomination_type": 0,
4183+ "resolution": 1,
4184+ "main_sha": null,
4185+ "because_sha": null
4186+ },
4187+ {
4188+ "sha": "3e3ec5989591cb97d45910a80f685870c6c82935",
4189+ "description": "freedreno/a6xx: Skip nv_copy_image tests",
4190+ "nominated": false,
4191+ "nomination_type": null,
4192+ "resolution": 4,
4193+ "main_sha": null,
4194+ "because_sha": null
4195+ },
4196+ {
4197+ "sha": "fff2aa46a7be9cd3af7a22c812e86de58455ce3f",
4198+ "description": "freedreno/a6xx: Flip on copy_image",
4199+ "nominated": false,
4200+ "nomination_type": null,
4201+ "resolution": 4,
4202+ "main_sha": null,
4203+ "because_sha": null
4204+ },
4205+ {
4206+ "sha": "6ca9f4f5ca686527f7ec2fcc0051f5c5dbe1df1a",
4207+ "description": "freedreno: Fix for multi-draw blits",
4208+ "nominated": false,
4209+ "nomination_type": null,
4210+ "resolution": 4,
4211+ "main_sha": null,
4212+ "because_sha": null
4213+ },
4214+ {
4215+ "sha": "9629f3aa4632f8379631a44b95f7394fdce25fa0",
4216+ "description": "freedreno/a6xx: Handle u/snorm vs u/sint validation",
4217+ "nominated": false,
4218+ "nomination_type": null,
4219+ "resolution": 4,
4220+ "main_sha": null,
4221+ "because_sha": null
4222+ },
4223+ {
4224+ "sha": "678e4842cca21c5098b0f458464375dac5153897",
4225+ "description": "freedreno/a6xx: Use UNORM for SNORM copy blits",
4226+ "nominated": false,
4227+ "nomination_type": null,
4228+ "resolution": 4,
4229+ "main_sha": null,
4230+ "because_sha": null
4231+ },
4232+ {
4233+ "sha": "70d571e558cb6e32e8631ca51f98920d4dfaeeba",
4234+ "description": "freedreno/blitter: Flush before self-blits",
4235+ "nominated": false,
4236+ "nomination_type": null,
4237+ "resolution": 4,
4238+ "main_sha": null,
4239+ "because_sha": null
4240+ },
4241+ {
4242+ "sha": "2f29425a0ac345e037a72bc62a5065cfd1e64db9",
4243+ "description": "freedreno: Fix flushes with NULL batch",
4244+ "nominated": false,
4245+ "nomination_type": null,
4246+ "resolution": 4,
4247+ "main_sha": null,
4248+ "because_sha": null
4249+ },
4250+ {
4251+ "sha": "4c67924251292106963afa4f27639fe5d3c32eef",
4252+ "description": "intel/nir: Fix txs for null surfaces",
4253+ "nominated": true,
4254+ "nomination_type": 1,
4255+ "resolution": 1,
4256+ "main_sha": null,
4257+ "because_sha": "05a37e2422080278a668f048cd8bc7a0e4d5d644"
4258+ },
4259+ {
4260+ "sha": "ac9ae97d304c5050262285db6d2fe4897a932653",
4261+ "description": "freedreno: Flush batches upon destroying the ctx.",
4262+ "nominated": false,
4263+ "nomination_type": null,
4264+ "resolution": 4,
4265+ "main_sha": null,
4266+ "because_sha": null
4267+ },
4268+ {
4269+ "sha": "2a9225d05f544925cd8f92fff41af61f71a69dfa",
4270+ "description": "freedreno: Remove broken back_blit optimization.",
4271+ "nominated": false,
4272+ "nomination_type": null,
4273+ "resolution": 4,
4274+ "main_sha": null,
4275+ "because_sha": null
4276+ },
4277+ {
4278+ "sha": "09e1fb2bceb650d700bf94f668c116ec93a58319",
4279+ "description": "freedreno: Move the !MAP_WRITE write batch refcounting to the branch.",
4280+ "nominated": false,
4281+ "nomination_type": null,
4282+ "resolution": 4,
4283+ "main_sha": null,
4284+ "because_sha": null
4285+ },
4286+ {
4287+ "sha": "fd571565d2c71c47a6894e31db84f2150b5f3e86",
4288+ "description": "freedreno: Fix batch reference handling in flush_resource().",
4289+ "nominated": false,
4290+ "nomination_type": null,
4291+ "resolution": 4,
4292+ "main_sha": null,
4293+ "because_sha": null
4294+ },
4295+ {
4296+ "sha": "cf2747e7ace0a62e18e7f0910af1ab1d4f5e1019",
4297+ "description": "v3dv: implement VK_EXT_index_type_uint8",
4298+ "nominated": false,
4299+ "nomination_type": null,
4300+ "resolution": 4,
4301+ "main_sha": null,
4302+ "because_sha": null
4303+ },
4304+ {
4305+ "sha": "d9c53c50ad37fd8474baced71d14d52e6b7ddbf6",
4306+ "description": "v3dv: enable ASTC formats",
4307+ "nominated": false,
4308+ "nomination_type": null,
4309+ "resolution": 4,
4310+ "main_sha": null,
4311+ "because_sha": null
4312+ },
4313+ {
4314+ "sha": "26a7afc94fae80a105d877d2372b3c20b07461b2",
4315+ "description": "v3dv: add ASTC formats to get_compatible_tlb_format",
4316+ "nominated": false,
4317+ "nomination_type": null,
4318+ "resolution": 4,
4319+ "main_sha": null,
4320+ "because_sha": null
4321+ },
4322+ {
4323+ "sha": "56bf92ff0b15db77e34a5382fdd047c7dc2a42fe",
4324+ "description": "v3dv: divide by block size in copy_image_blit",
4325+ "nominated": false,
4326+ "nomination_type": null,
4327+ "resolution": 4,
4328+ "main_sha": null,
4329+ "because_sha": null
4330+ },
4331+ {
4332+ "sha": "6756f55c842b98a27f41714b89b39301c4abc1de",
4333+ "description": "v3dv: add the unswizzled RGBA4444 format",
4334+ "nominated": false,
4335+ "nomination_type": null,
4336+ "resolution": 4,
4337+ "main_sha": null,
4338+ "because_sha": null
4339+ },
4340+ {
4341+ "sha": "8aaa08844fcdefb5d3ca9af871ead70ac7bef282",
4342+ "description": "r600/sfn: Clean up some ALU lowering and move code",
4343+ "nominated": false,
4344+ "nomination_type": null,
4345+ "resolution": 4,
4346+ "main_sha": null,
4347+ "because_sha": null
4348+ },
4349+ {
4350+ "sha": "82c076d2c3147d632e951bc143a65d79ca183113",
4351+ "description": "r600/sfn: Don't read return values of atomic ops that are not used",
4352+ "nominated": false,
4353+ "nomination_type": null,
4354+ "resolution": 4,
4355+ "main_sha": null,
4356+ "because_sha": null
4357+ },
4358+ {
4359+ "sha": "800bfefde58924826889756288326f24acf27e2d",
4360+ "description": "r600/sfn: Drop method for emit_atomic_add, it is handled in generic code",
4361+ "nominated": false,
4362+ "nomination_type": null,
4363+ "resolution": 4,
4364+ "main_sha": null,
4365+ "because_sha": null
4366+ },
4367+ {
4368+ "sha": "2e8901a07228d235bedc50cf69613e35183a4fac",
4369+ "description": "r600/sfn: don't read back unused image atomic result values",
4370+ "nominated": false,
4371+ "nomination_type": null,
4372+ "resolution": 4,
4373+ "main_sha": null,
4374+ "because_sha": null
4375+ },
4376+ {
4377+ "sha": "5e1a7039340cdabb4fcef63a1bd24bb927031810",
4378+ "description": "r600/sfn: don't designates initializers, since they are c++20",
4379+ "nominated": false,
4380+ "nomination_type": null,
4381+ "resolution": 4,
4382+ "main_sha": null,
4383+ "because_sha": null
4384+ },
4385+ {
4386+ "sha": "f9d8d9acbb6a620684fb4dac4affe25816587d92",
4387+ "description": "iris: Avoid abort() if kernel can't allocate memory",
4388+ "nominated": false,
4389+ "nomination_type": null,
4390+ "resolution": 4,
4391+ "main_sha": null,
4392+ "because_sha": null
4393+ },
4394+ {
4395+ "sha": "d873e30d3b29582880b23a34e047d965849ae590",
4396+ "description": "v3dv: expose VK_KHR_shader_non_semantic_info",
4397+ "nominated": false,
4398+ "nomination_type": null,
4399+ "resolution": 4,
4400+ "main_sha": null,
4401+ "because_sha": null
4402+ },
4403+ {
4404+ "sha": "0fd152dab3db152c8734b5ee0e312cab4257cd04",
4405+ "description": "disk_cache: use UTIL_QUEUE_INIT_SCALE_THREADS",
4406+ "nominated": false,
4407+ "nomination_type": null,
4408+ "resolution": 4,
4409+ "main_sha": null,
4410+ "because_sha": null
4411+ },
4412+ {
4413+ "sha": "3713dc6b2a7472a838885b9ff1e4e07f9b9b7713",
4414+ "description": "util/u_queue: add UTIL_QUEUE_INIT_SCALE_THREADS flag",
4415+ "nominated": false,
4416+ "nomination_type": null,
4417+ "resolution": 4,
4418+ "main_sha": null,
4419+ "because_sha": null
4420+ },
4421+ {
4422+ "sha": "0c88df1f6a524c52c8d893ed8db2cff01e8bd14a",
4423+ "description": "util/u_queue: move function definition up",
4424+ "nominated": false,
4425+ "nomination_type": null,
4426+ "resolution": 4,
4427+ "main_sha": null,
4428+ "because_sha": null
4429+ },
4430+ {
4431+ "sha": "edb77ec3c770135280cc321326c7924b73fb535c",
4432+ "description": "radeonsi: delay sample_pos_buffer creation until first use",
4433+ "nominated": false,
4434+ "nomination_type": null,
4435+ "resolution": 4,
4436+ "main_sha": null,
4437+ "because_sha": null
4438+ },
4439+ {
4440+ "sha": "84dca32c51e9f70b20515afd304826091c775a92",
4441+ "description": "vbo: delay vbo_exec_vtx_map call",
4442+ "nominated": false,
4443+ "nomination_type": null,
4444+ "resolution": 4,
4445+ "main_sha": null,
4446+ "because_sha": null
4447+ },
4448+ {
4449+ "sha": "3333a96b6fed7020c70af5809c791a3875b5b19a",
4450+ "description": "nvc0/ir: Initialize CodeEmitterNVC0 member progType in constructor.",
4451+ "nominated": false,
4452+ "nomination_type": null,
4453+ "resolution": 4,
4454+ "main_sha": null,
4455+ "because_sha": null
4456+ },
4457+ {
4458+ "sha": "849ab4ea0caf9e2ce3d4bb5d2f1308edff9913fd",
4459+ "description": "mesa: execute glFlush asynchronously if no image has been imported/exported",
4460+ "nominated": false,
4461+ "nomination_type": null,
4462+ "resolution": 4,
4463+ "main_sha": null,
4464+ "because_sha": null
4465+ },
4466+ {
4467+ "sha": "0336b13e1e6307429efdf560d523727d88d556aa",
4468+ "description": "mesa: move _mesa_notifySwapBuffers into the x11 swrast driver",
4469+ "nominated": false,
4470+ "nomination_type": null,
4471+ "resolution": 4,
4472+ "main_sha": null,
4473+ "because_sha": null
4474+ },
4475+ {
4476+ "sha": "b7dc72380a474aeb3ff7179536727391116a3448",
4477+ "description": "mesa: add gallium flush_flags param into ctx->Driver.Flush",
4478+ "nominated": false,
4479+ "nomination_type": null,
4480+ "resolution": 4,
4481+ "main_sha": null,
4482+ "because_sha": null
4483+ },
4484+ {
4485+ "sha": "ee6929a77986f6933d6e9717f8f5ada379248db4",
4486+ "description": "st/mesa: move the st_flush_bitmap_cache call into st_flush",
4487+ "nominated": false,
4488+ "nomination_type": null,
4489+ "resolution": 4,
4490+ "main_sha": null,
4491+ "because_sha": null
4492+ },
4493+ {
4494+ "sha": "37bf4184db5c85a92266ae604d87b59fc9797022",
4495+ "description": "st/mesa: fix an incorrect comment in st_context_flush",
4496+ "nominated": false,
4497+ "nomination_type": null,
4498+ "resolution": 4,
4499+ "main_sha": null,
4500+ "because_sha": null
4501+ },
4502+ {
4503+ "sha": "3da170faaec2a57d76e668ab56781621c23c6703",
4504+ "description": "glthread: change when glFlush flushes asynchronously",
4505+ "nominated": false,
4506+ "nomination_type": null,
4507+ "resolution": 4,
4508+ "main_sha": null,
4509+ "because_sha": null
4510+ },
4511+ {
4512+ "sha": "0510a947ba287f8b416601fcbc64512164b2918e",
4513+ "description": "anv: Fix dynamic primitive topology for tess on Gfx7.x too",
4514+ "nominated": true,
4515+ "nomination_type": 1,
4516+ "resolution": 1,
4517+ "main_sha": null,
4518+ "because_sha": "24342e499bc58348b257716f629dccca3c1b0833"
4519+ },
4520+ {
4521+ "sha": "9908da1b7a5eaf0156d458e0e24b694c070ba345",
4522+ "description": "Add default driver selections for RISC-V",
4523+ "nominated": false,
4524+ "nomination_type": null,
4525+ "resolution": 4,
4526+ "main_sha": null,
4527+ "because_sha": null
4528+ },
4529+ {
4530+ "sha": "0ea8becff0b117dd626a004331da11c8508f84bb",
4531+ "description": "zink: always defer image descriptor barriers",
4532+ "nominated": false,
4533+ "nomination_type": null,
4534+ "resolution": 4,
4535+ "main_sha": null,
4536+ "because_sha": null
4537+ },
4538+ {
4539+ "sha": "5341b985e49a5e79468c4a55c3bb02bbf4542007",
4540+ "description": "zink: use fake buffer barriers for descriptors",
4541+ "nominated": false,
4542+ "nomination_type": null,
4543+ "resolution": 4,
4544+ "main_sha": null,
4545+ "because_sha": null
4546+ },
4547+ {
4548+ "sha": "3c2f343618535bf9833111adb47c8e83f30810bc",
4549+ "description": "zink: check actual mem props to determine if resource object is coherent",
4550+ "nominated": false,
4551+ "nomination_type": null,
4552+ "resolution": 4,
4553+ "main_sha": null,
4554+ "because_sha": null
4555+ },
4556+ {
4557+ "sha": "b1b6aecf9d14eccd386378a138ae04eae1ccabfb",
4558+ "description": "zink: key alloc cache on heap index, not heap flags",
4559+ "nominated": false,
4560+ "nomination_type": null,
4561+ "resolution": 4,
4562+ "main_sha": null,
4563+ "because_sha": null
4564+ },
4565+ {
4566+ "sha": "c56a10049419401f3b28dc74d18bf6ecb82081b2",
4567+ "description": "zink: avoid caching visible vram allocations",
4568+ "nominated": false,
4569+ "nomination_type": null,
4570+ "resolution": 4,
4571+ "main_sha": null,
4572+ "because_sha": null
4573+ },
4574+ {
4575+ "sha": "18b71c0da33c31fdb2b104b27e8a7b169ce3a0bb",
4576+ "description": "zink: change a bunch of sparse buffer resource checks to host-visible checks",
4577+ "nominated": false,
4578+ "nomination_type": null,
4579+ "resolution": 4,
4580+ "main_sha": null,
4581+ "because_sha": null
4582+ },
4583+ {
4584+ "sha": "5fee58bf599cb525c9251b5f4ceed5db85803c8f",
4585+ "description": "zink: collapse host_visible and non-coherent alignment alloc cases",
4586+ "nominated": false,
4587+ "nomination_type": null,
4588+ "resolution": 4,
4589+ "main_sha": null,
4590+ "because_sha": null
4591+ },
4592+ {
4593+ "sha": "eb272f65715c21c38c0dc0f5a84f431851aa87d0",
4594+ "description": "compiler/glsl: Use mutex lock while freeing up mem_ctx",
4595+ "nominated": true,
4596+ "nomination_type": 1,
4597+ "resolution": 1,
4598+ "main_sha": null,
4599+ "because_sha": "e4da8b9c331cc3ae1b86b3a7860231e202463db0"
4600+ },
4601+ {
4602+ "sha": "4a407e0ad8801cc822666f41591094b2cbb2e826",
4603+ "description": "zink: mark some functions inline",
4604+ "nominated": false,
4605+ "nomination_type": null,
4606+ "resolution": 4,
4607+ "main_sha": null,
4608+ "because_sha": null
4609+ },
4610+ {
4611+ "sha": "e19f1124353bf0c76072d8687bb93b78fd2970cf",
4612+ "description": "ir3/ra: Fix array parallelcopy confusion",
4613+ "nominated": false,
4614+ "nomination_type": 1,
4615+ "resolution": 4,
4616+ "main_sha": null,
4617+ "because_sha": "0ffcb19b9d9fbe902224542047c389a661fbf816"
4618+ },
4619+ {
4620+ "sha": "2c21dab36e55eaa3f6b083bc5c3bc0573321fdb5",
4621+ "description": "ir3: Improve printing of array parallelcopies/phis",
4622+ "nominated": false,
4623+ "nomination_type": null,
4624+ "resolution": 4,
4625+ "main_sha": null,
4626+ "because_sha": null
4627+ },
4628+ {
4629+ "sha": "d0d2108425409defa25a13cb519a0ab7604a3bcb",
4630+ "description": "shader_enums: change VERT_BIT back to the 32-bit shift",
4631+ "nominated": false,
4632+ "nomination_type": null,
4633+ "resolution": 4,
4634+ "main_sha": null,
4635+ "because_sha": null
4636+ },
4637+ {
4638+ "sha": "45cbb08848e6c1f0219a225e0bd637c330b8d38d",
4639+ "description": "gallium/pb: change alignment to 32 bits",
4640+ "nominated": false,
4641+ "nomination_type": null,
4642+ "resolution": 4,
4643+ "main_sha": null,
4644+ "because_sha": null
4645+ },
4646+ {
4647+ "sha": "97a57538121ecda139881ea5068c1922d582ad4a",
4648+ "description": "radeonsi: remove -Wstrict-overflow=0 since it doesn't seem to be needed",
4649+ "nominated": false,
4650+ "nomination_type": null,
4651+ "resolution": 4,
4652+ "main_sha": null,
4653+ "because_sha": null
4654+ },
4655+ {
4656+ "sha": "72a395b6de004d92c5fcc15873248682d6d5582a",
4657+ "description": "radeonsi: remove the chip_class dimension from the draw_vbo array",
4658+ "nominated": false,
4659+ "nomination_type": null,
4660+ "resolution": 4,
4661+ "main_sha": null,
4662+ "because_sha": null
4663+ },
4664+ {
4665+ "sha": "1e4d91355fa9716de2432fe1f3ff93ce1de0cfd2",
4666+ "description": "radeonsi: compile si_state_draw.cpp for each gfx generation separately",
4667+ "nominated": false,
4668+ "nomination_type": null,
4669+ "resolution": 4,
4670+ "main_sha": null,
4671+ "because_sha": null
4672+ },
4673+ {
4674+ "sha": "24895f020a11caaa2a7c7f49889d633f4e712a7c",
4675+ "description": "radeonsi: move a few functions from si_state_draw.cpp into si_gfx_cs.c",
4676+ "nominated": false,
4677+ "nomination_type": null,
4678+ "resolution": 4,
4679+ "main_sha": null,
4680+ "because_sha": null
4681+ },
4682+ {
4683+ "sha": "b8ce8530a0fe4cded04f4041ba99108c173730c2",
4684+ "description": "venus: remove workarounds for multi-planar format interop",
4685+ "nominated": false,
4686+ "nomination_type": null,
4687+ "resolution": 4,
4688+ "main_sha": null,
4689+ "because_sha": null
4690+ },
4691+ {
4692+ "sha": "357e7ae30b6aae492abeb5f16e57ea8df2792ec2",
4693+ "description": "anv: fix build errors after commit 8b7ff78",
4694+ "nominated": false,
4695+ "nomination_type": null,
4696+ "resolution": 4,
4697+ "main_sha": null,
4698+ "because_sha": null
4699+ },
4700+ {
4701+ "sha": "ec1968dcc99f38a4a9ac2089373548a668e446b7",
4702+ "description": "radv: fix build errors after commit 8b7ff784",
4703+ "nominated": false,
4704+ "nomination_type": null,
4705+ "resolution": 4,
4706+ "main_sha": null,
4707+ "because_sha": null
4708+ },
4709+ {
4710+ "sha": "25972df4b796c0363441317a184d9c63e693e491",
4711+ "description": "zink: ci updates",
4712+ "nominated": false,
4713+ "nomination_type": null,
4714+ "resolution": 4,
4715+ "main_sha": null,
4716+ "because_sha": null
4717+ },
4718+ {
4719+ "sha": "d0833f611a22f4be4d1f2e5c4ba8c395552902f8",
4720+ "description": "zink: support more RGBX formats",
4721+ "nominated": false,
4722+ "nomination_type": null,
4723+ "resolution": 4,
4724+ "main_sha": null,
4725+ "because_sha": null
4726+ },
4727+ {
4728+ "sha": "1e86cdd8b7b9b817735e453dacd116473a829e00",
4729+ "description": "zink: also nope out of any dst alpha blends for rgbx formats",
4730+ "nominated": false,
4731+ "nomination_type": null,
4732+ "resolution": 4,
4733+ "main_sha": null,
4734+ "because_sha": null
4735+ },
4736+ {
4737+ "sha": "f091392c0d5412718b589310761b757f58ed4475",
4738+ "description": "zink: smash dstAlphaBlendFactor to ZERO for RGBX attachments",
4739+ "nominated": false,
4740+ "nomination_type": null,
4741+ "resolution": 4,
4742+ "main_sha": null,
4743+ "because_sha": null
4744+ },
4745+ {
4746+ "sha": "2f2976e9e1c2f4a2258d4710cdb27d011e246c5b",
4747+ "description": "zink: add a more direct check for rgbx formats in create_sampler_view hook",
4748+ "nominated": false,
4749+ "nomination_type": null,
4750+ "resolution": 4,
4751+ "main_sha": null,
4752+ "because_sha": null
4753+ },
4754+ {
4755+ "sha": "a3a6611e96fba9a519046acf4918099f600dca92",
4756+ "description": "util/queue: add a global data pointer for the queue object",
4757+ "nominated": false,
4758+ "nomination_type": null,
4759+ "resolution": 4,
4760+ "main_sha": null,
4761+ "because_sha": null
4762+ },
4763+ {
4764+ "sha": "d305a8fc5f72328a583d5db9604f412428679fa4",
4765+ "description": "radeonsi: set desc[3] of all buffer descriptors at context creation",
4766+ "nominated": false,
4767+ "nomination_type": null,
4768+ "resolution": 4,
4769+ "main_sha": null,
4770+ "because_sha": null
4771+ },
4772+ {
4773+ "sha": "42801731b8d32441f65f16a0757ed72d7c213985",
4774+ "description": "radeonsi: remove no-op unref in si_set_constant_buffer",
4775+ "nominated": false,
4776+ "nomination_type": null,
4777+ "resolution": 4,
4778+ "main_sha": null,
4779+ "because_sha": null
4780+ },
4781+ {
4782+ "sha": "a29ff4c67ec03105e6d2549b386099dcc3a347df",
4783+ "description": "radeonsi: restructure si_set_sampler_views for faster unbinding trailing slots",
4784+ "nominated": false,
4785+ "nomination_type": null,
4786+ "resolution": 4,
4787+ "main_sha": null,
4788+ "because_sha": null
4789+ },
4790+ {
4791+ "sha": "10cf7b30314a14428d0584a5383305940d4a6144",
4792+ "description": "radeonsi: don't clear register fields in si_set_mutable_tex_desc_fields",
4793+ "nominated": false,
4794+ "nomination_type": null,
4795+ "resolution": 4,
4796+ "main_sha": null,
4797+ "because_sha": null
4798+ },
4799+ {
4800+ "sha": "810e84387b4ebcafcdf9d22a4d8de313c02e1404",
4801+ "description": "radeonsi: use the restrict keyword to set sampler view descriptors faster",
4802+ "nominated": false,
4803+ "nomination_type": null,
4804+ "resolution": 4,
4805+ "main_sha": null,
4806+ "because_sha": null
4807+ },
4808+ {
4809+ "sha": "53853d0b27c1a9609cb2701c59944a91d1f76db2",
4810+ "description": "radeonsi: check is_buffer once instead of 4 times in si_set_sampler_view_desc",
4811+ "nominated": false,
4812+ "nomination_type": null,
4813+ "resolution": 4,
4814+ "main_sha": null,
4815+ "because_sha": null
4816+ },
4817+ {
4818+ "sha": "a8fc38b276fcdcf3c5f3d3ea0351843c7e8e38c3",
4819+ "description": "zink: do not check buffer-format for usage-bits",
4820+ "nominated": true,
4821+ "nomination_type": 1,
4822+ "resolution": 1,
4823+ "main_sha": null,
4824+ "because_sha": "00dc0036bb6d0c6de1ec3dc395e1d9e63d05ed83"
4825+ },
4826+ {
4827+ "sha": "662dc70002c0749cdab796701424bf6876f49b9e",
4828+ "description": "zink: drop repeated usage-bit",
4829+ "nominated": true,
4830+ "nomination_type": 1,
4831+ "resolution": 1,
4832+ "main_sha": null,
4833+ "because_sha": "00dc0036bb6d0c6de1ec3dc395e1d9e63d05ed83"
4834+ },
4835+ {
4836+ "sha": "c35fc7ad2cbb0098dc28c71481185756d327de59",
4837+ "description": "zink: remove unused function",
4838+ "nominated": false,
4839+ "nomination_type": 1,
4840+ "resolution": 4,
4841+ "main_sha": null,
4842+ "because_sha": "e4e20556d62729a4feaa97fcdbb18c0dd2d530cf"
4843+ },
4844+ {
4845+ "sha": "0360533d6c7a57fa07e16b9ddb9dbd0779e0beb0",
4846+ "description": "zink: fixup signedness of subtraction",
4847+ "nominated": false,
4848+ "nomination_type": 1,
4849+ "resolution": 4,
4850+ "main_sha": null,
4851+ "because_sha": "0c1fe392e8d50b08d4e5cd8f7280ceedfb331442"
4852+ },
4853+ {
4854+ "sha": "806251c72df16d0b5a4670dcddc5b677915496ed",
4855+ "description": "zink: move queue init to screen creation",
4856+ "nominated": false,
4857+ "nomination_type": null,
4858+ "resolution": 4,
4859+ "main_sha": null,
4860+ "because_sha": null
4861+ },
4862+ {
4863+ "sha": "0cfcc0602b8ec5ee2dfab302983d8159676720c8",
4864+ "description": "zink: set subdata hook as PIPE_MAP_ONCE",
4865+ "nominated": false,
4866+ "nomination_type": null,
4867+ "resolution": 4,
4868+ "main_sha": null,
4869+ "because_sha": null
4870+ },
4871+ {
4872+ "sha": "3e66808a821f2bdb7ee23e6aa549e0d382f38bca",
4873+ "description": "zink: update pipe_screen::num_contexts",
4874+ "nominated": false,
4875+ "nomination_type": null,
4876+ "resolution": 4,
4877+ "main_sha": null,
4878+ "because_sha": null
4879+ },
4880+ {
4881+ "sha": "24342e499bc58348b257716f629dccca3c1b0833",
4882+ "description": "anv: fix dynamic primitive topology for tess",
4883+ "nominated": true,
4884+ "nomination_type": 1,
4885+ "resolution": 1,
4886+ "main_sha": null,
4887+ "because_sha": "f6fa4a8000053fc6e9a25a30f482c59466390898"
4888+ },
4889+ {
4890+ "sha": "bcd82a90c2429d3079083a4f119ce3f99f9bb764",
4891+ "description": "zink: correct type of flags to flush",
4892+ "nominated": false,
4893+ "nomination_type": null,
4894+ "resolution": 4,
4895+ "main_sha": null,
4896+ "because_sha": null
4897+ },
4898+ {
4899+ "sha": "fde7b6694b7f2b7d60d1eedafd20c9ab00ef9cb3",
4900+ "description": "zink: use alloca instead of hard-to-size vlas",
4901+ "nominated": false,
4902+ "nomination_type": null,
4903+ "resolution": 4,
4904+ "main_sha": null,
4905+ "because_sha": null
4906+ },
4907+ {
4908+ "sha": "14597315f89b71fd5e465b9cb0844908b4fd3ae2",
4909+ "description": "zink: use max-descriptor define",
4910+ "nominated": false,
4911+ "nomination_type": null,
4912+ "resolution": 4,
4913+ "main_sha": null,
4914+ "because_sha": null
4915+ },
4916+ {
4917+ "sha": "4439f500a2c51aa25774021699b0cdbc4ae906f4",
4918+ "description": "zink: introduce a define for max descriptors per type",
4919+ "nominated": false,
4920+ "nomination_type": null,
4921+ "resolution": 4,
4922+ "main_sha": null,
4923+ "because_sha": null
4924+ },
4925+ {
4926+ "sha": "0ee48216ddbb949a73369ae378f3a4aebaa9c56e",
4927+ "description": "zink: fix more initializer styles",
4928+ "nominated": false,
4929+ "nomination_type": null,
4930+ "resolution": 4,
4931+ "main_sha": null,
4932+ "because_sha": null
4933+ },
4934+ {
4935+ "sha": "3179ce61e936e097090d88632bcd95dcaaebc8dc",
4936+ "description": "zink: drop some more vla usage",
4937+ "nominated": false,
4938+ "nomination_type": null,
4939+ "resolution": 4,
4940+ "main_sha": null,
4941+ "because_sha": null
4942+ },
4943+ {
4944+ "sha": "c14af0065e4ed743c832ccde6ea0a277f7ecf629",
4945+ "description": "zink: add missing compiler-dependency",
4946+ "nominated": false,
4947+ "nomination_type": 1,
4948+ "resolution": 4,
4949+ "main_sha": null,
4950+ "because_sha": "ed2fb8099e4588e058e7a18df6f63543d88bd493"
4951+ },
4952+ {
4953+ "sha": "b20c1c2a3bd368c86adb15606d55e5cd0ed2b8b1",
4954+ "description": "zink: drop paranoid code",
4955+ "nominated": false,
4956+ "nomination_type": null,
4957+ "resolution": 4,
4958+ "main_sha": null,
4959+ "because_sha": null
4960+ },
4961+ {
4962+ "sha": "0bb47032922b6faf043311ada0407bb43460de0c",
4963+ "description": "zink: do not unmap dt-buffers twice",
4964+ "nominated": true,
4965+ "nomination_type": 1,
4966+ "resolution": 1,
4967+ "main_sha": null,
4968+ "because_sha": "5159f406d895c6a253e90c6b076045ac133e55af"
4969+ },
4970+ {
4971+ "sha": "bb9efa527afccce2d40d196fe3b0ffa2460ea4d5",
4972+ "description": "zink: split stencil ref changes to separate dirty flag",
4973+ "nominated": false,
4974+ "nomination_type": null,
4975+ "resolution": 4,
4976+ "main_sha": null,
4977+ "because_sha": null
4978+ },
4979+ {
4980+ "sha": "e6a100b4cd5a8404877ad1d22544d76906593efb",
4981+ "description": "zink: add update flag for dsa state change",
4982+ "nominated": false,
4983+ "nomination_type": null,
4984+ "resolution": 4,
4985+ "main_sha": null,
4986+ "because_sha": null
4987+ },
4988+ {
4989+ "sha": "57ee14dd8c9b7c60c9f07c29537c7b78d02f541a",
4990+ "description": "zink: add update flag for rasterizer state change",
4991+ "nominated": false,
4992+ "nomination_type": null,
4993+ "resolution": 4,
4994+ "main_sha": null,
4995+ "because_sha": null
4996+ },
4997+ {
4998+ "sha": "541af28cb28810a041c5c363b4210d65a2fbdc4f",
4999+ "description": "zink: handle nir_op_pack_64_2x32",
5000+ "nominated": false,
5001+ "nomination_type": null,
5002+ "resolution": 4,
5003+ "main_sha": null,
5004+ "because_sha": null
5005+ },
5006+ {
5007+ "sha": "9753dec07dcdb56be5a4bf97b37b40861033a2b3",
5008+ "description": "v3dv: remove sRGB blending workaround",
5009+ "nominated": false,
5010+ "nomination_type": null,
5011+ "resolution": 4,
5012+ "main_sha": null,
5013+ "because_sha": null
5014+ },
5015+ {
5016+ "sha": "70d3ba1b689ef529aa33cc65598279a2cf274860",
5017+ "description": "v3dv: clamp srgb render targets",
5018+ "nominated": false,
5019+ "nomination_type": null,
5020+ "resolution": 4,
5021+ "main_sha": null,
5022+ "because_sha": null
5023+ },
5024+ {
5025+ "sha": "a78e7a76c81b6a11bb198ef5077f7b578c2b9b10",
5026+ "description": "Revert \"v3dv: allow creating uncompressed views from compressed images and vice versa\"",
5027+ "nominated": false,
5028+ "nomination_type": 2,
5029+ "resolution": 4,
5030+ "main_sha": null,
5031+ "because_sha": "b32a48c7e26bffdc696d3cceef0305e2c4731c96"
5032+ },
5033+ {
5034+ "sha": "8ae5b44339187521999a621efd47ebc6c718f703",
5035+ "description": "v3dv: don't support VK_IMAGE_CREATE_BLOCK_TEXEL_VIEW_COMPATIBLE_BIT",
5036+ "nominated": false,
5037+ "nomination_type": null,
5038+ "resolution": 4,
5039+ "main_sha": null,
5040+ "because_sha": null
5041+ },
5042+ {
5043+ "sha": "c1f938b6475b1c936a78f6aacf76a1601c87a0bb",
5044+ "description": "nv50/ir: fix surface lowering when values get shared accross operations",
5045+ "nominated": true,
5046+ "nomination_type": 1,
5047+ "resolution": 1,
5048+ "main_sha": null,
5049+ "because_sha": "869e32593a9096b845dd6106f8f86e1c41fac968"
5050+ },
5051+ {
35052 "sha": "561f9ae74b2b7da06bb4830aaca8d017a3dd2746",
45053 "description": "st/mesa: always report the max samples as supported",
55054 "nominated": false,
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
1-21.1.3
1+21.1.4
--- /dev/null
+++ b/docs/relnotes/21.1.4.rst
@@ -0,0 +1,156 @@
1+Mesa 21.1.4 Release Notes / 2021-06-30
2+======================================
3+
4+Mesa 21.1.4 is a bug fix release which fixes bugs found since the 21.1.3 release.
5+
6+Mesa 21.1.4 implements the OpenGL 4.6 API, but the version reported by
7+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
8+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
9+Some drivers don't support all the features required in OpenGL 4.6. OpenGL
10+4.6 is **only** available if requested at context creation.
11+Compatibility contexts may report a lower version depending on each driver.
12+
13+Mesa 21.1.4 implements the Vulkan 1.2 API, but the version reported by
14+the apiVersion property of the VkPhysicalDeviceProperties struct
15+depends on the particular driver being used.
16+
17+SHA256 checksum
18+---------------
19+
20+::
21+
22+ TBD.
23+
24+
25+New features
26+------------
27+
28+- None
29+
30+
31+Bug fixes
32+---------
33+
34+- [anv] GravityMark (benchmark) crashes on ANV
35+- [opengl] We happy few not being rendered correctly
36+- Factorio: GPU hang when opening machine inventory
37+- RuneScape on Mesa 21.1.1 (VEGA10) has bad performance and leaks memory
38+- Supraland: flickering black bars on ground
39+- radv: GPU hang in Cyberpunk 2077 on Big Navi
40+- [amdgpu][renoir][rx5500m]: [drm:0xffffffff8198ad5e] \*ERROR* ring gfx timeout, signaled seq=10952, emitted seq=10954
41+- [spirv-fuzz] SPIR-V parsing FAILED: Invalid back or cross-edge in the CFG
42+- panfrost Mount and Blade: Warband (glitches)
43+- anv: dEQP-VK.robustness.robustness2*no_fmt_qual.null_descriptor.samples* fail
44+
45+
46+Changes
47+-------
48+
49+Bas Nieuwenhuizen (3):
50+
51+- util/fossilize_db: Pull seek into lock.
52+- util/fossilize_db: Split out reading the index.
53+- util/fossilize_db: Do not lock the fossilize db permanently.
54+
55+Caio Marcelo de Oliveira Filho (2):
56+
57+- spirv: Fix handling of OpBranchConditional with same THEN and ELSE
58+- nir/opt_if: Don't split ALU for single block infinite loops
59+
60+Daniel Stone (1):
61+
62+- llvmpipe: Add handle export for resource_get_param
63+
64+Dave Airlie (1):
65+
66+- i965: fix regression in pipe control on g45
67+
68+Eric Engestrom (2):
69+
70+- .pick_status.json: Update to 977355c6e5efd781dde85d834172dd23cd4852f1
71+- .pick_status.json: Update to 40b67a292297606f0a7576e3ef4087028d5edd17
72+
73+Erik Faye-Lund (7):
74+
75+- zink: do not unmap dt-buffers twice
76+- zink: drop repeated usage-bit
77+- zink: do not check buffer-format for usage-bits
78+- zink: remove unused moltenvk functions
79+- libgl-gdi: add missing include
80+- aux/trace: fix bool argument
81+- ci/windows: work around meson encoding issues
82+
83+Francisco Jerez (2):
84+
85+- intel/fs: Teach IR about EOT instruction writing the accumulator implicitly on TGL+.
86+- intel/fs: Fix synchronization of accumulator-clearing W/A move on TGL+.
87+
88+Icecream95 (5):
89+
90+- pan/mdg: Add a bundle ID to instructions
91+- pan/mdg: Reorder some code in mir_spill_register
92+- pan/mdg: Fill from TLS before spilling non-SSA nodes
93+- pan/mdg: Fix reading a spilt register in the bundle it's written
94+- pan/mdg: Add 16 bytes of padding to the end of shaders
95+
96+Iván Briano (1):
97+
98+- intel/nir: Fix txs for null surfaces
99+
100+Jason Ekstrand (1):
101+
102+- spirv: Create acceleration structure and shader record variables
103+
104+Karol Herbst (1):
105+
106+- nv50/ir: fix surface lowering when values get shared accross operations
107+
108+Kenneth Graunke (1):
109+
110+- anv: Fix dynamic primitive topology for tess on Gfx7.x too
111+
112+Lionel Landwerlin (1):
113+
114+- anv: allocate bigger batches as we grow command buffers
115+
116+Marek Olšák (1):
117+
118+- mesa: unreference zombie buffers when creating buffers to lower memory usage
119+
120+Martin Krastev (1):
121+
122+- compiler/glsl: Use mutex lock while freeing up mem_ctx
123+
124+Mike Blumenkrantz (2):
125+
126+- anv: fix dynamic primitive topology for tess
127+- zink: handle custom border color without matching wrap mode case
128+
129+Pierre-Eric Pelloux-Prayer (2):
130+
131+- radeonsi: skip instance_count==0 draws on <= GFX9
132+- radeonsi: disable ngg culling on llvm < 12
133+
134+Samuel Pitoiset (2):
135+
136+- radv: reject binding buffer/image when the device memory is too small
137+- radv: always decompress both aspects of a depth/stencil image
138+
139+Simon Ser (1):
140+
141+- amd/addrlib: remove Meson debug message()
142+
143+Thong Thai (1):
144+
145+- radeon/vcn/enc: Add missing line to HEVC SPS header code
146+
147+Timothy Arceri (1):
148+
149+- util: add work around for the game We Happy Few
150+
151+Timur Kristóf (4):
152+
153+- ac/nir: Update TCS output barriers with nir_var_mem_shared.
154+- radv/llvm: Emit s_barrier at the beginning of NGG non-GS shaders.
155+- aco/gfx10: NGG zero output workaround for conservative rasterization.
156+- aco/gfx10: Emit barrier at the start of NGG VS and TES.
--- a/src/amd/addrlib/meson.build
+++ b/src/amd/addrlib/meson.build
@@ -68,8 +68,6 @@ foreach w : ['-Wno-unused-variable', '-Wno-unused-local-typedefs',
6868 endif
6969 endforeach
7070
71-message(cpp_args_addrlib)
72-
7371 libamdgpu_addrlib = static_library(
7472 'addrlib',
7573 files_addrlib,
--- a/src/amd/ci/deqp-radv-oland-aco-fails.txt
+++ b/src/amd/ci/deqp-radv-oland-aco-fails.txt
@@ -2637,11 +2637,3 @@ dEQP-VK.glsl.texture_gather.offsets.min_required_offset.2d_array.rgba8ui.base_le
26372637 dEQP-VK.glsl.texture_gather.offsets.min_required_offset.2d_array.rgba8ui.base_level.sparse_level_2_amd_bias,Fail
26382638 dEQP-VK.glsl.texture_gather.offsets.min_required_offset.2d_array.rgba8ui.base_level.sparse_level_2_amd_lod,Fail
26392639
2640-# Oland specific issues, might need further investigation
2641-dEQP-VK.renderpass.suballocation.subpass_dependencies.late_fragment_tests.render_size_128_128.subpass_count_2.d32_sfloat_s8_uint,Fail
2642-dEQP-VK.renderpass.suballocation.subpass_dependencies.late_fragment_tests.render_size_128_128.subpass_count_3.d32_sfloat_s8_uint,Fail
2643-dEQP-VK.renderpass.suballocation.subpass_dependencies.late_fragment_tests.render_size_128_128.subpass_count_5.d32_sfloat_s8_uint,Fail
2644-dEQP-VK.renderpass2.suballocation.subpass_dependencies.late_fragment_tests.render_size_128_128.subpass_count_2.d32_sfloat_s8_uint,Fail
2645-dEQP-VK.renderpass2.suballocation.subpass_dependencies.late_fragment_tests.render_size_128_128.subpass_count_3.d32_sfloat_s8_uint,Fail
2646-dEQP-VK.renderpass2.suballocation.subpass_dependencies.late_fragment_tests.render_size_128_128.subpass_count_5.d32_sfloat_s8_uint,Fail
2647-
--- a/src/amd/common/ac_nir_lower_tess_io_to_mem.c
+++ b/src/amd/common/ac_nir_lower_tess_io_to_mem.c
@@ -430,6 +430,18 @@ lower_hs_output_load(nir_builder *b,
430430 .align_mul = 16u, .align_offset = (nir_intrinsic_component(intrin) * 4u) % 16u);
431431 }
432432
433+static void
434+update_hs_scoped_barrier(nir_intrinsic_instr *intrin)
435+{
436+ /* Output loads and stores are lowered to shared memory access,
437+ * so we have to update the barriers to also reflect this.
438+ */
439+ unsigned mem_modes = nir_intrinsic_memory_modes(intrin);
440+ if (mem_modes & nir_var_shader_out)
441+ mem_modes |= nir_var_mem_shared;
442+ nir_intrinsic_set_memory_modes(intrin, mem_modes);
443+}
444+
433445 static nir_ssa_def *
434446 lower_hs_output_access(nir_builder *b,
435447 nir_instr *instr,
@@ -442,8 +454,14 @@ lower_hs_output_access(nir_builder *b,
442454 intrin->intrinsic == nir_intrinsic_store_per_vertex_output) {
443455 lower_hs_output_store(b, intrin, st);
444456 return NIR_LOWER_INSTR_PROGRESS_REPLACE;
445- } else {
457+ } else if (intrin->intrinsic == nir_intrinsic_load_output ||
458+ intrin->intrinsic == nir_intrinsic_load_per_vertex_output) {
446459 return lower_hs_output_load(b, intrin, st);
460+ } else if (intrin->intrinsic == nir_intrinsic_scoped_barrier) {
461+ update_hs_scoped_barrier(intrin);
462+ return NIR_LOWER_INSTR_PROGRESS;
463+ } else {
464+ unreachable("intrinsic not supported by lower_hs_output_access");
447465 }
448466 }
449467
@@ -571,7 +589,7 @@ lower_tes_input_load(nir_builder *b,
571589 }
572590
573591 static bool
574-filter_any_output_access(const nir_instr *instr,
592+filter_hs_output_access(const nir_instr *instr,
575593 UNUSED const void *st)
576594 {
577595 if (instr->type != nir_instr_type_intrinsic)
@@ -581,7 +599,8 @@ filter_any_output_access(const nir_instr *instr,
581599 return intrin->intrinsic == nir_intrinsic_store_output ||
582600 intrin->intrinsic == nir_intrinsic_store_per_vertex_output ||
583601 intrin->intrinsic == nir_intrinsic_load_output ||
584- intrin->intrinsic == nir_intrinsic_load_per_vertex_output;
602+ intrin->intrinsic == nir_intrinsic_load_per_vertex_output ||
603+ intrin->intrinsic == nir_intrinsic_scoped_barrier;
585604 }
586605
587606 static bool
@@ -658,7 +677,7 @@ ac_nir_lower_hs_outputs_to_mem(nir_shader *shader,
658677 };
659678
660679 nir_shader_lower_instructions(shader,
661- filter_any_output_access,
680+ filter_hs_output_access,
662681 lower_hs_output_access,
663682 &state);
664683
--- a/src/amd/compiler/aco_instruction_selection.cpp
+++ b/src/amd/compiler/aco_instruction_selection.cpp
@@ -11187,7 +11187,9 @@ void ngg_emit_sendmsg_gs_alloc_req(isel_context *ctx, Temp vtx_cnt = Temp(), Tem
1118711187 bld.sopp(aco_opcode::s_sendmsg, bld.m0(tmp), -1, sendmsg_gs_alloc_req);
1118811188
1118911189 if (prm_cnt_0.id()) {
11190- /* Navi 1x workaround: export a zero-area triangle when GS has no output. */
11190+ /* Navi 1x workaround: export a triangle with NaN coordinates when GS has no output.
11191+ * It can't have all-zero positions because that would render an undesired pixel with conservative rasterization.
11192+ */
1119111193 Temp first_lane = bld.sop1(Builder::s_ff1_i32, bld.def(s1), Operand(exec, bld.lm));
1119211194 Temp cond = bld.sop2(Builder::s_lshl, bld.def(bld.lm), bld.def(s1, scc),
1119311195 Operand(1u, ctx->program->wave_size == 64), first_lane);
@@ -11198,11 +11200,15 @@ void ngg_emit_sendmsg_gs_alloc_req(isel_context *ctx, Temp vtx_cnt = Temp(), Tem
1119811200 bld.reset(ctx->block);
1119911201 ctx->block->kind |= block_kind_export_end;
1120011202
11203+ /* Use zero: means that it's a triangle whose every vertex index is 0. */
1120111204 Temp zero = bld.copy(bld.def(v1), Operand(0u));
11205+ /* Use NaN for the coordinates, so that the rasterizer allways culls it. */
11206+ Temp nan_coord = bld.copy(bld.def(v1), Operand(-1u));
11207+
1120211208 bld.exp(aco_opcode::exp, zero, Operand(v1), Operand(v1), Operand(v1),
1120311209 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM /* dest */,
1120411210 false /* compressed */, true /* done */, false /* valid mask */);
11205- bld.exp(aco_opcode::exp, zero, zero, zero, zero,
11211+ bld.exp(aco_opcode::exp, nan_coord, nan_coord, nan_coord, nan_coord,
1120611212 0xf /* enabled mask */, V_008DFC_SQ_EXP_POS /* dest */,
1120711213 false /* compressed */, true /* done */, true /* valid mask */);
1120811214
@@ -11830,6 +11836,13 @@ void select_program(Program *program,
1183011836 create_workgroup_barrier(bld);
1183111837 }
1183211838
11839+ if (program->chip_class == GFX10 &&
11840+ program->stage.hw == HWStage::NGG &&
11841+ program->stage.num_sw_stages() == 1) {
11842+ /* Workaround for Navi 1x HW bug to ensure all NGG waves launch before s_sendmsg(GS_ALLOC_REQ). */
11843+ Builder(ctx.program, ctx.block).sopp(aco_opcode::s_barrier, -1u, 0u);
11844+ }
11845+
1183311846 if (check_merged_wave_info) {
1183411847 Temp cond = merged_wave_info_to_mask(&ctx, i);
1183511848 begin_divergent_if_then(&ctx, &ic_merged_wave_info, cond);
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -5427,14 +5427,27 @@ radv_GetDeviceMemoryCommitment(VkDevice device, VkDeviceMemory memory,
54275427 }
54285428
54295429 VkResult
5430-radv_BindBufferMemory2(VkDevice device, uint32_t bindInfoCount,
5430+radv_BindBufferMemory2(VkDevice _device, uint32_t bindInfoCount,
54315431 const VkBindBufferMemoryInfo *pBindInfos)
54325432 {
5433+ RADV_FROM_HANDLE(radv_device, device, _device);
5434+
54335435 for (uint32_t i = 0; i < bindInfoCount; ++i) {
54345436 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
54355437 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
54365438
54375439 if (mem) {
5440+ if (mem->alloc_size) {
5441+ VkMemoryRequirements req;
5442+
5443+ radv_GetBufferMemoryRequirements(_device, pBindInfos[i].buffer, &req);
5444+
5445+ if (pBindInfos[i].memoryOffset + req.size > mem->alloc_size) {
5446+ return vk_errorf(device->instance, VK_ERROR_UNKNOWN,
5447+ "Device memory object too small for the buffer.\n");
5448+ }
5449+ }
5450+
54385451 buffer->bo = mem->bo;
54395452 buffer->offset = pBindInfos[i].memoryOffset;
54405453 } else {
@@ -5457,14 +5470,27 @@ radv_BindBufferMemory(VkDevice device, VkBuffer buffer, VkDeviceMemory memory,
54575470 }
54585471
54595472 VkResult
5460-radv_BindImageMemory2(VkDevice device, uint32_t bindInfoCount,
5473+radv_BindImageMemory2(VkDevice _device, uint32_t bindInfoCount,
54615474 const VkBindImageMemoryInfo *pBindInfos)
54625475 {
5476+ RADV_FROM_HANDLE(radv_device, device, _device);
5477+
54635478 for (uint32_t i = 0; i < bindInfoCount; ++i) {
54645479 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
54655480 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
54665481
54675482 if (mem) {
5483+ if (mem->alloc_size) {
5484+ VkMemoryRequirements req;
5485+
5486+ radv_GetImageMemoryRequirements(_device, pBindInfos[i].image, &req);
5487+
5488+ if (pBindInfos[i].memoryOffset + req.size > mem->alloc_size) {
5489+ return vk_errorf(device->instance, VK_ERROR_UNKNOWN,
5490+ "Device memory object too small for the image.\n");
5491+ }
5492+ }
5493+
54685494 image->bo = mem->bo;
54695495 image->offset = pBindInfos[i].memoryOffset;
54705496 } else {
--- a/src/amd/vulkan/radv_meta_decompress.c
+++ b/src/amd/vulkan/radv_meta_decompress.c
@@ -324,17 +324,9 @@ radv_get_depth_pipeline(struct radv_cmd_buffer *cmd_buffer, struct radv_image *i
324324 struct radv_meta_state *state = &cmd_buffer->device->meta_state;
325325 uint32_t samples = image->info.samples;
326326 uint32_t samples_log2 = ffs(samples) - 1;
327- enum radv_depth_decompress decompress;
327+ enum radv_depth_decompress decompress = DECOMPRESS_DEPTH_STENCIL;
328328 VkPipeline *pipeline;
329329
330- if (subresourceRange->aspectMask == VK_IMAGE_ASPECT_DEPTH_BIT) {
331- decompress = DECOMPRESS_DEPTH;
332- } else if (subresourceRange->aspectMask == VK_IMAGE_ASPECT_STENCIL_BIT) {
333- decompress = DECOMPRESS_STENCIL;
334- } else {
335- decompress = DECOMPRESS_DEPTH_STENCIL;
336- }
337-
338330 if (!state->depth_decomp[samples_log2].decompress_pipeline[decompress]) {
339331 VkResult ret;
340332
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -3023,6 +3023,10 @@ ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm, struct nir_shader *co
30233023 LLVMSetInitializer(ctx.gs_ngg_scratch, LLVMGetUndef(asi32));
30243024 LLVMSetAlignment(ctx.gs_ngg_scratch, 4);
30253025 }
3026+
3027+ /* GFX10 hang workaround - there needs to be an s_barrier before gs_alloc_req always */
3028+ if (ctx.ac.chip_class == GFX10 && shader_count == 1)
3029+ ac_build_s_barrier(&ctx.ac);
30263030 }
30273031
30283032 for (int shader_idx = 0; shader_idx < shader_count; ++shader_idx) {
--- a/src/compiler/glsl/builtin_functions.cpp
+++ b/src/compiler/glsl/builtin_functions.cpp
@@ -90,6 +90,8 @@
9090
9191 using namespace ir_builder;
9292
93+static mtx_t builtins_lock = _MTX_INITIALIZER_NP;
94+
9395 /**
9496 * Availability predicates:
9597 * @{
@@ -1296,7 +1298,15 @@ builtin_builder::builtin_builder()
12961298
12971299 builtin_builder::~builtin_builder()
12981300 {
1301+ mtx_lock(&builtins_lock);
1302+
12991303 ralloc_free(mem_ctx);
1304+ mem_ctx = NULL;
1305+
1306+ ralloc_free(shader);
1307+ shader = NULL;
1308+
1309+ mtx_unlock(&builtins_lock);
13001310 }
13011311
13021312 ir_function_signature *
@@ -7753,7 +7763,6 @@ builtin_builder::_helper_invocation()
77537763
77547764 /* The singleton instance of builtin_builder. */
77557765 static builtin_builder builtins;
7756-static mtx_t builtins_lock = _MTX_INITIALIZER_NP;
77577766 static uint32_t builtin_users = 0;
77587767
77597768 /**
--- a/src/compiler/nir/nir_lower_tex.c
+++ b/src/compiler/nir/nir_lower_tex.c
@@ -1091,10 +1091,14 @@ nir_lower_txs_lod(nir_builder *b, nir_tex_instr *tex)
10911091 nir_instr_rewrite_src(&tex->instr, &tex->src[lod_idx].src,
10921092 nir_src_for_ssa(nir_imm_int(b, 0)));
10931093
1094- /* TXS(LOD) = max(TXS(0) >> LOD, 1) */
1094+ /* TXS(LOD) = max(TXS(0) >> LOD, 1)
1095+ * But we do min(TXS(0), TXS(LOD)) to catch the case of a null surface,
1096+ * which should return 0, not 1.
1097+ */
10951098 b->cursor = nir_after_instr(&tex->instr);
1096- nir_ssa_def *minified = nir_imax(b, nir_ushr(b, &tex->dest.ssa, lod),
1097- nir_imm_int(b, 1));
1099+ nir_ssa_def *minified = nir_imin(b, &tex->dest.ssa,
1100+ nir_imax(b, nir_ushr(b, &tex->dest.ssa, lod),
1101+ nir_imm_int(b, 1)));
10981102
10991103 /* Make sure the component encoding the array size (if any) is not
11001104 * minified.
--- a/src/compiler/nir/nir_opt_if.c
+++ b/src/compiler/nir/nir_opt_if.c
@@ -408,6 +408,10 @@ opt_split_alu_of_phi(nir_builder *b, nir_loop *loop)
408408 if (header_block->predecessors->entries != 2)
409409 return false;
410410
411+ nir_block *continue_block = find_continue_block(loop);
412+ if (continue_block == header_block)
413+ return false;
414+
411415 nir_foreach_instr_safe(instr, header_block) {
412416 if (instr->type != nir_instr_type_alu)
413417 continue;
@@ -499,8 +503,6 @@ opt_split_alu_of_phi(nir_builder *b, nir_loop *loop)
499503 }
500504
501505 /* Split ALU of Phi */
502- nir_block *const continue_block = find_continue_block(loop);
503-
504506 b->cursor = nir_after_block(prev_block);
505507 nir_ssa_def *prev_value = clone_alu_and_replace_src_defs(b, alu, prev_srcs);
506508
@@ -683,7 +685,7 @@ opt_simplify_bcsel_of_phi(nir_builder *b, nir_loop *loop)
683685 * continue_block from the other bcsel source. Both sources have
684686 * already been verified to be phi nodes.
685687 */
686- nir_block *const continue_block = find_continue_block(loop);
688+ nir_block *continue_block = find_continue_block(loop);
687689 nir_phi_instr *const phi = nir_phi_instr_create(b->shader);
688690 nir_phi_src *phi_src;
689691
--- a/src/compiler/spirv/vtn_cfg.c
+++ b/src/compiler/spirv/vtn_cfg.c
@@ -722,26 +722,11 @@ vtn_process_block(struct vtn_builder *b,
722722 cond_val->type->type != glsl_bool_type(),
723723 "Condition must be a Boolean type scalar");
724724
725- struct vtn_block *then_block = vtn_block(b, block->branch[2]);
726- struct vtn_block *else_block = vtn_block(b, block->branch[3]);
727-
728- if (then_block == else_block) {
729- /* This is uncommon but it can happen. We treat this the same way as
730- * an unconditional branch.
731- */
732- block->branch_type = vtn_handle_branch(b, cf_parent, then_block);
733-
734- if (block->branch_type == vtn_branch_type_none)
735- return then_block;
736- else
737- return NULL;
738- }
739-
740725 struct vtn_if *if_stmt = rzalloc(b, struct vtn_if);
741726
742727 if_stmt->node.type = vtn_cf_node_type_if;
743728 if_stmt->node.parent = cf_parent;
744- if_stmt->condition = block->branch[1];
729+ if_stmt->header_block = block;
745730 list_inithead(&if_stmt->then_body);
746731 list_inithead(&if_stmt->else_body);
747732
@@ -759,16 +744,20 @@ vtn_process_block(struct vtn_builder *b,
759744 if_stmt->control = block->merge[2];
760745 }
761746
747+ struct vtn_block *then_block = vtn_block(b, block->branch[2]);
762748 if_stmt->then_type = vtn_handle_branch(b, &if_stmt->node, then_block);
763749 if (if_stmt->then_type == vtn_branch_type_none) {
764750 vtn_add_cfg_work_item(b, work_list, &if_stmt->node,
765751 &if_stmt->then_body, then_block);
766752 }
767753
768- if_stmt->else_type = vtn_handle_branch(b, &if_stmt->node, else_block);
769- if (if_stmt->else_type == vtn_branch_type_none) {
770- vtn_add_cfg_work_item(b, work_list, &if_stmt->node,
771- &if_stmt->else_body, else_block);
754+ struct vtn_block *else_block = vtn_block(b, block->branch[3]);
755+ if (then_block != else_block) {
756+ if_stmt->else_type = vtn_handle_branch(b, &if_stmt->node, else_block);
757+ if (if_stmt->else_type == vtn_branch_type_none) {
758+ vtn_add_cfg_work_item(b, work_list, &if_stmt->node,
759+ &if_stmt->else_body, else_block);
760+ }
772761 }
773762
774763 return if_stmt->merge_block;
@@ -1101,10 +1090,22 @@ vtn_emit_cf_list_structured(struct vtn_builder *b, struct list_head *cf_list,
11011090
11021091 case vtn_cf_node_type_if: {
11031092 struct vtn_if *vtn_if = vtn_cf_node_as_if(node);
1093+ const uint32_t *branch = vtn_if->header_block->branch;
1094+ vtn_assert((branch[0] & SpvOpCodeMask) == SpvOpBranchConditional);
1095+
1096+ /* If both branches are the same, just emit the first block, which is
1097+ * the only one we filled when building the CFG.
1098+ */
1099+ if (branch[2] == branch[3]) {
1100+ vtn_emit_cf_list_structured(b, &vtn_if->then_body,
1101+ switch_fall_var, has_switch_break, handler);
1102+ break;
1103+ }
1104+
11041105 bool sw_break = false;
11051106
11061107 nir_if *nif =
1107- nir_push_if(&b->nb, vtn_get_nir_ssa(b, vtn_if->condition));
1108+ nir_push_if(&b->nb, vtn_get_nir_ssa(b, branch[1]));
11081109
11091110 nif->control = vtn_selection_control(b, vtn_if);
11101111
--- a/src/compiler/spirv/vtn_private.h
+++ b/src/compiler/spirv/vtn_private.h
@@ -181,14 +181,13 @@ struct vtn_loop {
181181 struct vtn_if {
182182 struct vtn_cf_node node;
183183
184- uint32_t condition;
185-
186184 enum vtn_branch_type then_type;
187185 struct list_head then_body;
188186
189187 enum vtn_branch_type else_type;
190188 struct list_head else_body;
191189
190+ struct vtn_block *header_block;
192191 struct vtn_block *merge_block;
193192
194193 SpvSelectionControlMask control;
--- a/src/compiler/spirv/vtn_variables.c
+++ b/src/compiler/spirv/vtn_variables.c
@@ -1831,6 +1831,8 @@ vtn_create_variable(struct vtn_builder *b, struct vtn_value *val,
18311831 case vtn_variable_mode_ubo:
18321832 case vtn_variable_mode_ssbo:
18331833 case vtn_variable_mode_push_constant:
1834+ case vtn_variable_mode_accel_struct:
1835+ case vtn_variable_mode_shader_record:
18341836 var->var = rzalloc(b->shader, nir_variable);
18351837 var->var->name = ralloc_strdup(var->var, val->name);
18361838
@@ -1936,11 +1938,6 @@ vtn_create_variable(struct vtn_builder *b, struct vtn_value *val,
19361938 break;
19371939 }
19381940
1939- case vtn_variable_mode_accel_struct:
1940- case vtn_variable_mode_shader_record:
1941- /* These don't need actual variables. */
1942- break;
1943-
19441941 case vtn_variable_mode_image:
19451942 case vtn_variable_mode_phys_ssbo:
19461943 case vtn_variable_mode_generic:
--- a/src/gallium/auxiliary/driver_trace/tr_screen.c
+++ b/src/gallium/auxiliary/driver_trace/tr_screen.c
@@ -836,7 +836,7 @@ trace_screen_create(struct pipe_screen *screen)
836836 const char *driver = debug_get_option("MESA_LOADER_DRIVER_OVERRIDE", NULL);
837837 if (driver && !strcmp(driver, "zink")) {
838838 /* the user wants zink: check whether they want to trace zink or lavapipe */
839- bool trace_lavapipe = debug_get_bool_option("ZINK_TRACE_LAVAPIPE", NULL);
839+ bool trace_lavapipe = debug_get_bool_option("ZINK_TRACE_LAVAPIPE", false);
840840 if (!strncmp(screen->get_name(screen), "zink", 4)) {
841841 /* this is the zink screen: only trace if lavapipe tracing is disabled */
842842 if (trace_lavapipe)
--- a/src/gallium/drivers/llvmpipe/lp_texture.c
+++ b/src/gallium/drivers/llvmpipe/lp_texture.c
@@ -53,6 +53,10 @@
5353
5454 #include "frontend/sw_winsys.h"
5555
56+#ifndef _WIN32
57+#include "drm-uapi/drm_fourcc.h"
58+#endif
59+
5660
5761 #ifdef DEBUG
5862 static struct llvmpipe_resource resource_list;
@@ -917,6 +921,7 @@ llvmpipe_resource_get_param(struct pipe_screen *screen,
917921 uint64_t *value)
918922 {
919923 struct llvmpipe_resource *lpr = llvmpipe_resource(resource);
924+ struct winsys_handle whandle;
920925
921926 switch (param) {
922927 case PIPE_RESOURCE_PARAM_NPLANES:
@@ -931,10 +936,29 @@ llvmpipe_resource_get_param(struct pipe_screen *screen,
931936 case PIPE_RESOURCE_PARAM_LAYER_STRIDE:
932937 *value = lpr->img_stride[level];
933938 return true;
939+#ifndef _WIN32
934940 case PIPE_RESOURCE_PARAM_MODIFIER:
941+ *value = DRM_FORMAT_MOD_INVALID;
942+ return true;
943+#endif
935944 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED:
936945 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS:
937946 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD:
947+ if (!lpr->dt)
948+ return false;
949+
950+ memset(&whandle, 0, sizeof(whandle));
951+ if (param == PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED)
952+ whandle.type = WINSYS_HANDLE_TYPE_SHARED;
953+ else if (param == PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS)
954+ whandle.type = WINSYS_HANDLE_TYPE_KMS;
955+ else if (param == PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD)
956+ whandle.type = WINSYS_HANDLE_TYPE_FD;
957+
958+ if (!llvmpipe_resource_get_handle(screen, context, resource, &whandle, handle_usage))
959+ return false;
960+ *value = whandle.handle;
961+ return true;
938962 default:
939963 break;
940964 }
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -2328,15 +2328,15 @@ NVC0LoweringPass::insertOOBSurfaceOpResult(TexInstruction *su)
23282328 bld.setPosition(su, true);
23292329
23302330 for (unsigned i = 0; su->defExists(i); ++i) {
2331- ValueDef &def = su->def(i);
2331+ Value *def = su->getDef(i);
2332+ Value *newDef = bld.getSSA();
2333+ su->setDef(i, newDef);
23322334
23332335 Instruction *mov = bld.mkMov(bld.getSSA(), bld.loadImm(NULL, 0));
23342336 assert(su->cc == CC_NOT_P);
23352337 mov->setPredicate(CC_P, su->getPredicate());
2336- Instruction *uni = bld.mkOp2(OP_UNION, TYPE_U32, bld.getSSA(), NULL, mov->getDef(0));
2337-
2338- def.replace(uni->getDef(0), false);
2339- uni->setSrc(0, def.get());
2338+ Instruction *uni = bld.mkOp2(OP_UNION, TYPE_U32, bld.getSSA(), newDef, mov->getDef(0));
2339+ bld.mkMov(def, uni->getDef(0));
23402340 }
23412341 }
23422342
@@ -2613,10 +2613,12 @@ NVC0LoweringPass::processSurfaceCoordsGM107(TexInstruction *su, Instruction *ret
26132613 for (unsigned i = 0; su->defExists(i); ++i) {
26142614 assert(i < 4);
26152615
2616- ValueDef &def = su->def(i);
2616+ Value *def = su->getDef(i);
2617+ Value *newDef = bld.getSSA();
26172618 ValueDef &def2 = su2d->def(i);
26182619 Instruction *mov = NULL;
26192620
2621+ su->setDef(i, newDef);
26202622 if (pred) {
26212623 mov = bld.mkMov(bld.getSSA(), bld.loadImm(NULL, 0));
26222624 mov->setPredicate(CC_P, pred->getDef(0));
@@ -2624,11 +2626,10 @@ NVC0LoweringPass::processSurfaceCoordsGM107(TexInstruction *su, Instruction *ret
26242626
26252627 Instruction *uni = ret[i] = bld.mkOp2(OP_UNION, TYPE_U32,
26262628 bld.getSSA(),
2627- NULL, def2.get());
2628- def.replace(uni->getDef(0), false);
2629- uni->setSrc(0, def.get());
2629+ newDef, def2.get());
26302630 if (mov)
26312631 uni->setSrc(2, mov->getDef(0));
2632+ bld.mkMov(def, uni->getDef(0));
26322633 }
26332634 } else if (pred) {
26342635 // Create a UNION so that RA assigns the same registers
@@ -2636,16 +2637,17 @@ NVC0LoweringPass::processSurfaceCoordsGM107(TexInstruction *su, Instruction *ret
26362637 for (unsigned i = 0; su->defExists(i); ++i) {
26372638 assert(i < 4);
26382639
2639- ValueDef &def = su->def(i);
2640+ Value *def = su->getDef(i);
2641+ Value *newDef = bld.getSSA();
2642+ su->setDef(i, newDef);
26402643
26412644 Instruction *mov = bld.mkMov(bld.getSSA(), bld.loadImm(NULL, 0));
26422645 mov->setPredicate(CC_P, pred->getDef(0));
26432646
26442647 Instruction *uni = ret[i] = bld.mkOp2(OP_UNION, TYPE_U32,
26452648 bld.getSSA(),
2646- NULL, mov->getDef(0));
2647- def.replace(uni->getDef(0), false);
2648- uni->setSrc(0, def.get());
2649+ newDef, mov->getDef(0));
2650+ bld.mkMov(def, uni->getDef(0));
26492651 }
26502652 }
26512653
--- a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
@@ -412,6 +412,7 @@ static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc)
412412 radeon_enc_code_ue(enc, enc->enc_pic.session_init.padding_height / 2);
413413 radeon_enc_code_ue(enc, enc->enc_pic.session_init.padding_height / 2);
414414 } else
415+ radeon_enc_code_fixed_bits(enc, 0x0, 1);
415416
416417 radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_luma_minus8);
417418 radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_chroma_minus8);
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -1224,7 +1224,9 @@ static struct pipe_screen *radeonsi_screen_create_impl(struct radeon_winsys *ws,
12241224 sscreen->info.chip_class >= GFX10 &&
12251225 (sscreen->info.family != CHIP_NAVI14 ||
12261226 sscreen->info.is_pro_graphics);
1227- sscreen->use_ngg_culling = sscreen->use_ngg && !(sscreen->debug_flags & DBG(NO_NGG_CULLING));
1227+ sscreen->use_ngg_culling = sscreen->use_ngg &&
1228+ !((sscreen->debug_flags & DBG(NO_NGG_CULLING)) ||
1229+ LLVM_VERSION_MAJOR <= 11 /* hangs on 11, see #4874 */);
12281230 sscreen->use_ngg_streamout = false;
12291231
12301232 /* Only set this for the cases that are known to work, which are:
--- a/src/gallium/drivers/radeonsi/si_state_draw.cpp
+++ b/src/gallium/drivers/radeonsi/si_state_draw.cpp
@@ -1755,8 +1755,10 @@ static void si_draw_vbo(struct pipe_context *ctx,
17551755 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
17561756 * no workaround for indirect draws, but we can at least skip
17571757 * direct draws.
1758+ * 'instance_count == 0' seems to be problematic on Renoir chips (#4866),
1759+ * so simplify the condition and drop these draws for all <= GFX9 chips.
17581760 */
1759- if (GFX_VERSION <= GFX7 && unlikely(!indirect && !instance_count))
1761+ if (GFX_VERSION <= GFX9 && unlikely(!indirect && !instance_count))
17601762 return;
17611763
17621764 struct si_shader_selector *vs = sctx->shader.vs.cso;
--- a/src/gallium/drivers/zink/zink_context.c
+++ b/src/gallium/drivers/zink/zink_context.c
@@ -240,7 +240,7 @@ wrap_needs_border_color(unsigned wrap)
240240 }
241241
242242 static VkBorderColor
243-get_border_color(const union pipe_color_union *color, bool is_integer)
243+get_border_color(const union pipe_color_union *color, bool is_integer, bool need_custom)
244244 {
245245 if (is_integer) {
246246 if (color->ui[0] == 0 && color->ui[1] == 0 && color->ui[2] == 0 && color->ui[3] == 0)
@@ -249,7 +249,7 @@ get_border_color(const union pipe_color_union *color, bool is_integer)
249249 return VK_BORDER_COLOR_INT_OPAQUE_BLACK;
250250 if (color->ui[0] == 1 && color->ui[1] == 1 && color->ui[2] == 1 && color->ui[3] == 1)
251251 return VK_BORDER_COLOR_INT_OPAQUE_WHITE;
252- return VK_BORDER_COLOR_INT_CUSTOM_EXT;
252+ return need_custom ? VK_BORDER_COLOR_INT_CUSTOM_EXT : VK_BORDER_COLOR_INT_TRANSPARENT_BLACK;
253253 }
254254
255255 if (color->f[0] == 0 && color->f[1] == 0 && color->f[2] == 0 && color->f[3] == 0)
@@ -258,7 +258,7 @@ get_border_color(const union pipe_color_union *color, bool is_integer)
258258 return VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK;
259259 if (color->f[0] == 1 && color->f[1] == 1 && color->f[2] == 1 && color->f[3] == 1)
260260 return VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE;
261- return VK_BORDER_COLOR_FLOAT_CUSTOM_EXT;
261+ return need_custom ? VK_BORDER_COLOR_FLOAT_CUSTOM_EXT : VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK;
262262 }
263263
264264 static void *
@@ -302,7 +302,7 @@ zink_create_sampler_state(struct pipe_context *pctx,
302302
303303 bool is_integer = state->border_color_is_integer;
304304
305- sci.borderColor = get_border_color(&state->border_color, is_integer);
305+ sci.borderColor = get_border_color(&state->border_color, is_integer, need_custom);
306306 if (sci.borderColor > VK_BORDER_COLOR_INT_OPAQUE_WHITE && need_custom) {
307307 if (screen->info.have_EXT_custom_border_color &&
308308 screen->info.border_color_feats.customBorderColorWithoutFormat) {
--- a/src/gallium/drivers/zink/zink_resource.c
+++ b/src/gallium/drivers/zink/zink_resource.c
@@ -226,23 +226,16 @@ create_bci(struct zink_screen *screen, const struct pipe_resource *templ, unsign
226226 VK_BUFFER_USAGE_TRANSFER_DST_BIT |
227227 VK_BUFFER_USAGE_STORAGE_BUFFER_BIT;
228228
229- VkFormatProperties props = screen->format_props[templ->format];
230-
231229 bci.usage |= VK_BUFFER_USAGE_UNIFORM_TEXEL_BUFFER_BIT |
232230 VK_BUFFER_USAGE_INDIRECT_BUFFER_BIT |
231+ VK_BUFFER_USAGE_VERTEX_BUFFER_BIT |
233232 VK_BUFFER_USAGE_INDEX_BUFFER_BIT |
234233 VK_BUFFER_USAGE_UNIFORM_BUFFER_BIT |
235234 VK_BUFFER_USAGE_TRANSFORM_FEEDBACK_BUFFER_BIT_EXT |
236235 VK_BUFFER_USAGE_TRANSFORM_FEEDBACK_COUNTER_BUFFER_BIT_EXT;
237- if (props.bufferFeatures & VK_FORMAT_FEATURE_VERTEX_BUFFER_BIT)
238- bci.usage |= VK_BUFFER_USAGE_VERTEX_BUFFER_BIT;
239- if (props.bufferFeatures & VK_FORMAT_FEATURE_UNIFORM_TEXEL_BUFFER_BIT)
240- bci.usage |= VK_BUFFER_USAGE_UNIFORM_TEXEL_BUFFER_BIT;
241236
242- if (bind & PIPE_BIND_SHADER_IMAGE) {
243- assert(props.bufferFeatures & VK_FORMAT_FEATURE_STORAGE_TEXEL_BUFFER_BIT);
237+ if (bind & PIPE_BIND_SHADER_IMAGE)
244238 bci.usage |= VK_BUFFER_USAGE_STORAGE_TEXEL_BUFFER_BIT;
245- }
246239 return bci;
247240 }
248241
--- a/src/gallium/drivers/zink/zink_screen.c
+++ b/src/gallium/drivers/zink/zink_screen.c
@@ -1061,8 +1061,6 @@ zink_flush_frontbuffer(struct pipe_screen *pscreen,
10611061 winsys->displaytarget_unmap(winsys, res->dt);
10621062 }
10631063
1064- winsys->displaytarget_unmap(winsys, res->dt);
1065-
10661064 assert(res->dt);
10671065 if (res->dt)
10681066 winsys->displaytarget_display(winsys, res->dt, winsys_drawable_handle, sub_box);
@@ -1263,11 +1261,7 @@ zink_internal_setup_moltenvk(struct zink_screen *screen)
12631261
12641262 GET_PROC_ADDR_INSTANCE(GetMoltenVKConfigurationMVK);
12651263 GET_PROC_ADDR_INSTANCE(SetMoltenVKConfigurationMVK);
1266-
1267- GET_PROC_ADDR_INSTANCE(GetPhysicalDeviceMetalFeaturesMVK);
12681264 GET_PROC_ADDR_INSTANCE(GetVersionStringsMVK);
1269- GET_PROC_ADDR_INSTANCE(UseIOSurfaceMVK);
1270- GET_PROC_ADDR_INSTANCE(GetIOSurfaceMVK);
12711265
12721266 if (screen->vk_GetVersionStringsMVK) {
12731267 char molten_version[64] = {0};
--- a/src/gallium/drivers/zink/zink_screen.h
+++ b/src/gallium/drivers/zink/zink_screen.h
@@ -139,11 +139,7 @@ struct zink_screen {
139139 #if defined(MVK_VERSION)
140140 PFN_vkGetMoltenVKConfigurationMVK vk_GetMoltenVKConfigurationMVK;
141141 PFN_vkSetMoltenVKConfigurationMVK vk_SetMoltenVKConfigurationMVK;
142-
143- PFN_vkGetPhysicalDeviceMetalFeaturesMVK vk_GetPhysicalDeviceMetalFeaturesMVK;
144142 PFN_vkGetVersionStringsMVK vk_GetVersionStringsMVK;
145- PFN_vkUseIOSurfaceMVK vk_UseIOSurfaceMVK;
146- PFN_vkGetIOSurfaceMVK vk_GetIOSurfaceMVK;
147143 #endif
148144
149145 struct {
--- a/src/gallium/targets/libgl-gdi/libgl_gdi.c
+++ b/src/gallium/targets/libgl-gdi/libgl_gdi.c
@@ -41,6 +41,7 @@
4141 #include "stw_winsys.h"
4242 #include "stw_device.h"
4343 #include "gdi/gdi_sw_winsys.h"
44+#include "pipe/p_screen.h"
4445 #include "pipe/p_context.h"
4546
4647 #ifdef GALLIUM_SOFTPIPE
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -1917,6 +1917,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
19171917 struct brw_reg src[4], dst;
19181918 unsigned int last_insn_offset = p->next_insn_offset;
19191919 bool multiple_instructions_emitted = false;
1920+ tgl_swsb swsb = inst->sched;
19201921
19211922 /* From the Broadwell PRM, Volume 7, "3D-Media-GPGPU", in the
19221923 * "Register Region Restrictions" section: for BDW, SKL:
@@ -1951,8 +1952,10 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
19511952 brw_set_default_exec_size(p, BRW_EXECUTE_16);
19521953 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
19531954 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1955+ brw_set_default_swsb(p, tgl_swsb_src_dep(swsb));
19541956 brw_MOV(p, brw_acc_reg(8), brw_imm_f(0.0f));
19551957 last_insn_offset = p->next_insn_offset;
1958+ swsb = tgl_swsb_dst_dep(swsb, 1);
19561959 }
19571960
19581961 if (!is_accum_used && !inst->eot) {
@@ -2010,7 +2013,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
20102013 brw_set_default_saturate(p, inst->saturate);
20112014 brw_set_default_mask_control(p, inst->force_writemask_all);
20122015 brw_set_default_acc_write_control(p, inst->writes_accumulator);
2013- brw_set_default_swsb(p, inst->sched);
2016+ brw_set_default_swsb(p, swsb);
20142017
20152018 unsigned exec_size = inst->exec_size;
20162019 if (devinfo->ver == 7 && !devinfo->is_haswell &&
@@ -2426,8 +2429,8 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
24262429 }
24272430
24282431 case FS_OPCODE_SCHEDULING_FENCE:
2429- if (inst->sources == 0 && inst->sched.regdist == 0 &&
2430- inst->sched.mode == TGL_SBID_NULL) {
2432+ if (inst->sources == 0 && swsb.regdist == 0 &&
2433+ swsb.mode == TGL_SBID_NULL) {
24312434 if (unlikely(debug_flag))
24322435 disasm_info->use_tail = true;
24332436 break;
--- a/src/intel/compiler/brw_shader.cpp
+++ b/src/intel/compiler/brw_shader.cpp
@@ -1088,7 +1088,8 @@ backend_instruction::writes_accumulator_implicitly(const struct gen_device_info
10881088 ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
10891089 (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP))) ||
10901090 (opcode == FS_OPCODE_LINTERP &&
1091- (!devinfo->has_pln || devinfo->ver <= 6));
1091+ (!devinfo->has_pln || devinfo->ver <= 6)) ||
1092+ (eot && devinfo->ver >= 12); /* See Wa_14010017096. */
10921093 }
10931094
10941095 bool
--- a/src/intel/vulkan/anv_allocator.c
+++ b/src/intel/vulkan/anv_allocator.c
@@ -1670,7 +1670,9 @@ anv_device_alloc_bo(struct anv_device *device,
16701670 new_bo.map = anv_gem_mmap(device, new_bo.gem_handle, 0, size, 0);
16711671 if (new_bo.map == MAP_FAILED) {
16721672 anv_gem_close(device, new_bo.gem_handle);
1673- return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1673+ return vk_errorf(device, &device->vk.base,
1674+ VK_ERROR_OUT_OF_HOST_MEMORY,
1675+ "mmap failed: %m");
16741676 }
16751677 }
16761678
--- a/src/intel/vulkan/anv_batch_chain.c
+++ b/src/intel/vulkan/anv_batch_chain.c
@@ -347,6 +347,7 @@ anv_batch_emit_batch(struct anv_batch *batch, struct anv_batch *other)
347347
348348 static VkResult
349349 anv_batch_bo_create(struct anv_cmd_buffer *cmd_buffer,
350+ uint32_t size,
350351 struct anv_batch_bo **bbo_out)
351352 {
352353 VkResult result;
@@ -357,7 +358,7 @@ anv_batch_bo_create(struct anv_cmd_buffer *cmd_buffer,
357358 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
358359
359360 result = anv_bo_pool_alloc(&cmd_buffer->device->batch_bo_pool,
360- ANV_CMD_BUFFER_BATCH_SIZE, &bbo->bo);
361+ size, &bbo->bo);
361362 if (result != VK_SUCCESS)
362363 goto fail_alloc;
363364
@@ -668,11 +669,16 @@ anv_cmd_buffer_chain_batch(struct anv_batch *batch, void *_data)
668669 {
669670 struct anv_cmd_buffer *cmd_buffer = _data;
670671 struct anv_batch_bo *new_bbo;
672+ /* Cap reallocation to chunk. */
673+ uint32_t alloc_size = MIN2(cmd_buffer->total_batch_size,
674+ ANV_MAX_CMD_BUFFER_BATCH_SIZE);
671675
672- VkResult result = anv_batch_bo_create(cmd_buffer, &new_bbo);
676+ VkResult result = anv_batch_bo_create(cmd_buffer, alloc_size, &new_bbo);
673677 if (result != VK_SUCCESS)
674678 return result;
675679
680+ cmd_buffer->total_batch_size += alloc_size;
681+
676682 struct anv_batch_bo **seen_bbo = u_vector_add(&cmd_buffer->seen_bbos);
677683 if (seen_bbo == NULL) {
678684 anv_batch_bo_destroy(new_bbo, cmd_buffer);
@@ -839,7 +845,11 @@ anv_cmd_buffer_init_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer)
839845
840846 list_inithead(&cmd_buffer->batch_bos);
841847
842- result = anv_batch_bo_create(cmd_buffer, &batch_bo);
848+ cmd_buffer->total_batch_size = ANV_MIN_CMD_BUFFER_BATCH_SIZE;
849+
850+ result = anv_batch_bo_create(cmd_buffer,
851+ cmd_buffer->total_batch_size,
852+ &batch_bo);
843853 if (result != VK_SUCCESS)
844854 return result;
845855
@@ -945,8 +955,14 @@ anv_cmd_buffer_reset_batch_bo_chain(struct anv_cmd_buffer *cmd_buffer)
945955 cmd_buffer->seen_bbos.head = 0;
946956 cmd_buffer->seen_bbos.tail = 0;
947957
948- *(struct anv_batch_bo **)u_vector_add(&cmd_buffer->seen_bbos) =
949- anv_cmd_buffer_current_batch_bo(cmd_buffer);
958+ struct anv_batch_bo *first_bbo = anv_cmd_buffer_current_batch_bo(cmd_buffer);
959+
960+ *(struct anv_batch_bo **)u_vector_add(&cmd_buffer->seen_bbos) = first_bbo;
961+
962+
963+ assert(!cmd_buffer->device->can_chain_batches ||
964+ first_bbo->bo->size == ANV_MIN_CMD_BUFFER_BATCH_SIZE);
965+ cmd_buffer->total_batch_size = first_bbo->bo->size;
950966 }
951967
952968 void
@@ -1024,7 +1040,7 @@ anv_cmd_buffer_end_batch_buffer(struct anv_cmd_buffer *cmd_buffer)
10241040 */
10251041 batch_bo = anv_cmd_buffer_current_batch_bo(cmd_buffer);
10261042 } else if ((cmd_buffer->batch_bos.next == cmd_buffer->batch_bos.prev) &&
1027- (length < ANV_CMD_BUFFER_BATCH_SIZE / 2)) {
1043+ (length < ANV_MIN_CMD_BUFFER_BATCH_SIZE / 2)) {
10281044 /* If the secondary has exactly one batch buffer in its list *and*
10291045 * that batch buffer is less than half of the maximum size, we're
10301046 * probably better of simply copying it into our batch.
@@ -1799,7 +1815,11 @@ setup_execbuf_for_cmd_buffers(struct anv_execbuf *execbuf,
17991815 .buffers_ptr = (uintptr_t) execbuf->objects,
18001816 .buffer_count = execbuf->bo_count,
18011817 .batch_start_offset = 0,
1802- .batch_len = batch->next - batch->start,
1818+ /* On platforms that cannot chain batch buffers because of the i915
1819+ * command parser, we have to provide the batch length. Everywhere else
1820+ * we'll chain batches so no point in passing a length.
1821+ */
1822+ .batch_len = device->can_chain_batches ? 0 : batch->next - batch->start,
18031823 .cliprects_ptr = 0,
18041824 .num_cliprects = 0,
18051825 .DR1 = 0,
@@ -1919,7 +1939,8 @@ anv_queue_execbuf_locked(struct anv_queue *queue,
19191939 submit->perf_query_pool;
19201940
19211941 if (INTEL_DEBUG & DEBUG_SUBMIT) {
1922- fprintf(stderr, "Batch on queue 0\n");
1942+ fprintf(stderr, "Batch offset=0x%x len=0x%x on queue 0\n",
1943+ execbuf.execbuf.batch_start_offset, execbuf.execbuf.batch_len);
19231944 for (uint32_t i = 0; i < execbuf.bo_count; i++) {
19241945 const struct anv_bo *bo = execbuf.bos[i];
19251946
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -1926,20 +1926,7 @@ copy_non_dynamic_state(struct anv_graphics_pipeline *pipeline,
19261926
19271927 if (states & ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY) {
19281928 assert(pCreateInfo->pInputAssemblyState);
1929- bool has_tess = false;
1930- for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
1931- const VkPipelineShaderStageCreateInfo *sinfo = &pCreateInfo->pStages[i];
1932- gl_shader_stage stage = vk_to_mesa_shader_stage(sinfo->stage);
1933- if (stage == MESA_SHADER_TESS_CTRL || stage == MESA_SHADER_TESS_EVAL)
1934- has_tess = true;
1935- }
1936- if (has_tess) {
1937- const VkPipelineTessellationStateCreateInfo *tess_info =
1938- pCreateInfo->pTessellationState;
1939- dynamic->primitive_topology = _3DPRIM_PATCHLIST(tess_info->patchControlPoints);
1940- } else {
1941- dynamic->primitive_topology = pCreateInfo->pInputAssemblyState->topology;
1942- }
1929+ dynamic->primitive_topology = pCreateInfo->pInputAssemblyState->topology;
19431930 }
19441931
19451932 /* Section 9.2 of the Vulkan 1.0.15 spec says:
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -2880,7 +2880,8 @@ struct anv_cmd_pool {
28802880 VkCommandPoolCreateFlags flags;
28812881 };
28822882
2883-#define ANV_CMD_BUFFER_BATCH_SIZE 8192
2883+#define ANV_MIN_CMD_BUFFER_BATCH_SIZE 8192
2884+#define ANV_MAX_CMD_BUFFER_BATCH_SIZE (16 * 1024 * 1024)
28842885
28852886 enum anv_cmd_buffer_exec_mode {
28862887 ANV_CMD_BUFFER_EXEC_MODE_PRIMARY,
@@ -2969,6 +2970,12 @@ struct anv_cmd_buffer {
29692970 * used.
29702971 */
29712972 uint32_t perf_reloc_idx;
2973+
2974+ /**
2975+ * Sum of all the anv_batch_bo sizes allocated for this command buffer.
2976+ * Used to increase allocation size for long command buffers.
2977+ */
2978+ uint32_t total_batch_size;
29722979 };
29732980
29742981 /* Determine whether we can chain a given cmd_buffer to another one. We need
--- a/src/intel/vulkan/gfx7_cmd_buffer.c
+++ b/src/intel/vulkan/gfx7_cmd_buffer.c
@@ -338,7 +338,7 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
338338 ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY)) {
339339 uint32_t topology;
340340 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
341- topology = d->primitive_topology;
341+ topology = pipeline->topology;
342342 else
343343 topology = genX(vk_to_gen_primitive_type)[d->primitive_topology];
344344
--- a/src/intel/vulkan/gfx8_cmd_buffer.c
+++ b/src/intel/vulkan/gfx8_cmd_buffer.c
@@ -637,7 +637,7 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
637637 ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY)) {
638638 uint32_t topology;
639639 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
640- topology = d->primitive_topology;
640+ topology = pipeline->topology;
641641 else
642642 topology = genX(vk_to_gen_primitive_type)[d->primitive_topology];
643643
--- a/src/mesa/drivers/dri/i965/genX_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/genX_pipe_control.c
@@ -495,7 +495,7 @@ genX(emit_raw_pipe_control)(struct brw_context *brw, uint32_t flags,
495495 pc.InstructionCacheInvalidateEnable =
496496 flags & PIPE_CONTROL_INSTRUCTION_INVALIDATE;
497497 pc.NotifyEnable = flags & PIPE_CONTROL_NOTIFY_ENABLE;
498- #if GFX_VER >= 45
498+ #if GFX_VERx10 >= 45
499499 pc.IndirectStatePointersDisable =
500500 flags & PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE;
501501 #endif
--- a/src/mesa/main/bufferobj.c
+++ b/src/mesa/main/bufferobj.c
@@ -1084,8 +1084,18 @@ _mesa_handle_bind_buffer_gen(struct gl_context *ctx,
10841084 _mesa_error(ctx, GL_OUT_OF_MEMORY, "%s", caller);
10851085 return false;
10861086 }
1087- _mesa_HashInsertMaybeLocked(ctx->Shared->BufferObjects, buffer,
1088- *buf_handle, buf != NULL,
1087+ _mesa_HashLockMaybeLocked(ctx->Shared->BufferObjects,
1088+ ctx->BufferObjectsLocked);
1089+ _mesa_HashInsertLocked(ctx->Shared->BufferObjects, buffer,
1090+ *buf_handle, buf != NULL);
1091+ /* If one context only creates buffers and another context only deletes
1092+ * buffers, buffers don't get released because it only produces zombie
1093+ * buffers. Only the context that has created the buffers can release
1094+ * them. Thus, when we create buffers, we prune the list of zombie
1095+ * buffers.
1096+ */
1097+ unreference_zombie_buffers_for_ctx(ctx);
1098+ _mesa_HashUnlockMaybeLocked(ctx->Shared->BufferObjects,
10891099 ctx->BufferObjectsLocked);
10901100 }
10911101
@@ -1763,6 +1773,13 @@ create_buffers(struct gl_context *ctx, GLsizei n, GLuint *buffers, bool dsa)
17631773 */
17641774 _mesa_HashLockMaybeLocked(ctx->Shared->BufferObjects,
17651775 ctx->BufferObjectsLocked);
1776+ /* If one context only creates buffers and another context only deletes
1777+ * buffers, buffers don't get released because it only produces zombie
1778+ * buffers. Only the context that has created the buffers can release
1779+ * them. Thus, when we create buffers, we prune the list of zombie
1780+ * buffers.
1781+ */
1782+ unreference_zombie_buffers_for_ctx(ctx);
17661783
17671784 _mesa_HashFindFreeKeys(ctx->Shared->BufferObjects, buffers, n);
17681785
--- a/src/panfrost/midgard/compiler.h
+++ b/src/panfrost/midgard/compiler.h
@@ -183,6 +183,8 @@ typedef struct midgard_instruction {
183183
184184 midgard_branch branch;
185185 };
186+
187+ unsigned bundle_id;
186188 } midgard_instruction;
187189
188190 typedef struct midgard_block {
--- a/src/panfrost/midgard/midgard_compile.c
+++ b/src/panfrost/midgard/midgard_compile.c
@@ -3204,6 +3204,12 @@ midgard_compile_shader_nir(nir_shader *nir,
32043204 fflush(stdout);
32053205 }
32063206
3207+ /* A shader ending on a 16MB boundary causes INSTR_INVALID_PC faults,
3208+ * workaround by adding some padding to the end of the shader. (The
3209+ * kernel makes sure shader BOs can't cross 16MB boundaries.) */
3210+ if (binary->size)
3211+ memset(util_dynarray_grow(binary, uint8_t, 16), 0, 16);
3212+
32073213 if ((midgard_debug & MIDGARD_DBG_SHADERDB || inputs->shaderdb) &&
32083214 !nir->info.internal) {
32093215 unsigned nr_bundles = 0, nr_ins = 0;
--- a/src/panfrost/midgard/midgard_ra.c
+++ b/src/panfrost/midgard/midgard_ra.c
@@ -842,6 +842,19 @@ mir_spill_register(
842842 /* Allocate TLS slot (maybe) */
843843 unsigned spill_slot = !is_special ? (*spill_count)++ : 0;
844844
845+ /* For special reads, figure out how many bytes we need */
846+ unsigned read_bytemask = 0;
847+
848+ /* If multiple instructions write to this destination, we'll have to
849+ * fill from TLS before writing */
850+ unsigned write_count = 0;
851+
852+ mir_foreach_instr_global_safe(ctx, ins) {
853+ read_bytemask |= mir_bytemask_of_read_components(ins, spill_node);
854+ if (ins->dest == spill_node)
855+ ++write_count;
856+ }
857+
845858 /* For TLS, replace all stores to the spilled node. For
846859 * special reads, just keep as-is; the class will be demoted
847860 * implicitly. For special writes, spill to a work register */
@@ -855,8 +868,6 @@ mir_spill_register(
855868 mir_foreach_instr_in_block_safe(block, ins) {
856869 if (ins->dest != spill_node) continue;
857870
858- midgard_instruction st;
859-
860871 /* Note: it's important to match the mask of the spill
861872 * with the mask of the instruction whose destination
862873 * we're spilling, or otherwise we'll read invalid
@@ -864,20 +875,59 @@ mir_spill_register(
864875 */
865876
866877 if (is_special_w) {
867- st = v_mov(spill_node, spill_slot);
878+ midgard_instruction st = v_mov(spill_node, spill_slot);
868879 st.no_spill |= (1 << spill_class);
869880 st.mask = ins->mask;
870881 st.dest_type = st.src_types[1] = ins->dest_type;
882+
883+ /* Hint: don't rewrite this node */
884+ st.hint = true;
885+
886+ mir_insert_instruction_after_scheduled(ctx, block, ins, st);
871887 } else {
872- ins->dest = spill_index++;
888+ unsigned dest = spill_index++;
889+
890+ if (write_count > 1 && mir_bytemask(ins) != 0xF) {
891+ midgard_instruction read =
892+ v_load_store_scratch(dest, spill_slot, false, 0xF);
893+ mir_insert_instruction_before_scheduled(ctx, block, ins, read);
894+ }
895+
896+ ins->dest = dest;
873897 ins->no_spill |= (1 << spill_class);
874- st = v_load_store_scratch(ins->dest, spill_slot, true, ins->mask);
875- }
876898
877- /* Hint: don't rewrite this node */
878- st.hint = true;
899+ bool move = false;
900+
901+ /* In the same bundle, reads of the destination
902+ * of the spilt instruction need to be direct */
903+ midgard_instruction *it = ins;
904+ while ((it = list_first_entry(&it->link, midgard_instruction, link))
905+ && (it->bundle_id == ins->bundle_id)) {
879906
880- mir_insert_instruction_after_scheduled(ctx, block, ins, st);
907+ if (!mir_has_arg(it, spill_node)) continue;
908+
909+ mir_rewrite_index_src_single(it, spill_node, dest);
910+
911+ /* The spilt instruction will write to
912+ * a work register for `it` to read but
913+ * the spill needs an LD/ST register */
914+ move = true;
915+ }
916+
917+ if (move)
918+ dest = spill_index++;
919+
920+ midgard_instruction st =
921+ v_load_store_scratch(dest, spill_slot, true, ins->mask);
922+ mir_insert_instruction_after_scheduled(ctx, block, ins, st);
923+
924+ if (move) {
925+ midgard_instruction mv = v_mov(ins->dest, dest);
926+ mv.no_spill |= (1 << spill_class);
927+
928+ mir_insert_instruction_after_scheduled(ctx, block, ins, mv);
929+ }
930+ }
881931
882932 if (!is_special)
883933 ctx->spills++;
@@ -885,13 +935,6 @@ mir_spill_register(
885935 }
886936 }
887937
888- /* For special reads, figure out how many bytes we need */
889- unsigned read_bytemask = 0;
890-
891- mir_foreach_instr_global_safe(ctx, ins) {
892- read_bytemask |= mir_bytemask_of_read_components(ins, spill_node);
893- }
894-
895938 /* Insert a load from TLS before the first consecutive
896939 * use of the node, rewriting to use spilled indices to
897940 * break up the live range. Or, for special, insert a
--- a/src/panfrost/midgard/midgard_schedule.c
+++ b/src/panfrost/midgard/midgard_schedule.c
@@ -1416,6 +1416,10 @@ schedule_block(compiler_context *ctx, midgard_block *block)
14161416 else
14171417 break;
14181418
1419+ for (unsigned i = 0; i < bundle.instruction_count; ++i)
1420+ bundle.instructions[i]->bundle_id =
1421+ ctx->quadword_count + block->quadword_count;
1422+
14191423 util_dynarray_append(&bundles, midgard_bundle, bundle);
14201424 block->quadword_count += midgard_tag_props[bundle.tag].size;
14211425 }
--- a/src/util/00-mesa-defaults.conf
+++ b/src/util/00-mesa-defaults.conf
@@ -236,6 +236,10 @@ TODO: document the other workarounds.
236236 <option name="allow_glsl_cross_stage_interpolation_mismatch" value="true"/>
237237 </application>
238238
239+ <application name="We Happy Few" executable="GlimpseGame">
240+ <option name="allow_glsl_cross_stage_interpolation_mismatch" value="true"/>
241+ </application>
242+
239243 <application name="Google Earth VR" executable="Earth.exe">
240244 <option name="allow_glsl_builtin_const_expression" value="true"/>
241245 <option name="allow_glsl_relaxed_es" value="true"/>
--- a/src/util/fossilize_db.c
+++ b/src/util/fossilize_db.c
@@ -104,25 +104,122 @@ create_foz_db_filenames(char *cache_path, char *name, char **filename,
104104 return true;
105105 }
106106
107+
108+/* This looks at stuff that was added to the index since the last time we looked at it. This is safe
109+ * to do without locking the file as we assume the file is append only */
110+static void
111+update_foz_index(struct foz_db *foz_db, FILE *db_idx, unsigned file_idx)
112+{
113+ uint64_t offset = ftell(db_idx);
114+ fseek(db_idx, 0, SEEK_END);
115+ size_t len = ftell(db_idx);
116+ uint64_t parsed_offset = offset;
117+
118+ if (offset == len)
119+ return;
120+
121+ fseek(db_idx, offset, SEEK_SET);
122+ while (offset < len) {
123+ parsed_offset = offset;
124+
125+ char bytes_to_read[FOSSILIZE_BLOB_HASH_LENGTH + sizeof(struct foz_payload_header)];
126+ struct foz_payload_header *header;
127+
128+ /* Corrupt entry. Our process might have been killed before we
129+ * could write all data.
130+ */
131+ if (offset + sizeof(bytes_to_read) > len)
132+ break;
133+
134+ /* NAME + HEADER in one read */
135+ if (fread(bytes_to_read, 1, sizeof(bytes_to_read), db_idx) !=
136+ sizeof(bytes_to_read))
137+ break;
138+
139+ offset += sizeof(bytes_to_read);
140+ header = (struct foz_payload_header*)&bytes_to_read[FOSSILIZE_BLOB_HASH_LENGTH];
141+
142+ /* Corrupt entry. Our process might have been killed before we
143+ * could write all data.
144+ */
145+ if (offset + header->payload_size > len ||
146+ header->payload_size != sizeof(uint64_t))
147+ break;
148+
149+ char hash_str[FOSSILIZE_BLOB_HASH_LENGTH + 1] = {0};
150+ memcpy(hash_str, bytes_to_read, FOSSILIZE_BLOB_HASH_LENGTH);
151+
152+ struct foz_db_entry *entry = ralloc(foz_db->mem_ctx,
153+ struct foz_db_entry);
154+ entry->header = *header;
155+ entry->file_idx = file_idx;
156+ _mesa_sha1_hex_to_sha1(entry->key, hash_str);
157+
158+ /* read cache item offset from index file */
159+ uint64_t cache_offset;
160+ if (fread(&cache_offset, 1, sizeof(cache_offset), db_idx) !=
161+ sizeof(cache_offset))
162+ return;
163+
164+ entry->offset = cache_offset;
165+
166+ /* Truncate the entry's hash string to a 64bit hash for use with a
167+ * 64bit hash table for looking up file offsets.
168+ */
169+ hash_str[16] = '\0';
170+ uint64_t key = strtoull(hash_str, NULL, 16);
171+ _mesa_hash_table_u64_insert(foz_db->index_db, key, entry);
172+
173+ offset += header->payload_size;
174+ }
175+
176+
177+ fseek(db_idx, parsed_offset, SEEK_SET);
178+}
179+
180+/* exclusive flock with timeout. timeout is in nanoseconds */
181+static int lock_file_with_timeout(FILE *f, int64_t timeout)
182+{
183+ int err;
184+ int fd = fileno(f);
185+ int64_t iterations = MAX2(DIV_ROUND_UP(timeout, 1000000), 1);
186+
187+ /* Since there is no blocking flock with timeout and we don't want to totally spin on getting the
188+ * lock, use a nonblocking method and retry every millisecond. */
189+ for (int64_t iter = 0; iter < iterations; ++iter) {
190+ err = flock(fd, LOCK_EX | LOCK_NB);
191+ if (err == 0 || errno != EAGAIN)
192+ break;
193+ usleep(1000);
194+ }
195+ return err;
196+}
197+
107198 static bool
108199 load_foz_dbs(struct foz_db *foz_db, FILE *db_idx, uint8_t file_idx,
109200 bool read_only)
110201 {
111- int err = flock(fileno(foz_db->file[file_idx]), LOCK_EX | LOCK_NB);
112- if (err == -1)
113- goto fail;
114-
115- err = flock(fileno(db_idx), LOCK_EX | LOCK_NB);
116- if (err == -1)
117- goto fail;
118-
119202 /* Scan through the archive and get the list of cache entries. */
120203 fseek(db_idx, 0, SEEK_END);
121204 size_t len = ftell(db_idx);
122205 rewind(db_idx);
123206
124- if (!read_only)
125- fseek(foz_db->file[file_idx], 0, SEEK_END);
207+ /* Try not to take the lock if len > 0, but if it is 0 we take the lock to initialize the files. */
208+ if (len == 0) {
209+ /* Wait for 100 ms in case of contention, after that we prioritize getting the app started. */
210+ int err = lock_file_with_timeout(foz_db->file[file_idx], 100000000);
211+ if (err == -1)
212+ goto fail;
213+
214+ err = lock_file_with_timeout(db_idx, 100000000);
215+ if (err == -1)
216+ goto fail;
217+
218+ /* Compute length again so we know nobody else did it in the meantime */
219+ fseek(db_idx, 0, SEEK_END);
220+ len = ftell(db_idx);
221+ rewind(db_idx);
222+ }
126223
127224 if (len != 0) {
128225 uint8_t magic[FOZ_REF_MAGIC_SIZE];
@@ -138,67 +235,6 @@ load_foz_dbs(struct foz_db *foz_db, FILE *db_idx, uint8_t file_idx,
138235 version < FOSSILIZE_FORMAT_MIN_COMPAT_VERSION)
139236 goto fail;
140237
141- size_t offset = FOZ_REF_MAGIC_SIZE;
142- size_t begin_append_offset = len;
143-
144- while (offset < len) {
145- begin_append_offset = offset;
146-
147- char bytes_to_read[FOSSILIZE_BLOB_HASH_LENGTH + sizeof(struct foz_payload_header)];
148- struct foz_payload_header *header;
149-
150- /* Corrupt entry. Our process might have been killed before we
151- * could write all data.
152- */
153- if (offset + sizeof(bytes_to_read) > len)
154- break;
155-
156- /* NAME + HEADER in one read */
157- if (fread(bytes_to_read, 1, sizeof(bytes_to_read), db_idx) !=
158- sizeof(bytes_to_read))
159- goto fail;
160-
161- offset += sizeof(bytes_to_read);
162- header = (struct foz_payload_header*)&bytes_to_read[FOSSILIZE_BLOB_HASH_LENGTH];
163-
164- /* Corrupt entry. Our process might have been killed before we
165- * could write all data.
166- */
167- if (offset + header->payload_size > len ||
168- header->payload_size != sizeof(uint64_t))
169- break;
170-
171- char hash_str[FOSSILIZE_BLOB_HASH_LENGTH + 1] = {0};
172- memcpy(hash_str, bytes_to_read, FOSSILIZE_BLOB_HASH_LENGTH);
173-
174- struct foz_db_entry *entry = ralloc(foz_db->mem_ctx,
175- struct foz_db_entry);
176- entry->header = *header;
177- entry->file_idx = file_idx;
178- _mesa_sha1_hex_to_sha1(entry->key, hash_str);
179-
180- /* read cache item offset from index file */
181- uint64_t cache_offset;
182- if (fread(&cache_offset, 1, sizeof(cache_offset), db_idx) !=
183- sizeof(cache_offset))
184- return false;
185-
186- entry->offset = cache_offset;
187-
188- /* Truncate the entry's hash string to a 64bit hash for use with a
189- * 64bit hash table for looking up file offsets.
190- */
191- hash_str[16] = '\0';
192- uint64_t key = strtoull(hash_str, NULL, 16);
193- _mesa_hash_table_u64_insert(foz_db->index_db, key, entry);
194-
195- offset += header->payload_size;
196- }
197-
198- if (!read_only && offset != len) {
199- if (fseek(db_idx, begin_append_offset, SEEK_SET) < 0)
200- goto fail;
201- }
202238 } else {
203239 /* Appending to a fresh file. Make sure we have the magic. */
204240 if (fwrite(stream_reference_magic_and_version, 1,
@@ -212,10 +248,17 @@ load_foz_dbs(struct foz_db *foz_db, FILE *db_idx, uint8_t file_idx,
212248 goto fail;
213249 }
214250
251+ flock(fileno(db_idx), LOCK_UN);
252+ flock(fileno(foz_db->file[file_idx]), LOCK_UN);
253+
254+ update_foz_index(foz_db, db_idx, file_idx);
255+
215256 foz_db->alive = true;
216257 return true;
217258
218259 fail:
260+ flock(fileno(db_idx), LOCK_UN);
261+ flock(fileno(foz_db->file[file_idx]), LOCK_UN);
219262 foz_destroy(foz_db);
220263 return false;
221264 }
@@ -329,12 +372,15 @@ foz_read_entry(struct foz_db *foz_db, const uint8_t *cache_key_160bit,
329372 struct foz_db_entry *entry =
330373 _mesa_hash_table_u64_search(foz_db->index_db, hash);
331374 if (!entry) {
375+ update_foz_index(foz_db, foz_db->db_idx, 0);
376+ entry = _mesa_hash_table_u64_search(foz_db->index_db, hash);
377+ }
378+ if (!entry) {
332379 simple_mtx_unlock(&foz_db->mtx);
333380 return NULL;
334381 }
335382
336383 uint8_t file_idx = entry->file_idx;
337- off_t offset = ftell(foz_db->file[file_idx]);
338384 if (fseek(foz_db->file[file_idx], entry->offset, SEEK_SET) < 0)
339385 goto fail;
340386
@@ -367,16 +413,12 @@ foz_read_entry(struct foz_db *foz_db, const uint8_t *cache_key_160bit,
367413 if (size)
368414 *size = data_sz;
369415
370- /* Reset file offset to the end of the file ready for writing */
371- fseek(foz_db->file[file_idx], offset, SEEK_SET);
372-
373416 return data;
374417
375418 fail:
376419 free(data);
377420
378421 /* reading db entry failed. reset the file offset */
379- fseek(foz_db->file[file_idx], offset, SEEK_SET);
380422 simple_mtx_unlock(&foz_db->mtx);
381423
382424 return NULL;
@@ -393,8 +435,20 @@ foz_write_entry(struct foz_db *foz_db, const uint8_t *cache_key_160bit,
393435 if (!foz_db->alive)
394436 return false;
395437
438+ /* Wait for 1 second. This is done outside of the mutex as I believe there is more potential
439+ * for file contention than mtx contention of significant length. */
440+ int err = lock_file_with_timeout(foz_db->file[0], 1000000000);
441+ if (err == -1)
442+ goto fail_file;
443+
444+ err = lock_file_with_timeout(foz_db->db_idx, 1000000000);
445+ if (err == -1)
446+ goto fail_file;
447+
396448 simple_mtx_lock(&foz_db->mtx);
397449
450+ update_foz_index(foz_db, foz_db->db_idx, 0);
451+
398452 struct foz_db_entry *entry =
399453 _mesa_hash_table_u64_search(foz_db->index_db, hash);
400454 if (entry) {
@@ -409,6 +463,8 @@ foz_write_entry(struct foz_db *foz_db, const uint8_t *cache_key_160bit,
409463 header.payload_size = blob_size;
410464 header.crc = util_hash_crc32(blob, blob_size);
411465
466+ fseek(foz_db->file[0], 0, SEEK_END);
467+
412468 /* Write hash header to db */
413469 char hash_str[FOSSILIZE_BLOB_HASH_LENGTH + 1]; /* 40 digits + null */
414470 _mesa_sha1_format(hash_str, cache_key_160bit);
@@ -458,11 +514,16 @@ foz_write_entry(struct foz_db *foz_db, const uint8_t *cache_key_160bit,
458514 _mesa_hash_table_u64_insert(foz_db->index_db, hash, entry);
459515
460516 simple_mtx_unlock(&foz_db->mtx);
517+ flock(fileno(foz_db->db_idx), LOCK_UN);
518+ flock(fileno(foz_db->file[0]), LOCK_UN);
461519
462520 return true;
463521
464522 fail:
465523 simple_mtx_unlock(&foz_db->mtx);
524+fail_file:
525+ flock(fileno(foz_db->db_idx), LOCK_UN);
526+ flock(fileno(foz_db->file[0]), LOCK_UN);
466527 return false;
467528 }
468529 #else
Show on old repository browser