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external-mesa: List of commits

external/mesa


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Rev. Time Author
eddbc6f marshmallow-x86 android-x86-6.0-r3 2017-04-20 16:53:26 Chih-Wei Huang

Merge remote-tracking branch 'mesa/17.0' into marshmallow-x86

2a502c3 2017-04-20 16:52:49 Chih-Wei Huang

Revert "android: change some PIPE to SVGA3D format mappings"

Seems we don't need this now.

This reverts commit ec8dd7fc8139eb385aa7a13afd292f014aeb45ed.

1243496 2017-04-17 22:42:37 Emil Velikov

docs: add sha256 checksums for 17.0.4

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

367bafc 2017-04-17 22:38:04 Emil Velikov

docs: add release notes for 17.0.4

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

0feeceb 2017-04-17 22:33:57 Emil Velikov

Update version to 17.0.4

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

0e032a4 2017-04-13 21:41:51 Fabio Estevam

loader: Move non-error message to debug level

Currently when running mesa on imx6 the following loader warnings
are seen:

MESA-LOADER: device is not located on the PCI bus
MESA-LOADER: device is not located on the PCI bus
MESA-LOADER: device is not located on the PCI bus
Using display 0x1920948 with EGL version 1.4

As this is not an error message, change it to debug level in
order to have a cleaner log output.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 78c57726335fe22cb4579bcf562d2394adc234b5)
Nominated-by: Rob Clark <robdclark@gmail.com> (IRC)

b7d3c71 2017-04-12 21:30:22 Alex Smith

radv: Invalidate L2 for TRANSFER_WRITE barriers

CP DMA and PKT3_WRITE_DATA (in CmdUpdateBuffer) don't (currently) write
through L2. Therefore, to make these writes visible to later accesses
we must invalidate L2 rather than just writing it back, to avoid the
possibility that stale data is read through L2.

Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.0" <mesa-stable@lists.freedesktop.org>
[Bas: patch is a backport for 17.0 of the cherry-pick below]
(cherry picked from commit bc5d587a80b64fb3e0a5ea8067e6317fbca2bbc5)

a6114f0 2017-04-12 21:30:22 Julien Isorce

radeon_drm_bo: explicitly check return value of drmCommandWriteRead

CID 1313492

Signed-off-by: Julien Isorce <jisorce@oblong.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 521860b2a92bab6394546e6af8709c07e2292033)
Nominated-by: Emil Velikov <emil.velikov@collabora.com>

0f51d37 2017-04-12 21:30:22 Julien Isorce

radeon: initialize hole variable before calling container_of

Like in a few other places in that radeon_drm_bo.c file.

CID 715739.

Signed-off-by: Julien Isorce <jisorce@oblong.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit ce27b27c38acd5a92cf45e7ddc2434f2c04191ee)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99515
Nominated-by: Mauro Rossi <issor.oruam@gmail.com>

1b2bcb6 2017-04-12 21:30:22 Julien Isorce

winsys/radeon: check null return from radeon_cs_create_fence in cs_flush

Follow-up of patch:
"radeon_cs_create_fence: check null return from radeon_winsys_bo_create"

radeon_drm_cs_flush
radeon_cs_create_fence
radeon_winsys_bo_create

Signed-off-by: Julien Isorce <jisorce@oblong.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit d08c0930af8aaef5bdf80df618bb906e0b349830)
[Emil Velikov: resolve trivial conflicts]
Nominated-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
src/gallium/winsys/radeon/drm/radeon_drm_cs.c

99468c2 2017-04-12 21:30:21 Julien Isorce

winsys/radeon: check null in radeon_cs_create_fence

Fixes the following segmentation fault:

radeon_drm_cs_add_buffer (bo=0x0) at radeon_drm_cs.c
-> if (!bo->handle)
(gdb) bt
0 radeon_drm_cs_add_buffer (bo=0x0) at radeon_drm_cs.c
1 0x00007fffe73575de in radeon_cs_create_fence radeon_drm_cs.c
2 0x00007fffe7358c48 in radeon_drm_cs_flush radeon_drm_cs.c

Signed-off-by: Julien Isorce <jisorce@oblong.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit d09edb01468ca385b6a8ffe29ac434dc42a78d07)
Nominated-by: Emil Velikov <emil.velikov@collabora.com>

c0a73dd 2017-04-12 21:30:21 Emil Velikov

Revert "freedreno: fix memory leak"

This reverts commit c57a03585052e3bd7d61d1307cae9a922e663c20.

As requested by Rob Clark

"This seems to be causing a performance regression (reported by
Nicolas).. and the leak it fixes is quite hypothetical. (Ie. hit by
apps that destroy/create context many times.)

On master, I think this can be solved by switching on 'reorder' by
default but that is probably too much of a behaviour change for
stable."

f3ae08b 2017-04-12 21:30:21 Jerome Duval

haiku/winsys: fix dt prototype args

Add the missing front_private, introduced with earlier commit.

(cherry picked from commit 62e27170a7f7a90091b4121002b7ce209ac7ccb0)
Fixes: 2b676570960 ("gallium/swrast: fix front buffer blitting. (v2)")
Nominated-by: Emil Velikov <emil.velikov@collabora.com>
[Emil Velikov: add commit message, fixes tag]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

c1c3933 2017-04-12 21:30:21 Jerome Duval

haiku: build fixes around debug defines

Move the os/os_misc.h include further up, since it's the one that
implicitly provides the PIPE_OS_HAIKU define.

(cherry picked from commit 40b0c8666c337fd0fdff42ce70703cd300abcf0c)
Fixes: 373f118c6c7 ("gallium: do not wrap header inclusion in")
Nominated-by: Emil Velikov <emil.velikov@collabora.com>
[Emil Velikov: add commit message, fixes tag]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

a8e217d 2017-04-12 21:30:21 Kenneth Graunke

i965: Set kernel features before computing max GL version.

We check these bitfields when computing the Haswell max GL version.
We need to set them ahead of time, or they won't exist, and all our
checks will fail. That sets the max core profile GL version to 4.2.

This introduces the bizarre situation where asking for a GL context
with version 4.3+ fails, but asking for a GL core profile context
with version <= 4.2 actually promotes you a 4.5 context.

GLX_MESA_query_renderer also reported the bogus 4.2 value.
Now it shows 4.5.

Cc: "17.0" <mesa-stable@lists.freedesktop.org>
Reported-and-tested-by: Rafael Ristovski <rafael.ristovski@gmail.com>
(cherry picked from commit 02ccd8f52cffcc25e5fefdd0f900cf04230395f4)
[Emil Velikov: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
src/mesa/drivers/dri/i965/intel_screen.c

05eb1c7 2017-04-12 19:32:28 Kenneth Graunke

i965: Skip register write detection when possible.

Detecting register write support by trial and error introduces a
stall at screen creation time, which it would be nice to avoid.
Certain command parser versions guarantee this will work (see the
giant comment in intelInitScreen2 below, or a few commits ago):

- Ivybridge: version >= 1 (kernel v3.16)
- Baytrail: version >= 2 (kernel v3.19)
- Haswell: version >= 7 (kernel v4.8)

For simplicity, we don't bother with version 1 in this patch.

This assumes that the user hasn't disabled aliasing PPGTT via a kernel
command line parameter. Don't do that - you're only breaking things.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
(cherry picked from commit 5e29af5f772c1e1b02a4cc46d2f7d3b5d2151ad8)

e7f872f 2017-04-12 19:32:28 Kenneth Graunke

i965: Set screen->cmd_parser_version to 0 if we can't write registers.

If we can't write registers, then the effective command parser version
is 0 - it may exist, but it's not usefully enabling anything.

See kernel commit 1ca3712ca3429a617ed6c5f87718e4f6fe4ae0c6 (in v4.8)
where the kernel starts doing this for us. This makes us do more or
less the same thing on older kernels.

This should preserve a bit of sanity by allowing us to perform a
screen->cmd_parser_version > N check to determine that we really can
use the features promised by command parser version N.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
(cherry picked from commit 31693a13f8fbc52d4f19f1e8800a4edabeecbe19)
[Emil Velikov: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
src/mesa/drivers/dri/i965/intel_screen.c

20319f5 2017-04-12 19:32:28 Kenneth Graunke

i965: Document the sad story of the kernel command parser.

This should help us figure out the complexities of which kernel
versions we need to get various features on various platforms.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
(cherry picked from commit 4a2ad6b145b4dd0d19a8e5e0ee6bed09e08ce0eb)

a0a48b6 2017-04-12 19:32:28 Ilia Mirkin

nouveau: when mapping a persistent buffer, synchronize on former xfers

If the buffer is being used, we should wait for those uses to be
complete before returning the map.

Fixes: GL45-CTS.direct_state_access.buffers_functional
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit d9cc58d6ec56e676b1285508a4118a83f5325833)

b6168c3 2017-04-12 19:32:28 Ilia Mirkin

nvc0: increase texture buffer object alignment to 256 for pre-GM107

We currently don't pass the low byte of the address via the surface
info, so in order to work with images, these have to implicitly be
aligned to 256. The proprietary driver also doesn't go out of its way to
provide lower alignment.

Fixes GL45-CTS.texture_buffer.texture_buffer_texture_buffer_range

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 8036809799c453b02f4c8fedbb5faaeb19af90c2)

12d7da7 2017-04-12 19:32:28 Ilia Mirkin

nvc0/ir: fix overwriting of offset register with interpolateAtOffset

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 57a744025a2f705d29f60b0eac6e50f8a1ea6203)

4900fa3 2017-04-12 19:32:27 Ilia Mirkin

nvc0/ir: fix LSB/BFE/BFI implementations

Overwriting the src register is a very bad idea - it logically maps onto
the TGSI registers, and so is effectively overwriting the source values.

Reported-by: Boyan Ding <boyan.j.ding@gmail.com>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 60f5766db48fe81f55f4b7be47c2be27bdbe2c10)

29a7d73 2017-04-12 19:32:27 Jason Ekstrand

i965/blorp: Bump the batch space estimate

Commit f938354362655a378d474c5f79c52cea9852ab91 recently increased the
alignment on vertex buffer data from 32 to 64. This caused us to
consume a bit more batch than we were before and we now go over the
estimate by a small amount on certain blits on gen8+. This commit bumps
then gen8 batch estimate by a bit to compensate. Haswell and older
still seems to be well within the limit.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100582
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit c9c39812b91c8104bc0bea16053312547846249c)

ddd83c5 2017-04-12 19:32:27 Alex Deucher

radeonsi: add new polaris10 pci id

Reviewed-by: Christian König <christian.koenig@amd.com>
Cc: 13.0 17.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit d921af62f5761b331039eee1497861b5826ecf82)

04df217 2017-04-12 19:32:27 Jason Ekstrand

i965/blorp: Align vertex buffers to 64B

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit f938354362655a378d474c5f79c52cea9852ab91)
[Emil Velikov: brw_state_batch has different signature]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
src/mesa/drivers/dri/i965/genX_blorp_exec.c

33a9bed 2017-04-12 19:32:27 Jason Ekstrand

anv/blorp: Align vertex buffers to 64B

This fixes issues seen when adding support for full 48-bit addresses.
The 48-bit addresses themselves have nothing to do with it other than
that it caused the kernel to place buffers slightly differently so they
interacted differently with the caches.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 5d1ba2cb04f58b0c887304f0b8adda0b5623a710)

f509c83 2017-04-12 19:32:27 Jason Ekstrand

anv/pipeline: Properly handle unset gl_Layer and gl_ViewportIndex

When the shader does not set one of these values, they are supposed to
get a default value of 0. We have hardware bits in 3DSTATE_CLIP for
this but haven't been setting them. This fixes the intermittent failure
of dEQP-VK.geometry.layered.3d.render_to_default_layer.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit c6f69eea6ac549fc2ffa46944de4dd82c9b53329)

f77cecf 2017-04-12 19:32:27 Jason Ekstrand

i965/fs: Always provide a default LOD of 0 for TXS and TXL

We already provide a default LOD for textureQueryLevels and texture() on
non-fragment stages. However, there are more cases where one is needed
such as textureSize(gsampler2DMS*) in SPIR-V. Instead of trying to list
out all of the cases one at a time, just provide the default for all TXS
and TXL operations. This fixes a shader validation error in the new
Sascha deferredmultisampling demo which uses textureSize(gsampler2DMS).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100391
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 3503b2714b98684a2ceba5f4fd9a5bfbfbcaad38)

d20d8fd 2017-04-12 19:32:27 Marek Olšák

targets: export radeon winsys_create functions to silence LLVM warning

It silences the following radeonsi LLVM warning due to a previous
commit adding an LLVM workaround:
"mesa: for the -simplifycfg-sink-common option: may only occur zero or one
times!"

Cc: 17.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by; Emil Velikov <emil.velikov@collabora.com>

(cherry picked from commit 18b12bf53351e1a902dc1f2e527a94ec8d8f3eff)

c0e343f 2017-04-12 19:32:27 Michal Srb

st: Add cubeMapFace parameter to st_finalize_texture.

st_finalize_texture always accesses image at face 0, but it may not be
set if we are working with cubemap that had other face set.

This fixes crash in piglit
same-attachment-glFramebufferTexture2D-GL_DEPTH_STENCIL_ATTACHMENT.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
(cherry picked from commit 52f9ccefcb75a9d42307890d7714b1cd92e864cb)

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