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cc1101driver: Commit


Commit MetaInfo

Revision2602 (tree)
Time2014-10-02 13:25:09
Authorblackzoro

Log Message

現在フォルダを整理中

Change Summary

Incremental Difference

--- trunk/CC1101_AT/CC1101_source_ATmega88/default/Makefile (nonexistent)
+++ trunk/CC1101_AT/CC1101_source_ATmega88/default/Makefile (revision 2602)
@@ -0,0 +1,80 @@
1+###############################################################################
2+# Makefile for the project CC1101driver
3+###############################################################################
4+
5+## General Flags
6+PROJECT = CC1101driver
7+MCU = atmega88
8+TARGET = CC1101driver.elf
9+CC = avr-gcc
10+
11+CPP = avr-g++
12+
13+## Options common to compile, link and assembly rules
14+COMMON = -mmcu=$(MCU)
15+
16+## Compile options common for all C compilation units.
17+CFLAGS = $(COMMON)
18+CFLAGS += -Wall -gdwarf-2 -std=gnu99 -Os -funsigned-char -funsigned-bitfields -fpack-struct -fshort-enums
19+CFLAGS += -MD -MP -MT $(*F).o -MF dep/$(@F).d
20+
21+## Assembly specific flags
22+ASMFLAGS = $(COMMON)
23+ASMFLAGS += $(CFLAGS)
24+ASMFLAGS += -x assembler-with-cpp -Wa,-gdwarf2
25+
26+## Linker flags
27+LDFLAGS = $(COMMON)
28+LDFLAGS += -Wl,-Map=CC1101driver.map
29+
30+
31+## Intel Hex file production flags
32+HEX_FLASH_FLAGS = -R .eeprom -R .fuse -R .lock -R .signature
33+
34+HEX_EEPROM_FLAGS = -j .eeprom
35+HEX_EEPROM_FLAGS += --set-section-flags=.eeprom="alloc,load"
36+HEX_EEPROM_FLAGS += --change-section-lma .eeprom=0 --no-change-warnings
37+
38+
39+## Objects that must be built in order to link
40+OBJECTS = cc1100.o main.o spi1.o i2c.o
41+
42+## Objects explicitly added by the user
43+LINKONLYOBJECTS =
44+
45+## Build
46+all: $(TARGET) CC1101driver.hex CC1101driver.eep CC1101driver.lss## Compile
47+cc1100.o: ../cc1100.c
48+ $(CC) $(INCLUDES) $(CFLAGS) -c $<
49+
50+main.o: ../main.c
51+ $(CC) $(INCLUDES) $(CFLAGS) -c $<
52+
53+spi1.o: ../spi1.c
54+ $(CC) $(INCLUDES) $(CFLAGS) -c $<
55+
56+i2c.o: ../i2c.c
57+ $(CC) $(INCLUDES) $(CFLAGS) -c $<
58+
59+##Link
60+$(TARGET): $(OBJECTS)
61+ $(CC) $(LDFLAGS) $(OBJECTS) $(LINKONLYOBJECTS) $(LIBDIRS) $(LIBS) -o $(TARGET)
62+
63+%.hex: $(TARGET)
64+ avr-objcopy -O ihex $(HEX_FLASH_FLAGS) $< $@
65+
66+%.eep: $(TARGET)
67+ -avr-objcopy $(HEX_EEPROM_FLAGS) -O ihex $< $@ || exit 0
68+
69+%.lss: $(TARGET)
70+ avr-objdump -h -S $< > $@
71+
72+## Clean target
73+.PHONY: clean
74+clean:
75+ -rm -rf $(OBJECTS) CC1101driver.elf dep/* CC1101driver.hex CC1101driver.eep CC1101driver.lss CC1101driver.map
76+
77+
78+## Other dependencies
79+-include $(shell mkdir dep 2>NUL) $(wildcard dep/*)
80+
--- trunk/CC1101_AT/CC1101_source_ATmega88/default/dep/i2c.o.d (nonexistent)
+++ trunk/CC1101_AT/CC1101_source_ATmega88/default/dep/i2c.o.d (revision 2602)
@@ -0,0 +1,53 @@
1+i2c.o: ../i2c.c c:/winavr-20100110/lib/gcc/../../avr/include/avr/io.h \
2+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/sfr_defs.h \
3+ c:/winavr-20100110/lib/gcc/../../avr/include/inttypes.h \
4+ c:/winavr-20100110/lib/gcc/../../avr/include/stdint.h \
5+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/iom88.h \
6+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/iomx8.h \
7+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/portpins.h \
8+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/common.h \
9+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/version.h \
10+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/fuse.h \
11+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/lock.h \
12+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/interrupt.h \
13+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/eeprom.h \
14+ c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stddef.h \
15+ c:/winavr-20100110/lib/gcc/../../avr/include/string.h \
16+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/sleep.h \
17+ c:/winavr-20100110/lib/gcc/../../avr/include/util/twi.h ../macro.h
18+
19+c:/winavr-20100110/lib/gcc/../../avr/include/avr/io.h:
20+
21+c:/winavr-20100110/lib/gcc/../../avr/include/avr/sfr_defs.h:
22+
23+c:/winavr-20100110/lib/gcc/../../avr/include/inttypes.h:
24+
25+c:/winavr-20100110/lib/gcc/../../avr/include/stdint.h:
26+
27+c:/winavr-20100110/lib/gcc/../../avr/include/avr/iom88.h:
28+
29+c:/winavr-20100110/lib/gcc/../../avr/include/avr/iomx8.h:
30+
31+c:/winavr-20100110/lib/gcc/../../avr/include/avr/portpins.h:
32+
33+c:/winavr-20100110/lib/gcc/../../avr/include/avr/common.h:
34+
35+c:/winavr-20100110/lib/gcc/../../avr/include/avr/version.h:
36+
37+c:/winavr-20100110/lib/gcc/../../avr/include/avr/fuse.h:
38+
39+c:/winavr-20100110/lib/gcc/../../avr/include/avr/lock.h:
40+
41+c:/winavr-20100110/lib/gcc/../../avr/include/avr/interrupt.h:
42+
43+c:/winavr-20100110/lib/gcc/../../avr/include/avr/eeprom.h:
44+
45+c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stddef.h:
46+
47+c:/winavr-20100110/lib/gcc/../../avr/include/string.h:
48+
49+c:/winavr-20100110/lib/gcc/../../avr/include/avr/sleep.h:
50+
51+c:/winavr-20100110/lib/gcc/../../avr/include/util/twi.h:
52+
53+../macro.h:
--- trunk/CC1101_AT/CC1101_source_ATmega88/default/dep/main.o.d (nonexistent)
+++ trunk/CC1101_AT/CC1101_source_ATmega88/default/dep/main.o.d (revision 2602)
@@ -0,0 +1,64 @@
1+main.o: ../main.c c:/winavr-20100110/lib/gcc/../../avr/include/avr/io.h \
2+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/sfr_defs.h \
3+ c:/winavr-20100110/lib/gcc/../../avr/include/inttypes.h \
4+ c:/winavr-20100110/lib/gcc/../../avr/include/stdint.h \
5+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/iom88.h \
6+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/iomx8.h \
7+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/portpins.h \
8+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/common.h \
9+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/version.h \
10+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/fuse.h \
11+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/lock.h \
12+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/interrupt.h \
13+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/eeprom.h \
14+ c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stddef.h \
15+ c:/winavr-20100110/lib/gcc/../../avr/include/string.h \
16+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/wdt.h \
17+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/sleep.h ../macro.h \
18+ ../cc1100.h ../cc1100_globals.h ../cc1100_gdo.h ../spi1.h ../i2c.h
19+
20+c:/winavr-20100110/lib/gcc/../../avr/include/avr/io.h:
21+
22+c:/winavr-20100110/lib/gcc/../../avr/include/avr/sfr_defs.h:
23+
24+c:/winavr-20100110/lib/gcc/../../avr/include/inttypes.h:
25+
26+c:/winavr-20100110/lib/gcc/../../avr/include/stdint.h:
27+
28+c:/winavr-20100110/lib/gcc/../../avr/include/avr/iom88.h:
29+
30+c:/winavr-20100110/lib/gcc/../../avr/include/avr/iomx8.h:
31+
32+c:/winavr-20100110/lib/gcc/../../avr/include/avr/portpins.h:
33+
34+c:/winavr-20100110/lib/gcc/../../avr/include/avr/common.h:
35+
36+c:/winavr-20100110/lib/gcc/../../avr/include/avr/version.h:
37+
38+c:/winavr-20100110/lib/gcc/../../avr/include/avr/fuse.h:
39+
40+c:/winavr-20100110/lib/gcc/../../avr/include/avr/lock.h:
41+
42+c:/winavr-20100110/lib/gcc/../../avr/include/avr/interrupt.h:
43+
44+c:/winavr-20100110/lib/gcc/../../avr/include/avr/eeprom.h:
45+
46+c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stddef.h:
47+
48+c:/winavr-20100110/lib/gcc/../../avr/include/string.h:
49+
50+c:/winavr-20100110/lib/gcc/../../avr/include/avr/wdt.h:
51+
52+c:/winavr-20100110/lib/gcc/../../avr/include/avr/sleep.h:
53+
54+../macro.h:
55+
56+../cc1100.h:
57+
58+../cc1100_globals.h:
59+
60+../cc1100_gdo.h:
61+
62+../spi1.h:
63+
64+../i2c.h:
--- trunk/CC1101_AT/CC1101_source_ATmega88/default/dep/cc1100.o.d (nonexistent)
+++ trunk/CC1101_AT/CC1101_source_ATmega88/default/dep/cc1100.o.d (revision 2602)
@@ -0,0 +1,51 @@
1+cc1100.o: ../cc1100.c \
2+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/io.h \
3+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/sfr_defs.h \
4+ c:/winavr-20100110/lib/gcc/../../avr/include/inttypes.h \
5+ c:/winavr-20100110/lib/gcc/../../avr/include/stdint.h \
6+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/iom88.h \
7+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/iomx8.h \
8+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/portpins.h \
9+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/common.h \
10+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/version.h \
11+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/fuse.h \
12+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/lock.h \
13+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/signal.h \
14+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/interrupt.h ../spi1.h \
15+ ../macro.h ../cc1100.h ../cc1100_globals.h ../cc1100_gdo.h
16+
17+c:/winavr-20100110/lib/gcc/../../avr/include/avr/io.h:
18+
19+c:/winavr-20100110/lib/gcc/../../avr/include/avr/sfr_defs.h:
20+
21+c:/winavr-20100110/lib/gcc/../../avr/include/inttypes.h:
22+
23+c:/winavr-20100110/lib/gcc/../../avr/include/stdint.h:
24+
25+c:/winavr-20100110/lib/gcc/../../avr/include/avr/iom88.h:
26+
27+c:/winavr-20100110/lib/gcc/../../avr/include/avr/iomx8.h:
28+
29+c:/winavr-20100110/lib/gcc/../../avr/include/avr/portpins.h:
30+
31+c:/winavr-20100110/lib/gcc/../../avr/include/avr/common.h:
32+
33+c:/winavr-20100110/lib/gcc/../../avr/include/avr/version.h:
34+
35+c:/winavr-20100110/lib/gcc/../../avr/include/avr/fuse.h:
36+
37+c:/winavr-20100110/lib/gcc/../../avr/include/avr/lock.h:
38+
39+c:/winavr-20100110/lib/gcc/../../avr/include/avr/signal.h:
40+
41+c:/winavr-20100110/lib/gcc/../../avr/include/avr/interrupt.h:
42+
43+../spi1.h:
44+
45+../macro.h:
46+
47+../cc1100.h:
48+
49+../cc1100_globals.h:
50+
51+../cc1100_gdo.h:
--- trunk/CC1101_AT/CC1101_source_ATmega88/default/dep/spi1.o.d (nonexistent)
+++ trunk/CC1101_AT/CC1101_source_ATmega88/default/dep/spi1.o.d (revision 2602)
@@ -0,0 +1,38 @@
1+spi1.o: ../spi1.c c:/winavr-20100110/lib/gcc/../../avr/include/avr/io.h \
2+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/sfr_defs.h \
3+ c:/winavr-20100110/lib/gcc/../../avr/include/inttypes.h \
4+ c:/winavr-20100110/lib/gcc/../../avr/include/stdint.h \
5+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/iom88.h \
6+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/iomx8.h \
7+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/portpins.h \
8+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/common.h \
9+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/version.h \
10+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/fuse.h \
11+ c:/winavr-20100110/lib/gcc/../../avr/include/avr/lock.h ../spi1.h \
12+ ../macro.h
13+
14+c:/winavr-20100110/lib/gcc/../../avr/include/avr/io.h:
15+
16+c:/winavr-20100110/lib/gcc/../../avr/include/avr/sfr_defs.h:
17+
18+c:/winavr-20100110/lib/gcc/../../avr/include/inttypes.h:
19+
20+c:/winavr-20100110/lib/gcc/../../avr/include/stdint.h:
21+
22+c:/winavr-20100110/lib/gcc/../../avr/include/avr/iom88.h:
23+
24+c:/winavr-20100110/lib/gcc/../../avr/include/avr/iomx8.h:
25+
26+c:/winavr-20100110/lib/gcc/../../avr/include/avr/portpins.h:
27+
28+c:/winavr-20100110/lib/gcc/../../avr/include/avr/common.h:
29+
30+c:/winavr-20100110/lib/gcc/../../avr/include/avr/version.h:
31+
32+c:/winavr-20100110/lib/gcc/../../avr/include/avr/fuse.h:
33+
34+c:/winavr-20100110/lib/gcc/../../avr/include/avr/lock.h:
35+
36+../spi1.h:
37+
38+../macro.h:
--- trunk/CC1101_AT/CC1101_source_ATmega88/macro.h (nonexistent)
+++ trunk/CC1101_AT/CC1101_source_ATmega88/macro.h (revision 2602)
@@ -0,0 +1,276 @@
1+#ifndef _MACRO_H_
2+#define _MACRO_H_
3+
4+#define GFSK_DEF
5+#define PRG_VERSION 0xCD
6+//#define S3_DELAY 1
7+
8+typedef unsigned char u8;
9+typedef unsigned short u16;
10+typedef unsigned char uint8_t;
11+
12+//extern u8 status;
13+
14+#define bool u8
15+#define false 0
16+#define true 1
17+
18+#define LOW 0
19+#define HIGH 1
20+
21+
22+#define PCDDR DDRC
23+#define PCSEL PINC
24+#define PCINTIE
25+
26+
27+#define PBDDR DDRB
28+
29+#define B_CTL REGISTER_BIT(PORTB,0)
30+#define CS_CC1101 REGISTER_BIT(PORTB,2)
31+
32+#define CS_CC1101_LOW CS_CC1101 =0
33+#define CS_CC1101_HIGH CS_CC1101 =1
34+
35+
36+#define B_CTL_LOW B_CTL =0
37+#define B_CTL_HIGH B_CTL =1
38+
39+#define OUTPUT_HIGH OUTPUT = 1
40+#define OUTPUT_LOW OUTPUT = 0
41+
42+
43+#define SCLR_HIGH SCLR = 1
44+#define SCLR_LOW SCLR = 0
45+
46+
47+
48+
49+enum {
50+ STARTUP=0,
51+ CHK_INPUT,
52+ DATA_SEND,
53+ CHK_DATA_SEND,
54+ POWER_DONW
55+};
56+
57+
58+enum {
59+ SETUP_NONE=0,
60+ SETUP_READY,
61+ SETUP_TRX,
62+ SETUP_WRITE
63+};
64+
65+enum {
66+ MASTER=0,
67+ TEST_MDOE,
68+ SLAVE,
69+ SETUP
70+};
71+
72+enum {
73+
74+ OSC_8MHZ=0,
75+ OSC_1MHZ
76+};
77+
78+
79+
80+
81+enum {
82+ SL_BOOT=0,
83+ SL_SLEEP,
84+ SL_SEND,
85+ SL_SEND_WAIT,
86+ SL_SCH_SEND,
87+ SL_ALARM_WAIT,
88+ MS_BOOT,
89+ MS_UART_RECV,
90+};
91+
92+
93+enum {
94+ SR_RESET=0,
95+ SR_SET
96+};
97+
98+
99+
100+enum {
101+ ALARM_2SEC,
102+ ALARM_1MIN,
103+ ALARM_2MIN,
104+ ALARM_3MIN,
105+ ALARM_5MIN,
106+ ALARM_30MIN,
107+ ALARM_1hour,
108+ ALARM_24hour
109+};
110+
111+
112+
113+enum {
114+ SLEEP_2SEC = 0,
115+ SLEEP_1MIN = 1,
116+ SLEEP_2MIN = 3,
117+ SLEEP_5MIN = 9
118+};
119+
120+
121+
122+enum {
123+ AD_PIN_TEMPERATURE=0x02,
124+ AD_PIN_TAMPA=0x06,
125+ AD_PIN_BATT_LOW=0x07
126+};
127+
128+
129+enum {
130+ AD_VAL_FROM_R=0,
131+ AD_VAL_FROM_L=0x20
132+};
133+
134+
135+typedef struct _ctl_data_
136+{
137+ u8 adj_freq;
138+ u8 freq_add_sub;
139+ u8 serial[3];
140+ u8 adj_temper;
141+ u8 temper_add_sub;
142+}ctl_data;
143+
144+
145+
146+typedef struct _rtc_time_
147+{
148+
149+ u8 chk_hour;
150+ u8 chk_min;
151+ u8 curt_hour;
152+ u8 curt_min;
153+
154+}rtc_time;
155+
156+
157+
158+
159+typedef struct _fifo_option_
160+{
161+ u8 env_data[8];
162+ u8 level[7];
163+}f_option_t;
164+
165+
166+typedef struct _txfifo_data_
167+{
168+ u8 length;
169+ u8 slave_id[6];
170+ u8 master_id[3];
171+ u8 user_data0;
172+ u8 user_data1;
173+ u8 bat_val;
174+ u8 master_ctl;
175+ u8 setup_mode;
176+ u8 version_l;
177+ u8 rssi;
178+ u8 lqi;
179+ f_option_t opt;
180+}fifo_t;
181+
182+
183+typedef struct _reg_slave_
184+{
185+ u8 serial[3];
186+ u8 slave_ctl_set;
187+}reg_slave;
188+
189+
190+typedef struct _reg_cmd_
191+{
192+ u8 length;
193+ u8 cmd[4];
194+}reg_cmd;
195+
196+
197+typedef struct _reg_param_
198+{
199+ u8 length;
200+ u8 param[4];
201+}reg_param;
202+
203+
204+
205+
206+
207+typedef struct _client_status_
208+{
209+ u8 setup_mode;
210+ u8 version_l;
211+ u8 type;
212+ u8 serial[6];
213+ u8 sessionflag;
214+ u8 user_data0;
215+ u8 user_data1;
216+ u8 bat_val;
217+ u8 system_osc;
218+ u8 status;
219+ u8 send_err_cnt;
220+ u8 alert;
221+ u8 alert_old_temp;
222+ u8 make_alert;
223+ u8 make_alert_old;
224+ u8 sleep_time;
225+ u8 input_data;
226+ u8 fixed_temperature;
227+ u16 fixed_temperature02;
228+ u8 reserve[8];
229+
230+}client_status;
231+
232+
233+typedef struct _cc1101_client_
234+{
235+ client_status status;
236+ fifo_t fifo;
237+ ctl_data ctl;
238+}cc1101_client;
239+
240+
241+
242+
243+
244+typedef struct
245+{
246+ unsigned int bit0:1;
247+ unsigned int bit1:1;
248+ unsigned int bit2:1;
249+ unsigned int bit3:1;
250+ unsigned int bit4:1;
251+ unsigned int bit5:1;
252+ unsigned int bit6:1;
253+ unsigned int bit7:1;
254+} _io_reg;
255+
256+typedef struct _time_set_
257+{
258+ u8 hour;
259+ u8 min;
260+ u8 sec;
261+}time_set_t;
262+
263+
264+extern u8 edge_val_gdo0;
265+extern u8 edge_val_gdo1;
266+
267+extern u8 gdo0_status;
268+extern u8 gdo1_status;
269+
270+
271+
272+
273+
274+#define REGISTER_BIT(rg,bt) ((volatile _io_reg*)&rg)->bit##bt
275+
276+#endif
--- trunk/CC1101_AT/CC1101_source_ATmega88/main.c (nonexistent)
+++ trunk/CC1101_AT/CC1101_source_ATmega88/main.c (revision 2602)
@@ -0,0 +1,1869 @@
1+
2+
3+#include <avr/io.h>
4+#include <avr/interrupt.h>
5+#include <avr/eeprom.h>
6+#include <string.h>
7+#include <stdint.h>
8+#include <avr/wdt.h>
9+
10+#include <avr/sleep.h>
11+#include "macro.h"
12+#include "cc1100.h"
13+#include "cc1100_globals.h"
14+#include "spi1.h"
15+#include "i2c.h"
16+
17+
18+
19+
20+
21+#define EEPROM __attribute__((section(".eeprom")))
22+ctl_data EEPROM gctl_data;
23+reg_slave EEPROM greg_slave[100];
24+int EEPROM eprom_level[14];
25+char EEPROM eprom_fixid[3];
26+char EEPROM test_mode;
27+char EEPROM monitor_state;
28+int EEPROM wdt_cnt;
29+int EEPROM cnt_loop_break;
30+
31+
32+const time_set_t time_set[4]={
33+ {0x09,0x59,0x57}, //ALARM_2SEC
34+ {0x09,0x59,0x00}, //ALARM_1MIN
35+ {0x09,0x58,0x00}, //ALARM_2MIN
36+ {0x09,0x55,0x00}, //ALARM_5MIN
37+ #if 0
38+ {0x09,0x57,0x00}, //ALARM_3MIN
39+ {0x09,0x56,0x00}, //ALARM_4MIN
40+ {0x09,0x55,0x00}, //ALARM_5MIN
41+ {0x09,0x30,0x00}, //ALARM_30MIN
42+ {0x09,0x00,0x00}, //ALARM_1hour
43+ {0x10,0X00,0x01}, //ALARM_24hour
44+ #endif
45+ };
46+
47+reg_t reg_net_alarm[7]=
48+ {
49+ {0x0E,0x00},
50+ {0x0C,0x10},
51+ {0x0B,0x00},
52+ {0x02,0x00},
53+ {0x01,0x00},
54+ {0x00,0x00},
55+ {0x0E,0x40}
56+ };
57+
58+reg_t reg_next_sch_alarm[9]=
59+{
60+ {0x0e,0x00},
61+ {0x0C,0x00},
62+ {0x0B,0x00},
63+ {0x0a,0x00},
64+ {0x03,0x00},
65+ {0x02,0x00},
66+ {0x01,0x00},
67+ {0x00,0x01},
68+ {0x0e,0x60}
69+};
70+
71+u8 day_cnt[4]={ 0x40,0x20,0x08,0x04};
72+
73+
74+cc1101_client gClient;
75+char gWCmd[6][16];
76+u8 wakeup_condition=0;
77+u8 get_user0_data=0;
78+char rx_char[60];
79+u8 uart_data;
80+u8 uart_rx_index=0;
81+u8 uart_rx_length;
82+reg_slave tSlave,tSlave2;
83+ctl_data tCtl;
84+u16 gTemperature;
85+char * pC;
86+
87+u8 sr_status=0x00,sr_status_old=0x00;
88+u8 emg_status = 0x00;
89+u8 tampa_status = 0x00,tampa_status_old = 0x00;
90+u8 setup_mode = SETUP_NONE;
91+u8 gslave_master_ctl = 0x00;
92+u8 fix_id_mel[3]={0x4d,0x45,0x4c};
93+u16 gTemperature;
94+u8 gLevel;
95+u8 gRecvRssi=0x00, gRecvLqi= 0x00;
96+f_option_t gOpt;
97+int level_offset[14]={-3,-4,-4,-4,-3,-3,-1,0,1,2,3,4,5,5};
98+const int default_offset[14]={-3,-4,-4,-4,-3,-3,-1,0,1,2,3,4,5,5};
99+int SRBuf[2];
100+u8 SRBufIndex;
101+char gTestMode;
102+
103+void udelay(u16 usec)
104+{
105+ register u8 i;
106+
107+ for(i = 0 ; i < usec ; i++)
108+ {
109+ asm volatile("NOP");
110+ }
111+}
112+
113+
114+void mdelay(u16 msec)
115+{
116+ register u16 i;
117+
118+ for(i = 0 ; i < msec ; i++)
119+ {
120+ udelay(250);
121+ udelay(250);
122+ udelay(250);
123+ udelay(50);
124+ }
125+}
126+
127+
128+void sdelay(u16 msec)
129+{
130+ register u16 i;
131+
132+ for(i=0;i<msec;i++)
133+ {
134+ mdelay(1000);
135+ }
136+}
137+
138+
139+void putc_(u8 data)
140+{
141+ while(!(UCSR0A & (1<<UDRE0)));
142+ UDR0 = data;
143+}
144+
145+void putb(u8 data)
146+{
147+ if(data < 0x0a)
148+ putc_('0' + data);
149+ else
150+ putc_('a' + (data-10));
151+}
152+
153+void puthex(u8 data)
154+{
155+ putb(data/16);
156+ putb(data%16);
157+}
158+
159+
160+u8 putchr2hex(u8 data)
161+{
162+ u8 tmp;
163+
164+ if(data&0x60)
165+ tmp = data - 0x60;
166+ else
167+ tmp = data - 0x30;
168+
169+ return tmp;
170+}
171+
172+
173+u8 chr2hex(u8 data_h,u8 data_l)
174+{
175+ u8 test;
176+
177+ data_h = putchr2hex(data_h);
178+ data_l = putchr2hex(data_l);
179+
180+ test=(data_l&0x0F)|((data_h<<4)&0xF0);
181+
182+ return test;
183+}
184+
185+
186+void putstr(u8 * data)
187+{
188+ int i =0 ;
189+
190+ for( i = 0 ;i < 50 ; i++)
191+ {
192+ putc_(data[i]);
193+ if(data[i] == 0x0d || data[i] == 0x00) break;
194+ }
195+}
196+
197+
198+char asc_to_hex(u8 asc)
199+{
200+ if((asc >= '0') && (asc <= '9')) return (asc - '0');
201+ else if((asc >= 'A') && (asc <= 'F')) return (asc - 'A' + 0x0a);
202+ else if((asc >= 'a') && (asc <= 'f')) return (asc - 'a' + 0x0a);
203+ else return 0xff;
204+}
205+
206+u8 AscToHex(char * val)
207+{
208+ u8 tmp;
209+
210+ tmp = asc_to_hex(val[0]) << 4 | asc_to_hex(val[1]);
211+
212+ return tmp;
213+}
214+
215+char asc_to_int(u8 asc)
216+{
217+ if((asc >= '0') && (asc <= '9')) return (asc - '0');
218+ else return 0xff;
219+}
220+
221+int AscToInt(char * val)
222+{
223+ u8 tmp;
224+
225+ tmp = (asc_to_int(val[0]) * 10) + asc_to_int(val[1]);
226+
227+ return tmp;
228+}
229+
230+
231+char hex_to_asc(u8 hex)
232+{
233+ char da;
234+ da = hex & 0x0f;
235+ if((da >= 0) && (da <= 9)) return ('0' + da);
236+ else return ('a' + da - 0x0a);
237+}
238+
239+void hexToAsc(u8 hex,u8 * dest)
240+{
241+ dest[0] = hex_to_asc((hex >> 4 ) & 0x0f);
242+ dest[1] = hex_to_asc((hex >> 0 ) & 0x0f);
243+}
244+
245+
246+
247+u8 my_eeprom_read_byte(u16 addr)
248+{
249+ eeprom_busy_wait();
250+ return eeprom_read_byte((u8 *)addr);
251+}
252+
253+void my_eeprom_read_block(u8 * data,u8 *addr,u16 length)
254+{
255+ eeprom_busy_wait();
256+ return eeprom_read_block(data,addr,length);
257+}
258+
259+void led_onoff(u8 onoff)
260+{
261+ if(onoff == 1)
262+ B_CTL_HIGH;
263+ else
264+ B_CTL_LOW;
265+}
266+
267+
268+void led_flasher(u8 count,u16 msec)
269+{
270+ u8 i=0;
271+ while(i<count)
272+ {
273+ B_CTL_HIGH;
274+ mdelay(msec);
275+ B_CTL_LOW;
276+ mdelay(msec);
277+ i++;
278+ }
279+}
280+
281+
282+void inituart()
283+{
284+ UCSR0A = 0x02; //U2X = 1
285+ UCSR0B = 0x00; // Rx/Tx enable
286+ UCSR0C = 0x06; // 8bit, 1 stop bit, no parity
287+ UBRR0H = 0x00;
288+ UBRR0L = 0x33; // Baudrate 9600
289+ UCSR0B = 0x98; // rx / tx enable , rx int enable 0x98
290+}
291+
292+
293+void hw_setup(void)
294+{
295+
296+ CLKPR = _BV(CLKPCE); // CLKPCEビットを1にする
297+ CLKPR = 0b0001; // 2分周にする
298+
299+
300+
301+ DDRC=0x00;
302+ DDRD=0x00;
303+ DDRB=0x0D;
304+
305+ /*pull_up*/
306+ #if 0
307+ PORTC = (1<<PC0) | (1<<PC1);
308+ PORTD = 0xf3;
309+ #else
310+ PORTC = (1<<PC6) |(1<<PC0) | (1<<PC1);
311+ PORTD = 0xf7;
312+ #endif
313+
314+
315+ PORTB = 0x01; //for yellow LED
316+
317+
318+
319+ EICRA &= ~(1<<ISC00); //INT0の割り込み発生条件を立下り検知でトリガで固定
320+ EICRA &= ~(1<<ISC01);
321+
322+ EICRA &= ~(1<<ISC10); //INT1の割り込み発生条件を立下り検知でトリガで固定
323+ EICRA &= ~(1<<ISC11);
324+}
325+
326+
327+
328+u16 ad_get_val(u8 ad_ch,u8 adlar)
329+{
330+ u8 i=0;
331+ u8 ad_data_l=0;
332+ u8 ad_data_h=0;
333+ u16 ad=0;
334+
335+ //u8 temp=0xc0;
336+
337+ ADCSRA = 0b10000100; // AD許可:1 AD開始:0 AD自動起動:0 AD割込:0 AD完了割込:0 ck/16
338+
339+ // reg set
340+ ADMUX = 0xc0 | adlar | (ad_ch & 0x0f);
341+
342+ // dummy
343+ for(i = 0 ; i < 4 ; i++)
344+ {
345+ ADCSRA |= _BV(ADSC); //変換開始 要ﾙｰﾌﾟ内
346+ while((ADCSRA&0x10)==0x00);
347+ ADCSRA |= (1<<ADIF); //ADIF clear
348+ }
349+
350+ // read
351+ ADCSRA |= _BV(ADSC); //変換開始 要ﾙｰﾌﾟ内
352+ while((ADCSRA&0x10)==0x00);
353+ ADCSRA |= (1<<ADIF); //ADIF clear
354+
355+ ad_data_l = ADCL;
356+ ad_data_h = ADCH;
357+
358+ ad = ad_data_h;
359+ ad = (ad << 2);
360+ ad = (ad & 0x03FC) | ((ad_data_l >> 6) & 0x03);
361+
362+ ADCSRA = 0b00000100; // AD許可:0 AD開始:0 AD自動起動:0 AD割込:0 AD完了割込:0 ck/16
363+ return ad;
364+}
365+
366+
367+
368+void temperature_test_enable(void)
369+{
370+ cc1100_cmd_idle();
371+ PORTC &= ~(1<<PC2); //pull-up disenable
372+ cc1100_write_reg(CC1100_REG_PTEST,0xBF);
373+ cc1100_cfg_gdo0(0x80);
374+}
375+
376+
377+void temperature_test_disenable(void)
378+{
379+ cc1100_cfg_gdo0(0x3F);
380+ cc1100_write_reg(CC1100_REG_PTEST,0x7F);
381+}
382+
383+
384+u16 temperature_get(void)
385+{
386+ PORTC &= ~(1<<PC2); //pull-up disenable
387+ temperature_test_enable();
388+
389+ DIDR0 |= (1<<ADC2D); //ADC2 Digital disable
390+
391+ gTemperature = ad_get_val(AD_PIN_TEMPERATURE,AD_VAL_FROM_L);
392+
393+ DIDR0 &= ~(1<<ADC2D); //ADC2 Digital enable
394+
395+ temperature_test_disenable();
396+ PORTC |= (1<<PC2); //pull-up enable
397+
398+ return gTemperature;
399+}
400+
401+
402+int reg_slave_num_serch(u8 * id)
403+{
404+ u8 i=0;
405+ u8 Serial[6];
406+
407+ memcpy(Serial,fix_id_mel,3);
408+
409+ for(i=0;i<100;i++)
410+ {
411+ my_eeprom_read_block((u8 *)&tSlave,(u8 *)&greg_slave[i],sizeof(reg_slave));
412+
413+ memcpy((u8 *)&Serial[3],(u8 *)tSlave.serial,3);
414+ if(memcmp((u8 *)Serial,(u8 *)id,6) == 0)
415+ {
416+ return i;
417+ }
418+ }
419+ return -1;
420+}
421+
422+
423+
424+
425+u8 get_input_data(void)
426+{
427+ u8 reg = 0;
428+
429+ reg = (reg & 0xFF) | (((PIND) << 2) & 0x80); //F_SEL2
430+ reg = (reg & 0xFF) | (((PIND) << 2) & 0x40); //F_SEL1
431+
432+ reg = (reg & 0xFF) | (((PIND) >> 2) & 0x20); //D_SEL2
433+ reg = (reg & 0xFF) | (((PIND) >> 2) & 0x10); //D_SEL1
434+
435+ reg = (reg & 0xFF) | (((PINC) << 2) & 0x08); //M_SEL2
436+ reg = (reg & 0xFF) | (((PINC) << 2) & 0x04); //M_SEL1
437+
438+
439+ return reg;
440+}
441+
442+void level_change_hex(u8 * data)
443+{
444+ int i;
445+
446+ for(i = 0 ;i < 14 ; i+=2)
447+ {
448+ data[i/2] = (((level_offset[i] + 7) << 4) & 0xf0) | ((level_offset[i+1] + 7) & 0x0f);
449+ }
450+}
451+
452+void hex_change_level(u8 * data)
453+{
454+ int i;
455+
456+ for(i = 0 ;i < 7 ; i++)
457+ {
458+ level_offset[i * 2] = (int)((data[i] >> 4 ) & 0x0f) - 7;
459+ level_offset[i* 2 + 1] = (int)((data[i] ) & 0x0f) - 7;
460+ }
461+
462+ eeprom_busy_wait();
463+ eeprom_write_block(level_offset,&eprom_level,sizeof(level_offset));
464+}
465+
466+void slave_fifo_preset(fifo_t * fifo)
467+{
468+
469+ memcpy(fifo->slave_id,gClient.status.serial,6);
470+ memset(fifo->master_id,0xff,3);
471+ fifo->user_data0 = gClient.status.user_data0;
472+ if(gClient.status.bat_val < 0xbf)
473+ fifo->user_data0 |= (1<<0); // BATT_LOW active
474+
475+ if(gClient.status.status != SL_SCH_SEND)
476+ {
477+ if(tampa_status == 1)
478+ fifo->user_data0 |= (0x01 << 1); // Tampa
479+ else
480+ fifo->user_data0 &= ~(0x01 << 1); // Tampa
481+ }
482+
483+ #if 0
484+ if(tampa_status == 1)
485+ fifo->user_data0 |= (0x01 << 1); // Tampa
486+ else
487+ fifo->user_data0 &= ~(0x01 << 1); // Tampa
488+ #endif
489+
490+
491+ fifo->user_data1 = gslave_master_ctl;
492+ fifo->bat_val = gClient.status.bat_val;
493+ fifo->setup_mode = (setup_mode == SETUP_NONE ? 0 : 1) ;
494+ fifo->master_ctl = 0x00;
495+ fifo->version_l = PRG_VERSION;
496+
497+
498+ if(setup_mode != SETUP_NONE)
499+ {
500+ fifo->length = sizeof(fifo_t);
501+ fifo->opt.env_data[0] = (gTemperature >> 8) & 0xff;
502+ fifo->opt.env_data[1] = (gTemperature >> 0) & 0xff;
503+ fifo->opt.env_data[2] = my_eeprom_read_byte((u16)&gctl_data.adj_freq); //serial no 01;
504+ fifo->opt.env_data[3] = my_eeprom_read_byte((u16)&gctl_data.freq_add_sub); //serial no 01;
505+ fifo->opt.env_data[4] = my_eeprom_read_byte((u16)&gctl_data.adj_temper); //serial no 01;
506+ fifo->opt.env_data[5] = my_eeprom_read_byte((u16)&gctl_data.temper_add_sub); //serial no 01;
507+ level_change_hex(fifo->opt.level);
508+ }
509+ else
510+ {
511+ fifo->length = sizeof(fifo_t) - sizeof(f_option_t);
512+ }
513+}
514+
515+
516+
517+void tx_fifo_write(u8 * data,u8 length)
518+{
519+ data[0] = length + 2;
520+ cc1100_fifo_put(data,1);
521+ cc1100_fifo_put(data,length+2);
522+}
523+
524+
525+
526+u8 rx_fifo_read(u8 * data)
527+{
528+ u8 length;
529+
530+ cc1100_fifo_get(&length,1);
531+
532+ cc1100_fifo_get(data,length);
533+
534+ if(gClient.status.type != MASTER)
535+ {
536+ cc1100_fifo_get(&gClient.fifo.rssi,1);
537+ cc1100_fifo_get(&gClient.fifo.lqi,1);
538+ }
539+ else
540+ {
541+ cc1100_fifo_get(&gRecvRssi,1);
542+ cc1100_fifo_get(&gRecvLqi,1);
543+ }
544+
545+ return length - 2;
546+}
547+
548+
549+
550+#define GET_FR() (gClient.status.input_data & 0xC0) >> 6
551+
552+enum {
553+ CA_WAVE_CH5=3,
554+ CA_WAVE_CH9=2,
555+ CA_WAVE_CH13=1,
556+ CA_WAVE_CH17=0
557+};
558+
559+u8 get_frq()
560+{
561+ return (((~get_input_data()) >> 6) & 0x03);
562+}
563+
564+
565+void cc1101_carrier_wave_setup(void)
566+{
567+
568+ volatile u16 frq;
569+ volatile int fr;
570+ volatile u16 offset;
571+ volatile u16 level;
572+ volatile u16 temperature;
573+
574+
575+ fr = get_frq();//GET_FR();
576+
577+ //frq = 0x68FC + (fr * 0x0040); //25kHz next Ver0xAD
578+ //frq = 0x68FC + (fr * 0x003E); //25kHz next Ver0xAE
579+ frq = 0x68FC + (fr * 0x003F); //25kHz next
580+
581+
582+
583+ if(my_eeprom_read_byte((u16)&gctl_data.freq_add_sub) == 0x80)
584+ frq -= my_eeprom_read_byte((u16)&gctl_data.adj_freq);
585+ else
586+ frq += my_eeprom_read_byte((u16)&gctl_data.adj_freq);
587+
588+
589+ temperature = temperature_get();
590+
591+
592+ if(my_eeprom_read_byte((u16)&gctl_data.temper_add_sub) == 0x80)
593+ temperature -= my_eeprom_read_byte((u16)&gctl_data.adj_temper);
594+ else
595+ temperature += my_eeprom_read_byte((u16)&gctl_data.adj_temper);
596+
597+
598+ offset = 0x0339 - temperature;
599+
600+ level = 13 - (offset / 0x0c);
601+
602+
603+ if(offset & 0x8000)
604+ level = 13;
605+ else if((offset / 0x0c)>13)
606+ level = 0;
607+
608+ gLevel = level;
609+
610+ frq += level_offset[level];
611+
612+
613+ cc1100_write_reg(CC1100_REG_FREQ2, 0x10);
614+ cc1100_write_reg(CC1100_REG_FREQ1, (frq >> 8) & 0xff);
615+ cc1100_write_reg(CC1100_REG_FREQ0, frq & 0xff);
616+}
617+
618+
619+
620+void init_voltcomparator(void)
621+{
622+ ACSR = 0x4b;
623+ DIDR1 = 0x02;
624+}
625+
626+
627+
628+
629+
630+
631+void add_batt_low(void)
632+{
633+ u16 bat_val;
634+
635+ B_CTL_HIGH;
636+ mdelay(1);
637+
638+
639+ bat_val = ad_get_val(AD_PIN_BATT_LOW,AD_VAL_FROM_L);
640+
641+ gClient.status.bat_val = (bat_val>>2);
642+
643+
644+ B_CTL_LOW;
645+}
646+
647+
648+u8 get_sr_status(void)
649+{
650+ if((PINB >> 7) & 0x01)
651+ return 1;
652+
653+ return 0;
654+
655+}
656+
657+
658+
659+void sig_set(void)
660+{
661+ mdelay(10);
662+ gClient.status.make_alert = 0x00;
663+
664+
665+ //emg_status_old = emg_status;
666+ if(!(PINB & 0x02))
667+ emg_status = 0x01;
668+ else
669+ emg_status = 0x00;
670+
671+ sr_status_old = sr_status;
672+ sr_status = get_sr_status();
673+
674+
675+ tampa_status_old = tampa_status;
676+
677+// tampa_status = ad_get_val(AD_PIN_TAMPA,AD_VAL_FROM_L);
678+
679+ if(ad_get_val(AD_PIN_TAMPA,AD_VAL_FROM_L) > 0x80)
680+ tampa_status = 0;
681+ else
682+ tampa_status = 1;
683+
684+ //tampa_status = ad_get_val(AD_PIN_TAMPA,AD_VAL_FROM_L);
685+
686+
687+ add_batt_low();
688+
689+
690+ if(emg_status == 0x01 && emg_status == 0x01 && gClient.status.status != SL_ALARM_WAIT )
691+ gClient.status.make_alert |= 0x08;
692+
693+ if(sr_status_old ^ sr_status)
694+ {
695+ gClient.status.make_alert |= 0x04;
696+ }
697+
698+ if((tampa_status_old ^ tampa_status))
699+ gClient.status.make_alert |= 0x02;
700+
701+ if(gClient.status.bat_val < 0xbf)
702+ gClient.status.make_alert |= (1<<0); // BATT_LOW active
703+}
704+
705+
706+u8 sig_status(void)
707+{
708+ u8 status = 0x00;
709+ gClient.status.make_alert = 0x00;
710+
711+
712+ //emg_status_old = emg_status;
713+ if(!(PINB & 0x02))
714+ status|= 0x08;
715+
716+
717+ if(get_sr_status())
718+ status|= 0x04;
719+
720+
721+ tampa_status = ad_get_val(AD_PIN_TAMPA,AD_VAL_FROM_L);
722+
723+ //if(tampa_status == 0x00)
724+ if(tampa_status < 0x80)
725+ status|= 0x02;
726+
727+
728+ add_batt_low();
729+
730+
731+ if(gClient.status.bat_val < 0xbf)
732+ status |= 0x01;
733+
734+ return status;
735+}
736+
737+u8 cmd[40];
738+
739+
740+
741+
742+
743+
744+void carrier_sense()
745+{
746+ while(PINC&0x04); //Carrier sense
747+}
748+
749+void carrier_no_sense()
750+{
751+ while(!(PINC&0x04)); //Carrier sense
752+}
753+
754+void cc1101_tx_carrier(cc1101_client * client)
755+{
756+
757+ cc1101_carrier_wave_setup();
758+
759+ cc1100_cfg_txoff_mode(CC1100_TXOFF_MODE_STAY_TX);
760+ cc1100_cfg_manchester_en(CC1100_MANCHESTER_DISABLE);
761+ cc1100_write_reg(CC1100_REG_MDMCFG3,0x33);
762+ cc1100_cfg_mod_format(CC1100_MODULATION_ASK);
763+ cc1100_write_reg(CC1100_REG_FREND0,0x10);
764+ cc1100_cfg_gdo0(CC1100_GDOx_CLK_XOSC_1);
765+
766+ /* IDLE */
767+ cc1100_cmd_idle();
768+ /* MANCAL*/
769+ cc1100_cmd_calibrate();
770+ /* FS WAKEUP */
771+ cc1100_cmd_flush_tx();
772+
773+ cc1100_cfg_gdo0(0x0e);
774+ carrier_sense();
775+
776+ cc1100_cmd_tx();
777+}
778+
779+
780+void master_fifo_preset(void)
781+{
782+
783+}
784+
785+u8 gStatus=0x00;
786+
787+u8 cc1101_tx(u8 * data , u8 length,u8 th)
788+{
789+ //int i;
790+
791+ cc1101_rtx_reg_set(1); // rx
792+ cc1101_carrier_wave_setup();
793+ cc1100_cfg_gdo0(0x0e);
794+
795+ cc1100_cmd_idle();
796+ cc1100_cmd_flush_rx();
797+ cc1100_cmd_calibrate();
798+ cc1100_cmd_rx();
799+
800+ mdelay(5);
801+
802+ if(PINC & 0x04)
803+ {
804+ cc1100_cmd_idle();
805+ mdelay(195);
806+ if(th == 0)
807+ return 0;
808+
809+ }
810+
811+
812+ cc1101_rtx_reg_set(0); // tx
813+ cc1101_carrier_wave_setup();
814+ cc1100_cmd_idle();
815+ cc1100_cmd_calibrate();
816+ tx_fifo_write(data,length);
817+
818+ cc1100_write_reg(CC1100_REG_MCSM1,0x00);
819+ cc1100_cfg_gdo0(0x09);
820+
821+
822+
823+ cc1100_cfg_gdo0(CC1100_GDOx_SYNC_WORD);
824+ cc1100_cmd_tx();
825+ while(!(PINC&0x04)); //data send start
826+ while(PINC&0x04); //data send end
827+
828+ return 1;
829+}
830+
831+
832+
833+u8 cc1101_rx(u8 * data,u8 loop)
834+{
835+ u8 cnt_wait_syn_ack=0;
836+ u8 length;
837+
838+ cc1101_rtx_reg_set(1); // rx
839+ cc1101_carrier_wave_setup();
840+ cc1100_cfg_gdo0(CC1100_GDOx_SYNC_WORD);
841+
842+ cc1100_cmd_idle();
843+ cc1100_cmd_flush_rx();
844+ cc1100_cmd_calibrate();
845+ cc1100_cmd_rx();
846+
847+ while(!(PINC & 0x04))
848+ {
849+ mdelay(1);
850+ if(++cnt_wait_syn_ack > 50)
851+ return 0;
852+ }
853+
854+ while(1)
855+ {
856+ if(!( PINC & 0x04) )
857+ {
858+ if((cc1100_status_crc_lqi() & 0x80))
859+ {
860+
861+ length = rx_fifo_read(data);
862+ return length;
863+ }
864+ break;
865+ }
866+ }
867+
868+ return 0;
869+}
870+
871+
872+
873+
874+u8 my_memcmp(u8 * src,u8 * dest,u8 len)
875+{
876+ u8 i;
877+
878+ for(i= 0 ; i < len ; i++)
879+ {
880+ if(src[i] != dest[i]) return i;
881+ }
882+
883+ return 0;
884+}
885+
886+
887+
888+void rtc_alarm_disenable(void)
889+{
890+ u8 ret;
891+
892+ EIMSK &= ~(1<<INT0);
893+ ret = rtc_1byte_data_write(0x0E,0x00);
894+ if(ret == 0)
895+ ret = rtc_1byte_data_write(0x0E,0x00);
896+ if(ret == 0)
897+ ret = rtc_1byte_data_write(0x0E,0x00);
898+
899+ //rtc_1byte_data_write(0x0E,0x00); //Alarm enable disenable
900+}
901+
902+
903+
904+ISR(USART_RX_vect)
905+{
906+ uart_data=UDR0;
907+
908+ rx_char[uart_rx_index++]=uart_data;
909+
910+ if(uart_data==0x0d)
911+ {
912+ uart_rx_length = uart_rx_index;
913+ gClient.status.status=MS_UART_RECV;
914+ uart_rx_index = 0;
915+ }
916+}
917+
918+
919+void insert_sr_buf()
920+{
921+ if(SRBuf[0] == -1)
922+ {
923+ SRBuf[0] = (get_user0_data >> 2) & 0x01;
924+ }
925+ else
926+ {
927+ if(SRBuf[0] == 1 && !(get_user0_data & 0x40) && SRBuf[1] == -1)
928+ SRBuf[1] = 0;
929+ else if(SRBuf[0] == 0 && (get_user0_data & 0x40) && SRBuf[1] == -1)
930+ SRBuf[1] = 1;
931+ }
932+}
933+
934+ISR(INT1_vect)
935+{
936+
937+ //u8 gmonitor_state;
938+
939+ spi_signalpin_opendrain_nonactive();
940+
941+
942+ if(gClient.status.status == SL_SLEEP)
943+ rtc_alarm_disenable();
944+
945+
946+ gClient.status.input_data = ~get_input_data();
947+
948+ sig_set();
949+
950+
951+ //if(gClient.status.make_alert != 0x00 && gClient.status.status != SL_SEND)
952+ if(gClient.status.make_alert != 0x00)
953+ {
954+ get_user0_data = gClient.status.make_alert;
955+ if(sr_status == 0)
956+ get_user0_data &= ~0x04;
957+ else
958+ get_user0_data |= 0x04;
959+ }
960+
961+ if(gClient.status.status == SL_SLEEP )
962+ {
963+ gClient.status.status = SL_SEND;
964+ gClient.status.send_err_cnt = 0;
965+ }
966+ else if(gClient.status.status == SL_ALARM_WAIT )
967+ {
968+ if(gClient.status.make_alert & 0x06)
969+ {
970+ wakeup_condition = 1;
971+ gClient.status.status = SL_SEND;
972+ gClient.status.send_err_cnt = 0;
973+ }
974+
975+ }
976+
977+
978+ #if 0
979+ my_eeprom_read_block((u8 *)&gmonitor_state,(u8 *)&monitor_state,1);
980+
981+
982+ if(gClient.status.status != gmonitor_state)
983+ {
984+ eeprom_busy_wait();
985+ eeprom_write_block((u8 *)&gClient.status.status,(u8 *)&monitor_state,1);
986+ led_flasher(10,40);
987+ }
988+
989+
990+
991+ if(gClient.status.status == SL_SEND_WAIT || gClient.status.status == SL_ALARM_WAIT)
992+ led_flasher(4,200);
993+
994+ #endif
995+ //if(setup_mode == SETUP_READY /*&& get_user0_data */)
996+
997+
998+}
999+
1000+
1001+ISR(INT0_vect)
1002+{
1003+
1004+ EIMSK &= ~(1<<INT0);
1005+
1006+ spi_signalpin_opendrain_nonactive();
1007+
1008+ wakeup_condition = 1;
1009+
1010+ if(gClient.status.status == SL_SEND_WAIT)
1011+ gClient.status.status = SL_SEND;
1012+
1013+
1014+ //led_flasher(5,50);
1015+}
1016+
1017+
1018+/*
1019+ input_data
1020+ b0 b1 type 00=master,01=slave,10=carrier,11=setup
1021+*/
1022+
1023+void device_status_setup(void)
1024+{
1025+ memcpy((u8 *)&gClient.status.serial,fix_id_mel,3);
1026+ my_eeprom_read_block((u8 *)&gClient.status.serial[3],(u8 *)&gctl_data.serial,3);
1027+ gClient.status.send_err_cnt=0;
1028+
1029+ gClient.status.input_data = ~get_input_data();
1030+
1031+ gClient.status.type = (gClient.status.input_data >> 2) & 0x3;
1032+}
1033+
1034+
1035+u8 get_alarm_time()
1036+{
1037+ return (((~get_input_data()) >> 4) & 0x03);
1038+}
1039+
1040+
1041+
1042+
1043+void rtc_set_next_alarm(u8 alarm)
1044+{
1045+ volatile int i;
1046+ u8 ret;
1047+
1048+ if(alarm > 7)
1049+ {
1050+ led_flasher(20,500);
1051+ }
1052+
1053+ if(alarm < 4)
1054+ {
1055+ reg_net_alarm[3].data = time_set[alarm].hour;
1056+ reg_net_alarm[4].data = time_set[alarm].min;
1057+ reg_net_alarm[5].data = time_set[alarm].sec;
1058+
1059+ for(i = 0 ;i < 7 ; i++)
1060+ {
1061+ ret = rtc_1byte_data_write(reg_net_alarm[i].addr,reg_net_alarm[i].data);
1062+ if(ret == 0)
1063+ ret = rtc_1byte_data_write(reg_net_alarm[i].addr,reg_net_alarm[i].data);
1064+ if(ret == 0)
1065+ ret = rtc_1byte_data_write(reg_net_alarm[i].addr,reg_net_alarm[i].data);
1066+ }
1067+ }
1068+ else
1069+ {
1070+ //reg_next_sch_alarm[3].data = day_cnt[alarm-4];
1071+
1072+ for(i = 0 ;i < 9 ; i++)
1073+ {
1074+ ret = rtc_1byte_data_write(reg_next_sch_alarm[i].addr,reg_next_sch_alarm[i].data);
1075+ if(ret == 0)
1076+ ret = rtc_1byte_data_write(reg_next_sch_alarm[i].addr,reg_next_sch_alarm[i].data);
1077+ if(ret == 0)
1078+ ret = rtc_1byte_data_write(reg_next_sch_alarm[i].addr,reg_next_sch_alarm[i].data);
1079+ }
1080+ }
1081+}
1082+
1083+
1084+void temperature_carrier_test(void)
1085+{
1086+ cc1100_cfg_gdo2(0x30); //26MHz XOSC/1 output
1087+ while(1)
1088+ {
1089+ led_flasher(5,50);
1090+ add_batt_low();
1091+ cc1101_tx_carrier((cc1101_client *)&gClient);
1092+ sdelay(5);
1093+ temperature_test_enable();
1094+ sdelay(1);
1095+ temperature_test_disenable();
1096+ }
1097+}
1098+
1099+
1100+
1101+void random_tx_test(void)
1102+{
1103+ //cc1100_cfg_gdo2(0x30); //26MHz XOSC/1 output
1104+
1105+ //cc1101_rtx_reg_set(0); // tx
1106+ //cc1100_write_reg(CC1100_REG_PKTCTRL0,0x22); //random TX mode
1107+ //cc1101_carrier_wave_setup();
1108+ //cc1100_cmd_idle();
1109+ //cc1100_cmd_calibrate();
1110+ //cc1100_cmd_tx();
1111+
1112+ while(1)
1113+ {
1114+ cc1100_cmd_idle();
1115+ sdelay(3);
1116+
1117+ cc1101_rtx_reg_set(0); // tx
1118+ cc1100_write_reg(CC1100_REG_PKTCTRL0,0x22); //random TX mode
1119+ cc1101_carrier_wave_setup();
1120+ cc1100_cmd_idle();
1121+ cc1100_cmd_calibrate();
1122+ cc1100_cmd_tx();
1123+
1124+ //cc1100_cmd_tx();
1125+ wdt_disable();
1126+ sdelay(3);
1127+ }
1128+}
1129+
1130+
1131+
1132+
1133+u8 gggLength;
1134+void master_oper()
1135+{
1136+ int i;
1137+ int length=0;
1138+ int id=0;
1139+ fifo_t * fifo;
1140+
1141+ fifo = &gClient.fifo;
1142+
1143+ while(1)
1144+ {
1145+ wdt_reset();
1146+
1147+ length = cc1101_rx((u8 *)fifo,1);
1148+ if(length > 0 )
1149+ {
1150+ fifo->master_ctl = my_eeprom_read_byte(&greg_slave[id].slave_ctl_set);
1151+ memcpy(fifo->master_id,&gClient.status.serial[3],3);
1152+
1153+ if(setup_mode == SETUP_NONE)
1154+ {
1155+ id = reg_slave_num_serch(fifo->slave_id);
1156+ if( id >= 0 )
1157+ {
1158+ cc1101_tx((u8 *)fifo, sizeof(fifo_t) - sizeof(f_option_t),0);
1159+
1160+ if(length < sizeof(fifo_t))
1161+ {
1162+ i=0;
1163+ cmd[i++] = 'w';
1164+ cmd[i++] = 'r';
1165+ cmd[i++] = ' ';
1166+ cmd[i++] = 'e';
1167+ cmd[i++] = 'm';
1168+ cmd[i++] = 'g';
1169+ cmd[i++] = ' ';
1170+ hexToAsc(fifo->slave_id[3],(u8 *)&cmd[i]);
1171+ i+=2;
1172+ hexToAsc(fifo->slave_id[4],(u8 *)&cmd[i]);
1173+ i+=2;
1174+ hexToAsc(fifo->slave_id[5],&cmd[i]);
1175+ i+=2;
1176+ cmd[i++] = ' ';
1177+ hexToAsc(fifo->user_data0,&cmd[i]);
1178+ i+=2;
1179+ cmd[i++] = ' ';
1180+ hexToAsc(fifo->user_data1,&cmd[i]);
1181+ i+=2;
1182+ cmd[i++] = ' ';
1183+ hexToAsc(fifo->bat_val,&cmd[i]);
1184+ i+=2;
1185+ cmd[i++] = ' ';
1186+ hexToAsc(gRecvRssi,&cmd[i]);
1187+ i+=2;
1188+ cmd[i++] = ' ';
1189+ hexToAsc(fifo->rssi,&cmd[i]);
1190+ i+=2;
1191+ cmd[i++] = 0x0d;
1192+ cmd[i]=0;
1193+ putstr(cmd);
1194+ }
1195+ return;
1196+ }
1197+ //sdelay(2); //ACK limit delay
1198+ }
1199+ else
1200+ {
1201+ u8 * pD;
1202+
1203+ if(setup_mode == SETUP_WRITE)
1204+ {
1205+ fifo->setup_mode = SETUP_WRITE;
1206+
1207+ memcpy((u8 *)&fifo->opt,(u8 *)&gOpt,sizeof(f_option_t));
1208+ if(cc1101_tx((u8 *)fifo,sizeof(fifo_t),0) == true)
1209+ {
1210+ setup_mode = SETUP_READY;
1211+ putstr((u8 *)"wr ok\r");
1212+ }
1213+ }
1214+ else
1215+ {
1216+ putc_('w');
1217+ putc_('r');
1218+ putc_(' ');
1219+ putc_('d');
1220+ putc_('u');
1221+ putc_('m');
1222+ putc_('p');
1223+ putc_(' ');
1224+
1225+ pD = (u8 *) fifo;
1226+ for(i =0 ;i < length ; i++)
1227+ {
1228+ hexToAsc(pD[i],(u8 *)&cmd[0]);
1229+ putc_(cmd[0]);
1230+ putc_(cmd[1]);
1231+ }
1232+ hexToAsc(gRecvRssi,(u8 *)&cmd[0]);
1233+ putc_(cmd[0]);
1234+ putc_(cmd[1]);
1235+ hexToAsc(gRecvLqi,(u8 *)&cmd[0]);
1236+ putc_(cmd[0]);
1237+ putc_(cmd[1]);
1238+ putc_(0x0d);
1239+ }
1240+ }
1241+ }
1242+
1243+ if(gClient.status.status==MS_UART_RECV)
1244+ return;
1245+ }
1246+}
1247+
1248+
1249+
1250+void master_main()
1251+{
1252+ u8 ret=0;
1253+ int i;
1254+
1255+ while(1)
1256+ {
1257+ master_oper((cc1101_client *)&gClient);
1258+
1259+ if(gClient.status.status==MS_UART_RECV)
1260+ {
1261+ ret = 0;
1262+ memset(gWCmd,0,sizeof(gWCmd));
1263+
1264+ pC = strtok(rx_char," ");
1265+
1266+ i=0;
1267+ while(pC != NULL)
1268+ {
1269+ strcpy(&gWCmd[i][0],pC);
1270+ pC = strtok(NULL," ");
1271+ i++;
1272+ }
1273+
1274+ if(i != 0)
1275+ {
1276+ if(strstr(&gWCmd[0][0],"wr") != NULL)
1277+ {
1278+ if(strstr(&gWCmd[1][0],"env") != NULL)
1279+ {
1280+ int id=0;
1281+
1282+ id = AscToInt(&gWCmd[2][0]);
1283+ if(id >= 0 && id < 100)
1284+ {
1285+ tSlave.serial[0] = AscToHex(&gWCmd[3][0]);
1286+ tSlave.serial[1] = AscToHex(&gWCmd[3][2]);
1287+ tSlave.serial[2] = AscToHex(&gWCmd[3][4]);
1288+ tSlave.slave_ctl_set = AscToHex(&gWCmd[4][0]);
1289+
1290+
1291+ my_eeprom_read_block((u8 *)&tSlave2,(u8 *)&greg_slave[id],sizeof(reg_slave));
1292+
1293+ if(memcmp((u8 *)&tSlave,&tSlave2,sizeof(reg_slave)) != 0)
1294+ {
1295+ eeprom_busy_wait(); //EEPROM使用可能まで待機
1296+ eeprom_write_block(&tSlave, &greg_slave[id], sizeof(reg_slave)); //write 8byte
1297+ }
1298+
1299+ ret = 1;
1300+ putstr((u8 * )"ok\r");
1301+ }
1302+ }
1303+ }
1304+ else if(strstr(&gWCmd[0][0],"rd") != NULL)
1305+ {
1306+ if(strstr(&gWCmd[1][0],"env") != NULL)
1307+ {
1308+ int id=0;
1309+
1310+ id = AscToInt(&gWCmd[2][0]);
1311+ if(id >= 0 && id < 100)
1312+ {
1313+ my_eeprom_read_block((u8 *)&tSlave2,(u8 *)&greg_slave[id],sizeof(reg_slave));
1314+
1315+ i=0;
1316+ cmd[i++] = 'r';
1317+ cmd[i++] = 'd';
1318+ cmd[i++] = ' ';
1319+ cmd[i++] = 'e';
1320+ cmd[i++] = 'n';
1321+ cmd[i++] = 'v';
1322+ cmd[i++] = ' ';
1323+ hexToAsc(tSlave2.serial[0],(u8 *)&cmd[i]);
1324+ i+=2;
1325+ hexToAsc(tSlave2.serial[1],(u8 *)&cmd[i]);
1326+ i+=2;
1327+ hexToAsc(tSlave2.serial[2],&cmd[i]);
1328+ i+=2;
1329+ cmd[i++] = ' ';
1330+ hexToAsc(tSlave2.slave_ctl_set,&cmd[i]);
1331+ i+=2;
1332+ cmd[i++] = 0x0d;
1333+ cmd[i]=0;
1334+ putstr(cmd);
1335+ }
1336+ }
1337+ }
1338+ else if(strstr(&gWCmd[0][0],"setenv") != NULL)
1339+ {
1340+ if(strstr(&gWCmd[1][0],"enable") != NULL)
1341+ {
1342+ wdt_disable();
1343+ setup_mode = SETUP_READY;
1344+ putstr((u8 * )"ok\r");
1345+ }
1346+ else if(strstr(&gWCmd[1][0],"write") != NULL)
1347+ {
1348+ gOpt.env_data[0] = AscToHex(&gWCmd[2][0]); // serial 0
1349+ gOpt.env_data[1] = AscToHex(&gWCmd[2][2]); // serial 1
1350+ gOpt.env_data[2] = AscToHex(&gWCmd[2][4]); // serial 2
1351+ gOpt.env_data[3] = AscToHex(&gWCmd[3][0]); // ctl
1352+
1353+ gOpt.env_data[4] = AscToHex(&gWCmd[4][0]); //
1354+ gOpt.env_data[5] = AscToHex(&gWCmd[4][2]);
1355+ gOpt.env_data[6] = AscToHex(&gWCmd[4][4]);
1356+ gOpt.env_data[7] = AscToHex(&gWCmd[4][6]);
1357+
1358+ gOpt.level[0] = AscToHex(&gWCmd[5][0]);
1359+ gOpt.level[1] = AscToHex(&gWCmd[5][2]);
1360+ gOpt.level[2] = AscToHex(&gWCmd[5][4]);
1361+ gOpt.level[3] = AscToHex(&gWCmd[5][6]);
1362+ gOpt.level[4] = AscToHex(&gWCmd[5][8]);
1363+ gOpt.level[5] = AscToHex(&gWCmd[5][10]);
1364+ gOpt.level[6] = AscToHex(&gWCmd[5][12]);
1365+
1366+ setup_mode = SETUP_WRITE;
1367+ putstr((u8 * )"ok\r");
1368+ }
1369+ else if(strstr(&gWCmd[1][0],"save") != NULL)
1370+ {
1371+ tCtl.serial[0] = AscToHex(&gWCmd[2][0]);
1372+ tCtl.serial[1] = AscToHex(&gWCmd[2][2]);
1373+ tCtl.serial[2] = AscToHex(&gWCmd[2][4]);
1374+
1375+ tCtl.adj_freq = AscToHex(&gWCmd[4][0]);
1376+ tCtl.freq_add_sub = AscToHex(&gWCmd[4][2]);
1377+ tCtl.adj_temper = AscToHex(&gWCmd[4][4]);
1378+ tCtl.temper_add_sub = AscToHex(&gWCmd[4][6]);
1379+ eeprom_busy_wait(); //EEPROM使用可能まで待・
1380+ eeprom_write_block(&tCtl, &gctl_data, sizeof(ctl_data)); //write 8byte
1381+ putstr((u8 * )"ok\r");
1382+ }
1383+ else
1384+ {
1385+ setup_mode = SETUP_NONE;
1386+ }
1387+ }
1388+ else
1389+ {
1390+
1391+ }
1392+ }
1393+
1394+ memset(rx_char,0,60);
1395+ gClient.status.status = MS_BOOT;
1396+ }
1397+ }
1398+}
1399+
1400+
1401+
1402+u8 slave_oper()
1403+{
1404+ u8 ret;
1405+ u8 cnt;
1406+ u8 i=0;
1407+ fifo_t * fifo;
1408+ int length;
1409+
1410+
1411+ fifo = &gClient.fifo;
1412+
1413+ led_onoff(1);
1414+ cnt = 0;
1415+ for(i = 0 ; i < 7 ;i++)
1416+ {
1417+ slave_fifo_preset(fifo);
1418+ ret = cc1101_tx((u8 *)fifo,fifo->length,cnt > 5 ? 1 : 0);
1419+
1420+
1421+ if(ret == 0)
1422+ cnt++;
1423+
1424+ if(ret == 1)
1425+ {
1426+ wdt_reset();
1427+ length = cc1101_rx((u8 *)fifo,0);
1428+ if(length > 0)
1429+ {
1430+ if(my_memcmp(gClient.status.serial,fifo->slave_id,6) == 0)
1431+ {
1432+ gslave_master_ctl = fifo->master_ctl;
1433+ fifo->length=0;
1434+ led_onoff(0);
1435+ return 1;
1436+ }
1437+ }
1438+ }
1439+ }
1440+ led_onoff(0);
1441+ return 0;
1442+}
1443+
1444+
1445+void sleep_set(u8 alarm,u8 bo)
1446+{
1447+ WDTCSR &= ~(1 << WDIE);
1448+ wdt_disable();
1449+ if(bo == 0)
1450+ rtc_set_next_alarm(alarm);
1451+
1452+ cc1100_cmd_idle();
1453+ cc1100_cmd_pwd();
1454+
1455+ spi_signalpin_opendrain_active();
1456+ EIMSK |= (1<<INT0);
1457+ sleep_mode();
1458+ wdt_enable(WDTO_4S);
1459+ WDTCSR |= (1 << WDIE);
1460+}
1461+
1462+void slave_main()
1463+{
1464+ u8 throw=0;
1465+ u8 ret=0;
1466+ u8 alarm=0;
1467+ //int gwdt_cnt=0;
1468+ int i=0;
1469+ int gcnt_loop_break=0;
1470+
1471+ memset(SRBuf,0,3);
1472+ SRBufIndex = 0;
1473+ while(1)
1474+ {
1475+ throw = 0;
1476+ i=0;
1477+ wdt_reset();
1478+ spi_signalpin_opendrain_nonactive();
1479+ switch(gClient.status.status)
1480+ {
1481+ case SL_BOOT:
1482+ // config read
1483+ alarm = (gslave_master_ctl & 0x03) + 4;//ALARM_30MIN;
1484+ gClient.status.status = SL_SLEEP;
1485+ break;
1486+ case SL_SLEEP:
1487+ gClient.status.status = SL_SCH_SEND;
1488+ gClient.status.send_err_cnt = 0;
1489+ break;
1490+ case SL_SCH_SEND:
1491+ gClient.status.user_data0 = ((sig_status() & 0x1A) | 0x10);
1492+ ret = slave_oper((cc1101_client *)&gClient);
1493+ if(ret == 1)
1494+ {
1495+ throw = 1;
1496+ gClient.status.status = SL_BOOT;
1497+ #ifdef S3_DELAY
1498+ sdelay(3);
1499+ #endif
1500+ }
1501+ else
1502+ {
1503+ alarm = ALARM_2SEC;
1504+ gClient.status.send_err_cnt++;
1505+ if(gClient.status.send_err_cnt > 8)
1506+ {
1507+ throw = 1;
1508+ gClient.status.status = SL_BOOT;
1509+ #ifdef S3_DELAY
1510+ sdelay(3);
1511+ #endif
1512+ }
1513+ }
1514+ break;
1515+ case SL_SEND:
1516+ if(gClient.status.send_err_cnt == 0)
1517+ {
1518+ gClient.status.user_data0 = ((get_user0_data & 0x2F) | 0x20); //EMG_SIG_SET
1519+ }
1520+
1521+
1522+ ret = slave_oper((cc1101_client *)&gClient);
1523+ if(ret == 1)
1524+ {
1525+ #ifdef S3_DELAY
1526+ sdelay(3);
1527+ #endif
1528+ // config read
1529+ if((gClient.status.user_data0 & 0x04) != (get_user0_data & 0x04))
1530+ {
1531+ throw = 1;
1532+ gClient.status.send_err_cnt = 0;
1533+ }
1534+ else
1535+ {
1536+ wakeup_condition = 0;
1537+ alarm = get_alarm_time();
1538+ gClient.status.status = SL_ALARM_WAIT;
1539+ }
1540+ }
1541+ else
1542+ {
1543+ alarm = ALARM_2SEC;
1544+ gClient.status.send_err_cnt++;
1545+ gClient.status.status = SL_SEND_WAIT;
1546+ if(gClient.status.send_err_cnt > 6)
1547+ {
1548+ gClient.status.send_err_cnt = 0;
1549+ throw = 0;
1550+ #ifdef S3_DELAY
1551+ sdelay(3);
1552+ #endif
1553+ alarm = ALARM_1MIN;
1554+ wakeup_condition = 0;
1555+ gClient.status.status = SL_ALARM_WAIT;
1556+ }
1557+ }
1558+ break;
1559+ case SL_ALARM_WAIT:
1560+ throw = 1;
1561+ gClient.status.status = SL_BOOT;
1562+ break;
1563+ case SL_SEND_WAIT:
1564+ //led_flasher(4,200);
1565+ throw = 1;
1566+ break;
1567+ default:
1568+ break;
1569+
1570+
1571+ }
1572+
1573+ if(throw == 0)
1574+ {
1575+ if(gClient.status.status != SL_SCH_SEND)
1576+ sleep_set(alarm,0);
1577+
1578+ }
1579+
1580+ if(gClient.status.status == SL_SEND_WAIT)
1581+ sleep_set(alarm,1);
1582+
1583+ while(wakeup_condition == 0 && gClient.status.status == SL_ALARM_WAIT)
1584+ {
1585+ sleep_set(alarm,1);
1586+
1587+
1588+ #if 1
1589+ i++;
1590+ if(i>100)
1591+ {
1592+ wakeup_condition = 1;
1593+
1594+ led_flasher(10,40);
1595+ }
1596+ #endif
1597+ }
1598+ }
1599+}
1600+
1601+
1602+
1603+u8 setup_oper()
1604+{
1605+ u8 ret;
1606+ int length;
1607+ fifo_t * fifo;
1608+
1609+
1610+ fifo = &gClient.fifo;
1611+
1612+
1613+
1614+ temperature_get();
1615+
1616+ slave_fifo_preset(fifo);
1617+ ret = cc1101_tx((u8 *)fifo,sizeof(fifo_t),0);
1618+
1619+ if(ret == 1)
1620+ {
1621+ length = cc1101_rx((u8 *)fifo,0);
1622+ if(length > 0)
1623+ {
1624+ gggLength = length;
1625+ if(length == sizeof(fifo_t) && fifo->setup_mode == SETUP_WRITE)
1626+ {
1627+ memcpy((u8 *)tCtl.serial,(u8 *)&fifo->opt.env_data[0],3);
1628+ tCtl.adj_freq = fifo->opt.env_data[4];
1629+ tCtl.freq_add_sub = fifo->opt.env_data[5];
1630+ tCtl.adj_temper = fifo->opt.env_data[6];
1631+ tCtl.temper_add_sub = fifo->opt.env_data[7];
1632+
1633+ memcpy((u8 *)&gClient.status.serial[3],(u8 *)tCtl.serial,3);
1634+ memcpy((u8 *)&fifo->slave_id[3],(u8 *)tCtl.serial,3);
1635+
1636+ eeprom_busy_wait();
1637+ eeprom_write_block(&tCtl, &gctl_data, sizeof(ctl_data));
1638+
1639+ hex_change_level(fifo->opt.level);
1640+
1641+ gTestMode = 0xab;
1642+ eeprom_busy_wait(); //EEPROM使用可能まで待・
1643+ eeprom_write_block(&gTestMode, &test_mode, 1); //write 8byte
1644+ gTestMode = 0;
1645+
1646+ cc1101_tx_carrier((cc1101_client *)&gClient);
1647+ sdelay(5);
1648+
1649+ return 1;
1650+ }
1651+ fifo->length=0;
1652+ }
1653+ }
1654+ return 0;
1655+}
1656+
1657+extern u8 pt_data[];
1658+void setup_main()
1659+{
1660+ while(1)
1661+ {
1662+ if(setup_mode == SETUP_READY)
1663+ {
1664+ led_flasher(1,1000);
1665+ }
1666+ else
1667+ {
1668+ led_flasher(5,100);
1669+ pt_data[0] = 0xc0; //10dBm
1670+ //pt_data[0] = 0xc8; //7dBm
1671+ //pt_data[0] = 0x84; //5dBm
1672+ //pt_data[0] = 0x60; //0dBm
1673+ cc1101_8PATABLE_write_reg();
1674+ setup_oper();
1675+
1676+ #if 0
1677+ pt_data[0] = 0x60;
1678+ cc1101_8PATABLE_write_reg();
1679+ add_batt_low();
1680+ cc1101_tx_carrier((cc1101_client *)&gClient);
1681+ sdelay(2);
1682+ #endif
1683+ }
1684+ }
1685+}
1686+
1687+
1688+void check_env(void)
1689+{
1690+ u8 i;
1691+ u8 * pD;
1692+ u8 fixid[3];
1693+ u8 test;
1694+
1695+
1696+ my_eeprom_read_block((u8 *)&tCtl,(u8 *)&gctl_data,sizeof(ctl_data));
1697+
1698+ pD = (u8 *)&tCtl;
1699+
1700+ for(i = 0 ;i < 5 ; i++)
1701+ {
1702+ if(pD[i] != 0xff && pD[i] != 0x00) break;
1703+ }
1704+
1705+ if(i == 5)
1706+ {
1707+ // init;
1708+ tCtl.adj_freq = 0x24;
1709+ tCtl.freq_add_sub = 0x80;
1710+ tCtl.adj_temper = 0x18;
1711+ tCtl.temper_add_sub = 0x80;
1712+ eeprom_busy_wait();
1713+ eeprom_write_block(&tCtl,&gctl_data,sizeof(ctl_data));
1714+ }
1715+
1716+ my_eeprom_read_block((u8 *)level_offset,(u8 *)&eprom_level,sizeof(level_offset));
1717+
1718+
1719+ pD = (u8 *)&level_offset;
1720+
1721+ for(i = 0 ;i < sizeof(level_offset) ; i++)
1722+ {
1723+ if(pD[i] != 0xff && pD[i] != 0x00) break;
1724+ }
1725+
1726+
1727+ if(i == 5)
1728+ {
1729+ eeprom_busy_wait();
1730+ eeprom_write_block(default_offset,&eprom_level,sizeof(level_offset));
1731+ memcpy(level_offset,default_offset,sizeof(level_offset));
1732+
1733+ }
1734+
1735+ my_eeprom_read_block((u8 *)fixid,(u8 *)&eprom_fixid,sizeof(eprom_fixid));
1736+
1737+ if(fixid[0] == 0x00 || fixid[0] == 0xff )
1738+ {
1739+
1740+ }
1741+ else
1742+ {
1743+ fix_id_mel[0] = fixid[0];
1744+ fix_id_mel[1] = fixid[1];
1745+ fix_id_mel[2] = fixid[2];
1746+ }
1747+
1748+ my_eeprom_read_block((u8 *)&test,(u8 *)&test_mode,1);
1749+
1750+ if(test == 0xab)
1751+ {
1752+ gTestMode = 0;
1753+ }
1754+ else
1755+ {
1756+ gTestMode = 1;
1757+ }
1758+}
1759+
1760+
1761+
1762+void test_wave_mode(void)
1763+{
1764+ while(1)
1765+ {
1766+ device_status_setup();
1767+
1768+ if(gClient.status.type == MASTER)
1769+ {
1770+ led_flasher(50,30);
1771+ while(1)
1772+ {
1773+ device_status_setup();
1774+ if(gClient.status.type == SETUP)
1775+ {
1776+ led_flasher(50,10);
1777+ random_tx_test();
1778+ }
1779+ sdelay(2);
1780+ }
1781+ }
1782+ sdelay(2);
1783+ }
1784+}
1785+
1786+
1787+
1788+
1789+
1790+int main()
1791+{
1792+
1793+
1794+
1795+ hw_setup();
1796+ inituart();
1797+ i2c_init();
1798+ check_env();
1799+
1800+ device_status_setup();
1801+
1802+ cc1100_init();
1803+
1804+ cc1101_init_reg();
1805+ pt_data[0] = 0xC0; //10dB
1806+ //pt_data[0] = 0xc8; //7dBm
1807+ //pt_data[0] = 0x84; //5dBm
1808+ //pt_data[0] = 0x60; //0dB
1809+ cc1101_8PATABLE_write_reg();
1810+
1811+
1812+
1813+
1814+ set_sleep_mode(SLEEP_MODE_PWR_DOWN);
1815+
1816+ led_flasher(2,100);
1817+
1818+ if(gClient.status.type == SLAVE )
1819+ {
1820+ EIMSK |= (1<<INT1);
1821+ sr_status = get_sr_status();
1822+ sr_status_old = sr_status;
1823+ }
1824+
1825+ if(gClient.status.type == SLAVE || gClient.status.type == MASTER)
1826+ {
1827+ wdt_enable(WDTO_4S);
1828+ WDTCSR |= (1 << WDIE);
1829+ }
1830+
1831+ sei();
1832+ spi_signalpin_opendrain_nonactive();
1833+
1834+ if(gClient.status.type == SLAVE)
1835+ rtc_alarm_disenable();
1836+
1837+
1838+ /* Enter the infinite loop */
1839+ while (1)
1840+ {
1841+ if(gClient.status.type == MASTER)
1842+ {
1843+ gClient.status.status = MS_BOOT;
1844+ master_main();
1845+ }
1846+ else if(gClient.status.type == TEST_MDOE)
1847+ {
1848+ //temperature_carrier_test();
1849+
1850+ test_wave_mode();
1851+
1852+ }
1853+ else if(gClient.status.type == SETUP)
1854+ {
1855+ setup_mode = SETUP_TRX;
1856+ setup_main();
1857+ }
1858+ else
1859+ {
1860+ //gClient.status.status = SL_BOOT;
1861+ slave_main();
1862+ }
1863+ }
1864+}
1865+
1866+
1867+
1868+
1869+
--- trunk/CC1101_AT/CC1101_source_ATmega88/cc1100.c (nonexistent)
+++ trunk/CC1101_AT/CC1101_source_ATmega88/cc1100.c (revision 2602)
@@ -0,0 +1,360 @@
1+/*
2+ * Copyright 2008-2009 INRIA/SensTools
3+ *
4+ * <dev-team@sentools.info>
5+ *
6+ * This software is a set of libraries designed to develop applications
7+ * for the WSN430 embedded hardware platform.
8+ *
9+ * This software is governed by the CeCILL license under French law and
10+ * abiding by the rules of distribution of free software. You can use,
11+ * modify and/ or redistribute the software under the terms of the CeCILL
12+ * license as circulated by CEA, CNRS and INRIA at the following URL
13+ * "http://www.cecill.info".
14+ *
15+ * As a counterpart to the access to the source code and rights to copy,
16+ * modify and redistribute granted by the license, users are provided only
17+ * with a limited warranty and the software&apos;s author, the holder of the
18+ * economic rights, and the successive licensors have only limited
19+ * liability.
20+ *
21+ * In this respect, the user&apos;s attention is drawn to the risks associated
22+ * with loading, using, modifying and/or developing or reproducing the
23+ * software by the user in light of its specific status of free software,
24+ * that may mean that it is complicated to manipulate, and f that also
25+ * therefore means that it is reserved for developers and experienced
26+ * professionals having in-depth computer knowledge. Users are therefore
27+ * encouraged to load and test the software&apos;s suitability as regards their
28+ * requirements in conditions enabling the security of their systems and/or
29+ * data to be ensured and, more generally, to use and operate it in the
30+ * same conditions as regards security.
31+ *
32+ * The fact that you are presently reading this means that you have had
33+ * knowledge of the CeCILL license and that you accept its terms.
34+ */
35+
36+#include <avr/io.h>
37+#include <avr/signal.h>
38+#include <avr/interrupt.h>
39+//#include <avr/iomx8p.h>
40+//#include <avr/stdint.h>
41+
42+
43+#include "spi1.h"
44+
45+#include "cc1100.h"
46+#include "cc1100_gdo.h"
47+#include "cc1100_globals.h"
48+#include "macro.h"
49+
50+static u16 (*gdo0_cb)(void);
51+static u16 (*gdo2_cb)(void);
52+
53+
54+
55+void u100delay(u8 usec);
56+void mdelay(u16 msec);
57+
58+
59+
60+void cc1100_reinit(void)
61+{
62+ spi1_init();
63+}
64+
65+void cc1100_init(void)
66+{
67+
68+ //volatile unsigned char test_val1 = 0;
69+ //volatile unsigned char test_val2 = 0;
70+ //volatile unsigned char test_val3 = 0;
71+ //u8 pt_data[] = {0xC0,0x50,0xc2,0xc3,0xc4,0xc5,0xc6,0xc7};
72+
73+ gdo0_cb = 0x0;
74+ gdo2_cb = 0x0;
75+
76+ spi1_init();
77+ GDO_INIT();
78+
79+ spi1_select(SPI1_CC1100);
80+ spi1_deselect(SPI1_CC1100);
81+ spi1_select(SPI1_CC1100);
82+ spi1_deselect(SPI1_CC1100);
83+ //udelay(80);
84+ //u100delay(1);
85+ mdelay(1);
86+ spi1_select(SPI1_CC1100);
87+ while (spi1_read_somi()) ;
88+ spi1_write_single(CC1100_STROBE_SRES | CC1100_ACCESS_STROBE);
89+ while (spi1_read_somi()) ;
90+ spi1_deselect(SPI1_CC1100);
91+
92+ mdelay(1);
93+
94+
95+ //setup 426.361755MHz
96+ cc1100_write_reg(CC1100_REG_FREQ2, 0x10);
97+ //cc1100_write_reg(CC1100_REG_FREQ2, 0x10);
98+ cc1100_write_reg(CC1100_REG_FREQ1, 0x66);
99+ cc1100_write_reg(CC1100_REG_FREQ0, 0x07);
100+
101+
102+}
103+
104+u8 cc1100_read_reg(u8 addr)
105+{
106+ u8 reg;
107+ spi1_select(SPI1_CC1100);
108+ spi1_write_single(addr | CC1100_ACCESS_READ);
109+ reg = spi1_read_single();
110+ spi1_deselect(SPI1_CC1100);
111+ return reg;
112+}
113+
114+void cc1100_write_reg(u8 addr, u8 value)
115+{
116+ spi1_select(SPI1_CC1100);
117+ spi1_write_single(addr | CC1100_ACCESS_WRITE);
118+ spi1_write_single(value);
119+ spi1_deselect(SPI1_CC1100);
120+}
121+
122+u8 cc1100_strobe_cmd(u8 cmd)
123+{
124+ u8 ret;
125+ spi1_select(SPI1_CC1100);
126+ while(spi1_read_somi());
127+ //mdelay(3);
128+ ret = spi1_write_single(cmd | CC1100_ACCESS_STROBE);
129+ spi1_deselect(SPI1_CC1100);
130+ return ret;
131+}
132+
133+/*add 20100113 blackz*/
134+u8 cc1100_sleep_strobe_cmd(u8 cmd)
135+{
136+ u8 ret;
137+ //spi1_select(SPI1_CC1100);
138+ //while(spi1_read_somi());
139+ //mdelay(3);
140+ ret = spi1_write_single(cmd | CC1100_ACCESS_STROBE);
141+ //spi1_deselect(SPI1_CC1100);
142+ return ret;
143+}
144+
145+void cc1100_fifo_put(u8* buffer, u16 length)
146+{
147+ spi1_select(SPI1_CC1100);
148+ spi1_write_single(CC1100_DATA_FIFO_ADDR | CC1100_ACCESS_WRITE_BURST);
149+ spi1_write(buffer, length);
150+ spi1_deselect(SPI1_CC1100);
151+}
152+
153+//void cc1100_fifo_get(u8* buffer, u16 length)
154+void cc1100_fifo_get(u8* buffer, u16 length)
155+{
156+ spi1_select(SPI1_CC1100);
157+ spi1_write_single(CC1100_DATA_FIFO_ADDR | CC1100_ACCESS_READ_BURST);
158+ spi1_read(buffer, length);
159+ spi1_deselect(SPI1_CC1100);
160+}
161+
162+//u8 cc1100_read_status(u8 addr)
163+u8 cc1100_read_status(u8 addr)
164+{
165+ u8 temp;
166+
167+ temp = cc1100_read_reg(addr | CC1100_ACCESS_STATUS);
168+
169+
170+ return temp;
171+}
172+
173+
174+void cc1100_gdo0_register_callback(u16 (*cb)(void))
175+{
176+ gdo0_cb = cb;
177+}
178+
179+void cc1100_gdo2_register_callback(u16 (*cb)(void))
180+{
181+ gdo2_cb = cb;
182+}
183+
184+#define STATE_IDLE 0
185+#define STATE_RX 1
186+#define STATE_TX 2
187+#define STATE_FSTXON 3
188+#define STATE_CALIB 4
189+#define STATE_SETTL 5
190+#define STATE_RXOVER 6
191+#define STATE_TXUNDER 7
192+
193+#define WAIT_STATUS(status) \
194+ while ( ((cc1100_cmd_nop()>>4) & 0x7) != status) ;
195+
196+void cc1100_cmd_calibrate(void)
197+{
198+ u8 status;
199+ cc1100_cmd_idle();
200+ cc1100_strobe_cmd(CC1100_STROBE_SCAL);
201+
202+ do
203+ {
204+ status = ((cc1100_cmd_nop()>>4) & 0x7);
205+ }
206+ while(status != STATE_IDLE );
207+ //WAIT_STATUS(STATE_IDLE);
208+}
209+
210+void cc1100_cmd_idle(void)
211+{
212+ switch ((cc1100_cmd_nop() >> 4) & 0x7)
213+ {
214+ case STATE_RXOVER:
215+ cc1100_cmd_flush_rx();
216+ break;
217+ case STATE_TXUNDER:
218+ cc1100_cmd_flush_tx();
219+ break;
220+ default:
221+ cc1100_strobe_cmd(CC1100_STROBE_SIDLE);
222+ }
223+ WAIT_STATUS(STATE_IDLE);
224+}
225+
226+
227+
228+
229+
230+
231+u8 pt_data[] = {0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00}; //10dB
232+
233+
234+reg_t init_all[10]={
235+ {CC1100_REG_PKTCTRL1,0x04},
236+ {CC1100_REG_PKTCTRL0,0x45},
237+ {CC1100_REG_FSCTRL1,0x0C},
238+ {CC1100_REG_MCSM0,0x04},
239+ #ifdef GFSK_DEF
240+ {CC1100_REG_MDMCFG2,0x17}, //GFSK
241+ #else
242+ {CC1100_REG_MDMCFG2,0x07}, //2-FSK]
243+ #endif
244+ {CC1100_REG_PKTCTRL0,0x05},
245+ {CC1100_REG_MDMCFG3,0x83},
246+ {CC1100_REG_MDMCFG4,0x88},
247+
248+ //{CC1100_REG_DEVIATN,0x12}, //4kHz
249+
250+
251+ #ifdef GFSK_DEF
252+ //{CC1100_REG_DEVIATN,0x17}, //6kHz
253+ //{CC1100_REG_DEVIATN,0x15}, //5.1kHz
254+ //{CC1100_REG_DEVIATN,0x14}, //4.7kHz
255+ {CC1100_REG_DEVIATN,0x13}, //4.36kHz
256+ //{CC1100_REG_DEVIATN,0x27}, //12kHz
257+ //{CC1100_REG_DEVIATN,0x07}, //3kHz
258+ //{CC1100_REG_DEVIATN,0x12}, //4kHz
259+ //{CC1100_REG_DEVIATN,0x22}, //8kHz
260+ //{CC1100_REG_DEVIATN,0x11}, //3.5kHz
261+ //{CC1100_REG_DEVIATN,0x10}, //3.2kHz
262+ //{CC1100_REG_DEVIATN,0x0F}, //3.0kHz
263+ //{CC1100_REG_DEVIATN,0x0E}, //2.8kHz
264+ #else
265+ //{CC1100_REG_DEVIATN,0x17}, //6kHz
266+ //{CC1100_REG_DEVIATN,0x15}, //5.1kHz
267+ //{CC1100_REG_DEVIATN,0x14}, //4.7kHz
268+ {CC1100_REG_DEVIATN,0x13}, //4.36kHz
269+ //{CC1100_REG_DEVIATN,0x07}, //3kHz
270+ //{CC1100_REG_DEVIATN,0x12}, //4kHz
271+ //{CC1100_REG_DEVIATN,0x22}, //8kHz
272+ //{CC1100_REG_DEVIATN,0x11}, //3.5kHz
273+ //{CC1100_REG_DEVIATN,0x10}, //3.2kHz
274+ //{CC1100_REG_DEVIATN,0x0F}, //3.0kHz
275+ //{CC1100_REG_DEVIATN,0x0E}, //2.8kHz
276+ #endif
277+
278+
279+ {CC1100_REG_MDMCFG4,0xF8},
280+ {CC1100_REG_AGCCTRL1,0x50},
281+ };
282+#if 0
283+reg_t init_all[10]={
284+ {CC1100_REG_PKTCTRL1,0x04},
285+ {CC1100_REG_PKTCTRL0,0x45},
286+ {CC1100_REG_FSCTRL1,0x0C},
287+ {CC1100_REG_MCSM0,0x04},
288+ {CC1100_REG_MDMCFG2,0x07},
289+ {CC1100_REG_PKTCTRL0,0x05},
290+ {CC1100_REG_MDMCFG3,0x83},
291+ {CC1100_REG_MDMCFG4,0x88},
292+
293+ //{CC1100_REG_DEVIATN,0x12}, //4kHz
294+ {CC1100_REG_DEVIATN,0x17},
295+ {CC1100_REG_MDMCFG4,0xF8},
296+ {CC1100_REG_AGCCTRL1,0x50},
297+ };
298+#endif
299+
300+
301+
302+
303+void cc1101_init_reg(void)
304+{
305+ int i;
306+
307+ for(i = 0 ;i < 10 ; i++)
308+ {
309+ cc1100_write_reg(init_all[i].addr,init_all[i].data);
310+ }
311+}
312+
313+
314+void cc1101_rtx_reg_set(u8 rtx)
315+{
316+ cc1101_init_reg();
317+ cc1100_write_reg(CC1100_REG_PKTCTRL1,rtx == 1 ? 0x0c : 0x04);
318+}
319+
320+
321+
322+
323+
324+#if 0
325+void cc1101_8PATABLE_read_reg(void)
326+{
327+ u8 i;
328+ u8 reg[10];
329+
330+ spi1_select(SPI1_CC1100);
331+ spi1_write_single(0x3e | CC1100_ACCESS_READ_BURST);
332+ for(i=0;i<8;i++)
333+ {
334+ reg[i] = spi1_read_single();
335+ }
336+ spi1_deselect(SPI1_CC1100);
337+
338+}
339+#endif
340+
341+
342+
343+void cc1101_8PATABLE_write_reg(void)
344+{
345+ u8 i;
346+
347+
348+ spi1_select(SPI1_CC1100);
349+ spi1_write_single(0x3e | CC1100_ACCESS_WRITE_BURST);
350+ for(i=0;i<8;i++)
351+ {
352+ spi1_write_single(pt_data[i]);
353+ }
354+ spi1_deselect(SPI1_CC1100);
355+
356+}
357+
358+
359+
360+
--- trunk/CC1101_AT/CC1101_source_ATmega88/i2c.c (nonexistent)
+++ trunk/CC1101_AT/CC1101_source_ATmega88/i2c.c (revision 2602)
@@ -0,0 +1,144 @@
1+#include <avr/io.h>
2+#include <avr/interrupt.h>
3+#include <avr/eeprom.h>
4+#include <string.h>
5+#include <avr/sleep.h>
6+#include <util/twi.h>
7+
8+
9+#include "macro.h"
10+
11+// エラー
12+u8 i2c_error_flag = 0;
13+void i2c_error(void)
14+{
15+ mdelay(10);
16+ i2c_error_flag = 1;
17+}
18+
19+
20+
21+
22+// 通信速度の初期化
23+void i2c_init(void)
24+{
25+ TWSR = 0b00000000; // 1分周
26+ //TWBR = 0; // 250k = 4MHz / (16 + 2 * TWBR * 1)
27+ TWBR = 12; // 250k = 4MHz / (16 + 2 * TWBR * 1)
28+}
29+
30+
31+void i2c_wait_int_clear(void)
32+{
33+ u8 i=0;
34+
35+ while( !(TWCR & _BV(TWINT)) )
36+ {
37+ udelay(250);
38+ i++;
39+ if(i > 100) return;
40+ }
41+}
42+// master 1byte送信
43+void i2c_write(u8 d)
44+{
45+ TWDR = d; // 送信データ
46+ TWCR = _BV(TWINT) | _BV(TWEN);
47+ i2c_wait_int_clear();//while( !(TWCR & _BV(TWINT)) ) ; // データの送出完了待機
48+ if((TWSR & TW_STATUS_MASK) != TW_MT_DATA_ACK) i2c_error();
49+}
50+
51+// master 1byte受信(ackを返す)
52+u8 i2c_read_ack(void)
53+{
54+ TWCR = _BV(TWINT) | _BV(TWEN) | _BV(TWEA);
55+ i2c_wait_int_clear();//while( !(TWCR & _BV(TWINT)) ) ; // 受信完了待ち
56+ if((TWSR & TW_STATUS_MASK) != TW_MR_DATA_ACK) i2c_error();
57+ return TWDR; // データを返す
58+}
59+
60+// master 1byte受信(noackを返す)
61+u8 i2c_read_nak(void)
62+{
63+ TWCR = _BV(TWINT) | _BV(TWEN);
64+ i2c_wait_int_clear();//while( !(TWCR & _BV(TWINT)) ) ; // 受信完了待ち
65+ if((TWSR & TW_STATUS_MASK) != TW_MR_DATA_NACK) i2c_error();
66+ return TWDR; // データを返す
67+}
68+
69+// master送信開始、IDはslave address ＜＜ 1
70+void i2c_start(u8 id)
71+{
72+ u8 s;
73+
74+ // 開始条件を送る
75+ TWCR = _BV(TWINT) | _BV(TWSTA) | _BV(TWEN);
76+ i2c_wait_int_clear();//while( !(TWCR & _BV(TWINT)) ) ; // 開始条件の送出完了待機
77+ s = TWSR & TW_STATUS_MASK;
78+ if(s != TW_START && s != TW_REP_START) i2c_error();
79+
80+ // アドレスを送る
81+ TWDR = id;
82+ TWCR = _BV(TWINT) | _BV(TWEN);
83+ i2c_wait_int_clear();//while( !(TWCR & _BV(TWINT)) ) ; // アドレスの送出完了待機
84+ s = TWSR & TW_STATUS_MASK;
85+ if(s != TW_MT_SLA_ACK && s != TW_MR_SLA_ACK) i2c_error();
86+}
87+
88+// master送信終了
89+void i2c_stop(void)
90+{
91+ TWCR = _BV(TWINT) | _BV(TWSTO) | _BV(TWEN);
92+ while( !(TWCR & _BV(TWSTO)) ) ;
93+ // statusはTW_NO_INFOになる
94+}
95+
96+
97+
98+#define RTC_R2223L (0x32 << 1) // RICOH RTC R2223L/Tのslave address
99+
100+
101+u8 rtc_1byte_data_write(u8 addr,u8 data)
102+{
103+ /*write*/
104+ cli();
105+ i2c_error_flag = 0;
106+ i2c_start(RTC_R2223L | TW_WRITE);
107+ i2c_write((addr<<4)&0xf0); // register 4
108+ i2c_write(data); // 14bit resolution
109+ i2c_stop();
110+
111+ sei();
112+ if(i2c_error_flag == 1) return false;
113+
114+ return true;
115+}
116+
117+
118+u8 rtc_1byte_data_read(u8 addr)
119+{
120+ u8 data;
121+
122+ cli();
123+ i2c_start(RTC_R2223L | TW_WRITE);
124+ i2c_write((addr << 4)&0xF0); // register 0
125+ i2c_start(RTC_R2223L | TW_READ);
126+ data = i2c_read_nak(); // 下位読み込み(最後はNAKを返す)
127+ i2c_stop();
128+ sei();
129+ return data;
130+}
131+
132+
133+void rtc_3byte_data_read(u8 start_addr,u8 * data)
134+{
135+ i2c_start(RTC_R2223L | TW_WRITE);
136+ i2c_write((start_addr << 4)&0xF0); // register 0
137+ i2c_start(RTC_R2223L | TW_READ);
138+ data[0] = i2c_read_ack(); // 上位読み込み
139+ data[1] = i2c_read_ack(); // 上位読み込み
140+ data[2] = i2c_read_nak(); // 下位読み込み(最後はNAKを返す)
141+ i2c_stop();
142+}
143+
144+
--- trunk/CC1101_AT/CC1101_source_ATmega88/i2c.h (nonexistent)
+++ trunk/CC1101_AT/CC1101_source_ATmega88/i2c.h (revision 2602)
@@ -0,0 +1,9 @@
1+#ifndef I2C_H
2+#define I2C_H
3+
4+void i2c_init(void);
5+u8 rtc_1byte_data_write(u8 addr,u8 data);
6+u8 rtc_1byte_data_read(u8 addr);
7+void rtc_3byte_data_read(u8 start_addr,u8 * data);
8+
9+#endif
--- trunk/CC1101_AT/CC1101_source_ATmega88/spi1.c (nonexistent)
+++ trunk/CC1101_AT/CC1101_source_ATmega88/spi1.c (revision 2602)
@@ -0,0 +1,144 @@
1+#include <avr/io.h>
2+#include "spi1.h"
3+#include "macro.h"
4+
5+/* Local Macros */
6+
7+/*
8+ * wait until a byte has been received on spi port
9+ */
10+#define WAIT_EORX() while (! (SPSR & _BV(SPIF))){} // SPIFがセットされるのを待つ
11+
12+
13+/*
14+ * wait until a byte has been sent on spi port
15+ */
16+#define CC1100_CS_PIN (1<<2)
17+
18+#define CC1100_ENABLE() PORTB &= ~CC1100_CS_PIN
19+#define CC1100_DISABLE() PORTB |= CC1100_CS_PIN
20+
21+
22+void spi1_init(void)
23+{
24+ /* Configure IO pins */
25+ PBDDR |= (1<<5) | (1<<3); /* output for CLK and MOSI */
26+ PBDDR &= ~(1<<4); /* input for MISO */
27+
28+ PORTB &= ~(1<<3); //MOSI LOW
29+
30+ SPCR = _BV(SPE) | _BV(MSTR);
31+ CC1100_DISABLE();
32+}
33+
34+
35+
36+
37+
38+
39+u8 spi1_write_single(u8 byte)
40+{
41+ u8 dummy;
42+
43+ SPDR = byte;
44+ while (! (SPSR & _BV(SPIF))) {
45+ ; // SPIFがセットされるのを待つ
46+ }
47+
48+ WAIT_EORX();
49+ dummy = SPDR;
50+ return dummy;
51+}
52+
53+u8 spi1_read_single(void)
54+{
55+ return spi1_write_single(0x0);
56+}
57+
58+u8 spi1_write(u8* data, u16 len)
59+{
60+ u8 dummy=0;
61+ u16 i;
62+
63+ for (i=0; i<len; i++)
64+ {
65+ SPDR = data[i];
66+ WAIT_EORX();
67+ dummy = SPDR;
68+ }
69+ return dummy;
70+}
71+void spi1_read(u8* data, u16 len)
72+{
73+ u16 i;
74+
75+ for (i=0; i<len; i++)
76+ {
77+ SPDR = 0x0;
78+ WAIT_EORX();
79+ data[i] = SPDR;
80+ }
81+}
82+
83+void spi1_select(u16 chip)
84+{
85+ switch (chip) {
86+ case SPI1_CC1100:
87+ CC1100_ENABLE();
88+ break;
89+ default:
90+ break;
91+ }
92+}
93+
94+void spi1_deselect(u16 chip) {
95+ switch (chip) {
96+ case SPI1_CC1100:
97+ CC1100_DISABLE();
98+ break;
99+ default:
100+ break;
101+ }
102+}
103+
104+u16 spi1_read_somi(void)
105+{
106+ return PINB & (1<<2);
107+}
108+
109+
110+u8 spi_active=0;
111+void spi_signalpin_opendrain_active(void)
112+{
113+ SPCR &= ~(1<<SPE); //SPI non active
114+ DDRB &= ~(1<<PB2); //CSn
115+ DDRB &= ~(1<<PB3); //MOSI
116+ DDRB &= ~(1<<PB5); //SCK
117+
118+ PORTB &= ~(1<<PB2); //CSn
119+
120+ PORTC = 0x00;
121+ PORTD = 0x00;
122+ spi_active =1 ;
123+}
124+
125+
126+void spi_signalpin_opendrain_nonactive(void)
127+{
128+ spi1_init();
129+ //DDRB |= (1<<PB0); //B_CTL
130+ PORTB &= ~(1<<PB2); //CSn
131+ DDRB |= (1<<PB2); //CSn output
132+
133+ PORTC |= (1<<PC0);
134+ PORTC |= (1<<PC1);
135+ PORTC |= (1<<PC2);
136+ PORTC |= (1<<PC3);
137+ PORTC |= (1<<PC4);
138+ PORTC |= (1<<PC5);
139+ PORTD = 0xf7;
140+ spi_active =0 ;
141+}
142+
143+
144+
--- trunk/CC1101_AT/CC1101_source_ATmega88/spi1.h (nonexistent)
+++ trunk/CC1101_AT/CC1101_source_ATmega88/spi1.h (revision 2602)
@@ -0,0 +1,64 @@
1+/*
2+ * Copyright 2008-2009 INRIA/SensTools
3+ *
4+ * <dev-team@sentools.info>
5+ *
6+ * This software is a set of libraries designed to develop applications
7+ * for the WSN430 embedded hardware platform.
8+ *
9+ * This software is governed by the CeCILL license under French law and
10+ * abiding by the rules of distribution of free software. You can use,
11+ * modify and/ or redistribute the software under the terms of the CeCILL
12+ * license as circulated by CEA, CNRS and INRIA at the following URL
13+ * "http://www.cecill.info".
14+ *
15+ * As a counterpart to the access to the source code and rights to copy,
16+ * modify and redistribute granted by the license, users are provided only
17+ * with a limited warranty and the software&apos;s author, the holder of the
18+ * economic rights, and the successive licensors have only limited
19+ * liability.
20+ *
21+ * In this respect, the user&apos;s attention is drawn to the risks associated
22+ * with loading, using, modifying and/or developing or reproducing the
23+ * software by the user in light of its specific status of free software,
24+ * that may mean that it is complicated to manipulate, and that also
25+ * therefore means that it is reserved for developers and experienced
26+ * professionals having in-depth computer knowledge. Users are therefore
27+ * encouraged to load and test the software&apos;s suitability as regards their
28+ * requirements in conditions enabling the security of their systems and/or
29+ * data to be ensured and, more generally, to use and operate it in the
30+ * same conditions as regards security.
31+ *
32+ * The fact that you are presently reading this means that you have had
33+ * knowledge of the CeCILL license and that you accept its terms.
34+ */
35+#ifndef SPI1_H
36+#define SPI1_H
37+#include "macro.h"
38+
39+extern u8 spi1_tx_return_value;
40+
41+enum {
42+ SPI1_CC1100 = 1,
43+ SPI1_CC2420 = 1,
44+ SPI1_DS1722 = 2,
45+ SPI1_M25P80 = 3
46+};
47+
48+void spi1_init(void);
49+
50+u8 spi1_write_single(u8 byte);
51+u8 spi1_read_single(void);
52+
53+u8 spi1_write(u8* data, u16 len);
54+void spi1_read(u8* data, u16 len);
55+
56+void spi1_select(u16 chip);
57+void spi1_deselect(u16 chip);
58+
59+u16 spi1_read_somi(void);
60+void spi_signalpin_opendrain_active(void);
61+void spi_signalpin_opendrain_nonactive(void);
62+
63+#endif
64+
--- trunk/CC1101_AT/CC1101_source_ATmega88/cc1100.h (nonexistent)
+++ trunk/CC1101_AT/CC1101_source_ATmega88/cc1100.h (revision 2602)
@@ -0,0 +1,525 @@
1+/*
2+ * Copyright 2008-2009 INRIA/SensTools
3+ *
4+ * <dev-team@sentools.info>
5+ *
6+ * This software is a set of libraries designed to develop applications
7+ * for the WSN430 embedded hardware platform.
8+ *
9+ * This software is governed by the CeCILL license under French law and
10+ * abiding by the rules of distribution of free software. You can use,
11+ * modify and/ or redistribute the software under the terms of the CeCILL
12+ * license as circulated by CEA, CNRS and INRIA at the following URL
13+ * "http://www.cecill.info".
14+ *
15+ * As a counterpart to the access to the source code and rights to copy,
16+ * modify and redistribute granted by the license, users are provided only
17+ * with a limited warranty and the software&apos;s author, the holder of the
18+ * economic rights, and the successive licensors have only limited
19+ * liability.
20+ *
21+ * In this respect, the user&apos;s attention is drawn to the risks associated
22+ * with loading, using, modifying and/or developing or reproducing the
23+ * software by the user in light of its specific status of free software,
24+ * that may mean that it is complicated to manipulate, and that also
25+ * therefore means that it is reserved for developers and experienced
26+ * professionals having in-depth computer knowledge. Users are therefore
27+ * encouraged to load and test the software&apos;s suitability as regards their
28+ * requirements in conditions enabling the security of their systems and/or
29+ * data to be ensured and, more generally, to use and operate it in the
30+ * same conditions as regards security.
31+ *
32+ * The fact that you are presently reading this means that you have had
33+ * knowledge of the CeCILL license and that you accept its terms.
34+ */
35+
36+#ifndef _CC1100_H
37+#define _CC1100_H
38+
39+#include "cc1100_globals.h"
40+#include "cc1100_gdo.h"
41+#include "macro.h"
42+
43+
44+typedef struct _cc1101_reg_
45+{
46+ u8 addr;
47+ u8 data;
48+}reg_t;
49+
50+// other
51+void micro_delay(register unsigned int n);
52+
53+// real functions
54+void cc1100_init(void);
55+
56+void cc1100_reinit(void);
57+
58+u8 cc1100_read_reg(u8 addr);
59+
60+void cc1100_write_reg(u8 addr, u8 value);
61+
62+void cc1100_fifo_put(u8* buffer, u16 length);
63+
64+void cc1100_fifo_get(u8* buffer, u16 length);
65+
66+u8 cc1100_read_status(u8 addr);
67+
68+u8 cc1100_strobe_cmd(u8 cmd);
69+
70+u8 cc1100_sleep_strobe_cmd(u8 cmd);
71+
72+// status byte
73+#define cc1100_status() \
74+ cc1100_strobe_cmd(CC1100_STROBE_SNOP)
75+
76+// commands macros
77+
78+#define cc1100_cmd_reset() \
79+ cc1100_strobe_cmd(CC1100_STROBE_SRES)
80+
81+#define cc1100_cmd_xoff() \
82+ cc1100_strobe_cmd(CC1100_STROBE_SXOFF)
83+
84+void cc1100_cmd_calibrate(void);
85+
86+#define cc1100_cmd_rx() \
87+ cc1100_strobe_cmd(CC1100_STROBE_SRX)
88+
89+#define cc1100_cmd_tx() \
90+ cc1100_strobe_cmd(CC1100_STROBE_STX)
91+
92+void cc1100_cmd_idle(void);
93+
94+#define cc1100_cmd_wor() \
95+ cc1100_strobe_cmd(CC1100_STROBE_SWOR)
96+
97+#define cc1100_cmd_pwd() \
98+ cc1100_strobe_cmd(CC1100_STROBE_SPWD)
99+
100+
101+/*add 20100113*/
102+#define cc1100_sleep_cmd_pwd() \
103+ cc1100_sleep_strobe_cmd(CC1100_STROBE_SPWD)
104+
105+
106+#define cc1100_cmd_flush_rx() \
107+ cc1100_strobe_cmd(CC1100_STROBE_SFRX)
108+
109+#define cc1100_cmd_flush_tx() \
110+ cc1100_strobe_cmd(CC1100_STROBE_SFTX)
111+
112+#define cc1100_cmd_reset_wor() \
113+ cc1100_strobe_cmd(CC1100_STROBE_SWORRST)
114+
115+#define cc1100_cmd_nop() \
116+ cc1100_strobe_cmd(CC1100_STROBE_SNOP)
117+
118+
119+// Power Table Config
120+#define cc1100_cfg_patable(table, length) \
121+ cc1100_write_reg(CC1100_PATABLE_ADDR | CC1100_ACCESS_WRITE_BURST, (table)[0])
122+
123+#define CC1100_GDOx_RX_FIFO 0x00 /* assert above threshold, deassert when below */
124+#define CC1100_GDOx_RX_FIFO_EOP 0x01 /* assert above threshold or EOP, deassert when empty */
125+#define CC1100_GDOx_TX_FIFO 0x02 /* assert above threshold, deassert when below */
126+#define CC1100_GDOx_TX_THR_FULL 0x03 /* asserts TX FIFO full. De-asserts when below thr */
127+#define CC1100_GDOx_RX_OVER 0x04 /* asserts when RX overflow, deassert when flushed */
128+#define CC1100_GDOx_TX_UNDER 0x05 /* asserts when RX underflow, deassert when flushed */
129+#define CC1100_GDOx_SYNC_WORD 0x06 /* assert SYNC sent/recv, deasserts on EOP */
130+ /* In RX, de-assert on overflow or bad address */
131+ /* In TX, de-assert on underflow */
132+#define CC1100_GDOx_RX_OK 0x07 /* assert when RX PKT with CRC ok, de-assert on 1byte */
133+ /* read from RX Fifo */
134+#define CC1100_GDOx_PREAMB_OK 0x08 /* assert when preamble quality reached : PQI/PQT ok */
135+#define CC1100_GDOx_CCA 0x09 /* Clear channel assessment. High when RSSI level is */
136+ /* below threshold (dependent on the current CCA_MODE) */
137+#define cc1100_cfg_gdo0(cfg) \
138+ cc1100_write_reg(CC1100_REG_IOCFG0, cfg)
139+
140+#define cc1100_cfg_gdo2(cfg) \
141+ cc1100_write_reg(CC1100_REG_IOCFG2, cfg)
142+
143+#define cc1100_cfg_fifo_thr(cfg) \
144+ cc1100_write_reg(CC1100_REG_FIFOTHR, ((cfg)&0x0F))
145+
146+#define cc1100_cfg_packet_length(cfg) \
147+ cc1100_write_reg(CC1100_REG_PKTLEN, (cfg))
148+
149+#define cc1100_cfg_pqt(cfg) do { \
150+ u8 reg; \
151+ reg = cc1100_read_reg(CC1100_REG_PKTCTRL1); \
152+ reg = (reg & 0x1F) | (((cfg) << 5) & 0xE0); \
153+ cc1100_write_reg(CC1100_REG_PKTCTRL1, reg); \
154+} while (0)
155+
156+#define CC1100_CRC_AUTOFLUSH_ENABLE 0x1
157+#define CC1100_CRC_AUTOFLUSH_DISABLE 0x0
158+
159+#define cc1100_cfg_crc_autoflush(cfg) do { \
160+ u8 reg; \
161+ reg = cc1100_read_reg(CC1100_REG_PKTCTRL1); \
162+ reg = (reg & 0xF7) | (((cfg) << 3) & 0x08); \
163+ cc1100_write_reg(CC1100_REG_PKTCTRL1, reg); \
164+} while (0)
165+
166+#define CC1100_APPEND_STATUS_ENABLE 0x1
167+#define CC1100_APPEND_STATUS_DISABLE 0x0
168+
169+#define cc1100_cfg_append_status(cfg) do { \
170+ u8 reg; \
171+ reg = cc1100_read_reg(CC1100_REG_PKTCTRL1); \
172+ reg = (reg & 0xFB) | (((cfg) << 2) & 0x04); \
173+ cc1100_write_reg(CC1100_REG_PKTCTRL1, reg); \
174+} while (0)
175+
176+#define CC1100_ADDR_NO_CHECK 0x0
177+#define CC1100_ADDR_CHECK_NO_BROADCAST 0x1
178+#define CC1100_ADDR_CHECK_BROADCAST_0 0x2
179+#define CC1100_ADDR_CHECK_NO_BROADCAST_0_255 0x3
180+
181+#define cc1100_cfg_adr_check(cfg) do { \
182+ u8 reg; \
183+ reg = cc1100_read_reg(CC1100_REG_PKTCTRL1); \
184+ reg = (reg & 0xFC) | (((cfg) << 0) & 0x03); \
185+ cc1100_write_reg(CC1100_REG_PKTCTRL1, reg); \
186+} while (0)
187+
188+#define CC1100_DATA_WHITENING_ENABLE 0x1
189+#define CC1100_DATA_WHITENING_DISABLE 0x0
190+
191+#define cc1100_cfg_white_data(cfg) do { \
192+ u8 reg; \
193+ reg = cc1100_read_reg(CC1100_REG_PKTCTRL0); \
194+ reg = (reg & 0xBF) | (((cfg) << 6) & 0x40); \
195+ cc1100_write_reg(CC1100_REG_PKTCTRL0, reg); \
196+} while (0)
197+
198+
199+#define CC1100_CRC_CALCULATION_ENABLE 0x1
200+#define CC1100_CRC_CALCULATION_DISABLE 0x0
201+
202+#define cc1100_cfg_crc_en(cfg) do { \
203+ u8 reg; \
204+ reg = cc1100_read_reg(CC1100_REG_PKTCTRL0); \
205+ reg = (reg & 0xFB) | (((cfg) << 2) & 0x04); \
206+ cc1100_write_reg(CC1100_REG_PKTCTRL0, reg); \
207+} while (0)
208+
209+#define CC1100_PACKET_LENGTH_FIXED 0x0
210+#define CC1100_PACKET_LENGTH_VARIABLE 0x1
211+#define CC1100_PACKET_LENGTH_INFINITE 0x2
212+
213+#define cc1100_cfg_length_config(cfg) do { \
214+ u8 reg; \
215+ reg = cc1100_read_reg(CC1100_REG_PKTCTRL0); \
216+ reg = (reg & 0xFC) | (((cfg) << 0) & 0x03); \
217+ cc1100_write_reg(CC1100_REG_PKTCTRL0, reg); \
218+} while (0)
219+
220+#define cc1100_cfg_device_addr(cfg) \
221+ cc1100_write_reg(CC1100_REG_ADDR, (cfg))
222+
223+#define cc1100_cfg_chan(cfg) \
224+ cc1100_write_reg(CC1100_REG_CHANNR, (cfg))
225+
226+#define cc1100_cfg_freq_if(cfg) \
227+ cc1100_write_reg(CC1100_REG_FSCTRL1, ((cfg) & 0x1F))
228+
229+#define cc1100_cfg_freq(cfg) do { \
230+ u8 reg; \
231+ reg = (u8) ( ((cfg)>>16)&0xFF ); \
232+ cc1100_write_reg(CC1100_REG_FREQ2, reg); \
233+ reg = (u8) ( ((cfg)>>8)&0xFF ); \
234+ cc1100_write_reg(CC1100_REG_FREQ1, reg); \
235+ reg = (u8) ( (cfg)&0xFF ); \
236+ cc1100_write_reg(CC1100_REG_FREQ0, reg); \
237+} while (0)
238+
239+#define cc1100_cfg_chanbw_e(cfg) do { \
240+ u8 reg; \
241+ reg = cc1100_read_reg(CC1100_REG_MDMCFG4); \
242+ reg = (reg & 0x3F) | (((cfg) << 6) & 0xC0); \
243+ cc1100_write_reg(CC1100_REG_MDMCFG4, reg); \
244+} while (0)
245+
246+#define cc1100_cfg_chanbw_m(cfg) do { \
247+ u8 reg; \
248+ reg = cc1100_read_reg(CC1100_REG_MDMCFG4); \
249+ reg = (reg & 0xCF) | (((cfg)<<4) & 0x30); \
250+ cc1100_write_reg(CC1100_REG_MDMCFG4, reg); \
251+} while (0)
252+
253+#define cc1100_cfg_drate_e(cfg) do { \
254+ u8 reg; \
255+ reg = cc1100_read_reg(CC1100_REG_MDMCFG4); \
256+ reg = (reg & 0xF0) | (((cfg)) & 0x0F); \
257+ cc1100_write_reg(CC1100_REG_MDMCFG4, reg); \
258+} while (0)
259+
260+#define cc1100_cfg_drate_m(cfg) \
261+ cc1100_write_reg(CC1100_REG_MDMCFG3, (cfg))
262+
263+#define CC1100_MODULATION_2FSK 0x00
264+#define CC1100_MODULATION_GFSK 0x01
265+#define CC1100_MODULATION_ASK 0x03
266+#define CC1100_MODULATION_MSK 0x07
267+
268+#define cc1100_cfg_mod_format(cfg) do { \
269+ u8 reg; \
270+ reg = cc1100_read_reg(CC1100_REG_MDMCFG2); \
271+ reg = (reg & 0x8F) | (((cfg) << 4) & 0x70); \
272+ cc1100_write_reg(CC1100_REG_MDMCFG2, reg); \
273+} while (0)
274+
275+#define CC1100_MANCHESTER_ENABLE 0x1
276+#define CC1100_MANCHESTER_DISABLE 0x0
277+
278+#define cc1100_cfg_manchester_en(cfg) do { \
279+ u8 reg; \
280+ reg = cc1100_read_reg(CC1100_REG_MDMCFG2); \
281+ reg = (reg & 0xF7) | (((cfg) << 3) & 0x08); \
282+ cc1100_write_reg(CC1100_REG_MDMCFG2, reg); \
283+} while (0)
284+
285+
286+#define CC1100_SYNCMODE_NO_PREAMB 0x0
287+#define CC1100_SYNCMODE_15_16 0x1
288+#define CC1100_SYNCMODE_16_16 0x2
289+#define CC1100_SYNCMODE_30_32 0x3
290+#define CC1100_SYNCMODE_NO_PREAMB_CS 0x4
291+#define CC1100_SYNCMODE_15_16_CS 0x5
292+#define CC1100_SYNCMODE_16_16_CS 0x6
293+#define CC1100_SYNCMODE_30_32_CS 0x7
294+
295+#define cc1100_cfg_sync_mode(cfg) do { \
296+ u8 reg; \
297+ reg = cc1100_read_reg(CC1100_REG_MDMCFG2); \
298+ reg = (reg & 0xF8) | (((cfg) << 0) & 0x07); \
299+ cc1100_write_reg(CC1100_REG_MDMCFG2, reg); \
300+} while (0)
301+
302+#define CC1100_FEC_ENABLE 0x1
303+#define CC1100_FEC_DISABLE 0x0
304+
305+#define cc1100_cfg_fec_en(cfg) do { \
306+ u8 reg; \
307+ reg = cc1100_read_reg(CC1100_REG_MDMCFG1); \
308+ reg = (reg & 0x7F) | (((cfg) << 7) & 0x80); \
309+ cc1100_write_reg(CC1100_REG_MDMCFG1, reg); \
310+} while (0)
311+
312+#define cc1100_cfg_num_preamble(cfg) do { \
313+ u8 reg; \
314+ reg = cc1100_read_reg(CC1100_REG_MDMCFG1); \
315+ reg = (reg & 0x8F) | (((cfg) << 4) & 0x70); \
316+ cc1100_write_reg(CC1100_REG_MDMCFG1, reg); \
317+} while (0)
318+
319+#define cc1100_cfg_chanspc_e(cfg) do { \
320+ u8 reg; \
321+ reg = cc1100_read_reg(CC1100_REG_MDMCFG1); \
322+ reg = (reg & 0xFE) | (((cfg) << 0) & 0x01); \
323+ cc1100_write_reg(CC1100_REG_MDMCFG1, reg); \
324+} while (0)
325+
326+#define cc1100_cfg_chanspc_m(cfg) \
327+ cc1100_write_reg(CC1100_REG_MDMCFG0, (cfg))
328+
329+#define CC1100_RX_TIME_RSSI_ENABLE 0x1
330+#define CC1100_RX_TIME_RSSI_DISABLE 0x0
331+
332+#define cc1100_cfg_rx_time_rssi(cfg) do { \
333+ u8 reg; \
334+ reg = cc1100_read_reg(CC1100_REG_MCSM2); \
335+ reg = (reg & 0xEF) | (((cfg) << 4) & 0x10); \
336+ cc1100_write_reg(CC1100_REG_MCSM2, reg); \
337+} while (0)
338+
339+#define cc1100_cfg_rx_time(cfg) do { \
340+ u8 reg; \
341+ reg = cc1100_read_reg(CC1100_REG_MCSM2); \
342+ reg = (reg & 0xF8) | (((cfg) << 0) & 0x07); \
343+ cc1100_write_reg(CC1100_REG_MCSM2, reg); \
344+} while (0)
345+
346+#define CC1100_CCA_MODE_ALWAYS 0x0
347+#define CC1100_CCA_MODE_RSSI 0x1
348+#define CC1100_CCA_MODE_PKT_RX 0x2
349+#define CC1100_CCA_MODE_RSSI_PKT_RX 0x3
350+
351+#define cc1100_cfg_cca_mode(cfg) do { \
352+ u8 reg; \
353+ reg = cc1100_read_reg(CC1100_REG_MCSM1); \
354+ reg = (reg & 0xCF) | (((cfg) << 4) & 0x30); \
355+ cc1100_write_reg(CC1100_REG_MCSM1, reg); \
356+} while (0)
357+
358+#define CC1100_RXOFF_MODE_IDLE 0x00
359+#define CC1100_RXOFF_MODE_FSTXON 0x01 /* freq synth on, ready to Tx */
360+#define CC1100_RXOFF_MODE_TX 0x02
361+#define CC1100_RXOFF_MODE_STAY_RX 0x03
362+
363+#define cc1100_cfg_rxoff_mode(cfg) do { \
364+ u8 reg; \
365+ reg = cc1100_read_reg(CC1100_REG_MCSM1); \
366+ reg = (reg & 0xF3) | (((cfg) << 2) & 0x0C); \
367+ cc1100_write_reg(CC1100_REG_MCSM1, reg); \
368+} while (0)
369+
370+#define CC1100_TXOFF_MODE_IDLE 0x00
371+#define CC1100_TXOFF_MODE_FSTXON 0x01 /* freq synth on, ready to Tx */
372+#define CC1100_TXOFF_MODE_STAY_TX 0x02
373+#define CC1100_TXOFF_MODE_RX 0x03
374+
375+#define cc1100_cfg_txoff_mode(cfg) do { \
376+ u8 reg; \
377+ reg = cc1100_read_reg(CC1100_REG_MCSM1); \
378+ reg = (reg & 0xFC) | (((cfg) << 0) & 0x03); \
379+ cc1100_write_reg(CC1100_REG_MCSM1, reg); \
380+} while (0)
381+
382+
383+#define CC1100_AUTOCAL_NEVER 0x00
384+#define CC1100_AUTOCAL_IDLE_TO_TX_RX 0x01
385+#define CC1100_AUTOCAL_TX_RX_TO_IDLE 0x02
386+#define CC1100_AUTOCAL_4TH_TX_RX_TO_IDLE 0x03
387+
388+#define cc1100_cfg_fs_autocal(cfg) do { \
389+ u8 reg; \
390+ reg = cc1100_read_reg(CC1100_REG_MCSM0); \
391+ reg = (reg & 0xCF) | (((cfg) << 4) & 0x30); \
392+ cc1100_write_reg(CC1100_REG_MCSM0, reg); \
393+} while (0)
394+
395+#define cc1100_cfg_carrier_sense_rel_thr(cfg) do { \
396+ u8 reg; \
397+ reg = cc1100_read_reg(CC1100_REG_AGCCTRL1); \
398+ reg = (reg & 0xCF) | (((cfg) << 4) & 0x30); \
399+ cc1100_write_reg(CC1100_REG_AGCCTRL1, reg); \
400+} while (0)
401+
402+#define cc1100_cfg_carrier_sense_abs_thr(cfg) do { \
403+ u8 reg; \
404+ reg = cc1100_read_reg(CC1100_REG_AGCCTRL1); \
405+ reg = (reg & 0xF0) | (((cfg) << 0) & 0x0F); \
406+ cc1100_write_reg(CC1100_REG_AGCCTRL1, reg); \
407+} while (0)
408+
409+#define cc1100_cfg_event0(cfg) do { \
410+ u8 reg; \
411+ reg = (u8)((cfg >> 8) & 0xFF); \
412+ cc1100_write_reg(CC1100_REG_WOREVT1, reg); \
413+ reg = (u8)((cfg) & 0xFF); \
414+ cc1100_write_reg(CC1100_REG_WOREVT0, reg); \
415+} while (0)
416+
417+#define CC1100_RC_OSC_ENABLE 0x0
418+#define CC1100_RC_OSC_DISABLE 0x1
419+
420+#define cc1100_cfg_rc_pd(cfg) do { \
421+ u8 reg; \
422+ reg = cc1100_read_reg(CC1100_REG_WORCTRL); \
423+ reg = (reg & 0x7F) | (((cfg) << 7) & 0x80); \
424+ cc1100_write_reg(CC1100_REG_WORCTRL, reg); \
425+} while (0)
426+
427+#define cc1100_cfg_event1(cfg) do { \
428+ u8 reg; \
429+ reg = cc1100_read_reg(CC1100_REG_WORCTRL); \
430+ reg = (reg & 0x8F) | (((cfg) << 4) & 0x70); \
431+ cc1100_write_reg(CC1100_REG_WORCTRL, reg); \
432+} while (0)
433+
434+#define cc1100_cfg_wor_res(cfg) do { \
435+ u8 reg; \
436+ reg = cc1100_read_reg(CC1100_REG_WORCTRL); \
437+ reg = (reg & 0xFC) | (((cfg) << 0) & 0x03); \
438+ cc1100_write_reg(CC1100_REG_WORCTRL, reg); \
439+} while (0)
440+
441+#define cc1100_cfg_pa_power(cfg) do { \
442+ u8 reg; \
443+ reg = cc1100_read_reg(CC1100_REG_FREND0); \
444+ reg = (reg & 0xF8) | (((cfg) << 0) & 0x07); \
445+ cc1100_write_reg(CC1100_REG_FREND0, reg); \
446+} while (0)
447+
448+// Status Registers access
449+#define cc1100_status_crc_lqi() \
450+ cc1100_read_status(CC1100_REG_LQI)
451+
452+#define cc1100_status_rssi() \
453+ cc1100_read_status(CC1100_REG_RSSI)
454+
455+#define cc1100_status_marcstate() \
456+ cc1100_read_status(CC1100_REG_MARCSTATE)
457+
458+#define cc1100_status_wortime1() \
459+ cc1100_read_status(CC1100_REG_WORTIME1)
460+
461+#define cc1100_status_wortime0() \
462+ cc1100_read_status(CC1100_REG_WORTIME0)
463+
464+#define cc1100_status_pktstatus() \
465+ cc1100_read_status(CC1100_REG_PKTSTATUS)
466+
467+#define cc1100_status_txbytes() \
468+ cc1100_read_status(CC1100_REG_TXBYTES)
469+
470+#define cc1100_status_rxbytes() \
471+ cc1100_read_status(CC1100_REG_RXBYTES)
472+
473+
474+// GDOx int config & access
475+
476+
477+
478+#define cc1100_gdo0_int_enable() \
479+ GDO0_INT_ENABLE()
480+
481+#define cc1100_gdo0_int_disable() \
482+ GDO0_INT_DISABLE()
483+
484+#define cc1100_gdo0_int_clear() \
485+ GDO0_INT_CLEAR()
486+
487+#define cc1100_gdo0_int_set_falling_edge() \
488+ GDO0_INT_SET_FALLING()
489+
490+#define cc1100_gdo0_int_set_rising_edge() \
491+ GDO0_INT_SET_RISING()
492+
493+#define cc1100_gdo0_read() \
494+ GDO0_READ()
495+
496+void cc1100_gdo0_register_callback(u16 (*cb)(void));
497+
498+#define cc1100_gdo2_int_enable() \
499+ GDO2_INT_ENABLE()
500+
501+#define cc1100_gdo2_int_disable() \
502+ GDO2_INT_DISABLE()
503+
504+#define cc1100_gdo2_int_clear() \
505+ GDO2_INT_CLEAR()
506+
507+#define cc1100_gdo2_int_set_falling_edge() \
508+ GDO2_INT_SET_FALLING()
509+
510+#define cc1100_gdo2_int_set_rising_edge() \
511+ GDO2_INT_SET_RISING()
512+
513+#define cc1100_gdo2_read() \
514+ GDO2_READ()
515+
516+void cc1100_gdo2_register_callback(u16 (*cb)(void));
517+
518+
519+// my function
520+void cc1101_init_reg(void);
521+void cc1101_rtx_reg_set(u8 rtx);
522+void cc1101_8PATABLE_write_reg(void);
523+
524+#endif
525+
--- trunk/CC1101_AT/CC1101_source_ATmega88/cc1100_globals.h (nonexistent)
+++ trunk/CC1101_AT/CC1101_source_ATmega88/cc1100_globals.h (revision 2602)
@@ -0,0 +1,268 @@
1+/*
2+ * Copyright 2008-2009 INRIA/SensTools
3+ *
4+ * <dev-team@sentools.info>
5+ *
6+ * This software is a set of libraries designed to develop applications
7+ * for the WSN430 embedded hardware platform.
8+ *
9+ * This software is governed by the CeCILL license under French law and
10+ * abiding by the rules of distribution of free software. You can use,
11+ * modify and/ or redistribute the software under the terms of the CeCILL
12+ * license as circulated by CEA, CNRS and INRIA at the following URL
13+ * "http://www.cecill.info".
14+ *
15+ * As a counterpart to the access to the source code and rights to copy,
16+ * modify and redistribute granted by the license, users are provided only
17+ * with a limited warranty and the software&apos;s author, the holder of the
18+ * economic rights, and the successive licensors have only limited
19+ * liability.
20+ *
21+ * In this respect, the user&apos;s attention is drawn to the risks associated
22+ * with loading, using, modifying and/or developing or reproducing the
23+ * software by the user in light of its specific status of free software,
24+ * that may mean that it is complicated to manipulate, and that also
25+ * therefore means that it is reserved for developers and experienced
26+ * professionals having in-depth computer knowledge. Users are therefore
27+ * encouraged to load and test the software&apos;s suitability as regards their
28+ * requirements in conditions enabling the security of their systems and/or
29+ * data to be ensured and, more generally, to use and operate it in the
30+ * same conditions as regards security.
31+ *
32+ * The fact that you are presently reading this means that you have had
33+ * knowledge of the CeCILL license and that you accept its terms.
34+ */
35+
36+#ifndef _CC1100_GLOBALS_H
37+#define _CC1100_GLOBALS_H
38+
39+
40+#define CC1100_POWER_UP_DELAY_NS 40000
41+#define CC1100_POWER_UP_DELAY_US 40
42+#define CC1100_MANCAL_DELAY_NS 721000
43+#define CC1100_MANCAL_DELAY_US 721
44+#define CC1100_FS_WAKEUP_DELAY_NS 44200
45+#define CC1100_FS_WAKEUP_DELAY_US 45
46+#define CC1100_SETTLING_DELAY_NS 44200
47+#define CC1100_SETTLING_DELAY_US 44
48+#define CC1100_CALIBRATE_DELAY_NS 720600
49+#define CC1100_CALIBRATE_DELAY_US 720
50+#define CC1100_IDLE_NOCAL_DELAY_NS 100
51+#define CC1100_IDLE_NOCAL_DELAY_US 1
52+#define CC1100_TX_RX_DELAY_NS 21500
53+#define CC1100_TX_RX_DELAY_US 22
54+#define CC1100_RX_TX_DELAY_NS 9600
55+#define CC1100_RX_TX_DELAY_US 10
56+
57+#define CC1100_STATUS_IDLE 0x00
58+#define CC1100_STATUS_RX 0x01
59+#define CC1100_STATUS_TX 0x02
60+#define CC1100_STATUS_FSTXON 0x03
61+#define CC1100_STATUS_CALIBRATE 0x04
62+#define CC1100_STATUS_SETTLING 0x05
63+#define CC1100_STATUS_RXFIFO_OVERFLOW 0x06
64+#define CC1100_STATUS_TXFIFO_UNDERFLOW 0x07
65+
66+#define CC1100_STATE_SLEEP 0x00
67+#define CC1100_STATE_IDLE 0x01
68+#define CC1100_STATE_XOFF 0x02
69+#define CC1100_STATE_MANCAL 0x03
70+#define CC1100_STATE_FS_WAKEUP 0x06
71+#define CC1100_STATE_FS_CALIBRATE 0x08
72+#define CC1100_STATE_SETTLING 0x09
73+#define CC1100_STATE_CALIBRATE 0x12
74+#define CC1100_STATE_RX 0x13
75+#define CC1100_STATE_TXRX_SETTLING 0x16
76+#define CC1100_STATE_RX_OVERFLOW 0x17
77+#define CC1100_STATE_FSTXON 0x18
78+#define CC1100_STATE_TX 0x19
79+#define CC1100_STATE_RXTX_SETTLING 0x21
80+#define CC1100_STATE_TX_UNDERFLOW 0x22
81+#define CC1100_STATE_IDLING 0x23
82+
83+#define CC1100_ACCESS_READ 0x80
84+#define CC1100_ACCESS_READ_BURST 0xC0
85+#define CC1100_ACCESS_WRITE 0x00
86+#define CC1100_ACCESS_WRITE_BURST 0x40
87+#define CC1100_ACCESS_STATUS 0xC0
88+#define CC1100_ACCESS_STROBE 0x00
89+
90+#define CC1100_STROBE_SRES 0x30 /* reset */
91+#define CC1100_STROBE_SFSTXON 0x31 /* enable and calibrate */
92+#define CC1100_STROBE_SXOFF 0x32 /* crystall off */
93+#define CC1100_STROBE_SCAL 0x33 /* calibrate */
94+#define CC1100_STROBE_SRX 0x34 /* enable rx */
95+#define CC1100_STROBE_STX 0x35 /* enable tx */
96+#define CC1100_STROBE_SIDLE 0x36 /* go idle */
97+#define CC1100_STROBE_SAFC 0x37 /* AFC adjustment */
98+#define CC1100_STROBE_SWOR 0x38 /* wake on radio */
99+#define CC1100_STROBE_SPWD 0x39 /* power down */
100+#define CC1100_STROBE_SFRX 0x3A /* flush Rx fifo */
101+#define CC1100_STROBE_SFTX 0x3B /* flush Tx fifo */
102+#define CC1100_STROBE_SWORRST 0x3C /* reset WOR timer */
103+#define CC1100_STROBE_SNOP 0x3D /* no operation */
104+
105+#define CC1100_REG_IOCFG2 0x00
106+#define CC1100_REG_IOCFG2_DEFAULT 0x29
107+#define CC1100_REG_IOCFG1 0x01
108+#define CC1100_REG_IOCFG1_DEFAULT 0x2E
109+#define CC1100_REG_IOCFG0 0x02
110+#define CC1100_REG_IOCFG0_DEFAULT 0x3F
111+#define CC1100_REG_FIFOTHR 0x03
112+#define CC1100_REG_FIFOTHR_DEFAULT 0x07
113+#define CC1100_REG_SYNC1 0x04
114+#define CC1100_REG_SYNC1_DEFAULT 0xD3
115+#define CC1100_REG_SYNC0 0x05
116+#define CC1100_REG_SYNC0_DEFAULT 0x91
117+#define CC1100_REG_PKTLEN 0x06
118+#define CC1100_REG_PKTLEN_DEFAULT 0xFF
119+#define CC1100_REG_PKTCTRL1 0x07
120+#define CC1100_REG_PKTCTRL1_DEFAULT 0x04
121+#define CC1100_REG_PKTCTRL0 0x08
122+#define CC1100_REG_PKTCTRL0_DEFAULT 0x45
123+#define CC1100_REG_ADDR 0x09
124+#define CC1100_REG_ADDR_DEFAULT 0x00
125+#define CC1100_REG_CHANNR 0x0A
126+#define CC1100_REG_CHANNR_DEFAULT 0x00
127+#define CC1100_REG_FSCTRL1 0x0B
128+#define CC1100_REG_FSCTRL1_DEFAULT 0x0F
129+#define CC1100_REG_FSCTRL0 0x0C
130+#define CC1100_REG_FSCTRL0_DEFAULT 0x00
131+#define CC1100_REG_FREQ2 0x0D
132+#define CC1100_REG_FREQ2_DEFAULT 0x1E
133+#define CC1100_REG_FREQ1 0x0E
134+#define CC1100_REG_FREQ1_DEFAULT 0xC4
135+#define CC1100_REG_FREQ0 0x0F
136+#define CC1100_REG_FREQ0_DEFAULT 0xEC
137+#define CC1100_REG_MDMCFG4 0x10
138+#define CC1100_REG_MDMCFG4_DEFAULT 0x8C
139+#define CC1100_REG_MDMCFG3 0x11
140+#define CC1100_REG_MDMCFG3_DEFAULT 0x22
141+#define CC1100_REG_MDMCFG2 0x12
142+#define CC1100_REG_MDMCFG2_DEFAULT 0x02
143+#define CC1100_REG_MDMCFG1 0x13
144+#define CC1100_REG_MDMCFG1_DEFAULT 0x22
145+#define CC1100_REG_MDMCFG0 0x14
146+#define CC1100_REG_MDMCFG0_DEFAULT 0xF8
147+#define CC1100_REG_DEVIATN 0x15
148+#define CC1100_REG_DEVIATN_DEFAULT 0x47
149+#define CC1100_REG_MCSM2 0x16
150+#define CC1100_REG_MCSM2_DEFAULT 0x07
151+#define CC1100_REG_MCSM1 0x17
152+#define CC1100_REG_MCSM1_DEFAULT 0x30
153+#define CC1100_REG_MCSM0 0x18
154+#define CC1100_REG_MCSM0_DEFAULT 0x04
155+#define CC1100_REG_FOCCFG 0x19
156+#define CC1100_REG_FOCCFG_DEFAULT 0x36
157+#define CC1100_REG_BSCFG 0x1A
158+#define CC1100_REG_BSCFG_DEFAULT 0x6C
159+#define CC1100_REG_AGCCTRL2 0x1B
160+#define CC1100_REG_AGCCTRL2_DEFAULT 0x03
161+#define CC1100_REG_AGCCTRL1 0x1C
162+#define CC1100_REG_AGCCTRL1_DEFAULT 0x40
163+#define CC1100_REG_AGCCTRL0 0x1D
164+#define CC1100_REG_AGCCTRL0_DEFAULT 0x91
165+#define CC1100_REG_WOREVT1 0x1E
166+#define CC1100_REG_WOREVT1_DEFAULT 0x87
167+#define CC1100_REG_WOREVT0 0x1F
168+#define CC1100_REG_WOREVT0_DEFAULT 0x6B
169+#define CC1100_REG_WORCTRL 0x20
170+#define CC1100_REG_WORCTRL_DEFAULT 0xF8
171+#define CC1100_REG_FREND1 0x21
172+#define CC1100_REG_FREND1_DEFAULT 0xA6
173+#define CC1100_REG_FREND0 0x22
174+#define CC1100_REG_FREND0_DEFAULT 0x10
175+#define CC1100_REG_FSCAL3 0x23
176+#define CC1100_REG_FSCAL3_DEFAULT 0xA9
177+#define CC1100_REG_FSCAL2 0x24
178+#define CC1100_REG_FSCAL2_DEFAULT 0x0A
179+#define CC1100_REG_FSCAL1 0x25
180+#define CC1100_REG_FSCAL1_DEFAULT 0x20
181+#define CC1100_REG_FSCAL0 0x26
182+#define CC1100_REG_FSCAL0_DEFAULT 0x0D
183+#define CC1100_REG_RCCTRL1 0x27
184+#define CC1100_REG_RCCTRL1_DEFAULT 0x41
185+#define CC1100_REG_RCCTRL0 0x28
186+#define CC1100_REG_RCCTRL0_DEFAULT 0x00
187+
188+#define CC1100_REG_FSTEST 0x29
189+#define CC1100_REG_FSTEST_DEFAULT 0x57
190+#define CC1100_REG_PTEST 0x2A
191+#define CC1100_REG_PTEST_DEFAULT 0x7F
192+#define CC1100_REG_AGCTEST 0x2B
193+#define CC1100_REG_AGCTEST_DEFAULT 0x3F
194+#define CC1100_REG_TEST2 0x2C
195+#define CC1100_REG_TEST2_DEFAULT 0x88
196+#define CC1100_REG_TEST1 0x2D
197+#define CC1100_REG_TEST1_DEFAULT 0x31
198+#define CC1100_REG_TEST0 0x2E
199+#define CC1100_REG_TEST0_DEFAULT 0x0B
200+
201+#define CC1100_REG_PARTNUM 0x30
202+#define CC1100_REG_PARTNUM_DEFAULT 0x00
203+#define CC1100_REG_VERSION 0x31
204+#define CC1100_REG_VERSION_DEFAULT 0x01
205+#define CC1100_REG_FREQEST 0x32
206+#define CC1100_REG_FREQEST_DEFAULT 0x00
207+#define CC1100_REG_LQI 0x33
208+#define CC1100_REG_LQI_DEFAULT 0x7F
209+#define CC1100_REG_RSSI 0x34
210+#define CC1100_REG_RSSI_DEFAULT 0x80
211+#define CC1100_REG_MARCSTATE 0x35
212+#define CC1100_REG_MARCSTATE_DEFAULT 0x01
213+#define CC1100_REG_WORTIME1 0x36
214+#define CC1100_REG_WORTIME1_DEFAULT 0x00
215+#define CC1100_REG_WORTIME0 0x37
216+#define CC1100_REG_WORTIME0_DEFAULT 0x00
217+#define CC1100_REG_PKTSTATUS 0x38
218+#define CC1100_REG_PKTSTATUS_DEFAULT 0x00
219+#define CC1100_REG_VCO_VC_DAC 0x39
220+#define CC1100_REG_VCO_VC_DAC_DEFAULT 0x94
221+#define CC1100_REG_TXBYTES 0x3A
222+#define CC1100_REG_TXBYTES_DEFAULT 0x00
223+#define CC1100_REG_RXBYTES 0x3B
224+#define CC1100_REG_RXBYTES_DEFAULT 0x00
225+
226+
227+#define CC1100_PATABLE_ADDR 0x3E
228+#define CC1100_DATA_FIFO_ADDR 0x3F
229+
230+#define CC1100_GDOx_RX_FIFO 0x00 /* assert above threshold, deassert when below */
231+#define CC1100_GDOx_RX_FIFO_EOP 0x01 /* assert above threshold or EOP */
232+#define CC1100_GDOx_TX_FIFO 0x02 /* assert above threshold, deassert below thr */
233+#define CC1100_GDOx_TX_THR_FULL 0x03 /* asserts when TX FIFO is full. De-asserts when */
234+ /* the TX FIFO is drained below TXFIFO_THR. */
235+#define CC1100_GDOx_RX_OVER 0x04 /* asserts when RX overflow, deassert when flushed */
236+#define CC1100_GDOx_TX_UNDER 0x05 /* asserts when RX underflow, deassert when flushed */
237+#define CC1100_GDOx_SYNC_WORD 0x06 /* assert SYNC sent/recv, deasserts on EOP */
238+ /* In RX, de-assert on overflow or bad address */
239+ /* In TX, de-assert on underflow */
240+#define CC1100_GDOx_RX_OK 0x07 /* assert when RX PKT with CRC ok, de-assert on 1byte */
241+ /* read from RX Fifo */
242+#define CC1100_GDOx_PREAMB_OK 0x08 /* assert when preamble quality reached : PQI/PQT ok */
243+#define CC1100_GDOx_CCA 0x09 /* Clear channel assessment. High when RSSI level is */
244+ /* below threshold (dependent on the current CCA_MODE) */
245+
246+#define CC1100_GDOx_CHIP_RDY 0x29 /* CHIP_RDY */
247+
248+#define CC1100_GDOx_XOSC_STABLE 0x2B /* XOSC_STABLE */
249+
250+#define CC1100_GDOx_CLK_XOSC_1 0x30 /* CLK_XOSC/1 */
251+#define CC1100_GDOx_CLK_XOSC_1p5 0x31 /* CLK_XOSC/1.5 */
252+#define CC1100_GDOx_CLK_XOSC_2 0x32 /* CLK_XOSC/2 */
253+#define CC1100_GDOx_CLK_XOSC_3 0x33 /* CLK_XOSC/3 */
254+#define CC1100_GDOx_CLK_XOSC_4 0x34 /* CLK_XOSC/4 */
255+#define CC1100_GDOx_CLK_XOSC_6 0x35 /* CLK_XOSC/6 */
256+#define CC1100_GDOx_CLK_XOSC_8 0x36 /* CLK_XOSC/8 */
257+#define CC1100_GDOx_CLK_XOSC_12 0x37 /* CLK_XOSC/12 */
258+#define CC1100_GDOx_CLK_XOSC_16 0x38 /* CLK_XOSC/16 */
259+#define CC1100_GDOx_CLK_XOSC_24 0x39 /* CLK_XOSC/24 */
260+#define CC1100_GDOx_CLK_XOSC_32 0x3A /* CLK_XOSC/32 */
261+#define CC1100_GDOx_CLK_XOSC_48 0x3B /* CLK_XOSC/48 */
262+#define CC1100_GDOx_CLK_XOSC_64 0x3C /* CLK_XOSC/64 */
263+#define CC1100_GDOx_CLK_XOSC_96 0x3D /* CLK_XOSC/96 */
264+#define CC1100_GDOx_CLK_XOSC_128 0x3E /* CLK_XOSC/128 */
265+#define CC1100_GDOx_CLK_XOSC_192 0x3F /* CLK_XOSC/192 */
266+
267+#endif
268+
--- trunk/CC1101_AT/CC1101_source_ATmega88/cc1100_gdo.h (nonexistent)
+++ trunk/CC1101_AT/CC1101_source_ATmega88/cc1100_gdo.h (revision 2602)
@@ -0,0 +1,245 @@
1+/*
2+ * Copyright 2008-2009 INRIA/SensTools
3+ *
4+ * <dev-team@sentools.info>
5+ *
6+ * This software is a set of libraries designed to develop applications
7+ * for the WSN430 embedded hardware platform.
8+ *
9+ * This software is governed by the CeCILL license under French law and
10+ * abiding by the rules of distribution of free software. You can use,
11+ * modify and/ or redistribute the software under the terms of the CeCILL
12+ * license as circulated by CEA, CNRS and INRIA at the following URL
13+ * "http://www.cecill.info".
14+ *
15+ * As a counterpart to the access to the source code and rights to copy,
16+ * modify and redistribute granted by the license, users are provided only
17+ * with a limited warranty and the software&apos;s author, the holder of the
18+ * economic rights, and the successive licensors have only limited
19+ * liability.
20+ *
21+ * In this respect, the user&apos;s attention is drawn to the risks associated
22+ * with loading, using, modifying and/or developing or reproducing the
23+ * software by the user in light of its specific status of free software,
24+ * that may mean that it is complicated to manipulate, and that also
25+ * therefore means that it is reserved for developers and experienced
26+ * professionals having in-depth computer knowledge. Users are therefore
27+ * encouraged to load and test the software&apos;s suitability as regards their
28+ * requirements in conditions enabling the security of their systems and/or
29+ * data to be ensured and, more generally, to use and operate it in the
30+ * same conditions as regards security.
31+ *
32+ * The fact that you are presently reading this means that you have had
33+ * knowledge of the CeCILL license and that you accept its terms.
34+ */
35+
36+
37+
38+#ifndef _CC1100_GDO_H
39+#define _CC1100_GDO_H
40+
41+
42+#include "macro.h"
43+
44+
45+#define GDO0_PIN (1<<2)
46+#define GDO2_PIN (1<<3)
47+
48+enum {
49+ LOW_EDGE=0,
50+ HIGH_EDGE
51+};
52+
53+
54+
55+/*
56+
57+#define GDO_INIT() do \
58+{ \
59+ PCSEL &= ~(GDO0_PIN | GDO2_PIN); \
60+ PCDDR &= ~(GDO0_PIN | GDO2_PIN); \
61+ P1IE &= ~(GDO0_PIN | GDO2_PIN); \
62+} while (0)
63+
64+*/
65+
66+
67+/*
68+#define GDO_INIT() do \
69+{ \
70+ PINC &= ~(GDO0_PIN | GDO2_PIN); \
71+ DDRC &= ~(GDO0_PIN | GDO2_PIN); \
72+ PCMSK1 |= (1<<PCINT10); \
73+ PCMSK1 |= (1<<PCINT11); \
74+} while (0)
75+*/
76+
77+
78+
79+#define GDO_INIT() do \
80+{ \
81+ DDRC &= ~(GDO0_PIN | GDO2_PIN); \
82+ PCMSK1 |= (1<<PCINT10); \
83+ PCMSK1 |= (1<<PCINT11); \
84+} while (0)
85+
86+
87+
88+
89+//#define GDO0_INT_ENABLE() P1IE |= GDO0_PIN
90+
91+#define GDO0_INT_ENABLE() PCMSK1 |= (1<<PCINT10)
92+
93+//#define GDO2_INT_ENABLE() P1IE |= GDO2_PIN
94+
95+#define GDO2_INT_ENABLE() PCMSK1 |= (1<<PCINT11)
96+
97+//#define GDO0_INT_DISABLE() P1IE &= ~GDO0_PIN
98+
99+#define GDO0_INT_DISABLE() PCMSK1 &= ~(1<<PCINT10)
100+
101+//#define GDO2_INT_DISABLE() P1IE &= ~GDO2_PIN
102+
103+#define GDO2_INT_DISABLE() PCMSK1 &= ~(1<<PCINT11)
104+
105+
106+
107+
108+//#define GDO0_INT_CLEAR() PCIFR &= ~(1<<PCIF1)
109+#define GDO0_INT_CLEAR() PCIFR |= (1<<PCIF1)
110+
111+//#define GDO2_INT_CLEAR() PCIFR &= ~(1<<PCIF1)
112+#define GDO2_INT_CLEAR() PCIFR |= (1<<PCIF1)
113+
114+
115+
116+#if 0
117+
118+//#define GDO0_INT_SET_RISING() P1IES &= ~GDO0_PIN
119+#define GDO0_INT_SET_RISING() edge_val_gdo0 = HIGH_EDGE
120+
121+//#define GDO0_INT_SET_FALLING() P1IES |= GDO0_PIN
122+#define GDO0_INT_SET_FALLING() edge_val_gdo0 = LOW_EDGE
123+
124+//#define GDO2_INT_SET_RISING() P1IES &= ~GDO2_PIN
125+#define GDO2_INT_SET_RISING() edge_val_gdo2 = HIGH_EDGE
126+
127+//#define GDO2_INT_SET_FALLING() P1IES |= GDO2_PIN
128+#define GDO2_INT_SET_FALLING() edge_val_gdo2 = LOW_EDGE
129+
130+//#define GDO0_READ() (P1IN & GDO0_PIN)
131+#define GDO0_READ() (PINC & 0x04)
132+
133+//#define GDO2_READ() (P1IN & GDO2_PIN)
134+#define GDO2_READ() (PINC & 0x08)
135+
136+#endif
137+
138+
139+
140+
141+
142+
143+
144+
145+
146+
147+
148+
149+#define SENSOR_INT1_PIN (1<<3)
150+
151+
152+#define SENSOR_INIT() do \
153+{ \
154+ DDRD &= ~(SENSOR_INT1_PIN); \
155+ EIMSK |= (1<<INT1); \
156+} while (0)
157+
158+
159+#define SENSOR_INT1_ENABLE() EIMSK |= (1<<INT1)
160+#define SENSOR_INT1_DISABLE() EIMSK &= ~(1<<INT1)
161+
162+
163+
164+
165+#define RTC_INT0_PIN (1<<2)
166+
167+#define RTC_INIT() do \
168+{ \
169+ DDRD &= ~(RTC_INT0_PIN); \
170+ EIMSK |= (1<<INT0); \
171+} while (0)
172+
173+
174+#define RTC_INT0_ENABLE() EIMSK |= (1<<INT0)
175+#define RTC_INT0_DISABLE() EIMSK &= ~(1<<INT0)
176+
177+
178+
179+
180+
181+
182+#define RTC_INT0_CLEAR() EIFR &= ~(1<<INTF0)
183+#define SENSOR_INT1_CLEAR() EIFR &= ~(1<<INTF1)
184+
185+
186+#define rtc_int0_int_clear() \
187+ RTC_INT0_CLEAR()
188+
189+#define sensor_int1_int_clear() \
190+ SENSOR_INT1_CLEAR()
191+
192+
193+#define RTC_INT0_SET_RISING() do \
194+{ \
195+ EICRA &= ~(1<<ISC00); \
196+ EICRA |= (1<<ISC01); \
197+} while(0)
198+
199+
200+#define RTC_INT0_SET_FALLING() do \
201+{ \
202+ EICRA |= (1<<ISC00); \
203+ EICRA |= (1<<ISC01); \
204+} while(0)
205+
206+
207+#define SENSOR_INT1_SET_RISING() do \
208+{ \
209+ EICRA &= ~(1<<ISC10); \
210+ EICRA |= (1<<ISC11); \
211+} while(0)
212+
213+
214+#define SENSOR_INT1_SET_FALLING() do \
215+{ \
216+ EICRA |= (1<<ISC10); \
217+ EICRA |= (1<<ISC11); \
218+} while(0)
219+
220+
221+#define rtc_int0_int_set_rising_edge() \
222+ RTC_INT0_SET_RISING()
223+
224+#define rtc_int0_int_set_falling_edge() \
225+ RTC_INT0_SET_RISING()
226+
227+
228+
229+#define sensor_int1_int_set_rising_edge() \
230+ SENSOR_INT1_SET_RISING()
231+
232+
233+#define sensor_int1_int_set_falling_edge() \
234+ SENSOR_INT1_SET_FALLING()
235+
236+
237+
238+
239+
240+
241+#endif
242+
243+
244+
245+
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