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chibios: Commit


Commit MetaInfo

Revision14014 (tree)
Time2021-01-06 17:38:25
Authorgdisirio

Log Message

Updates to STM32WBxx port.

Change Summary

Incremental Difference

--- trunk/os/common/ext/ST/STM32WBxx/stm32wb50xx.h (revision 14013)
+++ trunk/os/common/ext/ST/STM32WBxx/stm32wb50xx.h (revision 14014)
@@ -46,12 +46,12 @@
4646 /**
4747 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
4848 */
49-#define __CM4_REV 1 /*!< Core Revision r0p1 */
50-#define __MPU_PRESENT 1 /*!< M4 provides an MPU */
51-#define __VTOR_PRESENT 1 /*!< Vector Table Register supported */
52-#define __NVIC_PRIO_BITS 4 /*!< STM32WBxx uses 4 Bits for the Priority Levels */
53-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
54-#define __FPU_PRESENT 1 /*!< FPU present */
49+#define __CM4_REV 1U /*!< Core Revision r0p1 */
50+#define __MPU_PRESENT 1U /*!< M4 provides an MPU */
51+#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */
52+#define __NVIC_PRIO_BITS 4U /*!< STM32WBxx uses 4 Bits for the Priority Levels */
53+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
54+#define __FPU_PRESENT 1U /*!< FPU present */
5555 /**
5656 * @}
5757 */
@@ -354,7 +354,6 @@
354354 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
355355 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
356356 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
357- __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
358357 } LPTIM_TypeDef;
359358
360359 /**
@@ -386,7 +385,7 @@
386385 __IO uint32_t C2CR1; /*!< PWR Power Control Register 1 for CPU2, Address offset: 0x80 */
387386 __IO uint32_t C2CR3; /*!< PWR Power Control Register 3 for CPU2, Address offset: 0x84 */
388387 __IO uint32_t EXTSCR; /*!< PWR Power Status Reset Register for CPU2, Address offset: 0x88 */
389-} PWR_TypeDef;
388+} PWR_TypeDef;
390389
391390 /**
392391 * @brief Reset and Clock Control
@@ -393,65 +392,64 @@
393392 */
394393 typedef struct
395394 {
396- __IO uint32_t CR; /*!< RCC clock Control Register, Address offset: 0x00 */
397- __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */
398- __IO uint32_t CFGR; /*!< RCC Clocks Configuration Register, Address offset: 0x08 */
399- __IO uint32_t PLLCFGR; /*!< RCC System PLL configuration Register, Address offset: 0x0C */
400-uint32_t RESERVED11; /*!< Reserved, Address offset: 0x10 */
401-uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */
402- __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */
403- __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */
404- __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */
405-uint32_t RESERVED12; /*!< Reserved, Address offset: 0x24 */
406- __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */
407- __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */
408- __IO uint32_t AHB3RSTR; /*!< RCC AHB3 & AHB4 peripheral reset register, Address offset: 0x30 */
409-uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */
410- __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */
411- __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */
412- __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */
413- __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x44 */
414- __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */
415- __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */
416- __IO uint32_t AHB3ENR; /*!< RCC AHB3 & AHB4 peripheral clocks enable register, Address offset: 0x50 */
417-uint32_t RESERVED2; /*!< Reserved, Address offset: 0x54 */
418- __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */
419- __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */
420- __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */
421-uint32_t RESERVED3; /*!< Reserved, Address offset: 0x64 */
422- __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */
423- __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */
424- __IO uint32_t AHB3SMENR; /*!< RCC AHB3 & AHB4 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */
425-uint32_t RESERVED4; /*!< Reserved, Address offset: 0x74 */
426- __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
427- __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
428- __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
429-uint32_t RESERVED5; /*!< Reserved, Address offset: 0x84 */
430- __IO uint32_t CCIPR; /*!< RCC Peripherals Clock Configuration Independent Register, Address offset: 0x88 */
431-uint32_t RESERVED6; /*!< Reserved, Address offset: 0x8C */
432- __IO uint32_t BDCR; /*!< RCC Backup Domain Control Register, Address offset: 0x90 */
433- __IO uint32_t CSR; /*!< RCC Control and Status Register, Address offset: 0x94 */
434- __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register, Address offset: 0x98 */
435- __IO uint32_t HSECR; /*!< RCC HSE Clock Register, Address offset: 0x9C */
436-uint32_t RESERVED7[26]; /*!< Reserved, Address offset: 0xA0-0x104 */
437- __IO uint32_t EXTCFGR; /*!< RCC Extended Clock Recovery Register, Address offset: 0x108 */
438- __IO uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */
439- __IO uint32_t C2AHB1ENR; /*!< RRCC AHB1 peripheral CPU2 clocks enable register, Address offset: 0x148 */
440- __IO uint32_t C2AHB2ENR; /*!< RCC AHB2 peripheral CPU2 clocks enable register, Address offset: 0x14C */
441- __IO uint32_t C2AHB3ENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable register,, Address offset: 0x150 */
442-uint32_t RESERVED9; /*!< Reserved, Address offset: 0x154 */
443- __IO uint32_t C2APB1ENR1; /*!< RCC APB1 peripheral CPU2 clocks enable register 1, Address offset: 0x158 */
444- __IO uint32_t C2APB1ENR2; /*!< RCC APB1 peripheral CPU2 clocks enable register 2, Address offset: 0x15C */
445- __IO uint32_t C2APB2ENR; /*!< RCC APB2 peripheral CPU2 clocks enable register 1, Address offset: 0x160 */
446- __IO uint32_t C2APB3ENR; /*!< RCC APB3 peripheral CPU2 clocks enable register 1, Address offset: 0x164 */
447- __IO uint32_t C2AHB1SMENR; /*!< RCC AHB1 peripheral CPU2 clocks enable in sleep and stop modes register, Address offset: 0x168 */
448- __IO uint32_t C2AHB2SMENR; /*!< RCC AHB2 peripheral CPU2 clocks enable in sleep and stop modes register, Address offset: 0x16C */
449- __IO uint32_t C2AHB3SMENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable in sleep and stop modes register, Address offset: 0x170 */
450-uint32_t RESERVED10; /*!< Reserved, */
451- __IO uint32_t C2APB1SMENR1;/*!< RCC APB1 peripheral CPU2 clocks enable in sleep mode and stop modes register 1, Address offset: 0x178 */
452- __IO uint32_t C2APB1SMENR2;/*!< RCC APB1 peripheral CPU2 clocks enable in sleep mode and stop modes register 2, Address offset: 0x17C */
453- __IO uint32_t C2APB2SMENR; /*!< RCC APB2 peripheral CPU2 clocks enable in sleep mode and stop modes register, Address offset: 0x180 */
454- __IO uint32_t C2APB3SMENR; /*!< RCC APB3 peripheral CPU2 clocks enable in sleep mode and stop modes register, Address offset: 0x184 */
395+ __IO uint32_t CR; /*!< RCC clock Control Register, Address offset: 0x00 */
396+ __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */
397+ __IO uint32_t CFGR; /*!< RCC Clocks Configuration Register, Address offset: 0x08 */
398+ __IO uint32_t PLLCFGR; /*!< RCC System PLL configuration Register, Address offset: 0x0C */
399+uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x10-0x14 */
400+ __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */
401+ __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */
402+ __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */
403+uint32_t RESERVED11; /*!< Reserved, Address offset: 0x24 */
404+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */
405+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */
406+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 & AHB4 peripheral reset register, Address offset: 0x30 */
407+uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */
408+ __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */
409+ __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */
410+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */
411+ __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x44 */
412+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */
413+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */
414+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 & AHB4 peripheral clocks enable register, Address offset: 0x50 */
415+uint32_t RESERVED2; /*!< Reserved, Address offset: 0x54 */
416+ __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */
417+ __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */
418+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */
419+uint32_t RESERVED3; /*!< Reserved, Address offset: 0x64 */
420+ __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */
421+ __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */
422+ __IO uint32_t AHB3SMENR; /*!< RCC AHB3 & AHB4 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */
423+uint32_t RESERVED4; /*!< Reserved, Address offset: 0x74 */
424+ __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
425+ __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
426+ __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
427+uint32_t RESERVED5; /*!< Reserved, Address offset: 0x84 */
428+ __IO uint32_t CCIPR; /*!< RCC Peripherals Clock Configuration Independent Register, Address offset: 0x88 */
429+uint32_t RESERVED6; /*!< Reserved, Address offset: 0x8C */
430+ __IO uint32_t BDCR; /*!< RCC Backup Domain Control Register, Address offset: 0x90 */
431+ __IO uint32_t CSR; /*!< RCC Control and Status Register, Address offset: 0x94 */
432+ __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register, Address offset: 0x98 */
433+ __IO uint32_t HSECR; /*!< RCC HSE Clock Register, Address offset: 0x9C */
434+uint32_t RESERVED7[26]; /*!< Reserved, Address offset: 0xA0-0x104 */
435+ __IO uint32_t EXTCFGR; /*!< RCC Extended Clock Recovery Register, Address offset: 0x108 */
436+uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */
437+ __IO uint32_t C2AHB1ENR; /*!< RRCC AHB1 peripheral CPU2 clocks enable register, Address offset: 0x148 */
438+ __IO uint32_t C2AHB2ENR; /*!< RCC AHB2 peripheral CPU2 clocks enable register, Address offset: 0x14C */
439+ __IO uint32_t C2AHB3ENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable register,, Address offset: 0x150 */
440+uint32_t RESERVED9; /*!< Reserved, Address offset: 0x154 */
441+ __IO uint32_t C2APB1ENR1; /*!< RCC APB1 peripheral CPU2 clocks enable register 1, Address offset: 0x158 */
442+ __IO uint32_t C2APB1ENR2; /*!< RCC APB1 peripheral CPU2 clocks enable register 2, Address offset: 0x15C */
443+ __IO uint32_t C2APB2ENR; /*!< RCC APB2 peripheral CPU2 clocks enable register 1, Address offset: 0x160 */
444+ __IO uint32_t C2APB3ENR; /*!< RCC APB3 peripheral CPU2 clocks enable register 1, Address offset: 0x164 */
445+ __IO uint32_t C2AHB1SMENR; /*!< RCC AHB1 peripheral CPU2 clocks enable in sleep and stop modes register, Address offset: 0x168 */
446+ __IO uint32_t C2AHB2SMENR; /*!< RCC AHB2 peripheral CPU2 clocks enable in sleep and stop modes register, Address offset: 0x16C */
447+ __IO uint32_t C2AHB3SMENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable in sleep and stop modes register, Address offset: 0x170 */
448+uint32_t RESERVED10; /*!< Reserved, */
449+ __IO uint32_t C2APB1SMENR1; /*!< RCC APB1 peripheral CPU2 clocks enable in sleep mode and stop modes register 1, Address offset: 0x178 */
450+ __IO uint32_t C2APB1SMENR2; /*!< RCC APB1 peripheral CPU2 clocks enable in sleep mode and stop modes register 2, Address offset: 0x17C */
451+ __IO uint32_t C2APB2SMENR; /*!< RCC APB2 peripheral CPU2 clocks enable in sleep mode and stop modes register, Address offset: 0x180 */
452+ __IO uint32_t C2APB3SMENR; /*!< RCC APB3 peripheral CPU2 clocks enable in sleep mode and stop modes register, Address offset: 0x184 */
455453 } RCC_TypeDef;
456454
457455
@@ -543,15 +541,6 @@
543541 } SYSCFG_TypeDef;
544542
545543 /**
546- * @brief VREFBUF
547- */
548-typedef struct
549-{
550- __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
551- __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
552-} VREFBUF_TypeDef;
553-
554-/**
555544 * @brief TIM
556545 */
557546 typedef struct
@@ -810,7 +799,6 @@
810799
811800 /*!< APB2 peripherals */
812801 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000UL)
813-#define VREFBUF_BASE (APB2PERIPH_BASE + 0x00000030UL)
814802 #define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL)
815803 #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL)
816804 #define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL)
@@ -857,7 +845,6 @@
857845 #define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000UL)
858846 #define ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300UL)
859847
860-
861848 /*!< AHB Shared peripherals */
862849 #define RCC_BASE (AHB4PERIPH_BASE + 0x00000000UL)
863850 #define PWR_BASE (AHB4PERIPH_BASE + 0x00000400UL)
@@ -900,7 +887,6 @@
900887
901888 /* Peripherals available on APB2 bus */
902889 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
903-#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
904890 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
905891 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
906892 #define USART1 ((USART_TypeDef *) USART1_BASE)
@@ -985,6 +971,9 @@
985971 /* Analog to Digital Converter (ADC) */
986972 /* */
987973 /******************************************************************************/
974+
975+#define ADC_SUPPORT_5_MSPS /* ADC sampling rate 5 Msamples/sec */
976+
988977 /******************** Bit definition for ADC_ISR register *******************/
989978 #define ADC_ISR_ADRDY_Pos (0U)
990979 #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
@@ -2496,7 +2485,7 @@
24962485 /******************************************************************************/
24972486 /******************** Bits definition for DMAMUX_CxCR register **************/
24982487 #define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
2499-#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */
2488+#define DMAMUX_CxCR_DMAREQ_ID_Msk (0x3FUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x0000003F */
25002489 #define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk /*!< DMA Request ID */
25012490 #define DMAMUX_CxCR_DMAREQ_ID_0 (0x01U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */
25022491 #define DMAMUX_CxCR_DMAREQ_ID_1 (0x02U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */
@@ -2504,8 +2493,6 @@
25042493 #define DMAMUX_CxCR_DMAREQ_ID_3 (0x08U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */
25052494 #define DMAMUX_CxCR_DMAREQ_ID_4 (0x10U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */
25062495 #define DMAMUX_CxCR_DMAREQ_ID_5 (0x20U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */
2507-#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */
2508-#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */
25092496 #define DMAMUX_CxCR_SOIE_Pos (8U)
25102497 #define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */
25112498 #define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */
@@ -2559,27 +2546,6 @@
25592546 #define DMAMUX_CSR_SOF6_Pos (6U)
25602547 #define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos) /*!< 0x00000040 */
25612548 #define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk /*!< Synchronization Overrun Flag 6 */
2562-#define DMAMUX_CSR_SOF7_Pos (7U)
2563-#define DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos) /*!< 0x00000080 */
2564-#define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk /*!< Synchronization Overrun Flag 7 */
2565-#define DMAMUX_CSR_SOF8_Pos (8U)
2566-#define DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos) /*!< 0x00000100 */
2567-#define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk /*!< Synchronization Overrun Flag 8 */
2568-#define DMAMUX_CSR_SOF9_Pos (9U)
2569-#define DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos) /*!< 0x00000200 */
2570-#define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk /*!< Synchronization Overrun Flag 9 */
2571-#define DMAMUX_CSR_SOF10_Pos (10U)
2572-#define DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos) /*!< 0x00000400 */
2573-#define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk /*!< Synchronization Overrun Flag 10 */
2574-#define DMAMUX_CSR_SOF11_Pos (11U)
2575-#define DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos) /*!< 0x00000800 */
2576-#define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk /*!< Synchronization Overrun Flag 11 */
2577-#define DMAMUX_CSR_SOF12_Pos (12U)
2578-#define DMAMUX_CSR_SOF12_Msk (0x1UL << DMAMUX_CSR_SOF12_Pos) /*!< 0x00001000 */
2579-#define DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk /*!< Synchronization Overrun Flag 12 */
2580-#define DMAMUX_CSR_SOF13_Pos (13U)
2581-#define DMAMUX_CSR_SOF13_Msk (0x1UL << DMAMUX_CSR_SOF13_Pos) /*!< 0x00002000 */
2582-#define DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk /*!< Synchronization Overrun Flag 13 */
25832549
25842550 /******************** Bits definition for DMAMUX_CFR register **************/
25852551 #define DMAMUX_CFR_CSOF0_Pos (0U)
@@ -2603,27 +2569,6 @@
26032569 #define DMAMUX_CFR_CSOF6_Pos (6U)
26042570 #define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */
26052571 #define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk /*!< Clear Overrun Flag 6 */
2606-#define DMAMUX_CFR_CSOF7_Pos (7U)
2607-#define DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos) /*!< 0x00000080 */
2608-#define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk /*!< Clear Overrun Flag 7 */
2609-#define DMAMUX_CFR_CSOF8_Pos (8U)
2610-#define DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos) /*!< 0x00000100 */
2611-#define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk /*!< Clear Overrun Flag 8 */
2612-#define DMAMUX_CFR_CSOF9_Pos (9U)
2613-#define DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos) /*!< 0x00000200 */
2614-#define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk /*!< Clear Overrun Flag 9 */
2615-#define DMAMUX_CFR_CSOF10_Pos (10U)
2616-#define DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos) /*!< 0x00000400 */
2617-#define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk /*!< Clear Overrun Flag 10 */
2618-#define DMAMUX_CFR_CSOF11_Pos (11U)
2619-#define DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos) /*!< 0x00000800 */
2620-#define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk /*!< Clear Overrun Flag 11 */
2621-#define DMAMUX_CFR_CSOF12_Pos (12U)
2622-#define DMAMUX_CFR_CSOF12_Msk (0x1UL << DMAMUX_CFR_CSOF12_Pos) /*!< 0x00001000 */
2623-#define DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk /*!< Clear Overrun Flag 12 */
2624-#define DMAMUX_CFR_CSOF13_Pos (13U)
2625-#define DMAMUX_CFR_CSOF13_Msk (0x1UL << DMAMUX_CFR_CSOF13_Pos) /*!< 0x00002000 */
2626-#define DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk /*!< Clear Overrun Flag 13 */
26272572
26282573 /******************** Bits definition for DMAMUX_RGxCR register ************/
26292574 #define DMAMUX_RGxCR_SIG_ID_Pos (0U)
@@ -2752,15 +2697,6 @@
27522697 #define EXTI_RTSR1_RT19_Pos (19U)
27532698 #define EXTI_RTSR1_RT19_Msk (0x1UL << EXTI_RTSR1_RT19_Pos) /*!< 0x00080000 */
27542699 #define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
2755-#define EXTI_RTSR1_RT20_Pos (20U)
2756-#define EXTI_RTSR1_RT20_Msk (0x1UL << EXTI_RTSR1_RT20_Pos) /*!< 0x00100000 */
2757-#define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
2758-#define EXTI_RTSR1_RT21_Pos (21U)
2759-#define EXTI_RTSR1_RT21_Msk (0x1UL << EXTI_RTSR1_RT21_Pos) /*!< 0x00200000 */
2760-#define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
2761-#define EXTI_RTSR1_RT31_Pos (31U)
2762-#define EXTI_RTSR1_RT31_Msk (0x1UL << EXTI_RTSR1_RT31_Pos) /*!< 0x80000000 */
2763-#define EXTI_RTSR1_RT31 EXTI_RTSR1_RT31_Msk /*!< Rising trigger event configuration bit of line 31 */
27642700
27652701 /****************** Bit definition for EXTI_FTSR1 register ******************/
27662702 #define EXTI_FTSR1_FT_Pos (0U)
@@ -2826,15 +2762,6 @@
28262762 #define EXTI_FTSR1_FT19_Pos (19U)
28272763 #define EXTI_FTSR1_FT19_Msk (0x1UL << EXTI_FTSR1_FT19_Pos) /*!< 0x00080000 */
28282764 #define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
2829-#define EXTI_FTSR1_FT20_Pos (20U)
2830-#define EXTI_FTSR1_FT20_Msk (0x1UL << EXTI_FTSR1_FT20_Pos) /*!< 0x00100000 */
2831-#define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
2832-#define EXTI_FTSR1_FT21_Pos (21U)
2833-#define EXTI_FTSR1_FT21_Msk (0x1UL << EXTI_FTSR1_FT21_Pos) /*!< 0x00200000 */
2834-#define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
2835-#define EXTI_FTSR1_FT31_Pos (31U)
2836-#define EXTI_FTSR1_FT31_Msk (0x1UL << EXTI_FTSR1_FT31_Pos) /*!< 0x80000000 */
2837-#define EXTI_FTSR1_FT31 EXTI_FTSR1_FT31_Msk /*!< Falling trigger event configuration bit of line 31 */
28382765
28392766 /****************** Bit definition for EXTI_SWIER1 register *****************/
28402767 #define EXTI_SWIER1_SWI_Pos (0U)
@@ -2900,15 +2827,6 @@
29002827 #define EXTI_SWIER1_SWI19_Pos (19U)
29012828 #define EXTI_SWIER1_SWI19_Msk (0x1UL << EXTI_SWIER1_SWI19_Pos) /*!< 0x00080000 */
29022829 #define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk /*!< Software Interrupt on line 19 */
2903-#define EXTI_SWIER1_SWI20_Pos (20U)
2904-#define EXTI_SWIER1_SWI20_Msk (0x1UL << EXTI_SWIER1_SWI20_Pos) /*!< 0x00100000 */
2905-#define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk /*!< Software Interrupt on line 20 */
2906-#define EXTI_SWIER1_SWI21_Pos (21U)
2907-#define EXTI_SWIER1_SWI21_Msk (0x1UL << EXTI_SWIER1_SWI21_Pos) /*!< 0x00200000 */
2908-#define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk /*!< Software Interrupt on line 21 */
2909-#define EXTI_SWIER1_SWI31_Pos (31U)
2910-#define EXTI_SWIER1_SWI31_Msk (0x1UL << EXTI_SWIER1_SWI31_Pos) /*!< 0x80000000 */
2911-#define EXTI_SWIER1_SWI31 EXTI_SWIER1_SWI31_Msk /*!< Software Interrupt on line 31 */
29122830
29132831 /******************* Bit definition for EXTI_PR1 register *******************/
29142832 #define EXTI_PR1_PIF_Pos (0U)
@@ -2974,15 +2892,6 @@
29742892 #define EXTI_PR1_PIF19_Pos (19U)
29752893 #define EXTI_PR1_PIF19_Msk (0x1UL << EXTI_PR1_PIF19_Pos) /*!< 0x00080000 */
29762894 #define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk /*!< Pending bit for line 19 */
2977-#define EXTI_PR1_PIF20_Pos (20U)
2978-#define EXTI_PR1_PIF20_Msk (0x1UL << EXTI_PR1_PIF20_Pos) /*!< 0x00100000 */
2979-#define EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk /*!< Pending bit for line 20 */
2980-#define EXTI_PR1_PIF21_Pos (21U)
2981-#define EXTI_PR1_PIF21_Msk (0x1UL << EXTI_PR1_PIF21_Pos) /*!< 0x00200000 */
2982-#define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk /*!< Pending bit for line 21 */
2983-#define EXTI_PR1_PIF31_Pos (31U)
2984-#define EXTI_PR1_PIF31_Msk (0x1UL << EXTI_PR1_PIF31_Pos) /*!< 0x80000000 */
2985-#define EXTI_PR1_PIF31 EXTI_PR1_PIF31_Msk /*!< Pending bit for line 31 */
29862895
29872896 /****************** Bit definition for EXTI_RTSR2 register ******************/
29882897 #define EXTI_RTSR2_RT_Pos (0U)
@@ -3104,27 +3013,12 @@
31043013 #define EXTI_IMR1_IM19_Pos (19U)
31053014 #define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
31063015 #define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< CPU1 Interrupt Mask on line 19 */
3107-#define EXTI_IMR1_IM20_Pos (20U)
3108-#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
3109-#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< CPU1 Interrupt Mask on line 20 */
3110-#define EXTI_IMR1_IM21_Pos (21U)
3111-#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
3112-#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< CPU1 Interrupt Mask on line 21 */
31133016 #define EXTI_IMR1_IM22_Pos (22U)
31143017 #define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
31153018 #define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< CPU1 Interrupt Mask on line 22 */
3116-#define EXTI_IMR1_IM23_Pos (23U)
3117-#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
3118-#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< CPU1 Interrupt Mask on line 23 */
31193019 #define EXTI_IMR1_IM24_Pos (24U)
31203020 #define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
31213021 #define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< CPU1 Interrupt Mask on line 24 */
3122-#define EXTI_IMR1_IM25_Pos (25U)
3123-#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
3124-#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< CPU1 Interrupt Mask on line 25 */
3125-#define EXTI_IMR1_IM28_Pos (28U)
3126-#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
3127-#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< CPU1 Interrupt Mask on line 28 */
31283022 #define EXTI_IMR1_IM29_Pos (29U)
31293023 #define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */
31303024 #define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< CPU1 Interrupt Mask on line 29 */
@@ -3131,9 +3025,6 @@
31313025 #define EXTI_IMR1_IM30_Pos (30U)
31323026 #define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */
31333027 #define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< CPU1 Interrupt Mask on line 30 */
3134-#define EXTI_IMR1_IM31_Pos (31U)
3135-#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */
3136-#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< CPU1 Interrupt Mask on line 31 */
31373028
31383029 /******************** Bits definition for EXTI_EMR1 register ****************/
31393030 #define EXTI_EMR1_Pos (0U)
@@ -3196,12 +3087,6 @@
31963087 #define EXTI_EMR1_EM19_Pos (19U)
31973088 #define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */
31983089 #define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< CPU1 Event Mask on line 19 */
3199-#define EXTI_EMR1_EM20_Pos (20U)
3200-#define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */
3201-#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< CPU1 Event Mask on line 20 */
3202-#define EXTI_EMR1_EM21_Pos (21U)
3203-#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
3204-#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< CPU1 Event Mask on line 21 */
32053090
32063091 /******************** Bits definition for EXTI_IMR2 register ****************/
32073092 #define EXTI_IMR2_Pos (0U)
@@ -3319,27 +3204,12 @@
33193204 #define EXTI_C2IMR1_IM19_Pos (19U)
33203205 #define EXTI_C2IMR1_IM19_Msk (0x1UL << EXTI_C2IMR1_IM19_Pos) /*!< 0x00080000 */
33213206 #define EXTI_C2IMR1_IM19 EXTI_C2IMR1_IM19_Msk /*!< CPU2 Interrupt Mask on line 19 */
3322-#define EXTI_C2IMR1_IM20_Pos (20U)
3323-#define EXTI_C2IMR1_IM20_Msk (0x1UL << EXTI_C2IMR1_IM20_Pos) /*!< 0x00100000 */
3324-#define EXTI_C2IMR1_IM20 EXTI_C2IMR1_IM20_Msk /*!< CPU2 Interrupt Mask on line 20 */
3325-#define EXTI_C2IMR1_IM21_Pos (21U)
3326-#define EXTI_C2IMR1_IM21_Msk (0x1UL << EXTI_C2IMR1_IM21_Pos) /*!< 0x00200000 */
3327-#define EXTI_C2IMR1_IM21 EXTI_C2IMR1_IM21_Msk /*!< CPU2 Interrupt Mask on line 21 */
33283207 #define EXTI_C2IMR1_IM22_Pos (22U)
33293208 #define EXTI_C2IMR1_IM22_Msk (0x1UL << EXTI_C2IMR1_IM22_Pos) /*!< 0x00400000 */
33303209 #define EXTI_C2IMR1_IM22 EXTI_C2IMR1_IM22_Msk /*!< CPU2 Interrupt Mask on line 22 */
3331-#define EXTI_C2IMR1_IM23_Pos (23U)
3332-#define EXTI_C2IMR1_IM23_Msk (0x1UL << EXTI_C2IMR1_IM23_Pos) /*!< 0x00800000 */
3333-#define EXTI_C2IMR1_IM23 EXTI_C2IMR1_IM23_Msk /*!< CPU2 Interrupt Mask on line 23 */
33343210 #define EXTI_C2IMR1_IM24_Pos (24U)
33353211 #define EXTI_C2IMR1_IM24_Msk (0x1UL << EXTI_C2IMR1_IM24_Pos) /*!< 0x01000000 */
33363212 #define EXTI_C2IMR1_IM24 EXTI_C2IMR1_IM24_Msk /*!< CPU2 Interrupt Mask on line 24 */
3337-#define EXTI_C2IMR1_IM25_Pos (25U)
3338-#define EXTI_C2IMR1_IM25_Msk (0x1UL << EXTI_C2IMR1_IM25_Pos) /*!< 0x02000000 */
3339-#define EXTI_C2IMR1_IM25 EXTI_C2IMR1_IM25_Msk /*!< CPU2 Interrupt Mask on line 25 */
3340-#define EXTI_C2IMR1_IM28_Pos (28U)
3341-#define EXTI_C2IMR1_IM28_Msk (0x1UL << EXTI_C2IMR1_IM28_Pos) /*!< 0x10000000 */
3342-#define EXTI_C2IMR1_IM28 EXTI_C2IMR1_IM28_Msk /*!< CPU2 Interrupt Mask on line 28 */
33433213 #define EXTI_C2IMR1_IM29_Pos (29U)
33443214 #define EXTI_C2IMR1_IM29_Msk (0x1UL << EXTI_C2IMR1_IM29_Pos) /*!< 0x20000000 */
33453215 #define EXTI_C2IMR1_IM29 EXTI_C2IMR1_IM29_Msk /*!< CPU2 Interrupt Mask on line 29 */
@@ -3346,9 +3216,6 @@
33463216 #define EXTI_C2IMR1_IM30_Pos (30U)
33473217 #define EXTI_C2IMR1_IM30_Msk (0x1UL << EXTI_C2IMR1_IM30_Pos) /*!< 0x40000000 */
33483218 #define EXTI_C2IMR1_IM30 EXTI_C2IMR1_IM30_Msk /*!< CPU2 Interrupt Mask on line 30 */
3349-#define EXTI_C2IMR1_IM31_Pos (31U)
3350-#define EXTI_C2IMR1_IM31_Msk (0x1UL << EXTI_C2IMR1_IM31_Pos) /*!< 0x80000000 */
3351-#define EXTI_C2IMR1_IM31 EXTI_C2IMR1_IM31_Msk /*!< CPU2 Interrupt Mask on line 31 */
33523219
33533220 /******************** Bits definition for EXTI_C2EMR1 register **************/
33543221 #define EXTI_C2EMR1_Pos (0U)
@@ -3411,12 +3278,6 @@
34113278 #define EXTI_C2EMR1_EM19_Pos (19U)
34123279 #define EXTI_C2EMR1_EM19_Msk (0x1UL << EXTI_C2EMR1_EM19_Pos) /*!< 0x00080000 */
34133280 #define EXTI_C2EMR1_EM19 EXTI_C2EMR1_EM19_Msk /*!< CPU2 Event Mask on line 19 */
3414-#define EXTI_C2EMR1_EM20_Pos (20U)
3415-#define EXTI_C2EMR1_EM20_Msk (0x1UL << EXTI_C2EMR1_EM20_Pos) /*!< 0x00100000 */
3416-#define EXTI_C2EMR1_EM20 EXTI_C2EMR1_EM20_Msk /*!< CPU2 Event Mask on line 20 */
3417-#define EXTI_C2EMR1_EM21_Pos (21U)
3418-#define EXTI_C2EMR1_EM21_Msk (0x1UL << EXTI_C2EMR1_EM21_Pos) /*!< 0x00200000 */
3419-#define EXTI_C2EMR1_EM21 EXTI_C2EMR1_EM21_Msk /*!< CPU2 Event Mask on line 21 */
34203281
34213282 /******************** Bits definition for EXTI_C2IMR2 register **************/
34223283 #define EXTI_C2IMR2_Pos (0U)
@@ -3981,7 +3842,7 @@
39813842 /****************** Bits definition for FLASH_SRRVR register ************/
39823843 #define FLASH_SRRVR_SBRV_Pos (0U)
39833844 #define FLASH_SRRVR_SBRV_Msk (0x3FFFFUL << FLASH_SRRVR_SBRV_Pos) /*!< 0x0003FFFF */
3984-#define FLASH_SRRVR_SBRV FLASH_SRRVR_SBRV_Msk /* SCPU2 boot reset vector memory offset */
3845+#define FLASH_SRRVR_SBRV FLASH_SRRVR_SBRV_Msk /* CPU2 boot reset vector memory offset */
39853846
39863847 #define FLASH_SRRVR_SBRSA_Pos (18U)
39873848 #define FLASH_SRRVR_SBRSA_Msk (0x1FUL << FLASH_SRRVR_SBRSA_Pos) /*!< 0x007C0000 */
@@ -3998,7 +3859,7 @@
39983859 #define FLASH_SRRVR_NBRSD FLASH_SRRVR_NBRSD_Msk /* Non-backup SRAM2B secure mode */
39993860 #define FLASH_SRRVR_C2OPT_Pos (31U)
40003861 #define FLASH_SRRVR_C2OPT_Msk (0x1UL << FLASH_SRRVR_C2OPT_Pos) /*!< 0x80000000 */
4001-#define FLASH_SRRVR_C2OPT FLASH_SRRVR_C2OPT_Msk /* SCPU2 boot reset vector memory selection */
3862+#define FLASH_SRRVR_C2OPT FLASH_SRRVR_C2OPT_Msk /* CPU2 boot reset vector memory selection */
40023863
40033864 /****************** Bits definition for FLASH_C2ACR register ************/
40043865 #define FLASH_C2ACR_PRFTEN_Pos (8U)
@@ -5954,6 +5815,8 @@
59545815 /* */
59555816 /******************************************************************************/
59565817
5818+#define PWR_SUPPORT_STOP2
5819+
59575820 /******************** Bit definition for PWR_CR1 register ********************/
59585821 #define PWR_CR1_LPMS_Pos (0U)
59595822 #define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
@@ -6431,8 +6294,8 @@
64316294 /*
64326295 * @brief Specific device feature definitions
64336296 */
6434-#define RCC_MCO3_SUPPORT
6435-#define RCC_LSCO3_SUPPORT
6297+#define RCC_HSI48_SUPPORT
6298+#define RCC_802_SUPPORT
64366299
64376300 /******************** Bit definition for RCC_CR register *****************/
64386301 #define RCC_CR_MSION_Pos (0U)
@@ -6484,9 +6347,6 @@
64846347 #define RCC_CR_HSERDY_Pos (17U)
64856348 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
64866349 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */
6487-#define RCC_CR_HSEBYP_Pos (18U)
6488-#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
6489-#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed oscillator (HSE) clock bypass */
64906350 #define RCC_CR_CSSON_Pos (19U)
64916351 #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
64926352 #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */
@@ -6850,19 +6710,19 @@
68506710
68516711 /******************** Bit definition for RCC_APB2RSTR register **************/
68526712 #define RCC_APB2RSTR_TIM1RST_Pos (11U)
6853-#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
6713+#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
68546714 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
68556715 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
6856-#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
6716+#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
68576717 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
68586718 #define RCC_APB2RSTR_USART1RST_Pos (14U)
68596719 #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
68606720 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
68616721 #define RCC_APB2RSTR_TIM16RST_Pos (17U)
6862-#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
6722+#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
68636723 #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
68646724 #define RCC_APB2RSTR_TIM17RST_Pos (18U)
6865-#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
6725+#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
68666726 #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
68676727
68686728 /******************** Bit definition for RCC_APB3RSTR register **************/
@@ -6945,19 +6805,19 @@
69456805
69466806 /******************** Bit definition for RCC_APB2ENR register **************/
69476807 #define RCC_APB2ENR_TIM1EN_Pos (11U)
6948-#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
6808+#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
69496809 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
69506810 #define RCC_APB2ENR_SPI1EN_Pos (12U)
6951-#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
6811+#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
69526812 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
69536813 #define RCC_APB2ENR_USART1EN_Pos (14U)
69546814 #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
69556815 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
69566816 #define RCC_APB2ENR_TIM16EN_Pos (17U)
6957-#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
6817+#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
69586818 #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
69596819 #define RCC_APB2ENR_TIM17EN_Pos (18U)
6960-#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
6820+#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
69616821 #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
69626822
69636823 /******************** Bit definition for RCC_AHB1SMENR register ****************/
@@ -7035,19 +6895,19 @@
70356895
70366896 /******************** Bit definition for RCC_APB2SMENR register **************/
70376897 #define RCC_APB2SMENR_TIM1SMEN_Pos (11U)
7038-#define RCC_APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */
6898+#define RCC_APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */
70396899 #define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk
70406900 #define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
7041-#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
6901+#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
70426902 #define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk
70436903 #define RCC_APB2SMENR_USART1SMEN_Pos (14U)
70446904 #define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
70456905 #define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk
70466906 #define RCC_APB2SMENR_TIM16SMEN_Pos (17U)
7047-#define RCC_APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */
6907+#define RCC_APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */
70486908 #define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk
70496909 #define RCC_APB2SMENR_TIM17SMEN_Pos (18U)
7050-#define RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos) /*!< 0x00040000 */
6910+#define RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos) /*!< 0x00040000 */
70516911 #define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk
70526912
70536913 /******************** Bit definition for RCC_CCIPR register ******************/
@@ -7357,19 +7217,19 @@
73577217
73587218 /******************** Bit definition for RCC_C2APB2ENR register **************/
73597219 #define RCC_C2APB2ENR_TIM1EN_Pos (11U)
7360-#define RCC_C2APB2ENR_TIM1EN_Msk (0x1UL << RCC_C2APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
7220+#define RCC_C2APB2ENR_TIM1EN_Msk (0x1UL << RCC_C2APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
73617221 #define RCC_C2APB2ENR_TIM1EN RCC_C2APB2ENR_TIM1EN_Msk
73627222 #define RCC_C2APB2ENR_SPI1EN_Pos (12U)
7363-#define RCC_C2APB2ENR_SPI1EN_Msk (0x1UL << RCC_C2APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
7223+#define RCC_C2APB2ENR_SPI1EN_Msk (0x1UL << RCC_C2APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
73647224 #define RCC_C2APB2ENR_SPI1EN RCC_C2APB2ENR_SPI1EN_Msk
73657225 #define RCC_C2APB2ENR_USART1EN_Pos (14U)
73667226 #define RCC_C2APB2ENR_USART1EN_Msk (0x1UL << RCC_C2APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
73677227 #define RCC_C2APB2ENR_USART1EN RCC_C2APB2ENR_USART1EN_Msk
73687228 #define RCC_C2APB2ENR_TIM16EN_Pos (17U)
7369-#define RCC_C2APB2ENR_TIM16EN_Msk (0x1UL << RCC_C2APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
7229+#define RCC_C2APB2ENR_TIM16EN_Msk (0x1UL << RCC_C2APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
73707230 #define RCC_C2APB2ENR_TIM16EN RCC_C2APB2ENR_TIM16EN_Msk
73717231 #define RCC_C2APB2ENR_TIM17EN_Pos (18U)
7372-#define RCC_C2APB2ENR_TIM17EN_Msk (0x1UL << RCC_C2APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
7232+#define RCC_C2APB2ENR_TIM17EN_Msk (0x1UL << RCC_C2APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
73737233 #define RCC_C2APB2ENR_TIM17EN RCC_C2APB2ENR_TIM17EN_Msk
73747234
73757235 /******************** Bit definition for RCC_C2APB3ENR register **************/
@@ -7452,19 +7312,19 @@
74527312
74537313 /******************** Bit definition for RCC_C2APB2SMENR register **************/
74547314 #define RCC_C2APB2SMENR_TIM1SMEN_Pos (11U)
7455-#define RCC_C2APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_C2APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */
7315+#define RCC_C2APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_C2APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */
74567316 #define RCC_C2APB2SMENR_TIM1SMEN RCC_C2APB2SMENR_TIM1SMEN_Msk
74577317 #define RCC_C2APB2SMENR_SPI1SMEN_Pos (12U)
7458-#define RCC_C2APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_C2APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
7318+#define RCC_C2APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_C2APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
74597319 #define RCC_C2APB2SMENR_SPI1SMEN RCC_C2APB2SMENR_SPI1SMEN_Msk
74607320 #define RCC_C2APB2SMENR_USART1SMEN_Pos (14U)
74617321 #define RCC_C2APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_C2APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
74627322 #define RCC_C2APB2SMENR_USART1SMEN RCC_C2APB2SMENR_USART1SMEN_Msk
74637323 #define RCC_C2APB2SMENR_TIM16SMEN_Pos (17U)
7464-#define RCC_C2APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_C2APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */
7324+#define RCC_C2APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_C2APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */
74657325 #define RCC_C2APB2SMENR_TIM16SMEN RCC_C2APB2SMENR_TIM16SMEN_Msk
74667326 #define RCC_C2APB2SMENR_TIM17SMEN_Pos (18U)
7467-#define RCC_C2APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_C2APB2SMENR_TIM17SMEN_Pos) /*!< 0x00040000 */
7327+#define RCC_C2APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_C2APB2SMENR_TIM17SMEN_Pos) /*!< 0x00040000 */
74687328 #define RCC_C2APB2SMENR_TIM17SMEN RCC_C2APB2SMENR_TIM17SMEN_Msk
74697329
74707330 /******************** Bit definition for RCC_C2APB3SMENR register **************/
@@ -9661,17 +9521,9 @@
96619521 #define TIM1_OR_TI1_RMP TIM1_OR_TI1_RMP_Msk /*!< Input Capture 1 remap*/
96629522
96639523 /******************* Bit definition for TIM2_OR register *******************/
9664-#define TIM2_OR_TI4_RMP_Pos (2U)
9665-#define TIM2_OR_TI4_RMP_Msk (0x3UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x0000000C */
9666-#define TIM2_OR_TI4_RMP TIM2_OR_TI4_RMP_Msk /*!< TI4 RMA[1:0]Input capture 4 remap*/
9667-#define TIM2_OR_TI4_RMP_0 (0x1U << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000004 */
9668-#define TIM2_OR_TI4_RMP_1 (0x2U << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000008 */
96699524 #define TIM2_OR_ETR_RMP_Pos (1U)
96709525 #define TIM2_OR_ETR_RMP_Msk (0x1UL << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000002 */
96719526 #define TIM2_OR_ETR_RMP TIM2_OR_ETR_RMP_Msk /*!< External trigger remap*/
9672-#define TIM2_OR_ITR1_RMP_Pos (0U)
9673-#define TIM2_OR_ITR1_RMP_Msk (0x1UL << TIM2_OR_ITR1_RMP_Pos) /*!< 0x00000001 */
9674-#define TIM2_OR_ITR1_RMP TIM2_OR_ITR1_RMP_Msk /*!< Internal trigger remap*/
96759527
96769528 /******************* Bit definition for TIM16_OR register ******************/
96779529 #define TIM16_OR_TI1_RMP_Pos (0U)
@@ -9735,9 +9587,10 @@
97359587
97369588 /******************************************************************************/
97379589 /* */
9738-/* Low Power Timer (LPTTIM) */
9590+/* Low Power Timer (LPTIM) */
97399591 /* */
97409592 /******************************************************************************/
9593+
97419594 /****************** Bit definition for LPTIM_ISR register *******************/
97429595 #define LPTIM_ISR_CMPM_Pos (0U)
97439596 #define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
@@ -9901,12 +9754,6 @@
99019754 #define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
99029755 #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
99039756
9904-/****************** Bit definition for LPTIM_OR register *******************/
9905-#define LPTIM_OR_OR_Pos (0U)
9906-#define LPTIM_OR_OR_Msk (0x3UL << LPTIM_OR_OR_Pos) /*!< 0x00000003 */
9907-#define LPTIM_OR_OR LPTIM_OR_OR_Msk /*!< OR[1:0] bits (Remap selection) */
9908-#define LPTIM_OR_OR_0 (0x1U << LPTIM_OR_OR_Pos) /*!< 0x00000001 */
9909-#define LPTIM_OR_OR_1 (0x2U << LPTIM_OR_OR_Pos) /*!< 0x00000002 */
99109757
99119758 /******************************************************************************/
99129759 /* */
@@ -10678,30 +10525,6 @@
1067810525
1067910526 /******************************************************************************/
1068010527 /* */
10681-/* VREFBUF */
10682-/* */
10683-/******************************************************************************/
10684-/******************* Bit definition for VREFBUF_CSR register ****************/
10685-#define VREFBUF_CSR_ENVR_Pos (0U)
10686-#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */
10687-#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!<Voltage reference buffer enable */
10688-#define VREFBUF_CSR_HIZ_Pos (1U)
10689-#define VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos) /*!< 0x00000002 */
10690-#define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk /*!<High impedance mode */
10691-#define VREFBUF_CSR_VRS_Pos (2U)
10692-#define VREFBUF_CSR_VRS_Msk (0x1UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000004 */
10693-#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
10694-#define VREFBUF_CSR_VRR_Pos (3U)
10695-#define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */
10696-#define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference buffer ready */
10697-
10698-/******************* Bit definition for VREFBUF_CCR register ******************/
10699-#define VREFBUF_CCR_TRIM_Pos (0U)
10700-#define VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */
10701-#define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */
10702-
10703-/******************************************************************************/
10704-/* */
1070510528 /* Window WATCHDOG */
1070610529 /* */
1070710530 /******************************************************************************/
@@ -10751,7 +10574,7 @@
1075110574
1075210575 /******************************************************************************/
1075310576 /* */
10754-/* Debug MCU */
10577+/* Debug MCU */
1075510578 /* */
1075610579 /******************************************************************************/
1075710580 /******************** Bit definition for DBGMCU_IDCODE register *************/
@@ -11094,7 +10917,6 @@
1109410917 (((INSTANCE) == TIM16) && \
1109510918 ((CHANNEL) == TIM_CHANNEL_1)))
1109610919
11097-
1109810920 /****************** TIM Instances : supporting clock division *****************/
1109910921 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
1110010922 ((INSTANCE) == TIM2) || \
@@ -11121,7 +10943,9 @@
1112110943 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
1112210944
1112310945 /****************** TIM Instances : supporting commutation event generation ***/
11124-#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
10946+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10947+ ((INSTANCE) == TIM16) || \
10948+ ((INSTANCE) == TIM17))
1112510949
1112610950 /****************** TIM Instances : supporting counting mode selection ********/
1112710951 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
--- trunk/os/common/ext/ST/STM32WBxx/stm32wb55xx.h (revision 14013)
+++ trunk/os/common/ext/ST/STM32WBxx/stm32wb55xx.h (revision 14014)
@@ -46,12 +46,12 @@
4646 /**
4747 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
4848 */
49-#define __CM4_REV 1 /*!< Core Revision r0p1 */
50-#define __MPU_PRESENT 1 /*!< M4 provides an MPU */
51-#define __VTOR_PRESENT 1 /*!< Vector Table Register supported */
52-#define __NVIC_PRIO_BITS 4 /*!< STM32WBxx uses 4 Bits for the Priority Levels */
53-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
54-#define __FPU_PRESENT 1 /*!< FPU present */
49+#define __CM4_REV 1U /*!< Core Revision r0p1 */
50+#define __MPU_PRESENT 1U /*!< M4 provides an MPU */
51+#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */
52+#define __NVIC_PRIO_BITS 4U /*!< STM32WBxx uses 4 Bits for the Priority Levels */
53+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
54+#define __FPU_PRESENT 1U /*!< FPU present */
5555 /**
5656 * @}
5757 */
@@ -419,7 +419,7 @@
419419 __IO uint32_t C2CR1; /*!< PWR Power Control Register 1 for CPU2, Address offset: 0x80 */
420420 __IO uint32_t C2CR3; /*!< PWR Power Control Register 3 for CPU2, Address offset: 0x84 */
421421 __IO uint32_t EXTSCR; /*!< PWR Power Status Reset Register for CPU2, Address offset: 0x88 */
422-} PWR_TypeDef;
422+} PWR_TypeDef;
423423
424424 /**
425425 * @brief QUAD Serial Peripheral Interface
@@ -439,7 +439,7 @@
439439 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
440440 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
441441 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
442-} QUADSPI_TypeDef;
442+} QUADSPI_TypeDef;
443443
444444 /**
445445 * @brief Reset and Clock Control
@@ -446,65 +446,65 @@
446446 */
447447 typedef struct
448448 {
449- __IO uint32_t CR; /*!< RCC clock Control Register, Address offset: 0x00 */
450- __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */
451- __IO uint32_t CFGR; /*!< RCC Clocks Configuration Register, Address offset: 0x08 */
452- __IO uint32_t PLLCFGR; /*!< RCC System PLL configuration Register, Address offset: 0x0C */
453- __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration Register, Address offset: 0x10 */
454-uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */
455- __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */
456- __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */
457- __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */
458- __IO uint32_t SMPSCR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x24 */
459- __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */
460- __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */
461- __IO uint32_t AHB3RSTR; /*!< RCC AHB3 & AHB4 peripheral reset register, Address offset: 0x30 */
462-uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */
463- __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */
464- __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */
465- __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */
466- __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x44 */
467- __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */
468- __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */
469- __IO uint32_t AHB3ENR; /*!< RCC AHB3 & AHB4 peripheral clocks enable register, Address offset: 0x50 */
470-uint32_t RESERVED2; /*!< Reserved, Address offset: 0x54 */
471- __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */
472- __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */
473- __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */
474-uint32_t RESERVED3; /*!< Reserved, Address offset: 0x64 */
475- __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */
476- __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */
477- __IO uint32_t AHB3SMENR; /*!< RCC AHB3 & AHB4 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */
478-uint32_t RESERVED4; /*!< Reserved, Address offset: 0x74 */
479- __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
480- __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
481- __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
482-uint32_t RESERVED5; /*!< Reserved, Address offset: 0x84 */
483- __IO uint32_t CCIPR; /*!< RCC Peripherals Clock Configuration Independent Register, Address offset: 0x88 */
484-uint32_t RESERVED6; /*!< Reserved, Address offset: 0x8C */
485- __IO uint32_t BDCR; /*!< RCC Backup Domain Control Register, Address offset: 0x90 */
486- __IO uint32_t CSR; /*!< RCC Control and Status Register, Address offset: 0x94 */
487- __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register, Address offset: 0x98 */
488- __IO uint32_t HSECR; /*!< RCC HSE Clock Register, Address offset: 0x9C */
489-uint32_t RESERVED7[26]; /*!< Reserved, Address offset: 0xA0-0x104 */
490- __IO uint32_t EXTCFGR; /*!< RCC Extended Clock Recovery Register, Address offset: 0x108 */
491- __IO uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */
492- __IO uint32_t C2AHB1ENR; /*!< RRCC AHB1 peripheral CPU2 clocks enable register, Address offset: 0x148 */
493- __IO uint32_t C2AHB2ENR; /*!< RCC AHB2 peripheral CPU2 clocks enable register, Address offset: 0x14C */
494- __IO uint32_t C2AHB3ENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable register,, Address offset: 0x150 */
495-uint32_t RESERVED9; /*!< Reserved, Address offset: 0x154 */
496- __IO uint32_t C2APB1ENR1; /*!< RCC APB1 peripheral CPU2 clocks enable register 1, Address offset: 0x158 */
497- __IO uint32_t C2APB1ENR2; /*!< RCC APB1 peripheral CPU2 clocks enable register 2, Address offset: 0x15C */
498- __IO uint32_t C2APB2ENR; /*!< RCC APB2 peripheral CPU2 clocks enable register 1, Address offset: 0x160 */
499- __IO uint32_t C2APB3ENR; /*!< RCC APB3 peripheral CPU2 clocks enable register 1, Address offset: 0x164 */
500- __IO uint32_t C2AHB1SMENR; /*!< RCC AHB1 peripheral CPU2 clocks enable in sleep and stop modes register, Address offset: 0x168 */
501- __IO uint32_t C2AHB2SMENR; /*!< RCC AHB2 peripheral CPU2 clocks enable in sleep and stop modes register, Address offset: 0x16C */
502- __IO uint32_t C2AHB3SMENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable in sleep and stop modes register, Address offset: 0x170 */
503-uint32_t RESERVED10; /*!< Reserved, */
504- __IO uint32_t C2APB1SMENR1;/*!< RCC APB1 peripheral CPU2 clocks enable in sleep mode and stop modes register 1, Address offset: 0x178 */
505- __IO uint32_t C2APB1SMENR2;/*!< RCC APB1 peripheral CPU2 clocks enable in sleep mode and stop modes register 2, Address offset: 0x17C */
506- __IO uint32_t C2APB2SMENR; /*!< RCC APB2 peripheral CPU2 clocks enable in sleep mode and stop modes register, Address offset: 0x180 */
507- __IO uint32_t C2APB3SMENR; /*!< RCC APB3 peripheral CPU2 clocks enable in sleep mode and stop modes register, Address offset: 0x184 */
449+ __IO uint32_t CR; /*!< RCC clock Control Register, Address offset: 0x00 */
450+ __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */
451+ __IO uint32_t CFGR; /*!< RCC Clocks Configuration Register, Address offset: 0x08 */
452+ __IO uint32_t PLLCFGR; /*!< RCC System PLL configuration Register, Address offset: 0x0C */
453+ __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration Register, Address offset: 0x10 */
454+uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */
455+ __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */
456+ __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */
457+ __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */
458+ __IO uint32_t SMPSCR; /*!< RCC SMPS step-down converter control register, Address offset: 0x24 */
459+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */
460+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */
461+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 & AHB4 peripheral reset register, Address offset: 0x30 */
462+uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */
463+ __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */
464+ __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */
465+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */
466+ __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x44 */
467+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */
468+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */
469+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 & AHB4 peripheral clocks enable register, Address offset: 0x50 */
470+uint32_t RESERVED2; /*!< Reserved, Address offset: 0x54 */
471+ __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */
472+ __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */
473+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */
474+uint32_t RESERVED3; /*!< Reserved, Address offset: 0x64 */
475+ __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */
476+ __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */
477+ __IO uint32_t AHB3SMENR; /*!< RCC AHB3 & AHB4 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */
478+uint32_t RESERVED4; /*!< Reserved, Address offset: 0x74 */
479+ __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
480+ __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
481+ __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
482+uint32_t RESERVED5; /*!< Reserved, Address offset: 0x84 */
483+ __IO uint32_t CCIPR; /*!< RCC Peripherals Clock Configuration Independent Register, Address offset: 0x88 */
484+uint32_t RESERVED6; /*!< Reserved, Address offset: 0x8C */
485+ __IO uint32_t BDCR; /*!< RCC Backup Domain Control Register, Address offset: 0x90 */
486+ __IO uint32_t CSR; /*!< RCC Control and Status Register, Address offset: 0x94 */
487+ __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register, Address offset: 0x98 */
488+ __IO uint32_t HSECR; /*!< RCC HSE Clock Register, Address offset: 0x9C */
489+uint32_t RESERVED7[26]; /*!< Reserved, Address offset: 0xA0-0x104 */
490+ __IO uint32_t EXTCFGR; /*!< RCC Extended Clock Recovery Register, Address offset: 0x108 */
491+uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */
492+ __IO uint32_t C2AHB1ENR; /*!< RRCC AHB1 peripheral CPU2 clocks enable register, Address offset: 0x148 */
493+ __IO uint32_t C2AHB2ENR; /*!< RCC AHB2 peripheral CPU2 clocks enable register, Address offset: 0x14C */
494+ __IO uint32_t C2AHB3ENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable register,, Address offset: 0x150 */
495+uint32_t RESERVED9; /*!< Reserved, Address offset: 0x154 */
496+ __IO uint32_t C2APB1ENR1; /*!< RCC APB1 peripheral CPU2 clocks enable register 1, Address offset: 0x158 */
497+ __IO uint32_t C2APB1ENR2; /*!< RCC APB1 peripheral CPU2 clocks enable register 2, Address offset: 0x15C */
498+ __IO uint32_t C2APB2ENR; /*!< RCC APB2 peripheral CPU2 clocks enable register 1, Address offset: 0x160 */
499+ __IO uint32_t C2APB3ENR; /*!< RCC APB3 peripheral CPU2 clocks enable register 1, Address offset: 0x164 */
500+ __IO uint32_t C2AHB1SMENR; /*!< RCC AHB1 peripheral CPU2 clocks enable in sleep and stop modes register, Address offset: 0x168 */
501+ __IO uint32_t C2AHB2SMENR; /*!< RCC AHB2 peripheral CPU2 clocks enable in sleep and stop modes register, Address offset: 0x16C */
502+ __IO uint32_t C2AHB3SMENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable in sleep and stop modes register, Address offset: 0x170 */
503+uint32_t RESERVED10; /*!< Reserved, */
504+ __IO uint32_t C2APB1SMENR1; /*!< RCC APB1 peripheral CPU2 clocks enable in sleep mode and stop modes register 1, Address offset: 0x178 */
505+ __IO uint32_t C2APB1SMENR2; /*!< RCC APB1 peripheral CPU2 clocks enable in sleep mode and stop modes register 2, Address offset: 0x17C */
506+ __IO uint32_t C2APB2SMENR; /*!< RCC APB2 peripheral CPU2 clocks enable in sleep mode and stop modes register, Address offset: 0x180 */
507+ __IO uint32_t C2APB3SMENR; /*!< RCC APB3 peripheral CPU2 clocks enable in sleep mode and stop modes register, Address offset: 0x184 */
508508 } RCC_TypeDef;
509509
510510
@@ -1208,6 +1208,9 @@
12081208 /* Analog to Digital Converter (ADC) */
12091209 /* */
12101210 /******************************************************************************/
1211+
1212+#define ADC_SUPPORT_5_MSPS /* ADC sampling rate 5 Msamples/sec */
1213+
12111214 /******************** Bit definition for ADC_ISR register *******************/
12121215 #define ADC_ISR_ADRDY_Pos (0U)
12131216 #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
@@ -2779,7 +2782,7 @@
27792782 /******************************************************************************/
27802783 /******************** Bits definition for DMAMUX_CxCR register **************/
27812784 #define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
2782-#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */
2785+#define DMAMUX_CxCR_DMAREQ_ID_Msk (0x3FUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x0000003F */
27832786 #define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk /*!< DMA Request ID */
27842787 #define DMAMUX_CxCR_DMAREQ_ID_0 (0x01U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */
27852788 #define DMAMUX_CxCR_DMAREQ_ID_1 (0x02U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */
@@ -2787,8 +2790,6 @@
27872790 #define DMAMUX_CxCR_DMAREQ_ID_3 (0x08U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */
27882791 #define DMAMUX_CxCR_DMAREQ_ID_4 (0x10U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */
27892792 #define DMAMUX_CxCR_DMAREQ_ID_5 (0x20U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */
2790-#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */
2791-#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */
27922793 #define DMAMUX_CxCR_SOIE_Pos (8U)
27932794 #define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */
27942795 #define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */
@@ -4270,7 +4271,7 @@
42704271 /****************** Bits definition for FLASH_SRRVR register ************/
42714272 #define FLASH_SRRVR_SBRV_Pos (0U)
42724273 #define FLASH_SRRVR_SBRV_Msk (0x3FFFFUL << FLASH_SRRVR_SBRV_Pos) /*!< 0x0003FFFF */
4273-#define FLASH_SRRVR_SBRV FLASH_SRRVR_SBRV_Msk /* SCPU2 boot reset vector memory offset */
4274+#define FLASH_SRRVR_SBRV FLASH_SRRVR_SBRV_Msk /* CPU2 boot reset vector memory offset */
42744275
42754276 #define FLASH_SRRVR_SBRSA_Pos (18U)
42764277 #define FLASH_SRRVR_SBRSA_Msk (0x1FUL << FLASH_SRRVR_SBRSA_Pos) /*!< 0x007C0000 */
@@ -4287,7 +4288,7 @@
42874288 #define FLASH_SRRVR_NBRSD FLASH_SRRVR_NBRSD_Msk /* Non-backup SRAM2B secure mode */
42884289 #define FLASH_SRRVR_C2OPT_Pos (31U)
42894290 #define FLASH_SRRVR_C2OPT_Msk (0x1UL << FLASH_SRRVR_C2OPT_Pos) /*!< 0x80000000 */
4290-#define FLASH_SRRVR_C2OPT FLASH_SRRVR_C2OPT_Msk /* SCPU2 boot reset vector memory selection */
4291+#define FLASH_SRRVR_C2OPT FLASH_SRRVR_C2OPT_Msk /* CPU2 boot reset vector memory selection */
42914292
42924293 /****************** Bits definition for FLASH_C2ACR register ************/
42934294 #define FLASH_C2ACR_PRFTEN_Pos (8U)
@@ -6243,6 +6244,8 @@
62436244 /* */
62446245 /******************************************************************************/
62456246
6247+#define PWR_SUPPORT_STOP2
6248+
62466249 /******************** Bit definition for PWR_CR1 register ********************/
62476250 #define PWR_CR1_LPMS_Pos (0U)
62486251 #define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
@@ -7269,6 +7272,8 @@
72697272 #define RCC_SMPS_SUPPORT
72707273 #define RCC_MCO3_SUPPORT
72717274 #define RCC_LSCO3_SUPPORT
7275+#define RCC_HSI48_SUPPORT
7276+#define RCC_802_SUPPORT
72727277
72737278 /******************** Bit definition for RCC_CR register *****************/
72747279 #define RCC_CR_MSION_Pos (0U)
@@ -7320,9 +7325,6 @@
73207325 #define RCC_CR_HSERDY_Pos (17U)
73217326 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
73227327 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */
7323-#define RCC_CR_HSEBYP_Pos (18U)
7324-#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
7325-#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed oscillator (HSE) clock bypass */
73267328 #define RCC_CR_CSSON_Pos (19U)
73277329 #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
73287330 #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */
@@ -7798,22 +7800,22 @@
77987800
77997801 /******************** Bit definition for RCC_APB2RSTR register **************/
78007802 #define RCC_APB2RSTR_TIM1RST_Pos (11U)
7801-#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
7803+#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
78027804 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
78037805 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
7804-#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
7806+#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
78057807 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
78067808 #define RCC_APB2RSTR_USART1RST_Pos (14U)
78077809 #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
78087810 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
78097811 #define RCC_APB2RSTR_TIM16RST_Pos (17U)
7810-#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
7812+#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
78117813 #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
78127814 #define RCC_APB2RSTR_TIM17RST_Pos (18U)
7813-#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
7815+#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
78147816 #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
78157817 #define RCC_APB2RSTR_SAI1RST_Pos (21U)
7816-#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */
7818+#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */
78177819 #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
78187820
78197821 /******************** Bit definition for RCC_APB3RSTR register **************/
@@ -7929,19 +7931,19 @@
79297931
79307932 /******************** Bit definition for RCC_APB2ENR register **************/
79317933 #define RCC_APB2ENR_TIM1EN_Pos (11U)
7932-#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
7934+#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
79337935 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
79347936 #define RCC_APB2ENR_SPI1EN_Pos (12U)
7935-#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
7937+#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
79367938 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
79377939 #define RCC_APB2ENR_USART1EN_Pos (14U)
79387940 #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
79397941 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
79407942 #define RCC_APB2ENR_TIM16EN_Pos (17U)
7941-#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
7943+#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
79427944 #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
79437945 #define RCC_APB2ENR_TIM17EN_Pos (18U)
7944-#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
7946+#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
79457947 #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
79467948 #define RCC_APB2ENR_SAI1EN_Pos (21U)
79477949 #define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00200000 */
@@ -8055,22 +8057,22 @@
80558057
80568058 /******************** Bit definition for RCC_APB2SMENR register **************/
80578059 #define RCC_APB2SMENR_TIM1SMEN_Pos (11U)
8058-#define RCC_APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */
8060+#define RCC_APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */
80598061 #define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk
80608062 #define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
8061-#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
8063+#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
80628064 #define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk
80638065 #define RCC_APB2SMENR_USART1SMEN_Pos (14U)
80648066 #define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
80658067 #define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk
80668068 #define RCC_APB2SMENR_TIM16SMEN_Pos (17U)
8067-#define RCC_APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */
8069+#define RCC_APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */
80688070 #define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk
80698071 #define RCC_APB2SMENR_TIM17SMEN_Pos (18U)
8070-#define RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos) /*!< 0x00040000 */
8072+#define RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos) /*!< 0x00040000 */
80718073 #define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk
80728074 #define RCC_APB2SMENR_SAI1SMEN_Pos (21U)
8073-#define RCC_APB2SMENR_SAI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos) /*!< 0x00200000 */
8075+#define RCC_APB2SMENR_SAI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos) /*!< 0x00200000 */
80748076 #define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk
80758077
80768078 /******************** Bit definition for RCC_CCIPR register ******************/
@@ -8428,22 +8430,22 @@
84288430
84298431 /******************** Bit definition for RCC_C2APB2ENR register **************/
84308432 #define RCC_C2APB2ENR_TIM1EN_Pos (11U)
8431-#define RCC_C2APB2ENR_TIM1EN_Msk (0x1UL << RCC_C2APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
8433+#define RCC_C2APB2ENR_TIM1EN_Msk (0x1UL << RCC_C2APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
84328434 #define RCC_C2APB2ENR_TIM1EN RCC_C2APB2ENR_TIM1EN_Msk
84338435 #define RCC_C2APB2ENR_SPI1EN_Pos (12U)
8434-#define RCC_C2APB2ENR_SPI1EN_Msk (0x1UL << RCC_C2APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
8436+#define RCC_C2APB2ENR_SPI1EN_Msk (0x1UL << RCC_C2APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
84358437 #define RCC_C2APB2ENR_SPI1EN RCC_C2APB2ENR_SPI1EN_Msk
84368438 #define RCC_C2APB2ENR_USART1EN_Pos (14U)
84378439 #define RCC_C2APB2ENR_USART1EN_Msk (0x1UL << RCC_C2APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
84388440 #define RCC_C2APB2ENR_USART1EN RCC_C2APB2ENR_USART1EN_Msk
84398441 #define RCC_C2APB2ENR_TIM16EN_Pos (17U)
8440-#define RCC_C2APB2ENR_TIM16EN_Msk (0x1UL << RCC_C2APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
8442+#define RCC_C2APB2ENR_TIM16EN_Msk (0x1UL << RCC_C2APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
84418443 #define RCC_C2APB2ENR_TIM16EN RCC_C2APB2ENR_TIM16EN_Msk
84428444 #define RCC_C2APB2ENR_TIM17EN_Pos (18U)
8443-#define RCC_C2APB2ENR_TIM17EN_Msk (0x1UL << RCC_C2APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
8445+#define RCC_C2APB2ENR_TIM17EN_Msk (0x1UL << RCC_C2APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
84448446 #define RCC_C2APB2ENR_TIM17EN RCC_C2APB2ENR_TIM17EN_Msk
84458447 #define RCC_C2APB2ENR_SAI1EN_Pos (21U)
8446-#define RCC_C2APB2ENR_SAI1EN_Msk (0x1UL << RCC_C2APB2ENR_SAI1EN_Pos) /*!< 0x00200000 */
8448+#define RCC_C2APB2ENR_SAI1EN_Msk (0x1UL << RCC_C2APB2ENR_SAI1EN_Pos) /*!< 0x00200000 */
84478449 #define RCC_C2APB2ENR_SAI1EN RCC_C2APB2ENR_SAI1EN_Msk
84488450
84498451 /******************** Bit definition for RCC_C2APB3ENR register **************/
@@ -8556,22 +8558,22 @@
85568558
85578559 /******************** Bit definition for RCC_C2APB2SMENR register **************/
85588560 #define RCC_C2APB2SMENR_TIM1SMEN_Pos (11U)
8559-#define RCC_C2APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_C2APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */
8561+#define RCC_C2APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_C2APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */
85608562 #define RCC_C2APB2SMENR_TIM1SMEN RCC_C2APB2SMENR_TIM1SMEN_Msk
85618563 #define RCC_C2APB2SMENR_SPI1SMEN_Pos (12U)
8562-#define RCC_C2APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_C2APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
8564+#define RCC_C2APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_C2APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
85638565 #define RCC_C2APB2SMENR_SPI1SMEN RCC_C2APB2SMENR_SPI1SMEN_Msk
85648566 #define RCC_C2APB2SMENR_USART1SMEN_Pos (14U)
85658567 #define RCC_C2APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_C2APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
85668568 #define RCC_C2APB2SMENR_USART1SMEN RCC_C2APB2SMENR_USART1SMEN_Msk
85678569 #define RCC_C2APB2SMENR_TIM16SMEN_Pos (17U)
8568-#define RCC_C2APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_C2APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */
8570+#define RCC_C2APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_C2APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */
85698571 #define RCC_C2APB2SMENR_TIM16SMEN RCC_C2APB2SMENR_TIM16SMEN_Msk
85708572 #define RCC_C2APB2SMENR_TIM17SMEN_Pos (18U)
8571-#define RCC_C2APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_C2APB2SMENR_TIM17SMEN_Pos) /*!< 0x00040000 */
8573+#define RCC_C2APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_C2APB2SMENR_TIM17SMEN_Pos) /*!< 0x00040000 */
85728574 #define RCC_C2APB2SMENR_TIM17SMEN RCC_C2APB2SMENR_TIM17SMEN_Msk
85738575 #define RCC_C2APB2SMENR_SAI1SMEN_Pos (21U)
8574-#define RCC_C2APB2SMENR_SAI1SMEN_Msk (0x1UL << RCC_C2APB2SMENR_SAI1SMEN_Pos) /*!< 0x00200000 */
8576+#define RCC_C2APB2SMENR_SAI1SMEN_Msk (0x1UL << RCC_C2APB2SMENR_SAI1SMEN_Pos) /*!< 0x00200000 */
85758577 #define RCC_C2APB2SMENR_SAI1SMEN RCC_C2APB2SMENR_SAI1SMEN_Msk
85768578
85778579 /******************** Bit definition for RCC_C2APB3SMENR register **************/
@@ -11807,7 +11809,7 @@
1180711809 /******************* Bit definition for TIM2_OR register *******************/
1180811810 #define TIM2_OR_TI4_RMP_Pos (2U)
1180911811 #define TIM2_OR_TI4_RMP_Msk (0x3UL << TIM2_OR_TI4_RMP_Pos) /*!< 0x0000000C */
11810-#define TIM2_OR_TI4_RMP TIM2_OR_TI4_RMP_Msk /*!< TI4 RMA[1:0]Input capture 4 remap*/
11812+#define TIM2_OR_TI4_RMP TIM2_OR_TI4_RMP_Msk /*!< TI4 RMP[1:0]Input capture 4 remap*/
1181111813 #define TIM2_OR_TI4_RMP_0 (0x1U << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000004 */
1181211814 #define TIM2_OR_TI4_RMP_1 (0x2U << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000008 */
1181311815 #define TIM2_OR_ETR_RMP_Pos (1U)
@@ -11927,9 +11929,10 @@
1192711929
1192811930 /******************************************************************************/
1192911931 /* */
11930-/* Low Power Timer (LPTTIM) */
11932+/* Low Power Timer (LPTIM) */
1193111933 /* */
1193211934 /******************************************************************************/
11935+
1193311936 /****************** Bit definition for LPTIM_ISR register *******************/
1193411937 #define LPTIM_ISR_CMPM_Pos (0U)
1193511938 #define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
@@ -12944,7 +12947,7 @@
1294412947
1294512948 /******************************************************************************/
1294612949 /* */
12947-/* Debug MCU */
12950+/* Debug MCU */
1294812951 /* */
1294912952 /******************************************************************************/
1295012953 /******************** Bit definition for DBGMCU_IDCODE register *************/
@@ -13288,7 +13291,7 @@
1328813291
1328913292 /*********************** UART Instances : FIFO mode ***************************/
1329013293 #define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
13291- ((INSTANCE) == LPUART1))
13294+ ((INSTANCE) == LPUART1))
1329213295
1329313296 /*********************** UART Instances : SPI Slave mode **********************/
1329413297 #define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
@@ -13564,7 +13567,6 @@
1356413567 (((INSTANCE) == TIM16) && \
1356513568 ((CHANNEL) == TIM_CHANNEL_1)))
1356613569
13567-
1356813570 /****************** TIM Instances : supporting clock division *****************/
1356913571 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
1357013572 ((INSTANCE) == TIM2) || \
@@ -13591,7 +13593,9 @@
1359113593 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
1359213594
1359313595 /****************** TIM Instances : supporting commutation event generation ***/
13594-#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
13596+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
13597+ ((INSTANCE) == TIM16) || \
13598+ ((INSTANCE) == TIM17))
1359513599
1359613600 /****************** TIM Instances : supporting counting mode selection ********/
1359713601 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
--- trunk/os/common/ext/ST/STM32WBxx/stm32wbxx.h (revision 14013)
+++ trunk/os/common/ext/ST/STM32WBxx/stm32wbxx.h (revision 14014)
@@ -69,7 +69,7 @@
6969 * @brief CMSIS Device version number
7070 */
7171 #define __STM32WBxx_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
72-#define __STM32WBxx_CMSIS_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */
72+#define __STM32WBxx_CMSIS_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */
7373 #define __STM32WBxx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
7474 #define __STM32WBxx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
7575 #define __STM32WBxx_CMSIS_DEVICE_VERSION ((__STM32WBxx_CMSIS_VERSION_MAIN << 24)\
@@ -87,8 +87,14 @@
8787
8888 #if defined(STM32WB55xx)
8989 #include "stm32wb55xx.h"
90+#elif defined(STM32WB5Mxx)
91+ #include "stm32wb5mxx.h"
9092 #elif defined(STM32WB50xx)
9193 #include "stm32wb50xx.h"
94+#elif defined(STM32WB35xx)
95+ #include "stm32wb35xx.h"
96+#elif defined(STM32WB30xx)
97+ #include "stm32wb30xx.h"
9298 #else
9399 #error "Please select first the target STM32WBxx device used in your application, for instance xxx (in stm32wbxx.h file)"
94100 #endif
--- trunk/os/common/ext/ST/STM32WBxx/system_stm32wbxx.h (revision 14013)
+++ trunk/os/common/ext/ST/STM32WBxx/system_stm32wbxx.h (revision 14014)
@@ -64,7 +64,7 @@
6464 extern const uint32_t APBPrescTable[8]; /*!< APB prescalers table values */
6565 extern const uint32_t MSIRangeTable[16]; /*!< MSI ranges table values */
6666
67-#if defined(STM32WB55xx)
67+#if defined(STM32WB55xx) || defined(STM32WB5Mxx) || defined(STM32WB35xx)
6868 extern const uint32_t SmpsPrescalerTable[4][6]; /*!< SMPS factor ranges table values */
6969 #endif
7070 /**
--- trunk/os/hal/ports/STM32/STM32WBxx/hal_lld.c (revision 14013)
+++ trunk/os/hal/ports/STM32/STM32WBxx/hal_lld.c (revision 14014)
@@ -197,14 +197,11 @@
197197 #endif
198198
199199 #if STM32_HSE_ENABLED
200-#if defined(STM32_HSE_BYPASS)
201- /* HSE Bypass.*/
202- RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
203-#endif
204200 /* HSE activation.*/
205201 RCC->CR |= RCC_CR_HSEON;
206202 while ((RCC->CR & RCC_CR_HSERDY) == 0)
207203 ; /* Wait until HSE is stable. */
204+
208205 /* HSE PRE setting.*/
209206 RCC->CR |= STM32_HSEPRE;
210207 #endif
@@ -263,7 +260,7 @@
263260 /* PLL activation.*/
264261 RCC->CR |= RCC_CR_PLLON;
265262
266- /* Waiting for PLL lock.*/
263+ /* Waiting for PLL clock.*/
267264 while ((RCC->CR & RCC_CR_PLLRDY) == 0)
268265 ;
269266 #endif
@@ -276,7 +273,7 @@
276273 STM32_PLLSAI1N;
277274 RCC->CR |= RCC_CR_PLLSAI1ON;
278275
279- /* Waiting for PLL lock.*/
276+ /* Waiting for PLL clock.*/
280277 while ((RCC->CR & RCC_CR_PLLSAI1RDY) == 0)
281278 ;
282279 #endif
@@ -285,6 +282,21 @@
285282 RCC->CFGR = STM32_MCOPRE | STM32_MCOSEL | STM32_STOPWUCK |
286283 STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
287284
285+ /* Waiting for PPRE2, PPRE1 and HPRE applied. */
286+ while ((RCC->CFGR & (RCC_CFGR_PPRE2F_Msk | RCC_CFGR_PPRE1F_Msk |
287+ RCC_CFGR_HPREF_Msk)) !=
288+ (RCC_CFGR_PPRE2F | RCC_CFGR_PPRE1F | RCC_CFGR_HPREF))
289+ ;
290+
291+ /* Extended clock recovery register (HCLK2, HCLK4, HCLK5). */
292+ RCC->EXTCFGR = STM32_RFCSSSEL | STM32_C2HPRE | STM32_SHDHPRE;
293+
294+ /* Waiting for C2HPRE and SHDHPRE. */
295+ while ((RCC->EXTCFGR & (RCC_EXTCFGR_C2HPREF_Msk |
296+ RCC_EXTCFGR_SHDHPREF_Msk)) !=
297+ (RCC_EXTCFGR_C2HPREF | RCC_EXTCFGR_SHDHPREF))
298+ ;
299+
288300 /* CCIPR register initialization, note, must take care of the _OFF
289301 pseudo settings.*/
290302 {
--- trunk/os/hal/ports/STM32/STM32WBxx/hal_lld.h (revision 14013)
+++ trunk/os/hal/ports/STM32/STM32WBxx/hal_lld.h (revision 14014)
@@ -26,7 +26,6 @@
2626 * - STM32_LSEDRV.
2727 * - STM32_LSE_BYPASS (optionally).
2828 * - STM32_HSECLK.
29- * - STM32_HSE_BYPASS (optionally).
3029 * .
3130 * One of the following macros must also be defined:
3231 * - STM32WB55xx.
@@ -140,9 +139,14 @@
140139 #define STM32_HPRE_MASK (15 << 4) /**< HPRE field mask. */
141140 #define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */
142141 #define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */
142+#define STM32_HPRE_DIV3 (1 << 4) /**< SYSCLK divided by 3. */
143143 #define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */
144+#define STM32_HPRE_DIV5 (2 << 4) /**< SYSCLK divided by 5. */
145+#define STM32_HPRE_DIV6 (5 << 4) /**< SYSCLK divided by 6. */
144146 #define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */
147+#define STM32_HPRE_DIV10 (6 << 4) /**< SYSCLK divided by 10. */
145148 #define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */
149+#define STM32_HPRE_DIV32 (7 << 4) /**< SYSCLK divided by 32. */
146150 #define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */
147151 #define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */
148152 #define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
@@ -189,7 +193,18 @@
189193 * @name RCC_EXTCFGR register bits definitions
190194 * @{
191195 */
196+/**
197+ * @brief HCLK5 clock source (RFC and APB3).
198+ */
199+#define STM32_RFCSSSEL_MASK (1 << 20) /**< RFCSS field mask. */
200+#define STM32_RFCSSSEL_HSI16 (0 << 20) /**< RFCSS source is HSI16. */
201+#define STM32_RFCSSSEL_HSE (1 << 20) /**< RFCSS source is HSE/2. */
202+
203+/**
204+ * @brief HCLK4 shared prescaler (AHB3, Flash memory and SRAM2).
205+ */
192206 #define STM32_SHDHPRE_MASK (15 << 0) /**< SHDHPRE field mask. */
207+#define STM32_SHDHPRE_DIV1 (0 << 0) /**< SYSCLK divided by 1. */
193208 #define STM32_SHDHPRE_DIV2 (8 << 0) /**< SYSCLK divided by 2. */
194209 #define STM32_SHDHPRE_DIV3 (1 << 0) /**< SYSCLK divided by 3. */
195210 #define STM32_SHDHPRE_DIV4 (9 << 0) /**< SYSCLK divided by 4. */
@@ -204,7 +219,11 @@
204219 #define STM32_SHDHPRE_DIV256 (14 << 0) /**< SYSCLK divided by 256. */
205220 #define STM32_SHDHPRE_DIV512 (15 << 0) /**< SYSCLK divided by 512. */
206221
222+/**
223+ * @brief HCLK2 prescaler (CPU2).
224+ */
207225 #define STM32_C2HPRE_MASK (15 << 4) /**< C2HPRE field mask. */
226+#define STM32_C2HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */
208227 #define STM32_C2HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */
209228 #define STM32_C2HPRE_DIV3 (1 << 4) /**< SYSCLK divided by 3. */
210229 #define STM32_C2HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */
@@ -219,12 +238,9 @@
219238 #define STM32_C2HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
220239 #define STM32_C2HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
221240
222-#define STM32_SHDHPREF_MASK (1 << 16) /**< SHDHPREF field mask. */
223-#define STM32_SHDHPREF_HCLK4RDY (1 << 16) /**< SHDHPREF HCLK4 ready. */
224-
225-#define STM32_C2HPREF_MASK (1 << 17) /**< C2HPREF field mask. */
226-#define STM32_C2HPREF_HCLK2RDY (1 << 16) /**< C2HPREF HCLK2 ready. */
227-
241+/**
242+ * @brief HCLK5 and APB3 clock source.
243+ */
228244 #define STM32_RFCSS_MASK (1 << 20) /**< RFCSS field mask. */
229245 #define STM32_RFCSS_HSI16 (0 << 20) /**< HSI16 on HCLK5 and APB3. */
230246 #define STM32_RFCSS_HSEDIV2 (1 << 20) /**< HSE/2 on HCLK5 and APB3. */
@@ -231,22 +247,6 @@
231247 /** @} */
232248
233249 /**
234- * @name RCC_C2AHB1ENR register bits definitions
235- * @{
236- */
237-/* TODO(ilya): TSCEN, CRCEN, SRAM1EN, DMAMUX1, DMA2EN and DMA1EN */
238-#define STM32_DMA1EN_MASK (1 << 0) /**< DMA1EN field mask. */
239-/** @} */
240-
241-/**
242- * @name RCC_C2AHB2ENR register bits definitions
243- * @{
244- */
245-/* TODO(ilya): AES1EN, ADCEN, GPIOHEN, GPIOEEN, GPIODEN, GPIOCEN and
246- * GPIOBEN, GPIOAEN */
247-/** @} */
248-
249-/**
250250 * @name RCC_PLLCFGR register bits definitions
251251 * @{
252252 */
@@ -377,7 +377,7 @@
377377 * @brief Enables or disables the HSI16 clock source.
378378 */
379379 #if !defined(STM32_HSI16_ENABLED) || defined(__DOXYGEN__)
380-#define STM32_HSI16_ENABLED FALSE
380+#define STM32_HSI16_ENABLED TRUE
381381 #endif
382382
383383 /**
@@ -423,7 +423,7 @@
423423 #endif
424424
425425 /**
426- * @brief HSE prescaler setting.
426+ * @brief HSE and PLL M devider prescaler setting.
427427 */
428428 #if !defined(STM32_HSEPRE_VALUE) || defined(__DOXYGEN__)
429429 #define STM32_HSEPRE_VALUE 1
@@ -498,7 +498,7 @@
498498 #endif
499499
500500 /**
501- * @brief AHB prescaler value.
501+ * @brief HCLK1 (CPU1, AHB1, AHB2, AHB3 and SRAM1) prescaler value.
502502 * @note The default value is calculated for a 32MHz system clock from
503503 * the internal 4MHz MSI clock.
504504 */
@@ -521,6 +521,29 @@
521521 #endif
522522
523523 /**
524+ * @brief HCLK2 (CPU2) prescaler value.
525+ * @note The default value is calculated for a 32MHz system clock from
526+ * the internal 4MHz MSI clock.
527+ */
528+#if !defined(STM32_C2HPRE) || defined(__DOXYGEN__)
529+#define STM32_C2HPRE STM32_C2HPRE_DIV2
530+#endif
531+
532+/**
533+ * @brief HCLK4 (AHB4, Flash memory and SRAM2) prescaler value.
534+ */
535+#if !defined(STM32_SHDHPRE) || defined(__DOXYGEN__)
536+#define STM32_SHDHPRE STM32_SHDHPRE_DIV1
537+#endif
538+
539+/**
540+ * @brief HCLK5 (APB3, AHB5 and Radio system) clock source.
541+ */
542+#if !defined(STM32_RFCSSSEL) || defined(__DOXYGEN__)
543+#define STM32_RFCSSSEL STM32_RFCSSSEL_HSI16
544+#endif
545+
546+/**
524547 * @brief STOPWUCK clock setting.
525548 */
526549 #if !defined(STM32_STOPWUCK) || defined(__DOXYGEN__)
@@ -696,26 +719,21 @@
696719 #define STM32_SYSCLK_MAX 64000000
697720
698721 /**
699- * @brief Maximum HSE clock frequency at current voltage setting.
722+ * @brief Maximum C2HPRE clock frequency at current voltage setting.
700723 */
701-#define STM32_HSECLK_MAX 48000000
724+#define STM32_C2HPRE_MAX 32000000
702725
703726 /**
704- * @brief Maximum HSE clock frequency using an external source.
727+ * @brief Maximum HSE clock frequency at current voltage setting.
705728 */
706-#define STM32_HSECLK_BYP_MAX 48000000
729+#define STM32_HSECLK_MAX 32000000
707730
708731 /**
709732 * @brief Minimum HSE clock frequency.
710733 */
711-#define STM32_HSECLK_MIN 4000000
734+#define STM32_HSECLK_MIN 32000000
712735
713736 /**
714- * @brief Minimum HSE clock frequency using an external source.
715- */
716-#define STM32_HSECLK_BYP_MIN 8000000
717-
718-/**
719737 * @brief Maximum LSE clock frequency.
720738 */
721739 #define STM32_LSECLK_MAX 32768
@@ -773,7 +791,7 @@
773791 /**
774792 * @brief Minimum PLL-P output clock frequency.
775793 */
776-#define STM32_PLLP_MIN 3000000
794+#define STM32_PLLP_MIN 2000000
777795
778796 /**
779797 * @brief Maximum PLL-Q output clock frequency.
@@ -783,7 +801,7 @@
783801 /**
784802 * @brief Minimum PLL-Q output clock frequency.
785803 */
786-#define STM32_PLLQ_MIN 12000000
804+#define STM32_PLLQ_MIN 8000000
787805
788806 /**
789807 * @brief Maximum PLL-R output clock frequency.
@@ -793,7 +811,7 @@
793811 /**
794812 * @brief Minimum PLL-R output clock frequency.
795813 */
796-#define STM32_PLLR_MIN 12000000
814+#define STM32_PLLR_MIN 8000000
797815
798816 /**
799817 * @brief Maximum APB1 clock frequency.
@@ -815,33 +833,31 @@
815833 * @name Flash Wait states
816834 * @{
817835 */
818-#define STM32_0WS_THRESHOLD 16000000
819-#define STM32_1WS_THRESHOLD 32000000
820-#define STM32_2WS_THRESHOLD 48000000
821-#define STM32_3WS_THRESHOLD 64000000
836+#define STM32_0WS_THRESHOLD 18000000
837+#define STM32_1WS_THRESHOLD 36000000
838+#define STM32_2WS_THRESHOLD 54000000
822839 /** @} */
823840
824841 #elif STM32_VOS == STM32_VOS_RANGE2
825-#define STM32_SYSCLK_MAX 26000000
826-#define STM32_HSECLK_MAX 26000000
827-#define STM32_HSECLK_BYP_MAX 26000000
828-#define STM32_HSECLK_MIN 8000000
829-#define STM32_HSECLK_BYP_MIN 8000000
842+#define STM32_SYSCLK_MAX 16000000
843+#define STM32_C2HPRE_MAX 16000000
844+#define STM32_HSECLK_MAX 32000000
845+#define STM32_HSECLK_MIN 32000000
830846 #define STM32_LSECLK_MAX 32768
831847 #define STM32_LSECLK_BYP_MAX 1000000
832848 #define STM32_LSECLK_MIN 32768
833849 #define STM32_LSECLK_BYP_MIN 32768
834850 #define STM32_PLLIN_MAX 16000000
835-#define STM32_PLLIN_MIN 4000000
851+#define STM32_PLLIN_MIN 2660000
836852 #define STM32_PLLVCO_MAX 128000000
837-#define STM32_PLLVCO_MIN 96000000
853+#define STM32_PLLVCO_MIN 64000000
838854 #define STM32_PLLSAI1VCO_MAX 128000000
839855 #define STM32_PLLSAI1VCO_MIN 64000000
840-#define STM32_PLLP_MAX 26000000
841-#define STM32_PLLP_MIN 2064500
842-#define STM32_PLLQ_MAX 26000000
856+#define STM32_PLLP_MAX 16000000
857+#define STM32_PLLP_MIN 2000000
858+#define STM32_PLLQ_MAX 16000000
843859 #define STM32_PLLQ_MIN 8000000
844-#define STM32_PLLR_MAX 26000000
860+#define STM32_PLLR_MAX 16000000
845861 #define STM32_PLLR_MIN 8000000
846862 #define STM32_PCLK1_MAX 26000000
847863 #define STM32_PCLK2_MAX 26000000
@@ -849,8 +865,7 @@
849865
850866 #define STM32_0WS_THRESHOLD 6000000
851867 #define STM32_1WS_THRESHOLD 12000000
852-#define STM32_2WS_THRESHOLD 18000000
853-#define STM32_3WS_THRESHOLD 26000000
868+#define STM32_2WS_THRESHOLD 16000000
854869
855870 #else
856871 #error "invalid STM32_VOS value specified"
@@ -944,6 +959,10 @@
944959 #error "HSI16 not enabled, required by LPTIM2SEL"
945960 #endif
946961
962+#if (STM32_RFCSSSEL == STM32_RFCSSSEL_HSI16)
963+#error "HSI16 not enabled, required by RFCSS"
964+#endif
965+
947966 #endif /* !STM32_HSI16_ENABLED */
948967
949968 #if STM32_HSI48_ENABLED
@@ -966,15 +985,9 @@
966985 #if STM32_HSECLK == 0
967986 #error "HSE frequency not defined"
968987 #else /* STM32_HSECLK != 0 */
969- #if defined(STM32_HSE_BYPASS)
970- #if (STM32_HSECLK < STM32_HSECLK_BYP_MIN) || (STM32_HSECLK > STM32_HSECLK_BYP_MAX)
971- #error "STM32_HSECLK outside acceptable range (STM32_HSECLK_BYP_MIN...STM32_HSECLK_BYP_MAX)"
972- #endif
973- #else /* !defined(STM32_HSE_BYPASS) */
974- #if (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
975- #error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
976- #endif
977- #endif /* !defined(STM32_HSE_BYPASS) */
988+ #if (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
989+ #error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
990+ #endif
978991 #endif /* STM32_HSECLK != 0 */
979992
980993 #else /* !STM32_HSE_ENABLED */
@@ -1002,6 +1015,10 @@
10021015 #error "HSE not enabled, required by STM32_RTCSEL"
10031016 #endif
10041017
1018+ #if (STM32_RFCSSSEL == STM32_RFCSSSEL_HSE)
1019+ #error "HSE not enabled, required by RFCSS"
1020+ #endif
1021+
10051022 #endif /* !STM32_HSE_ENABLED */
10061023
10071024 /*
@@ -1282,7 +1299,7 @@
12821299 #endif
12831300
12841301 /**
1285- * @brief AHB frequency.
1302+ * @brief HCLK1 frequency.
12861303 */
12871304 #if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
12881305 #define STM32_HCLK (STM32_SYSCLK / 1)
@@ -1290,15 +1307,30 @@
12901307 #elif STM32_HPRE == STM32_HPRE_DIV2
12911308 #define STM32_HCLK (STM32_SYSCLK / 2)
12921309
1310+#elif STM32_HPRE == STM32_HPRE_DIV3
1311+#define STM32_HCLK (STM32_SYSCLK / 3)
1312+
12931313 #elif STM32_HPRE == STM32_HPRE_DIV4
12941314 #define STM32_HCLK (STM32_SYSCLK / 4)
12951315
1316+#elif STM32_HPRE == STM32_HPRE_DIV5
1317+#define STM32_HCLK (STM32_SYSCLK / 5)
1318+
1319+#elif STM32_HPRE == STM32_HPRE_DIV6
1320+#define STM32_HCLK (STM32_SYSCLK / 6)
1321+
12961322 #elif STM32_HPRE == STM32_HPRE_DIV8
12971323 #define STM32_HCLK (STM32_SYSCLK / 8)
12981324
1325+#elif STM32_HPRE == STM32_HPRE_DIV10
1326+#define STM32_HCLK (STM32_SYSCLK / 10)
1327+
12991328 #elif STM32_HPRE == STM32_HPRE_DIV16
13001329 #define STM32_HCLK (STM32_SYSCLK / 16)
13011330
1331+#elif STM32_HPRE == STM32_HPRE_DIV32
1332+#define STM32_HCLK (STM32_SYSCLK / 32)
1333+
13021334 #elif STM32_HPRE == STM32_HPRE_DIV64
13031335 #define STM32_HCLK (STM32_SYSCLK / 64)
13041336
@@ -1316,7 +1348,7 @@
13161348 #endif
13171349
13181350 /*
1319- * AHB frequency check.
1351+ * HCLK1 frequency check.
13201352 */
13211353 #if STM32_HCLK > STM32_SYSCLK_MAX
13221354 #error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
@@ -1380,7 +1412,112 @@
13801412 #error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
13811413 #endif
13821414
1415+/**
1416+ * @brief HCLK2 (CPU2) frequency.
1417+ */
1418+#if (STM32_C2HPRE == STM32_C2HPRE_DIV1) || defined(__DOXYGEN__)
1419+#define STM32_HCLK2 (STM32_SYSCLK / 1)
1420+
1421+#elif STM32_C2HPRE == STM32_C2HPRE_DIV2
1422+#define STM32_HCLK2 (STM32_SYSCLK / 2)
1423+
1424+#elif STM32_C2HPRE == STM32_C2HPRE_DIV3
1425+#define STM32_HCLK2 (STM32_SYSCLK / 3)
1426+
1427+#elif STM32_C2HPRE == STM32_C2HPRE_DIV4
1428+#define STM32_HCLK2 (STM32_SYSCLK / 4)
1429+
1430+#elif STM32_C2HPRE == STM32_C2HPRE_DIV5
1431+#define STM32_HCLK2 (STM32_SYSCLK / 5)
1432+
1433+#elif STM32_C2HPRE == STM32_C2HPRE_DIV6
1434+#define STM32_HCLK2 (STM32_SYSCLK / 6)
1435+
1436+#elif STM32_C2HPRE == STM32_C2HPRE_DIV8
1437+#define STM32_HCLK2 (STM32_SYSCLK / 8)
1438+
1439+#elif STM32_C2HPRE == STM32_C2HPRE_DIV10
1440+#define STM32_HCLK2 (STM32_SYSCLK / 10)
1441+
1442+#elif STM32_C2HPRE == STM32_C2HPRE_DIV16
1443+#define STM32_HCLK2 (STM32_SYSCLK / 16)
1444+
1445+#elif STM32_C2HPRE == STM32_C2HPRE_DIV32
1446+#define STM32_HCLK2 (STM32_SYSCLK / 32)
1447+
1448+#elif STM32_C2HPRE == STM32_C2HPRE_DIV64
1449+#define STM32_HCLK2 (STM32_SYSCLK / 64)
1450+
1451+#elif STM32_C2HPRE == STM32_C2HPRE_DIV128
1452+#define STM32_HCLK2 (STM32_SYSCLK / 128)
1453+
1454+#elif STM32_C2HPRE == STM32_C2HPRE_DIV256
1455+#define STM32_HCLK2 (STM32_SYSCLK / 256)
1456+
1457+#elif STM32_C2HPRE == STM32_C2HPRE_DIV512
1458+#define STM32_HCLK2 (STM32_SYSCLK / 512)
1459+
1460+#else
1461+#error "invalid STM32_C2HPRE value specified"
1462+#endif
1463+
13831464 /*
1465+ * HCLK2 (CPU2) frequency check.
1466+ */
1467+#if STM32_HCLK2 > STM32_C2HPRE_MAX
1468+#error "STM32_HCLK2 exceeding maximum frequency (STM32_C2HPRE_MAX)"
1469+#endif
1470+
1471+/**
1472+ * @brief AHB4 frequency.
1473+ */
1474+#if (STM32_SHDHPRE == STM32_SHDHPRE_DIV1) || defined(__DOXYGEN__)
1475+#define STM32_HCLK4 (STM32_SYSCLK / 1)
1476+
1477+#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV2
1478+#define STM32_HCLK4 (STM32_SYSCLK / 2)
1479+
1480+#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV3
1481+#define STM32_HCLK4 (STM32_SYSCLK / 3)
1482+
1483+#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV4
1484+#define STM32_HCLK4 (STM32_SYSCLK / 4)
1485+
1486+#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV5
1487+#define STM32_HCLK4 (STM32_SYSCLK / 5)
1488+
1489+#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV6
1490+#define STM32_HCLK4 (STM32_SYSCLK / 6)
1491+
1492+#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV8
1493+#define STM32_HCLK4 (STM32_SYSCLK / 8)
1494+
1495+#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV10
1496+#define STM32_HCLK4 (STM32_SYSCLK / 10)
1497+
1498+#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV16
1499+#define STM32_HCLK4 (STM32_SYSCLK / 16)
1500+
1501+#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV32
1502+#define STM32_HCLK4 (STM32_SYSCLK / 32)
1503+
1504+#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV64
1505+#define STM32_HCLK4 (STM32_SYSCLK / 64)
1506+
1507+#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV128
1508+#define STM32_HCLK4 (STM32_SYSCLK / 128)
1509+
1510+#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV256
1511+#define STM32_HCLK4 (STM32_SYSCLK / 256)
1512+
1513+#elif STM32_SHDHPRE == STM32_SHDHPRE_DIV512
1514+#define STM32_HCLK4 (STM32_SYSCLK / 512)
1515+
1516+#else
1517+#error "invalid STM32_SHDHPRE value specified"
1518+#endif
1519+
1520+/*
13841521 * PLLSAI1 enable check.
13851522 */
13861523 #if (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI1) || \
@@ -1727,7 +1864,7 @@
17271864 #elif STM32_RNGSEL == STM32_RNGSEL_LSE
17281865 #define STM32_RNGCLK STM32_LSECLK
17291866 #else
1730-#error "Invalid source selected for RNG clock"
1867+#error "invalid source selected for RNG clock"
17311868 #endif
17321869
17331870 /**
@@ -1778,11 +1915,8 @@
17781915 #elif STM32_HCLK <= STM32_2WS_THRESHOLD
17791916 #define STM32_FLASHBITS FLASH_ACR_LATENCY_2WS
17801917
1781-#elif STM32_HCLK <= STM32_3WS_THRESHOLD
1918+#else
17821919 #define STM32_FLASHBITS FLASH_ACR_LATENCY_3WS
1783-
1784-#else
1785-#define STM32_FLASHBITS FLASH_ACR_LATENCY_4WS
17861920 #endif
17871921
17881922 /**
@@ -1797,11 +1931,8 @@
17971931 #elif STM32_MSICLK <= STM32_2WS_THRESHOLD
17981932 #define STM32_MSI_FLASHBITS FLASH_ACR_LATENCY_2WS
17991933
1800-#elif STM32_MSICLK <= STM32_3WS_THRESHOLD
1934+#else
18011935 #define STM32_MSI_FLASHBITS FLASH_ACR_LATENCY_3WS
1802-
1803-#else
1804-#define STM32_MSI_FLASHBITS FLASH_ACR_LATENCY_4WS
18051936 #endif
18061937
18071938 /*===========================================================================*/
--- trunk/tools/ftl/schema/boards/stm32wbxx_board.xsd (revision 14013)
+++ trunk/tools/ftl/schema/boards/stm32wbxx_board.xsd (revision 14014)
@@ -36,17 +36,8 @@
3636 <xs:minInclusive value="0"></xs:minInclusive>
3737 </xs:restriction>
3838 </xs:simpleType>
39- </xs:attribute>
40- <xs:attribute name="LSEBypass" use="required">
41- <xs:simpleType>
42- <xs:restriction base="xs:string">
43- <xs:whiteSpace value="collapse">
44- </xs:whiteSpace>
45- <xs:enumeration value="false"></xs:enumeration>
46- <xs:enumeration value="true"></xs:enumeration>
47- </xs:restriction>
48- </xs:simpleType>
49- </xs:attribute>
39+ </xs:attribute> +
5040 <xs:attribute name="LSEDrive" use="required">
5141 <xs:simpleType>
5242 <xs:restriction base="xs:string">
--- trunk/tools/ftl/xml/stm32wbboard.xml (revision 14013)
+++ trunk/tools/ftl/xml/stm32wbboard.xml (revision 14014)
@@ -16,7 +16,7 @@
1616 <bus_type>RMII</bus_type>
1717 </ethernet_phy>
1818 <subtype>STM32WB55xx</subtype>
19- <clocks HSEFrequency="32000000" HSEBypass="false" LSEFrequency="32768"
19+ <clocks HSEFrequency="32000000" LSEFrequency="32768"
2020 LSEBypass="false" VDD="300" LSEDrive="3 High Drive (default)" />
2121 <ports>
2222 <GPIOA>
--- trunk/readme.txt (revision 14013)
+++ trunk/readme.txt (revision 14014)
@@ -74,6 +74,7 @@
7474 *****************************************************************************
7575
7676 *** Next ***
77+- NEW: Added support for STM32WB55.
7778 - NEW: Added chscanf() and buffered streams, contributed by Alex Lewontin.
7879 - NEW: Added option to LWIP bindings to use memory pools instead of heap
7980 allocator.
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