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chibios: Commit


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Revision14015 (tree)
Time2021-01-07 02:17:03
Authorgdisirio

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(empty log message)

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--- trunk/os/common/ext/ST/STM32WBxx/stm32wb30xx.h (nonexistent)
+++ trunk/os/common/ext/ST/STM32WBxx/stm32wb30xx.h (revision 14015)
@@ -0,0 +1,11025 @@
1+/**
2+ ******************************************************************************
3+ * @file stm32wb30xx.h
4+ * @author MCD Application Team
5+ * @brief CMSIS Cortex Device Peripheral Access Layer Header File.
6+ * This file contains all the peripheral register's definitions, bits
7+ * definitions and memory mapping for stm32wb30xx devices.
8+ *
9+ * This file contains:
10+ * - Data structures and the address mapping for all peripherals
11+ * - Peripheral's registers declarations and bits definition
12+ * - Macros to access peripheral's registers hardware
13+ *
14+ ******************************************************************************
15+ * @attention
16+ *
17+ * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
18+ * All rights reserved.</center></h2>
19+ *
20+ * This software component is licensed by ST under BSD 3-Clause license,
21+ * the "License"; You may not use this file except in compliance with the
22+ * License. You may obtain a copy of the License at:
23+ * opensource.org/licenses/BSD-3-Clause
24+ *
25+ ******************************************************************************
26+ */
27+
28+/** @addtogroup CMSIS_Device
29+ * @{
30+ */
31+
32+/** @addtogroup stm32wb30xx
33+ * @{
34+ */
35+
36+#ifndef __STM32WB30xx_H
37+#define __STM32WB30xx_H
38+
39+#ifdef __cplusplus
40+ extern "C" {
41+#endif /* __cplusplus */
42+
43+/** @addtogroup Configuration_section_for_CMSIS
44+ * @{
45+ */
46+/**
47+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
48+ */
49+#define __CM4_REV 1U /*!< Core Revision r0p1 */
50+#define __MPU_PRESENT 1U /*!< M4 provides an MPU */
51+#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */
52+#define __NVIC_PRIO_BITS 4U /*!< STM32WBxx uses 4 Bits for the Priority Levels */
53+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
54+#define __FPU_PRESENT 1U /*!< FPU present */
55+/**
56+ * @}
57+ */
58+
59+/** @addtogroup Peripheral_interrupt_number_definition
60+ * @{
61+ */
62+
63+/**
64+ * @brief stm32wb30xx Interrupt Number Definition, according to the selected device
65+ * in @ref Library_configuration_section
66+ */
67+/*!< Interrupt Number Definition for M4 */
68+typedef enum
69+{
70+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
71+ NonMaskableInt_IRQn = -14, /*!< Non Maskable Interrupt */
72+ HardFault_IRQn = -13, /*!< Cortex-M4 Hard Fault Interrupt */
73+ MemoryManagement_IRQn = -12, /*!< Cortex-M4 Memory Management Interrupt */
74+ BusFault_IRQn = -11, /*!< Cortex-M4 Bus Fault Interrupt */
75+ UsageFault_IRQn = -10, /*!< Cortex-M4 Usage Fault Interrupt */
76+ SVCall_IRQn = -5, /*!< Cortex-M4 SV Call Interrupt */
77+ DebugMonitor_IRQn = -4, /*!< Cortex-M4 Debug Monitor Interrupt */
78+ PendSV_IRQn = -2, /*!< Cortex-M4 Pend SV Interrupt */
79+ SysTick_IRQn = -1, /*!< Cortex-M4 System Tick Interrupt */
80+
81+/************* STM32WBxx specific Interrupt Numbers on M4 core ************************************************/
82+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
83+ PVD_PVM_IRQn = 1, /*!< PVD and PVM detector */
84+ TAMP_STAMP_LSECSS_IRQn = 2, /*!< RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts */
85+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Interrupt */
86+ FLASH_IRQn = 4, /*!< FLASH (CFI) global Interrupt */
87+ RCC_IRQn = 5, /*!< RCC Interrupt */
88+ EXTI0_IRQn = 6, /*!< EXTI Line 0 Interrupt */
89+ EXTI1_IRQn = 7, /*!< EXTI Line 1 Interrupt */
90+ EXTI2_IRQn = 8, /*!< EXTI Line 2 Interrupt */
91+ EXTI3_IRQn = 9, /*!< EXTI Line 3 Interrupt */
92+ EXTI4_IRQn = 10, /*!< EXTI Line 4 Interrupt */
93+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
94+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
95+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
96+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
97+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
98+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
99+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
100+ ADC1_IRQn = 18, /*!< ADC1 Interrupt */
101+ C2SEV_PWR_C2H_IRQn = 21, /*!< CPU2 SEV Interrupt */
102+ EXTI9_5_IRQn = 23, /*!< EXTI Lines [9:5] Interrupt */
103+ TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
104+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 global Interrupts */
105+ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Communication and TIM17 global Interrupts */
106+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
107+ TIM2_IRQn = 28, /*!< TIM2 Global Interrupt */
108+ PKA_IRQn = 29, /*!< PKA Interrupt */
109+ I2C1_EV_IRQn = 30, /*!< I2C1 Event Interrupt */
110+ I2C1_ER_IRQn = 31, /*!< I2C1 Error Interrupt */
111+ SPI1_IRQn = 34, /*!< SPI1 Interrupt */
112+ USART1_IRQn = 36, /*!< USART1 Interrupt */
113+ EXTI15_10_IRQn = 40, /*!< EXTI Lines1[15:10 ]Interrupts */
114+ RTC_Alarm_IRQn = 41, /*!< RTC Alarms (A and B) Interrupt */
115+ PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQn = 43, /*!< PWR switching on the fly interrupt
116+ PWR end of BLE activity interrupt
117+ PWR end of 802.15.4 (Zigbee) activity interrupt
118+ PWR end of critical radio phase interrupt */
119+ IPCC_C1_RX_IRQn = 44, /*!< IPCC RX Occupied Interrupt */
120+ IPCC_C1_TX_IRQn = 45, /*!< IPCC TX Free Interrupt */
121+ HSEM_IRQn = 46, /*!< HSEM Interrupt */
122+ LPTIM1_IRQn = 47, /*!< LPTIM1 Interrupt */
123+ LPTIM2_IRQn = 48, /*!< LPTIM2 Interrupt */
124+ AES2_IRQn = 52, /*!< AES2 Interrupt */
125+ RNG_IRQn = 53, /*!< RNG Interrupt */
126+ FPU_IRQn = 54, /*!< FPU Interrupt */
127+ DMAMUX1_OVR_IRQn = 62 /*!< DMAMUX1 overrun Interrupt */
128+} IRQn_Type;
129+/**
130+ * @}
131+ */
132+
133+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
134+#include "system_stm32wbxx.h"
135+#include <stdint.h>
136+
137+/** @addtogroup Peripheral_registers_structures
138+ * @{
139+ */
140+
141+/**
142+ * @brief Analog to Digital Converter
143+ */
144+typedef struct
145+{
146+ __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
147+ __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
148+ __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
149+ __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */
150+ __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
151+ __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */
152+ __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */
153+ uint32_t RESERVED1; /*!< Reserved, 0x1C */
154+ __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
155+ __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
156+ __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */
157+ uint32_t RESERVED2; /*!< Reserved, 0x2C */
158+ __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */
159+ __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */
160+ __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */
161+ __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */
162+ __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
163+ uint32_t RESERVED3; /*!< Reserved, 0x44 */
164+ uint32_t RESERVED4; /*!< Reserved, 0x48 */
165+ __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */
166+ uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */
167+ __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
168+ __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
169+ __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
170+ __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
171+ uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */
172+ __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */
173+ __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */
174+ __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */
175+ __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */
176+ uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
177+ __IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */
178+ __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */
179+ uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
180+ uint32_t RESERVED9; /*!< Reserved, 0x0AC */
181+ __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */
182+ __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */
183+
184+} ADC_TypeDef;
185+
186+typedef struct
187+{
188+ uint32_t RESERVED1; /*!< Reserved, Address offset: ADC1 base address + 0x300 */
189+ uint32_t RESERVED2; /*!< Reserved, Address offset: ADC1 base address + 0x304 */
190+ __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */
191+ uint32_t RESERVED3; /*!< Reserved, Address offset: ADC1 base address + 0x30C */
192+} ADC_Common_TypeDef;
193+
194+/**
195+ * @brief CRC calculation unit
196+ */
197+typedef struct
198+{
199+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
200+ __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
201+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
202+ uint32_t RESERVED2; /*!< Reserved, 0x0C */
203+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
204+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
205+} CRC_TypeDef;
206+
207+/**
208+ * @brief Debug MCU
209+ */
210+typedef struct
211+{
212+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
213+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
214+ uint32_t RESERVED1[13]; /*!< Reserved, 0x08-0x38 */
215+ __IO uint32_t APB1FZR1; /*!< Debug MCU CPU1 APB1 freeze register, Address offset: 0x3C */
216+ __IO uint32_t C2APB1FZR1; /*!< Debug MCU CPU2 APB1 freeze register, Address offset: 0x40 */
217+ __IO uint32_t APB1FZR2; /*!< Debug MCU CPU1 APB1 freeze register, Address offset: 0x44 */
218+ __IO uint32_t C2APB1FZR2; /*!< Debug MCU CPU2 APB1 freeze register, Address offset: 0x48 */
219+ __IO uint32_t APB2FZR; /*!< Debug MCU CPU1 APB2 freeze register, Address offset: 0x4C */
220+ __IO uint32_t C2APB2FZR; /*!< Debug MCU CPU2 APB2 freeze register, Address offset: 0x50 */
221+} DBGMCU_TypeDef;
222+
223+/**
224+ * @brief DMA Controller
225+ */
226+typedef struct
227+{
228+ __IO uint32_t CCR; /*!< DMA channel x configuration register 0x00 */
229+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register 0x04 */
230+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register 0x08 */
231+ __IO uint32_t CMAR; /*!< DMA channel x memory address register 0x0C */
232+ uint32_t RESERVED; /*!< Reserved, 0x10 */
233+} DMA_Channel_TypeDef;
234+
235+typedef struct
236+{
237+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
238+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
239+} DMA_TypeDef;
240+
241+/**
242+ * @brief DMA Multiplexer
243+ */
244+typedef struct
245+{
246+ __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */
247+}DMAMUX_Channel_TypeDef;
248+
249+typedef struct
250+{
251+ __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */
252+ __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */
253+}DMAMUX_ChannelStatus_TypeDef;
254+
255+typedef struct
256+{
257+ __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */
258+}DMAMUX_RequestGen_TypeDef;
259+
260+typedef struct
261+{
262+ __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */
263+ __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */
264+}DMAMUX_RequestGenStatus_TypeDef;
265+
266+/**
267+ * @brief FLASH Registers
268+ */
269+typedef struct
270+{
271+ __IO uint32_t ACR; /*!< FLASH Access control register, Address offset: 0x00 */
272+ __IO uint32_t RESERVED; /*!< Reserved, Address offset: 0x04 */
273+ __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */
274+ __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */
275+ __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */
276+ __IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */
277+ __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */
278+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
279+ __IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */
280+ __IO uint32_t PCROP1ASR; /*!< FLASH Bank 1 PCROP area A Start address register, Address offset: 0x24 */
281+ __IO uint32_t PCROP1AER; /*!< FLASH Bank 1 PCROP area A End address register, Address offset: 0x28 */
282+ __IO uint32_t WRP1AR; /*!< FLASH Bank 1 WRP area A address register, Address offset: 0x2C */
283+ __IO uint32_t WRP1BR; /*!< FLASH Bank 1 WRP area B address register, Address offset: 0x30 */
284+ __IO uint32_t PCROP1BSR; /*!< FLASH Bank 1 PCROP area B Start address register, Address offset: 0x34 */
285+ __IO uint32_t PCROP1BER; /*!< FLASH Bank 1 PCROP area B End address register, Address offset: 0x38 */
286+ __IO uint32_t IPCCBR; /*!< FLASH IPCC data buffer address, Address offset: 0x3C */
287+ uint32_t RESERVED2[7]; /*!< Reserved, Address offset: 0x40-0x58 */
288+ __IO uint32_t C2ACR; /*!< FLASH Core MO+ Access Control Register , Address offset: 0x5C */
289+ __IO uint32_t C2SR; /*!< FLASH Core MO+ Status Register, Address offset: 0x60 */
290+ __IO uint32_t C2CR; /*!< FLASH Core MO+ Control register, Address offset: 0x64 */
291+ uint32_t RESERVED3[6]; /*!< Reserved, Address offset: 0x68-0x7C */
292+ __IO uint32_t SFR; /*!< FLASH secure start address, Address offset: 0x80 */
293+ __IO uint32_t SRRVR; /*!< FlASH secure SRAM2 start addr and CPU2 reset vector Address offset: 0x84 */
294+} FLASH_TypeDef;
295+
296+/**
297+ * @brief General Purpose I/O
298+ */
299+typedef struct
300+{
301+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
302+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
303+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
304+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
305+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
306+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
307+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
308+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
309+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
310+ __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
311+} GPIO_TypeDef;
312+
313+/**
314+ * @brief Inter-integrated Circuit Interface
315+ */
316+typedef struct
317+{
318+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
319+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
320+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
321+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
322+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
323+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
324+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
325+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
326+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
327+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
328+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
329+} I2C_TypeDef;
330+
331+/**
332+ * @brief Independent WATCHDOG
333+ */
334+typedef struct
335+{
336+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
337+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
338+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
339+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
340+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
341+} IWDG_TypeDef;
342+
343+/**
344+ * @brief LPTIMER
345+ */
346+typedef struct
347+{
348+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
349+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
350+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
351+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
352+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
353+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
354+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
355+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
356+} LPTIM_TypeDef;
357+
358+/**
359+ * @brief Power Control
360+ */
361+typedef struct
362+{
363+ __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */
364+ __IO uint32_t CR2; /*!< PWR Power Control Register 2, Address offset: 0x04 */
365+ __IO uint32_t CR3; /*!< PWR Power Control Register 3, Address offset: 0x08 */
366+ __IO uint32_t CR4; /*!< PWR Power Control Register 4, Address offset: 0x0C */
367+ __IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */
368+ __IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */
369+ __IO uint32_t SCR; /*!< PWR Power Status Reset Register, Address offset: 0x18 */
370+ __IO uint32_t CR5; /*!< PWR Power Control Register 5, Address offset: 0x1C */
371+ __IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */
372+ __IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */
373+ __IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */
374+ __IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */
375+ __IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */
376+ __IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */
377+ uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x38-0x3C */
378+ __IO uint32_t PUCRE; /*!< PWR Pull-Up Control Register of port E, Address offset: 0x40 */
379+ __IO uint32_t PDCRE; /*!< PWR Pull-Down Control Register of port E, Address offset: 0x44 */
380+ uint32_t RESERVED0[4]; /*!< Reserved, Address offset: 0x48-0x54 */
381+ __IO uint32_t PUCRH; /*!< PWR Pull-Up Control Register of port H, Address offset: 0x58 */
382+ __IO uint32_t PDCRH; /*!< PWR Pull-Down Control Register of port H, Address offset: 0x5C */
383+ uint32_t RESERVED1[8]; /*!< Reserved, Address offset: 0x60-0x7C */
384+ __IO uint32_t C2CR1; /*!< PWR Power Control Register 1 for CPU2, Address offset: 0x80 */
385+ __IO uint32_t C2CR3; /*!< PWR Power Control Register 3 for CPU2, Address offset: 0x84 */
386+ __IO uint32_t EXTSCR; /*!< PWR Power Status Reset Register for CPU2, Address offset: 0x88 */
387+} PWR_TypeDef;
388+
389+/**
390+ * @brief Reset and Clock Control
391+ */
392+typedef struct
393+{
394+ __IO uint32_t CR; /*!< RCC clock Control Register, Address offset: 0x00 */
395+ __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */
396+ __IO uint32_t CFGR; /*!< RCC Clocks Configuration Register, Address offset: 0x08 */
397+ __IO uint32_t PLLCFGR; /*!< RCC System PLL configuration Register, Address offset: 0x0C */
398+uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x10-0x14 */
399+ __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */
400+ __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */
401+ __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */
402+uint32_t RESERVED11; /*!< Reserved, Address offset: 0x24 */
403+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */
404+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */
405+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 & AHB4 peripheral reset register, Address offset: 0x30 */
406+uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */
407+ __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */
408+ __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */
409+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */
410+ __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x44 */
411+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */
412+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */
413+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 & AHB4 peripheral clocks enable register, Address offset: 0x50 */
414+uint32_t RESERVED2; /*!< Reserved, Address offset: 0x54 */
415+ __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */
416+ __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */
417+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */
418+uint32_t RESERVED3; /*!< Reserved, Address offset: 0x64 */
419+ __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */
420+ __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */
421+ __IO uint32_t AHB3SMENR; /*!< RCC AHB3 & AHB4 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */
422+uint32_t RESERVED4; /*!< Reserved, Address offset: 0x74 */
423+ __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
424+ __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
425+ __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
426+uint32_t RESERVED5; /*!< Reserved, Address offset: 0x84 */
427+ __IO uint32_t CCIPR; /*!< RCC Peripherals Clock Configuration Independent Register, Address offset: 0x88 */
428+uint32_t RESERVED6; /*!< Reserved, Address offset: 0x8C */
429+ __IO uint32_t BDCR; /*!< RCC Backup Domain Control Register, Address offset: 0x90 */
430+ __IO uint32_t CSR; /*!< RCC Control and Status Register, Address offset: 0x94 */
431+ __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register, Address offset: 0x98 */
432+ __IO uint32_t HSECR; /*!< RCC HSE Clock Register, Address offset: 0x9C */
433+uint32_t RESERVED7[26]; /*!< Reserved, Address offset: 0xA0-0x104 */
434+ __IO uint32_t EXTCFGR; /*!< RCC Extended Clock Recovery Register, Address offset: 0x108 */
435+uint32_t RESERVED8[15]; /*!< Reserved, Address offset: 0x10C-0x144 */
436+ __IO uint32_t C2AHB1ENR; /*!< RRCC AHB1 peripheral CPU2 clocks enable register, Address offset: 0x148 */
437+ __IO uint32_t C2AHB2ENR; /*!< RCC AHB2 peripheral CPU2 clocks enable register, Address offset: 0x14C */
438+ __IO uint32_t C2AHB3ENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable register,, Address offset: 0x150 */
439+uint32_t RESERVED9; /*!< Reserved, Address offset: 0x154 */
440+ __IO uint32_t C2APB1ENR1; /*!< RCC APB1 peripheral CPU2 clocks enable register 1, Address offset: 0x158 */
441+ __IO uint32_t C2APB1ENR2; /*!< RCC APB1 peripheral CPU2 clocks enable register 2, Address offset: 0x15C */
442+ __IO uint32_t C2APB2ENR; /*!< RCC APB2 peripheral CPU2 clocks enable register 1, Address offset: 0x160 */
443+ __IO uint32_t C2APB3ENR; /*!< RCC APB3 peripheral CPU2 clocks enable register 1, Address offset: 0x164 */
444+ __IO uint32_t C2AHB1SMENR; /*!< RCC AHB1 peripheral CPU2 clocks enable in sleep and stop modes register, Address offset: 0x168 */
445+ __IO uint32_t C2AHB2SMENR; /*!< RCC AHB2 peripheral CPU2 clocks enable in sleep and stop modes register, Address offset: 0x16C */
446+ __IO uint32_t C2AHB3SMENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable in sleep and stop modes register, Address offset: 0x170 */
447+uint32_t RESERVED10; /*!< Reserved, */
448+ __IO uint32_t C2APB1SMENR1; /*!< RCC APB1 peripheral CPU2 clocks enable in sleep mode and stop modes register 1, Address offset: 0x178 */
449+ __IO uint32_t C2APB1SMENR2; /*!< RCC APB1 peripheral CPU2 clocks enable in sleep mode and stop modes register 2, Address offset: 0x17C */
450+ __IO uint32_t C2APB2SMENR; /*!< RCC APB2 peripheral CPU2 clocks enable in sleep mode and stop modes register, Address offset: 0x180 */
451+ __IO uint32_t C2APB3SMENR; /*!< RCC APB3 peripheral CPU2 clocks enable in sleep mode and stop modes register, Address offset: 0x184 */
452+} RCC_TypeDef;
453+
454+
455+
456+/**
457+ * @brief Real-Time Clock
458+ */
459+typedef struct
460+{
461+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
462+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
463+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
464+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
465+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
466+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
467+ uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
468+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
469+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
470+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
471+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
472+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
473+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
474+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
475+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
476+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
477+ __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
478+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
479+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
480+ __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */
481+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
482+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
483+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
484+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
485+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
486+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
487+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
488+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
489+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
490+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
491+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
492+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
493+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
494+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
495+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
496+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
497+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
498+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
499+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
500+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
501+} RTC_TypeDef;
502+
503+
504+
505+
506+/**
507+ * @brief Serial Peripheral Interface
508+ */
509+typedef struct
510+{
511+ __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
512+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
513+ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
514+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
515+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
516+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
517+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
518+} SPI_TypeDef;
519+
520+/**
521+ * @brief System configuration controller
522+ */
523+typedef struct
524+{
525+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register Address offset: 0x00 */
526+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
527+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
528+ __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */
529+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */
530+ __IO uint32_t SWPR1; /*!< SYSCFG SRAM2 write protection register part 1, Address offset: 0x20 */
531+ __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */
532+ __IO uint32_t SWPR2; /*!< SYSCFG write protection register part 2, Address offset: 0x28 */
533+ uint32_t RESERVED1[53]; /*!< Reserved, Address offset: 0x2C-0xFC */
534+ __IO uint32_t IMR1; /*!< SYSCFG CPU1 (CORTEX M4) interrupt masks control-status register part 1, Address offset: 0x100 */
535+ __IO uint32_t IMR2; /*!< SYSCFG CPU1 (CORTEX M4) interrupt masks control-status register part 2, Address offset: 0x104 */
536+ __IO uint32_t C2IMR1; /*!< SYSCFG CPU2 (CORTEX M0) interrupt masks control-status register part 1, Address offset: 0x108 */
537+ __IO uint32_t C2IMR2; /*!< SYSCFG CPU2 (CORTEX M0) interrupt masks control-status register part 2, Address offset: 0x10C */
538+ __IO uint32_t SIPCR; /*!< SYSCFG secure IP control register, Address offset: 0x110 */
539+
540+} SYSCFG_TypeDef;
541+
542+/**
543+ * @brief TIM
544+ */
545+typedef struct
546+{
547+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
548+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
549+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
550+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
551+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
552+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
553+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
554+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
555+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
556+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
557+ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
558+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
559+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
560+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
561+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
562+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
563+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
564+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
565+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
566+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
567+ __IO uint32_t OR; /*!< TIM option register Address offset: 0x50 */
568+ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
569+ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
570+ __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
571+ __IO uint32_t AF1; /*!< TIM Alternate function option register 1, Address offset: 0x60 */
572+ __IO uint32_t AF2; /*!< TIM Alternate function option register 2, Address offset: 0x64 */
573+} TIM_TypeDef;
574+
575+/**
576+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
577+ */
578+typedef struct
579+{
580+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
581+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
582+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
583+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
584+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
585+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
586+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
587+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
588+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
589+ __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
590+ __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
591+ __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */
592+} USART_TypeDef;
593+
594+
595+/**
596+ * @brief Window WATCHDOG
597+ */
598+typedef struct
599+{
600+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
601+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
602+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
603+} WWDG_TypeDef;
604+
605+
606+/**
607+ * @brief AES hardware accelerator
608+ */
609+typedef struct
610+{
611+ __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */
612+ __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */
613+ __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */
614+ __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */
615+ __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */
616+ __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */
617+ __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */
618+ __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */
619+ __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */
620+ __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */
621+ __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */
622+ __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */
623+ __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */
624+ __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */
625+ __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */
626+ __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */
627+ __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */
628+ __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */
629+ __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */
630+ __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */
631+ __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */
632+ __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */
633+ __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */
634+ __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x6C */
635+} AES_TypeDef;
636+
637+/**
638+ * @brief RNG
639+ */
640+typedef struct
641+{
642+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
643+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
644+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
645+} RNG_TypeDef;
646+
647+/**
648+ * @brief Inter-Processor Communication
649+ */
650+typedef struct
651+{
652+ __IO uint32_t C1CR; /*!< Inter-Processor Communication: C1 control register, Address offset: 0x000 */
653+ __IO uint32_t C1MR ; /*!< Inter-Processor Communication: C1 mask register, Address offset: 0x004 */
654+ __IO uint32_t C1SCR; /*!< Inter-Processor Communication: C1 status set clear register, Address offset: 0x008 */
655+ __IO uint32_t C1TOC2SR; /*!< Inter-Processor Communication: C1 to processor M4 status register, Address offset: 0x00C */
656+ __IO uint32_t C2CR; /*!< Inter-Processor Communication: C2 control register, Address offset: 0x010 */
657+ __IO uint32_t C2MR ; /*!< Inter-Processor Communication: C2 mask register, Address offset: 0x014 */
658+ __IO uint32_t C2SCR; /*!< Inter-Processor Communication: C2 status set clear register, Address offset: 0x018 */
659+ __IO uint32_t C2TOC1SR; /*!< Inter-Processor Communication: C2 to processor M4 status register, Address offset: 0x01C */
660+} IPCC_TypeDef;
661+
662+typedef struct
663+{
664+ __IO uint32_t CR; /*!< Control register, Address offset: 0x000 */
665+ __IO uint32_t MR; /*!< Mask register, Address offset: 0x004 */
666+ __IO uint32_t SCR; /*!< Status set clear register, Address offset: 0x008 */
667+ __IO uint32_t SR; /*!< Status register, Address offset: 0x00C */
668+} IPCC_CommonTypeDef;
669+
670+/**
671+ * @brief Async Interrupts and Events Controller
672+ */
673+typedef struct
674+{
675+ __IO uint32_t RTSR1; /*!< EXTI rising trigger selection register [31:0], Address offset: 0x00 */
676+ __IO uint32_t FTSR1; /*!< EXTI falling trigger selection register [31:0], Address offset: 0x04 */
677+ __IO uint32_t SWIER1; /*!< EXTI software interrupt event register [31:0], Address offset: 0x08 */
678+ __IO uint32_t PR1; /*!< EXTI pending register [31:0], Address offset: 0x0C */
679+ __IO uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x10 - 0x1C */
680+ __IO uint32_t RTSR2; /*!< EXTI rising trigger selection register [31:0], Address offset: 0x20 */
681+ __IO uint32_t FTSR2; /*!< EXTI falling trigger selection register [31:0], Address offset: 0x24 */
682+ __IO uint32_t SWIER2; /*!< EXTI software interrupt event register [31:0], Address offset: 0x28 */
683+ __IO uint32_t PR2; /*!< EXTI pending register [31:0], Address offset: 0x2C */
684+ __IO uint32_t RESERVED2[4]; /*!< Reserved, Address offset: 0x30 - 0x3C */
685+ __IO uint32_t RESERVED3[8]; /*!< Reserved, Address offset: 0x40 - 0x5C */
686+ __IO uint32_t RESERVED4[8]; /*!< Reserved, Address offset: 0x60 - 0x7C */
687+ __IO uint32_t IMR1; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */
688+ __IO uint32_t EMR1; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x84 */
689+ __IO uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x88 - 0x8C */
690+ __IO uint32_t IMR2; /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */
691+ __IO uint32_t EMR2; /*!< EXTI wakeup with event mask register for cpu1 [31:0], Address offset: 0x94 */
692+ __IO uint32_t RESERVED8[10]; /*!< Reserved, Address offset: 0x98 - 0xBC */
693+ __IO uint32_t C2IMR1; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */
694+ __IO uint32_t C2EMR1; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xC4 */
695+ __IO uint32_t RESERVED9[2]; /*!< Reserved, Address offset: 0xC8 - 0xCC */
696+ __IO uint32_t C2IMR2; /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */
697+ __IO uint32_t C2EMR2; /*!< EXTI wakeup with event mask register for cpu2 [31:0], Address offset: 0xD4 */
698+}EXTI_TypeDef;
699+
700+/**
701+ * @brief Public Key Accelerator (PKA)
702+ */
703+typedef struct
704+{
705+ __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */
706+ __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */
707+ __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */
708+ uint32_t Reserved1[253]; /*!< Reserved Address offset: 0x000C-0x03FC*/
709+ __IO uint32_t RAM[894]; /*!< PKA RAM, Address offset: 0x0400-0x11F4 */
710+} PKA_TypeDef;
711+
712+/**
713+ * @brief HW Semaphore HSEM
714+ */
715+typedef struct
716+{
717+ __IO uint32_t R[32]; /*!< HSEM 2-step write lock and read back registers, Address offset: 00h-7Ch */
718+ __IO uint32_t RLR[32]; /*!< HSEM 1-step read lock registers, Address offset: 80h-FCh */
719+ __IO uint32_t C1IER; /*!< HSEM CPU1 interrupt enable register , Address offset: 100h */
720+ __IO uint32_t C1ICR; /*!< HSEM CPU1 interrupt clear register , Address offset: 104h */
721+ __IO uint32_t C1ISR; /*!< HSEM CPU1 interrupt status register , Address offset: 108h */
722+ __IO uint32_t C1MISR; /*!< HSEM CPU1 masked interrupt status register , Address offset: 10Ch */
723+ __IO uint32_t C2IER; /*!< HSEM CPU2 interrupt enable register , Address offset: 110h */
724+ __IO uint32_t C2ICR; /*!< HSEM CPU2 interrupt clear register , Address offset: 114h */
725+ __IO uint32_t C2ISR; /*!< HSEM CPU2 interrupt status register , Address offset: 118h */
726+ __IO uint32_t C2MISR; /*!< HSEM CPU2 masked interrupt status register , Address offset: 11Ch */
727+ uint32_t Reserved[8]; /*!< Reserved Address offset: 120h-13Ch*/
728+ __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */
729+ __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */
730+} HSEM_TypeDef;
731+
732+typedef struct
733+{
734+ __IO uint32_t IER; /*!< HSEM interrupt enable register , Address offset: 0h */
735+ __IO uint32_t ICR; /*!< HSEM interrupt clear register , Address offset: 4h */
736+ __IO uint32_t ISR; /*!< HSEM interrupt status register , Address offset: 8h */
737+ __IO uint32_t MISR; /*!< HSEM masked interrupt status register , Address offset: Ch */
738+} HSEM_Common_TypeDef;
739+
740+/**
741+ * @}
742+ */
743+
744+/** @addtogroup Peripheral_memory_map
745+ * @{
746+ */
747+
748+/*!< Boundary memory map */
749+#define FLASH_BASE (0x08000000UL)/*!< FLASH(up to 1 MB) base address */
750+#define SRAM_BASE (0x20000000UL)/*!< SRAM(up to 256 KB) base address */
751+#define PERIPH_BASE (0x40000000UL)/*!< Peripheral base address */
752+
753+/*!< Memory, OTP and Option bytes */
754+
755+/* Base addresses */
756+#define SYSTEM_MEMORY_BASE (0x1FFF0000UL) /*!< System Memory : 28Kb (0x1FFF0000 – 0x1FFF6FFF) */
757+#define OTP_AREA_BASE (0x1FFF7000UL) /*!< OTP area : 1kB (0x1FFF7000 – 0x1FFF73FF) */
758+#define OPTION_BYTE_BASE (0x1FFF8000UL) /*!< Option Bytes : 4kB (0x1FFF8000 – 0x1FFF8FFF) */
759+#define ENGI_BYTE_BASE (0x1FFF7400UL) /*!< Engi Bytes : 3kB (0x1FFF7400 – 0x1FFF7FFF) */
760+
761+#define SRAM1_BASE SRAM_BASE /*!< SRAM1(up to 32 KB) base address */
762+#define SRAM2A_BASE (SRAM_BASE + 0x00030000UL)/*!< SRAM2A(32 KB) base address */
763+#define SRAM2B_BASE (SRAM_BASE + 0x00038000UL)/*!< SRAM2B(32 KB) base address */
764+
765+/* Memory Size */
766+#define FLASH_SIZE (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0x07FFUL)) << 10U)
767+#define SRAM1_SIZE 0x00008000UL /*!< SRAM1 default size : 32 kB */
768+#define SRAM2A_SIZE 0x00008000UL /*!< SRAM2a default size : 32 kB */
769+#define SRAM2B_SIZE 0x00008000UL /*!< SRAM2b default size : 32 kB */
770+
771+/* End addresses */
772+#define SRAM1_END_ADDR (0x20007FFFUL) /*!< SRAM1 : 32KB (0x20000000 – 0x20007FFF) */
773+#define SRAM2A_END_ADDR (0x20037FFFUL) /*!< SRAM2a (backup) : 32KB (0x20030000 – 0x20037FFF) */
774+#define SRAM2B_END_ADDR (0x2003FFFFUL) /*!< SRAM2b (non-backup) : 32KB (0x20038000 – 0x2003FFFF) */
775+
776+#define SYSTEM_MEMORY_END_ADDR (0x1FFF6FFFUL) /*!< System Memory : 28KB (0x1FFF0000 – 0x1FFF6FFF) */
777+#define OTP_AREA_END_ADDR (0x1FFF73FFUL) /*!< OTP area : 1KB (0x1FFF7000 – 0x1FFF73FF) */
778+#define OPTION_BYTE_END_ADDR (0x1FFF8FFFUL) /*!< Option Bytes : 4KB (0x1FFF8000 – 0x1FFF8FFF) */
779+#define ENGI_BYTE_END_ADDR (0x1FFF7FFFUL) /*!< Engi Bytes : 3kB (0x1FFF7400 – 0x1FFF7FFF) */
780+
781+/*!< Peripheral memory map */
782+#define APB1PERIPH_BASE PERIPH_BASE
783+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
784+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
785+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)
786+#define AHB4PERIPH_BASE (PERIPH_BASE + 0x18000000UL)
787+#define APB3PERIPH_BASE (PERIPH_BASE + 0x20000000UL)
788+#define AHB3PERIPH_BASE (PERIPH_BASE + 0x50000000UL)
789+
790+/*!< APB1 peripherals */
791+#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL)
792+#define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL)
793+#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL)
794+#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL)
795+#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL)
796+#define LPTIM1_BASE (APB1PERIPH_BASE + 0x00007C00UL)
797+#define LPTIM2_BASE (APB1PERIPH_BASE + 0x00009400UL)
798+
799+/*!< APB2 peripherals */
800+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000UL)
801+#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL)
802+#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL)
803+#define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL)
804+#define TIM16_BASE (APB2PERIPH_BASE + 0x00004400UL)
805+#define TIM17_BASE (APB2PERIPH_BASE + 0x00004800UL)
806+
807+/*!< AHB1 peripherals */
808+#define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000UL)
809+#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x00000800UL)
810+#define CRC_BASE (AHB1PERIPH_BASE + 0x00003000UL)
811+
812+#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)
813+#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)
814+#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
815+#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
816+#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
817+#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL)
818+#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL)
819+
820+#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
821+#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL)
822+#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL)
823+#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000CUL)
824+#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010UL)
825+#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x00000014UL)
826+#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x00000018UL)
827+
828+#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL)
829+#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL)
830+#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL)
831+#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010CUL)
832+
833+#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL)
834+#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL)
835+
836+/*!< AHB2 peripherals */
837+#define IOPORT_BASE (AHB2PERIPH_BASE + 0x00000000UL)
838+#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL)
839+#define GPIOB_BASE (IOPORT_BASE + 0x00000400UL)
840+#define GPIOC_BASE (IOPORT_BASE + 0x00000800UL)
841+#define GPIOE_BASE (IOPORT_BASE + 0x00001000UL)
842+#define GPIOH_BASE (IOPORT_BASE + 0x00001C00UL)
843+
844+#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000UL)
845+#define ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300UL)
846+
847+/*!< AHB Shared peripherals */
848+#define RCC_BASE (AHB4PERIPH_BASE + 0x00000000UL)
849+#define PWR_BASE (AHB4PERIPH_BASE + 0x00000400UL)
850+#define EXTI_BASE (AHB4PERIPH_BASE + 0x00000800UL)
851+#define IPCC_BASE (AHB4PERIPH_BASE + 0x00000C00UL)
852+#define RNG_BASE (AHB4PERIPH_BASE + 0x00001000UL)
853+#define HSEM_BASE (AHB4PERIPH_BASE + 0x00001400UL)
854+#define AES2_BASE (AHB4PERIPH_BASE + 0x00001800UL)
855+#define PKA_BASE (AHB4PERIPH_BASE + 0x00002000UL)
856+#define FLASH_REG_BASE (AHB4PERIPH_BASE + 0x00004000UL)
857+
858+/* Debug MCU registers base address */
859+#define DBGMCU_BASE (0xE0042000UL)
860+
861+
862+/*!< AHB3 peripherals */
863+
864+/*!< Device Electronic Signature */
865+#define PACKAGE_BASE ((uint32_t)0x1FFF7500UL) /*!< Package data register base address */
866+#define UID64_BASE ((uint32_t)0x1FFF7580UL) /*!< 64-bit Unique device Identification */
867+#define UID_BASE ((uint32_t)0x1FFF7590UL) /*!< Unique device ID register base address */
868+#define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0UL) /*!< Flash size data register base address */
869+
870+/**
871+ * @}
872+ */
873+
874+/** @addtogroup Peripheral_declaration
875+ * @{
876+ */
877+
878+/* Peripherals available on APB1 bus */
879+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
880+#define RTC ((RTC_TypeDef *) RTC_BASE)
881+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
882+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
883+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
884+#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
885+#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
886+
887+/* Peripherals available on APB2 bus */
888+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
889+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
890+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
891+#define USART1 ((USART_TypeDef *) USART1_BASE)
892+#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
893+#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
894+
895+/* Peripherals available on AHB1 bus */
896+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
897+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
898+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
899+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
900+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
901+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
902+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
903+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
904+
905+#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
906+#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
907+#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
908+#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
909+#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
910+#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
911+#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
912+#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
913+
914+#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
915+#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
916+#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
917+#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
918+
919+#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
920+#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
921+
922+#define CRC ((CRC_TypeDef *) CRC_BASE)
923+
924+/* Peripherals available on AHB2 bus */
925+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
926+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
927+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
928+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
929+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
930+
931+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
932+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
933+
934+
935+/* Peripherals available on AHB shared bus */
936+#define RCC ((RCC_TypeDef *) RCC_BASE)
937+#define PWR ((PWR_TypeDef *) PWR_BASE)
938+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
939+#define IPCC ((IPCC_TypeDef *) IPCC_BASE)
940+#define IPCC_C1 ((IPCC_CommonTypeDef *) IPCC_BASE)
941+#define IPCC_C2 ((IPCC_CommonTypeDef *) (IPCC_BASE + 0x10U))
942+#define RNG ((RNG_TypeDef *) RNG_BASE)
943+#define HSEM ((HSEM_TypeDef *) HSEM_BASE)
944+#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100U))
945+#define AES2 ((AES_TypeDef *) AES2_BASE)
946+#define PKA ((PKA_TypeDef *) PKA_BASE)
947+#define FLASH ((FLASH_TypeDef *) FLASH_REG_BASE)
948+
949+/* Peripherals available on AHB3 bus */
950+
951+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
952+/**
953+ * @}
954+ */
955+
956+/** @addtogroup Exported_constants
957+ * @{
958+ */
959+
960+/** @addtogroup Peripheral_Registers_Bits_Definition
961+ * @{
962+ */
963+
964+/******************************************************************************/
965+/* Peripheral Registers Bits Definition */
966+/******************************************************************************/
967+
968+/******************************************************************************/
969+/* */
970+/* Analog to Digital Converter (ADC) */
971+/* */
972+/******************************************************************************/
973+
974+#define ADC_SUPPORT_5_MSPS /* ADC sampling rate 5 Msamples/sec */
975+
976+/******************** Bit definition for ADC_ISR register *******************/
977+#define ADC_ISR_ADRDY_Pos (0U)
978+#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
979+#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
980+#define ADC_ISR_EOSMP_Pos (1U)
981+#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
982+#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
983+#define ADC_ISR_EOC_Pos (2U)
984+#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
985+#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
986+#define ADC_ISR_EOS_Pos (3U)
987+#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
988+#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
989+#define ADC_ISR_OVR_Pos (4U)
990+#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
991+#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
992+#define ADC_ISR_JEOC_Pos (5U)
993+#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
994+#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */
995+#define ADC_ISR_JEOS_Pos (6U)
996+#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
997+#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
998+#define ADC_ISR_AWD1_Pos (7U)
999+#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
1000+#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
1001+#define ADC_ISR_AWD2_Pos (8U)
1002+#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
1003+#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */
1004+#define ADC_ISR_AWD3_Pos (9U)
1005+#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
1006+#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */
1007+#define ADC_ISR_JQOVF_Pos (10U)
1008+#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
1009+#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */
1010+
1011+/******************** Bit definition for ADC_IER register *******************/
1012+#define ADC_IER_ADRDYIE_Pos (0U)
1013+#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
1014+#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
1015+#define ADC_IER_EOSMPIE_Pos (1U)
1016+#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
1017+#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
1018+#define ADC_IER_EOCIE_Pos (2U)
1019+#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
1020+#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
1021+#define ADC_IER_EOSIE_Pos (3U)
1022+#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
1023+#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
1024+#define ADC_IER_OVRIE_Pos (4U)
1025+#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
1026+#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
1027+#define ADC_IER_JEOCIE_Pos (5U)
1028+#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
1029+#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */
1030+#define ADC_IER_JEOSIE_Pos (6U)
1031+#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
1032+#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
1033+#define ADC_IER_AWD1IE_Pos (7U)
1034+#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
1035+#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
1036+#define ADC_IER_AWD2IE_Pos (8U)
1037+#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
1038+#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */
1039+#define ADC_IER_AWD3IE_Pos (9U)
1040+#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
1041+#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */
1042+#define ADC_IER_JQOVFIE_Pos (10U)
1043+#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
1044+#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */
1045+
1046+/******************** Bit definition for ADC_CR register ********************/
1047+#define ADC_CR_ADEN_Pos (0U)
1048+#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
1049+#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
1050+#define ADC_CR_ADDIS_Pos (1U)
1051+#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
1052+#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
1053+#define ADC_CR_ADSTART_Pos (2U)
1054+#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
1055+#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
1056+#define ADC_CR_JADSTART_Pos (3U)
1057+#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
1058+#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */
1059+#define ADC_CR_ADSTP_Pos (4U)
1060+#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
1061+#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
1062+#define ADC_CR_JADSTP_Pos (5U)
1063+#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
1064+#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */
1065+#define ADC_CR_ADVREGEN_Pos (28U)
1066+#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
1067+#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */
1068+#define ADC_CR_DEEPPWD_Pos (29U)
1069+#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
1070+#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */
1071+#define ADC_CR_ADCALDIF_Pos (30U)
1072+#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
1073+#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */
1074+#define ADC_CR_ADCAL_Pos (31U)
1075+#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
1076+#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
1077+
1078+/******************** Bit definition for ADC_CFGR1 register *****************/
1079+#define ADC_CFGR_DMAEN_Pos (0U)
1080+#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */
1081+#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA enable */
1082+#define ADC_CFGR_DMACFG_Pos (1U)
1083+#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */
1084+#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA configuration */
1085+
1086+#define ADC_CFGR_RES_Pos (3U)
1087+#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */
1088+#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */
1089+#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
1090+#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
1091+
1092+#define ADC_CFGR_ALIGN_Pos (5U)
1093+#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
1094+#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
1095+
1096+#define ADC_CFGR_EXTSEL_Pos (6U)
1097+#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
1098+#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */
1099+#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
1100+#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
1101+#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
1102+#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
1103+
1104+#define ADC_CFGR_EXTEN_Pos (10U)
1105+#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
1106+#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */
1107+#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
1108+#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
1109+
1110+#define ADC_CFGR_OVRMOD_Pos (12U)
1111+#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
1112+#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */
1113+#define ADC_CFGR_CONT_Pos (13U)
1114+#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
1115+#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */
1116+#define ADC_CFGR_AUTDLY_Pos (14U)
1117+#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
1118+#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */
1119+
1120+#define ADC_CFGR_DISCEN_Pos (16U)
1121+#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
1122+#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
1123+
1124+#define ADC_CFGR_DISCNUM_Pos (17U)
1125+#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
1126+#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */
1127+#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
1128+#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
1129+#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
1130+
1131+#define ADC_CFGR_JDISCEN_Pos (20U)
1132+#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
1133+#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */
1134+#define ADC_CFGR_JQM_Pos (21U)
1135+#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
1136+#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */
1137+#define ADC_CFGR_AWD1SGL_Pos (22U)
1138+#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
1139+#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
1140+#define ADC_CFGR_AWD1EN_Pos (23U)
1141+#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
1142+#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
1143+#define ADC_CFGR_JAWD1EN_Pos (24U)
1144+#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
1145+#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
1146+#define ADC_CFGR_JAUTO_Pos (25U)
1147+#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
1148+#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
1149+
1150+#define ADC_CFGR_AWD1CH_Pos (26U)
1151+#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
1152+#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
1153+#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
1154+#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
1155+#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
1156+#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
1157+#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
1158+
1159+#define ADC_CFGR_JQDIS_Pos (31U)
1160+#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x00800000 */
1161+#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */
1162+
1163+/******************** Bit definition for ADC_CFGR2 register *****************/
1164+#define ADC_CFGR2_ROVSE_Pos (0U)
1165+#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
1166+#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */
1167+
1168+#define ADC_CFGR2_JOVSE_Pos (1U)
1169+#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
1170+#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */
1171+
1172+#define ADC_CFGR2_OVSR_Pos (2U)
1173+#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
1174+#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */
1175+#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
1176+#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
1177+#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
1178+
1179+#define ADC_CFGR2_OVSS_Pos (5U)
1180+#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
1181+#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */
1182+#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
1183+#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
1184+#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
1185+#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
1186+
1187+#define ADC_CFGR2_TROVS_Pos (9U)
1188+#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
1189+#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
1190+
1191+#define ADC_CFGR2_ROVSM_Pos (10U)
1192+#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
1193+#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
1194+
1195+/******************** Bit definition for ADC_SMPR1 register *****************/
1196+#define ADC_SMPR1_SMP0_Pos (0U)
1197+#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
1198+#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */
1199+#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
1200+#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
1201+#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
1202+
1203+#define ADC_SMPR1_SMP1_Pos (3U)
1204+#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
1205+#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */
1206+#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
1207+#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
1208+#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
1209+
1210+#define ADC_SMPR1_SMP2_Pos (6U)
1211+#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
1212+#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */
1213+#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
1214+#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
1215+#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
1216+
1217+#define ADC_SMPR1_SMP3_Pos (9U)
1218+#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
1219+#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */
1220+#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
1221+#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
1222+#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
1223+
1224+#define ADC_SMPR1_SMP4_Pos (12U)
1225+#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
1226+#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */
1227+#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
1228+#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
1229+#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
1230+
1231+#define ADC_SMPR1_SMP5_Pos (15U)
1232+#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
1233+#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */
1234+#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
1235+#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
1236+#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
1237+
1238+#define ADC_SMPR1_SMP6_Pos (18U)
1239+#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
1240+#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */
1241+#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
1242+#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
1243+#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
1244+
1245+#define ADC_SMPR1_SMP7_Pos (21U)
1246+#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
1247+#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */
1248+#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
1249+#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
1250+#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
1251+
1252+#define ADC_SMPR1_SMP8_Pos (24U)
1253+#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
1254+#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */
1255+#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
1256+#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
1257+#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
1258+
1259+#define ADC_SMPR1_SMP9_Pos (27U)
1260+#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
1261+#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */
1262+#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
1263+#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
1264+#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
1265+
1266+/******************** Bit definition for ADC_SMPR2 register *****************/
1267+#define ADC_SMPR2_SMP10_Pos (0U)
1268+#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
1269+#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */
1270+#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
1271+#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
1272+#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
1273+
1274+#define ADC_SMPR2_SMP11_Pos (3U)
1275+#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
1276+#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */
1277+#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
1278+#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
1279+#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
1280+
1281+#define ADC_SMPR2_SMP12_Pos (6U)
1282+#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
1283+#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */
1284+#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
1285+#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
1286+#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
1287+
1288+#define ADC_SMPR2_SMP13_Pos (9U)
1289+#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
1290+#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */
1291+#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
1292+#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
1293+#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
1294+
1295+#define ADC_SMPR2_SMP14_Pos (12U)
1296+#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
1297+#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */
1298+#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
1299+#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
1300+#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
1301+
1302+#define ADC_SMPR2_SMP15_Pos (15U)
1303+#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
1304+#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */
1305+#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
1306+#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
1307+#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
1308+
1309+#define ADC_SMPR2_SMP16_Pos (18U)
1310+#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
1311+#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */
1312+#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
1313+#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
1314+#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
1315+
1316+#define ADC_SMPR2_SMP17_Pos (21U)
1317+#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
1318+#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */
1319+#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
1320+#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
1321+#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
1322+
1323+#define ADC_SMPR2_SMP18_Pos (24U)
1324+#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
1325+#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */
1326+#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
1327+#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
1328+#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
1329+
1330+/******************** Bit definition for ADC_TR1 register *******************/
1331+#define ADC_TR1_LT1_Pos (0U)
1332+#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
1333+#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
1334+#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */
1335+#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */
1336+#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */
1337+#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */
1338+#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */
1339+#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */
1340+#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */
1341+#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */
1342+#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */
1343+#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */
1344+#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */
1345+#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */
1346+
1347+#define ADC_TR1_HT1_Pos (16U)
1348+#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
1349+#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
1350+#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */
1351+#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */
1352+#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */
1353+#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */
1354+#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */
1355+#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */
1356+#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */
1357+#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */
1358+#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */
1359+#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */
1360+#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */
1361+#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */
1362+
1363+/******************** Bit definition for ADC_TR2 register *******************/
1364+#define ADC_TR2_LT2_Pos (0U)
1365+#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */
1366+#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
1367+#define ADC_TR2_LT2_0 (0x01UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */
1368+#define ADC_TR2_LT2_1 (0x02UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */
1369+#define ADC_TR2_LT2_2 (0x04UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */
1370+#define ADC_TR2_LT2_3 (0x08UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */
1371+#define ADC_TR2_LT2_4 (0x10UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */
1372+#define ADC_TR2_LT2_5 (0x20UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */
1373+#define ADC_TR2_LT2_6 (0x40UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */
1374+#define ADC_TR2_LT2_7 (0x80UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */
1375+
1376+#define ADC_TR2_HT2_Pos (16U)
1377+#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */
1378+#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
1379+#define ADC_TR2_HT2_0 (0x01UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */
1380+#define ADC_TR2_HT2_1 (0x02UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */
1381+#define ADC_TR2_HT2_2 (0x04UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */
1382+#define ADC_TR2_HT2_3 (0x08UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */
1383+#define ADC_TR2_HT2_4 (0x10UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */
1384+#define ADC_TR2_HT2_5 (0x20UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */
1385+#define ADC_TR2_HT2_6 (0x40UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */
1386+#define ADC_TR2_HT2_7 (0x80UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */
1387+
1388+/******************** Bit definition for ADC_TR3 register *******************/
1389+#define ADC_TR3_LT3_Pos (0U)
1390+#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */
1391+#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
1392+#define ADC_TR3_LT3_0 (0x01UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */
1393+#define ADC_TR3_LT3_1 (0x02UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */
1394+#define ADC_TR3_LT3_2 (0x04UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */
1395+#define ADC_TR3_LT3_3 (0x08UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */
1396+#define ADC_TR3_LT3_4 (0x10UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */
1397+#define ADC_TR3_LT3_5 (0x20UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */
1398+#define ADC_TR3_LT3_6 (0x40UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */
1399+#define ADC_TR3_LT3_7 (0x80UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */
1400+
1401+#define ADC_TR3_HT3_Pos (16U)
1402+#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */
1403+#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
1404+#define ADC_TR3_HT3_0 (0x01UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */
1405+#define ADC_TR3_HT3_1 (0x02UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */
1406+#define ADC_TR3_HT3_2 (0x04UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */
1407+#define ADC_TR3_HT3_3 (0x08UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */
1408+#define ADC_TR3_HT3_4 (0x10UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */
1409+#define ADC_TR3_HT3_5 (0x20UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */
1410+#define ADC_TR3_HT3_6 (0x40UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */
1411+#define ADC_TR3_HT3_7 (0x80UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */
1412+
1413+/******************** Bit definition for ADC_SQR1 register ******************/
1414+#define ADC_SQR1_L_Pos (0U)
1415+#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
1416+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
1417+#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
1418+#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
1419+#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
1420+#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */
1421+
1422+#define ADC_SQR1_SQ1_Pos (6U)
1423+#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
1424+#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
1425+#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
1426+#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
1427+#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
1428+#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
1429+#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
1430+
1431+#define ADC_SQR1_SQ2_Pos (12U)
1432+#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
1433+#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
1434+#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
1435+#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
1436+#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
1437+#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
1438+#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
1439+
1440+#define ADC_SQR1_SQ3_Pos (18U)
1441+#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
1442+#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
1443+#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
1444+#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
1445+#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
1446+#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
1447+#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
1448+
1449+#define ADC_SQR1_SQ4_Pos (24U)
1450+#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
1451+#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
1452+#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
1453+#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
1454+#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
1455+#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
1456+#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
1457+
1458+/******************** Bit definition for ADC_SQR2 register ******************/
1459+#define ADC_SQR2_SQ5_Pos (0U)
1460+#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
1461+#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
1462+#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
1463+#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
1464+#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
1465+#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
1466+#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
1467+
1468+#define ADC_SQR2_SQ6_Pos (6U)
1469+#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
1470+#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
1471+#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
1472+#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
1473+#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
1474+#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
1475+#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
1476+
1477+#define ADC_SQR2_SQ7_Pos (12U)
1478+#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
1479+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
1480+#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
1481+#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
1482+#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
1483+#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
1484+#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
1485+
1486+#define ADC_SQR2_SQ8_Pos (18U)
1487+#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
1488+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
1489+#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
1490+#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
1491+#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
1492+#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
1493+#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
1494+
1495+#define ADC_SQR2_SQ9_Pos (24U)
1496+#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
1497+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
1498+#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
1499+#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
1500+#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
1501+#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
1502+#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
1503+
1504+/******************** Bit definition for ADC_SQR3 register ******************/
1505+#define ADC_SQR3_SQ10_Pos (0U)
1506+#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
1507+#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
1508+#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
1509+#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
1510+#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
1511+#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
1512+#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
1513+
1514+#define ADC_SQR3_SQ11_Pos (6U)
1515+#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
1516+#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */
1517+#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
1518+#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
1519+#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
1520+#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
1521+#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
1522+
1523+#define ADC_SQR3_SQ12_Pos (12U)
1524+#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
1525+#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
1526+#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
1527+#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
1528+#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
1529+#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
1530+#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
1531+
1532+#define ADC_SQR3_SQ13_Pos (18U)
1533+#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
1534+#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
1535+#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
1536+#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
1537+#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
1538+#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
1539+#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
1540+
1541+#define ADC_SQR3_SQ14_Pos (24U)
1542+#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
1543+#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
1544+#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
1545+#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
1546+#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
1547+#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
1548+#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
1549+
1550+/******************** Bit definition for ADC_SQR4 register ******************/
1551+#define ADC_SQR4_SQ15_Pos (0U)
1552+#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
1553+#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
1554+#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
1555+#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
1556+#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
1557+#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
1558+#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
1559+
1560+#define ADC_SQR4_SQ16_Pos (6U)
1561+#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
1562+#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
1563+#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
1564+#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
1565+#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
1566+#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
1567+#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
1568+
1569+/******************** Bit definition for ADC_DR register ********************/
1570+#define ADC_DR_RDATA_Pos (0U)
1571+#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */
1572+#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */
1573+#define ADC_DR_RDATA_0 (0x0001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */
1574+#define ADC_DR_RDATA_1 (0x0002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */
1575+#define ADC_DR_RDATA_2 (0x0004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */
1576+#define ADC_DR_RDATA_3 (0x0008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */
1577+#define ADC_DR_RDATA_4 (0x0010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */
1578+#define ADC_DR_RDATA_5 (0x0020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */
1579+#define ADC_DR_RDATA_6 (0x0040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */
1580+#define ADC_DR_RDATA_7 (0x0080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */
1581+#define ADC_DR_RDATA_8 (0x0100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */
1582+#define ADC_DR_RDATA_9 (0x0200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */
1583+#define ADC_DR_RDATA_10 (0x0400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */
1584+#define ADC_DR_RDATA_11 (0x0800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */
1585+#define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */
1586+#define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */
1587+#define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */
1588+#define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */
1589+
1590+/******************** Bit definition for ADC_JSQR register ******************/
1591+#define ADC_JSQR_JL_Pos (0U)
1592+#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
1593+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
1594+#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
1595+#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
1596+
1597+#define ADC_JSQR_JEXTSEL_Pos (2U)
1598+#define ADC_JSQR_JEXTSEL_Msk (0xFUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */
1599+#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */
1600+#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
1601+#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
1602+#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
1603+#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
1604+
1605+#define ADC_JSQR_JEXTEN_Pos (6U)
1606+#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */
1607+#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */
1608+#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */
1609+#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
1610+
1611+#define ADC_JSQR_JSQ1_Pos (8U)
1612+#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */
1613+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
1614+#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */
1615+#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
1616+#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
1617+#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
1618+#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
1619+
1620+#define ADC_JSQR_JSQ2_Pos (14U)
1621+#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */
1622+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
1623+#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */
1624+#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
1625+#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
1626+#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
1627+#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
1628+
1629+#define ADC_JSQR_JSQ3_Pos (20U)
1630+#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */
1631+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
1632+#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */
1633+#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
1634+#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
1635+#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
1636+#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
1637+
1638+#define ADC_JSQR_JSQ4_Pos (26U)
1639+#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */
1640+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
1641+#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */
1642+#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
1643+#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
1644+#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
1645+#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
1646+
1647+/******************** Bit definition for ADC_OFR1 register ******************/
1648+#define ADC_OFR1_OFFSET1_Pos (0U)
1649+#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */
1650+#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */
1651+#define ADC_OFR1_OFFSET1_0 (0x001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
1652+#define ADC_OFR1_OFFSET1_1 (0x002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
1653+#define ADC_OFR1_OFFSET1_2 (0x004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
1654+#define ADC_OFR1_OFFSET1_3 (0x008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
1655+#define ADC_OFR1_OFFSET1_4 (0x010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
1656+#define ADC_OFR1_OFFSET1_5 (0x020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
1657+#define ADC_OFR1_OFFSET1_6 (0x040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
1658+#define ADC_OFR1_OFFSET1_7 (0x080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
1659+#define ADC_OFR1_OFFSET1_8 (0x100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
1660+#define ADC_OFR1_OFFSET1_9 (0x200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
1661+#define ADC_OFR1_OFFSET1_10 (0x400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
1662+#define ADC_OFR1_OFFSET1_11 (0x800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
1663+
1664+#define ADC_OFR1_OFFSET1_CH_Pos (26U)
1665+#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
1666+#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */
1667+#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
1668+#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
1669+#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
1670+#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
1671+#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
1672+
1673+#define ADC_OFR1_OFFSET1_EN_Pos (31U)
1674+#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */
1675+#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */
1676+
1677+/******************** Bit definition for ADC_OFR2 register ******************/
1678+#define ADC_OFR2_OFFSET2_Pos (0U)
1679+#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */
1680+#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */
1681+#define ADC_OFR2_OFFSET2_0 (0x001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
1682+#define ADC_OFR2_OFFSET2_1 (0x002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
1683+#define ADC_OFR2_OFFSET2_2 (0x004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
1684+#define ADC_OFR2_OFFSET2_3 (0x008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
1685+#define ADC_OFR2_OFFSET2_4 (0x010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
1686+#define ADC_OFR2_OFFSET2_5 (0x020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
1687+#define ADC_OFR2_OFFSET2_6 (0x040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
1688+#define ADC_OFR2_OFFSET2_7 (0x080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
1689+#define ADC_OFR2_OFFSET2_8 (0x100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
1690+#define ADC_OFR2_OFFSET2_9 (0x200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
1691+#define ADC_OFR2_OFFSET2_10 (0x400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
1692+#define ADC_OFR2_OFFSET2_11 (0x800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
1693+
1694+#define ADC_OFR2_OFFSET2_CH_Pos (26U)
1695+#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
1696+#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */
1697+#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
1698+#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
1699+#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
1700+#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
1701+#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
1702+
1703+#define ADC_OFR2_OFFSET2_EN_Pos (31U)
1704+#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */
1705+#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */
1706+
1707+/******************** Bit definition for ADC_OFR3 register ******************/
1708+#define ADC_OFR3_OFFSET3_Pos (0U)
1709+#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */
1710+#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */
1711+#define ADC_OFR3_OFFSET3_0 (0x001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
1712+#define ADC_OFR3_OFFSET3_1 (0x002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
1713+#define ADC_OFR3_OFFSET3_2 (0x004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
1714+#define ADC_OFR3_OFFSET3_3 (0x008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
1715+#define ADC_OFR3_OFFSET3_4 (0x010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
1716+#define ADC_OFR3_OFFSET3_5 (0x020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
1717+#define ADC_OFR3_OFFSET3_6 (0x040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
1718+#define ADC_OFR3_OFFSET3_7 (0x080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
1719+#define ADC_OFR3_OFFSET3_8 (0x100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
1720+#define ADC_OFR3_OFFSET3_9 (0x200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
1721+#define ADC_OFR3_OFFSET3_10 (0x400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
1722+#define ADC_OFR3_OFFSET3_11 (0x800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
1723+
1724+#define ADC_OFR3_OFFSET3_CH_Pos (26U)
1725+#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
1726+#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */
1727+#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
1728+#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
1729+#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
1730+#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
1731+#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
1732+
1733+#define ADC_OFR3_OFFSET3_EN_Pos (31U)
1734+#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */
1735+#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */
1736+
1737+/******************** Bit definition for ADC_OFR4 register ******************/
1738+#define ADC_OFR4_OFFSET4_Pos (0U)
1739+#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */
1740+#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */
1741+#define ADC_OFR4_OFFSET4_0 (0x001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
1742+#define ADC_OFR4_OFFSET4_1 (0x002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
1743+#define ADC_OFR4_OFFSET4_2 (0x004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
1744+#define ADC_OFR4_OFFSET4_3 (0x008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
1745+#define ADC_OFR4_OFFSET4_4 (0x010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
1746+#define ADC_OFR4_OFFSET4_5 (0x020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
1747+#define ADC_OFR4_OFFSET4_6 (0x040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
1748+#define ADC_OFR4_OFFSET4_7 (0x080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
1749+#define ADC_OFR4_OFFSET4_8 (0x100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
1750+#define ADC_OFR4_OFFSET4_9 (0x200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
1751+#define ADC_OFR4_OFFSET4_10 (0x400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
1752+#define ADC_OFR4_OFFSET4_11 (0x800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
1753+
1754+#define ADC_OFR4_OFFSET4_CH_Pos (26U)
1755+#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
1756+#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */
1757+#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
1758+#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
1759+#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
1760+#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
1761+#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
1762+
1763+#define ADC_OFR4_OFFSET4_EN_Pos (31U)
1764+#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */
1765+#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */
1766+
1767+/******************** Bit definition for ADC_JDR1 register ******************/
1768+#define ADC_JDR1_JDATA_Pos (0U)
1769+#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
1770+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
1771+#define ADC_JDR1_JDATA_0 (0x0001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
1772+#define ADC_JDR1_JDATA_1 (0x0002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
1773+#define ADC_JDR1_JDATA_2 (0x0004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
1774+#define ADC_JDR1_JDATA_3 (0x0008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
1775+#define ADC_JDR1_JDATA_4 (0x0010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
1776+#define ADC_JDR1_JDATA_5 (0x0020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
1777+#define ADC_JDR1_JDATA_6 (0x0040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
1778+#define ADC_JDR1_JDATA_7 (0x0080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
1779+#define ADC_JDR1_JDATA_8 (0x0100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
1780+#define ADC_JDR1_JDATA_9 (0x0200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
1781+#define ADC_JDR1_JDATA_10 (0x0400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
1782+#define ADC_JDR1_JDATA_11 (0x0800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
1783+#define ADC_JDR1_JDATA_12 (0x1000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
1784+#define ADC_JDR1_JDATA_13 (0x2000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
1785+#define ADC_JDR1_JDATA_14 (0x4000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
1786+#define ADC_JDR1_JDATA_15 (0x8000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
1787+
1788+/******************** Bit definition for ADC_JDR2 register ******************/
1789+#define ADC_JDR2_JDATA_Pos (0U)
1790+#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
1791+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
1792+#define ADC_JDR2_JDATA_0 (0x0001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
1793+#define ADC_JDR2_JDATA_1 (0x0002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
1794+#define ADC_JDR2_JDATA_2 (0x0004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
1795+#define ADC_JDR2_JDATA_3 (0x0008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
1796+#define ADC_JDR2_JDATA_4 (0x0010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
1797+#define ADC_JDR2_JDATA_5 (0x0020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
1798+#define ADC_JDR2_JDATA_6 (0x0040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
1799+#define ADC_JDR2_JDATA_7 (0x0080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
1800+#define ADC_JDR2_JDATA_8 (0x0100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
1801+#define ADC_JDR2_JDATA_9 (0x0200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
1802+#define ADC_JDR2_JDATA_10 (0x0400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
1803+#define ADC_JDR2_JDATA_11 (0x0800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
1804+#define ADC_JDR2_JDATA_12 (0x1000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
1805+#define ADC_JDR2_JDATA_13 (0x2000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
1806+#define ADC_JDR2_JDATA_14 (0x4000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
1807+#define ADC_JDR2_JDATA_15 (0x8000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
1808+
1809+/******************** Bit definition for ADC_JDR3 register ******************/
1810+#define ADC_JDR3_JDATA_Pos (0U)
1811+#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
1812+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
1813+#define ADC_JDR3_JDATA_0 (0x0001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
1814+#define ADC_JDR3_JDATA_1 (0x0002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
1815+#define ADC_JDR3_JDATA_2 (0x0004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
1816+#define ADC_JDR3_JDATA_3 (0x0008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
1817+#define ADC_JDR3_JDATA_4 (0x0010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
1818+#define ADC_JDR3_JDATA_5 (0x0020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
1819+#define ADC_JDR3_JDATA_6 (0x0040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
1820+#define ADC_JDR3_JDATA_7 (0x0080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
1821+#define ADC_JDR3_JDATA_8 (0x0100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
1822+#define ADC_JDR3_JDATA_9 (0x0200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
1823+#define ADC_JDR3_JDATA_10 (0x0400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
1824+#define ADC_JDR3_JDATA_11 (0x0800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
1825+#define ADC_JDR3_JDATA_12 (0x1000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
1826+#define ADC_JDR3_JDATA_13 (0x2000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
1827+#define ADC_JDR3_JDATA_14 (0x4000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
1828+#define ADC_JDR3_JDATA_15 (0x8000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
1829+
1830+/******************** Bit definition for ADC_JDR4 register ******************/
1831+#define ADC_JDR4_JDATA_Pos (0U)
1832+#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
1833+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
1834+#define ADC_JDR4_JDATA_0 (0x0001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
1835+#define ADC_JDR4_JDATA_1 (0x0002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
1836+#define ADC_JDR4_JDATA_2 (0x0004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
1837+#define ADC_JDR4_JDATA_3 (0x0008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
1838+#define ADC_JDR4_JDATA_4 (0x0010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
1839+#define ADC_JDR4_JDATA_5 (0x0020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
1840+#define ADC_JDR4_JDATA_6 (0x0040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
1841+#define ADC_JDR4_JDATA_7 (0x0080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
1842+#define ADC_JDR4_JDATA_8 (0x0100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
1843+#define ADC_JDR4_JDATA_9 (0x0200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
1844+#define ADC_JDR4_JDATA_10 (0x0400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
1845+#define ADC_JDR4_JDATA_11 (0x0800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
1846+#define ADC_JDR4_JDATA_12 (0x1000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
1847+#define ADC_JDR4_JDATA_13 (0x2000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
1848+#define ADC_JDR4_JDATA_14 (0x4000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
1849+#define ADC_JDR4_JDATA_15 (0x8000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
1850+
1851+/******************** Bit definition for ADC_AWD2CR register ****************/
1852+#define ADC_AWD2CR_AWD2CH_Pos (0U)
1853+#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
1854+#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */
1855+#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
1856+#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
1857+#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
1858+#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
1859+#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
1860+#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
1861+#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
1862+#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
1863+#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
1864+#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
1865+#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
1866+#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
1867+#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
1868+#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
1869+#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
1870+#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
1871+#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
1872+#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
1873+#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
1874+
1875+/******************** Bit definition for ADC_AWD3CR register ****************/
1876+#define ADC_AWD3CR_AWD3CH_Pos (0U)
1877+#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
1878+#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */
1879+#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
1880+#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
1881+#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
1882+#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
1883+#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
1884+#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
1885+#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
1886+#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
1887+#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
1888+#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
1889+#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
1890+#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
1891+#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
1892+#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
1893+#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
1894+#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
1895+#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
1896+#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
1897+#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
1898+
1899+/******************** Bit definition for ADC_DIFSEL register ****************/
1900+#define ADC_DIFSEL_DIFSEL_Pos (0U)
1901+#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */
1902+#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */
1903+#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
1904+#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
1905+#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
1906+#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
1907+#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
1908+#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
1909+#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
1910+#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
1911+#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
1912+#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
1913+#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
1914+#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
1915+#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
1916+#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
1917+#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
1918+#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
1919+#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
1920+#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
1921+#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
1922+
1923+/******************** Bit definition for ADC_CALFACT register ***************/
1924+#define ADC_CALFACT_CALFACT_S_Pos (0U)
1925+#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */
1926+#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */
1927+#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
1928+#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
1929+#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
1930+#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
1931+#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
1932+#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
1933+#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
1934+
1935+#define ADC_CALFACT_CALFACT_D_Pos (16U)
1936+#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */
1937+#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */
1938+#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
1939+#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
1940+#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
1941+#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
1942+#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
1943+#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
1944+#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
1945+
1946+/************************* ADC Common registers *****************************/
1947+/******************** Bit definition for ADC_CCR register *******************/
1948+#define ADC_CCR_DUAL_Pos (0U)
1949+#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */
1950+#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */
1951+#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */
1952+#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */
1953+#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */
1954+#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */
1955+#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */
1956+
1957+#define ADC_CCR_DELAY_Pos (8U)
1958+#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
1959+#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */
1960+#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
1961+#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
1962+#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
1963+#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
1964+
1965+#define ADC_CCR_DMACFG_Pos (13U)
1966+#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */
1967+#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */
1968+
1969+#define ADC_CCR_MDMA_Pos (14U)
1970+#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */
1971+#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */
1972+#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */
1973+#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */
1974+
1975+#define ADC_CCR_CKMODE_Pos (16U)
1976+#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
1977+#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
1978+#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
1979+#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
1980+
1981+#define ADC_CCR_PRESC_Pos (18U)
1982+#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003A0000 */
1983+#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */
1984+#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00000100 */
1985+#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00000200 */
1986+#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00000400 */
1987+#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00000800 */
1988+
1989+#define ADC_CCR_VREFEN_Pos (22U)
1990+#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
1991+#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
1992+#define ADC_CCR_TSEN_Pos (23U)
1993+#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
1994+#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */
1995+#define ADC_CCR_VBATEN_Pos (24U)
1996+#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
1997+#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
1998+
1999+/* Legacy defines */
2000+#define ADC_CCR_MULTI (ADC_CCR_DUAL)
2001+#define ADC_CCR_MULTI_0 (ADC_CCR_DUAL_0)
2002+#define ADC_CCR_MULTI_1 (ADC_CCR_DUAL_1)
2003+#define ADC_CCR_MULTI_2 (ADC_CCR_DUAL_2)
2004+#define ADC_CCR_MULTI_3 (ADC_CCR_DUAL_3)
2005+#define ADC_CCR_MULTI_4 (ADC_CCR_DUAL_4)
2006+
2007+/******************************************************************************/
2008+/* */
2009+/* CRC calculation unit */
2010+/* */
2011+/******************************************************************************/
2012+/******************* Bit definition for CRC_DR register *********************/
2013+#define CRC_DR_DR_Pos (0U)
2014+#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
2015+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
2016+
2017+/******************* Bit definition for CRC_IDR register ********************/
2018+#define CRC_IDR_IDR_Pos (0U)
2019+#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
2020+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bits data register bits */
2021+
2022+/******************** Bit definition for CRC_CR register ********************/
2023+#define CRC_CR_RESET_Pos (0U)
2024+#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
2025+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
2026+#define CRC_CR_POLYSIZE_Pos (3U)
2027+#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
2028+#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
2029+#define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
2030+#define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
2031+#define CRC_CR_REV_IN_Pos (5U)
2032+#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
2033+#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
2034+#define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
2035+#define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
2036+#define CRC_CR_REV_OUT_Pos (7U)
2037+#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
2038+#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
2039+
2040+/******************* Bit definition for CRC_INIT register *******************/
2041+#define CRC_INIT_INIT_Pos (0U)
2042+#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
2043+#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
2044+
2045+/******************* Bit definition for CRC_POL register ********************/
2046+#define CRC_POL_POL_Pos (0U)
2047+#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
2048+#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
2049+
2050+/******************************************************************************/
2051+/* */
2052+/* Advanced Encryption Standard (AES) */
2053+/* */
2054+/******************************************************************************/
2055+/******************* Bit definition for AES_CR register *********************/
2056+#define AES_CR_EN_Pos (0U)
2057+#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */
2058+#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */
2059+#define AES_CR_DATATYPE_Pos (1U)
2060+#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */
2061+#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */
2062+#define AES_CR_DATATYPE_0 (0x1U << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */
2063+#define AES_CR_DATATYPE_1 (0x2U << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */
2064+
2065+#define AES_CR_MODE_Pos (3U)
2066+#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */
2067+#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */
2068+#define AES_CR_MODE_0 (0x1U << AES_CR_MODE_Pos) /*!< 0x00000008 */
2069+#define AES_CR_MODE_1 (0x2U << AES_CR_MODE_Pos) /*!< 0x00000010 */
2070+
2071+#define AES_CR_CHMOD_Pos (5U)
2072+#define AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos) /*!< 0x00010060 */
2073+#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */
2074+#define AES_CR_CHMOD_0 (0x001U << AES_CR_CHMOD_Pos) /*!< 0x00000020 */
2075+#define AES_CR_CHMOD_1 (0x002U << AES_CR_CHMOD_Pos) /*!< 0x00000040 */
2076+#define AES_CR_CHMOD_2 (0x800U << AES_CR_CHMOD_Pos) /*!< 0x00010000 */
2077+
2078+#define AES_CR_CCFC_Pos (7U)
2079+#define AES_CR_CCFC_Msk (0x1UL << AES_CR_CCFC_Pos) /*!< 0x00000080 */
2080+#define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */
2081+#define AES_CR_ERRC_Pos (8U)
2082+#define AES_CR_ERRC_Msk (0x1UL << AES_CR_ERRC_Pos) /*!< 0x00000100 */
2083+#define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */
2084+#define AES_CR_CCFIE_Pos (9U)
2085+#define AES_CR_CCFIE_Msk (0x1UL << AES_CR_CCFIE_Pos) /*!< 0x00000200 */
2086+#define AES_CR_CCFIE AES_CR_CCFIE_Msk /*!< Computation Complete Flag Interrupt Enable */
2087+#define AES_CR_ERRIE_Pos (10U)
2088+#define AES_CR_ERRIE_Msk (0x1UL << AES_CR_ERRIE_Pos) /*!< 0x00000400 */
2089+#define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */
2090+#define AES_CR_DMAINEN_Pos (11U)
2091+#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */
2092+#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */
2093+#define AES_CR_DMAOUTEN_Pos (12U)
2094+#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */
2095+#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */
2096+
2097+#define AES_CR_GCMPH_Pos (13U)
2098+#define AES_CR_GCMPH_Msk (0x3UL << AES_CR_GCMPH_Pos) /*!< 0x00006000 */
2099+#define AES_CR_GCMPH AES_CR_GCMPH_Msk /*!< GCM Phase */
2100+#define AES_CR_GCMPH_0 (0x1U << AES_CR_GCMPH_Pos) /*!< 0x00002000 */
2101+#define AES_CR_GCMPH_1 (0x2U << AES_CR_GCMPH_Pos) /*!< 0x00004000 */
2102+
2103+#define AES_CR_KEYSIZE_Pos (18U)
2104+#define AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */
2105+#define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */
2106+
2107+#define AES_CR_NPBLB_Pos (20U)
2108+#define AES_CR_NPBLB_Msk (0xFUL << AES_CR_NPBLB_Pos) /*!< 0x00F00000 */
2109+#define AES_CR_NPBLB AES_CR_NPBLB_Msk /*!< Number of padding bytes in last payload block */
2110+#define AES_CR_NPBLB_0 (0x1U << AES_CR_NPBLB_Pos) /*!< 0x00100000 */
2111+#define AES_CR_NPBLB_1 (0x2U << AES_CR_NPBLB_Pos) /*!< 0x00200000 */
2112+#define AES_CR_NPBLB_2 (0x4U << AES_CR_NPBLB_Pos) /*!< 0x00400000 */
2113+#define AES_CR_NPBLB_3 (0x8U << AES_CR_NPBLB_Pos) /*!< 0x00800000 */
2114+
2115+/******************* Bit definition for AES_SR register *********************/
2116+#define AES_SR_CCF_Pos (0U)
2117+#define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */
2118+#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */
2119+#define AES_SR_RDERR_Pos (1U)
2120+#define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */
2121+#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */
2122+#define AES_SR_WRERR_Pos (2U)
2123+#define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */
2124+#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */
2125+#define AES_SR_BUSY_Pos (3U)
2126+#define AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos) /*!< 0x00000008 */
2127+#define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */
2128+
2129+/******************* Bit definition for AES_DINR register *******************/
2130+#define AES_DINR_Pos (0U)
2131+#define AES_DINR_Msk (0xFFFFFFFFUL << AES_DINR_Pos) /*!< 0xFFFFFFFF */
2132+#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */
2133+
2134+/******************* Bit definition for AES_DOUTR register ******************/
2135+#define AES_DOUTR_Pos (0U)
2136+#define AES_DOUTR_Msk (0xFFFFFFFFUL << AES_DOUTR_Pos) /*!< 0xFFFFFFFF */
2137+#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */
2138+
2139+/******************* Bit definition for AES_KEYR0 register ******************/
2140+#define AES_KEYR0_Pos (0U)
2141+#define AES_KEYR0_Msk (0xFFFFFFFFUL << AES_KEYR0_Pos) /*!< 0xFFFFFFFF */
2142+#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */
2143+
2144+/******************* Bit definition for AES_KEYR1 register ******************/
2145+#define AES_KEYR1_Pos (0U)
2146+#define AES_KEYR1_Msk (0xFFFFFFFFUL << AES_KEYR1_Pos) /*!< 0xFFFFFFFF */
2147+#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */
2148+
2149+/******************* Bit definition for AES_KEYR2 register ******************/
2150+#define AES_KEYR2_Pos (0U)
2151+#define AES_KEYR2_Msk (0xFFFFFFFFUL << AES_KEYR2_Pos) /*!< 0xFFFFFFFF */
2152+#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */
2153+
2154+/******************* Bit definition for AES_KEYR3 register ******************/
2155+#define AES_KEYR3_Pos (0U)
2156+#define AES_KEYR3_Msk (0xFFFFFFFFUL << AES_KEYR3_Pos) /*!< 0xFFFFFFFF */
2157+#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */
2158+
2159+/******************* Bit definition for AES_KEYR4 register ******************/
2160+#define AES_KEYR4_Pos (0U)
2161+#define AES_KEYR4_Msk (0xFFFFFFFFUL << AES_KEYR4_Pos) /*!< 0xFFFFFFFF */
2162+#define AES_KEYR4 AES_KEYR4_Msk /*!< AES Key Register 4 */
2163+
2164+/******************* Bit definition for AES_KEYR5 register ******************/
2165+#define AES_KEYR5_Pos (0U)
2166+#define AES_KEYR5_Msk (0xFFFFFFFFUL << AES_KEYR5_Pos) /*!< 0xFFFFFFFF */
2167+#define AES_KEYR5 AES_KEYR5_Msk /*!< AES Key Register 5 */
2168+
2169+/******************* Bit definition for AES_KEYR6 register ******************/
2170+#define AES_KEYR6_Pos (0U)
2171+#define AES_KEYR6_Msk (0xFFFFFFFFUL << AES_KEYR6_Pos) /*!< 0xFFFFFFFF */
2172+#define AES_KEYR6 AES_KEYR6_Msk /*!< AES Key Register 6 */
2173+
2174+/******************* Bit definition for AES_KEYR7 register ******************/
2175+#define AES_KEYR7_Pos (0U)
2176+#define AES_KEYR7_Msk (0xFFFFFFFFUL << AES_KEYR7_Pos) /*!< 0xFFFFFFFF */
2177+#define AES_KEYR7 AES_KEYR7_Msk /*!< AES Key Register 7 */
2178+
2179+/******************* Bit definition for AES_IVR0 register ******************/
2180+#define AES_IVR0_Pos (0U)
2181+#define AES_IVR0_Msk (0xFFFFFFFFUL << AES_IVR0_Pos) /*!< 0xFFFFFFFF */
2182+#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */
2183+
2184+/******************* Bit definition for AES_IVR1 register ******************/
2185+#define AES_IVR1_Pos (0U)
2186+#define AES_IVR1_Msk (0xFFFFFFFFUL << AES_IVR1_Pos) /*!< 0xFFFFFFFF */
2187+#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */
2188+
2189+/******************* Bit definition for AES_IVR2 register ******************/
2190+#define AES_IVR2_Pos (0U)
2191+#define AES_IVR2_Msk (0xFFFFFFFFUL << AES_IVR2_Pos) /*!< 0xFFFFFFFF */
2192+#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */
2193+
2194+/******************* Bit definition for AES_IVR3 register ******************/
2195+#define AES_IVR3_Pos (0U)
2196+#define AES_IVR3_Msk (0xFFFFFFFFUL << AES_IVR3_Pos) /*!< 0xFFFFFFFF */
2197+#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */
2198+
2199+/******************* Bit definition for AES_SUSP0R register ******************/
2200+#define AES_SUSP0R_Pos (0U)
2201+#define AES_SUSP0R_Msk (0xFFFFFFFFUL << AES_SUSP0R_Pos) /*!< 0xFFFFFFFF */
2202+#define AES_SUSP0R AES_SUSP0R_Msk /*!< AES Suspend registers 0 */
2203+
2204+/******************* Bit definition for AES_SUSP1R register ******************/
2205+#define AES_SUSP1R_Pos (0U)
2206+#define AES_SUSP1R_Msk (0xFFFFFFFFUL << AES_SUSP1R_Pos) /*!< 0xFFFFFFFF */
2207+#define AES_SUSP1R AES_SUSP1R_Msk /*!< AES Suspend registers 1 */
2208+
2209+/******************* Bit definition for AES_SUSP2R register ******************/
2210+#define AES_SUSP2R_Pos (0U)
2211+#define AES_SUSP2R_Msk (0xFFFFFFFFUL << AES_SUSP2R_Pos) /*!< 0xFFFFFFFF */
2212+#define AES_SUSP2R AES_SUSP2R_Msk /*!< AES Suspend registers 2 */
2213+
2214+/******************* Bit definition for AES_SUSP3R register ******************/
2215+#define AES_SUSP3R_Pos (0U)
2216+#define AES_SUSP3R_Msk (0xFFFFFFFFUL << AES_SUSP3R_Pos) /*!< 0xFFFFFFFF */
2217+#define AES_SUSP3R AES_SUSP3R_Msk /*!< AES Suspend registers 3 */
2218+
2219+/******************* Bit definition for AES_SUSP4R register ******************/
2220+#define AES_SUSP4R_Pos (0U)
2221+#define AES_SUSP4R_Msk (0xFFFFFFFFUL << AES_SUSP4R_Pos) /*!< 0xFFFFFFFF */
2222+#define AES_SUSP4R AES_SUSP4R_Msk /*!< AES Suspend registers 4 */
2223+
2224+/******************* Bit definition for AES_SUSP5R register ******************/
2225+#define AES_SUSP5R_Pos (0U)
2226+#define AES_SUSP5R_Msk (0xFFFFFFFFUL << AES_SUSP5R_Pos) /*!< 0xFFFFFFFF */
2227+#define AES_SUSP5R AES_SUSP5R_Msk /*!< AES Suspend registers 5 */
2228+
2229+/******************* Bit definition for AES_SUSP6R register ******************/
2230+#define AES_SUSP6R_Pos (0U)
2231+#define AES_SUSP6R_Msk (0xFFFFFFFFUL << AES_SUSP6R_Pos) /*!< 0xFFFFFFFF */
2232+#define AES_SUSP6R AES_SUSP6R_Msk /*!< AES Suspend registers 6 */
2233+
2234+/******************* Bit definition for AES_SUSP7R register ******************/
2235+#define AES_SUSP7R_Pos (0U)
2236+#define AES_SUSP7R_Msk (0xFFFFFFFFUL << AES_SUSP7R_Pos) /*!< 0xFFFFFFFF */
2237+#define AES_SUSP7R AES_SUSP7R_Msk /*!< AES Suspend registers 7 */
2238+
2239+/******************************************************************************/
2240+/* */
2241+/* DMA Controller (DMA) */
2242+/* */
2243+/******************************************************************************/
2244+
2245+/******************* Bit definition for DMA_ISR register ********************/
2246+#define DMA_ISR_GIF1_Pos (0U)
2247+#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
2248+#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
2249+#define DMA_ISR_TCIF1_Pos (1U)
2250+#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
2251+#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
2252+#define DMA_ISR_HTIF1_Pos (2U)
2253+#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
2254+#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
2255+#define DMA_ISR_TEIF1_Pos (3U)
2256+#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
2257+#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
2258+#define DMA_ISR_GIF2_Pos (4U)
2259+#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
2260+#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
2261+#define DMA_ISR_TCIF2_Pos (5U)
2262+#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
2263+#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
2264+#define DMA_ISR_HTIF2_Pos (6U)
2265+#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
2266+#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
2267+#define DMA_ISR_TEIF2_Pos (7U)
2268+#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
2269+#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
2270+#define DMA_ISR_GIF3_Pos (8U)
2271+#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
2272+#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
2273+#define DMA_ISR_TCIF3_Pos (9U)
2274+#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
2275+#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
2276+#define DMA_ISR_HTIF3_Pos (10U)
2277+#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
2278+#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
2279+#define DMA_ISR_TEIF3_Pos (11U)
2280+#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
2281+#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
2282+#define DMA_ISR_GIF4_Pos (12U)
2283+#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
2284+#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
2285+#define DMA_ISR_TCIF4_Pos (13U)
2286+#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
2287+#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
2288+#define DMA_ISR_HTIF4_Pos (14U)
2289+#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
2290+#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
2291+#define DMA_ISR_TEIF4_Pos (15U)
2292+#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
2293+#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
2294+#define DMA_ISR_GIF5_Pos (16U)
2295+#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
2296+#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
2297+#define DMA_ISR_TCIF5_Pos (17U)
2298+#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
2299+#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
2300+#define DMA_ISR_HTIF5_Pos (18U)
2301+#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
2302+#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
2303+#define DMA_ISR_TEIF5_Pos (19U)
2304+#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
2305+#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
2306+#define DMA_ISR_GIF6_Pos (20U)
2307+#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
2308+#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
2309+#define DMA_ISR_TCIF6_Pos (21U)
2310+#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
2311+#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
2312+#define DMA_ISR_HTIF6_Pos (22U)
2313+#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
2314+#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
2315+#define DMA_ISR_TEIF6_Pos (23U)
2316+#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
2317+#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
2318+#define DMA_ISR_GIF7_Pos (24U)
2319+#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
2320+#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
2321+#define DMA_ISR_TCIF7_Pos (25U)
2322+#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
2323+#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
2324+#define DMA_ISR_HTIF7_Pos (26U)
2325+#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
2326+#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
2327+#define DMA_ISR_TEIF7_Pos (27U)
2328+#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
2329+#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
2330+
2331+/******************* Bit definition for DMA_IFCR register *******************/
2332+#define DMA_IFCR_CGIF1_Pos (0U)
2333+#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
2334+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
2335+#define DMA_IFCR_CTCIF1_Pos (1U)
2336+#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
2337+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
2338+#define DMA_IFCR_CHTIF1_Pos (2U)
2339+#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
2340+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
2341+#define DMA_IFCR_CTEIF1_Pos (3U)
2342+#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
2343+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
2344+#define DMA_IFCR_CGIF2_Pos (4U)
2345+#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
2346+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
2347+#define DMA_IFCR_CTCIF2_Pos (5U)
2348+#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
2349+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
2350+#define DMA_IFCR_CHTIF2_Pos (6U)
2351+#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
2352+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
2353+#define DMA_IFCR_CTEIF2_Pos (7U)
2354+#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
2355+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
2356+#define DMA_IFCR_CGIF3_Pos (8U)
2357+#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
2358+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
2359+#define DMA_IFCR_CTCIF3_Pos (9U)
2360+#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
2361+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
2362+#define DMA_IFCR_CHTIF3_Pos (10U)
2363+#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
2364+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
2365+#define DMA_IFCR_CTEIF3_Pos (11U)
2366+#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
2367+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
2368+#define DMA_IFCR_CGIF4_Pos (12U)
2369+#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
2370+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
2371+#define DMA_IFCR_CTCIF4_Pos (13U)
2372+#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
2373+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
2374+#define DMA_IFCR_CHTIF4_Pos (14U)
2375+#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
2376+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
2377+#define DMA_IFCR_CTEIF4_Pos (15U)
2378+#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
2379+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
2380+#define DMA_IFCR_CGIF5_Pos (16U)
2381+#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
2382+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
2383+#define DMA_IFCR_CTCIF5_Pos (17U)
2384+#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
2385+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
2386+#define DMA_IFCR_CHTIF5_Pos (18U)
2387+#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
2388+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
2389+#define DMA_IFCR_CTEIF5_Pos (19U)
2390+#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
2391+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
2392+#define DMA_IFCR_CGIF6_Pos (20U)
2393+#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
2394+#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
2395+#define DMA_IFCR_CTCIF6_Pos (21U)
2396+#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
2397+#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
2398+#define DMA_IFCR_CHTIF6_Pos (22U)
2399+#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
2400+#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
2401+#define DMA_IFCR_CTEIF6_Pos (23U)
2402+#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
2403+#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
2404+#define DMA_IFCR_CGIF7_Pos (24U)
2405+#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
2406+#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
2407+#define DMA_IFCR_CTCIF7_Pos (25U)
2408+#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
2409+#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
2410+#define DMA_IFCR_CHTIF7_Pos (26U)
2411+#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
2412+#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
2413+#define DMA_IFCR_CTEIF7_Pos (27U)
2414+#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
2415+#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
2416+
2417+/******************* Bit definition for DMA_CCR register ********************/
2418+#define DMA_CCR_EN_Pos (0U)
2419+#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
2420+#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
2421+#define DMA_CCR_TCIE_Pos (1U)
2422+#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
2423+#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
2424+#define DMA_CCR_HTIE_Pos (2U)
2425+#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
2426+#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
2427+#define DMA_CCR_TEIE_Pos (3U)
2428+#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
2429+#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
2430+#define DMA_CCR_DIR_Pos (4U)
2431+#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
2432+#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
2433+#define DMA_CCR_CIRC_Pos (5U)
2434+#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
2435+#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
2436+#define DMA_CCR_PINC_Pos (6U)
2437+#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
2438+#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
2439+#define DMA_CCR_MINC_Pos (7U)
2440+#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
2441+#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
2442+
2443+#define DMA_CCR_PSIZE_Pos (8U)
2444+#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
2445+#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
2446+#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
2447+#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
2448+
2449+#define DMA_CCR_MSIZE_Pos (10U)
2450+#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
2451+#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
2452+#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
2453+#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
2454+
2455+#define DMA_CCR_PL_Pos (12U)
2456+#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
2457+#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
2458+#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
2459+#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
2460+
2461+#define DMA_CCR_MEM2MEM_Pos (14U)
2462+#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
2463+#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
2464+
2465+/****************** Bit definition for DMA_CNDTR register *******************/
2466+#define DMA_CNDTR_NDT_Pos (0U)
2467+#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
2468+#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
2469+
2470+/****************** Bit definition for DMA_CPAR register ********************/
2471+#define DMA_CPAR_PA_Pos (0U)
2472+#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
2473+#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
2474+
2475+/****************** Bit definition for DMA_CMAR register ********************/
2476+#define DMA_CMAR_MA_Pos (0U)
2477+#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
2478+#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
2479+
2480+/******************************************************************************/
2481+/* */
2482+/* DMAMUX Controller */
2483+/* */
2484+/******************************************************************************/
2485+/******************** Bits definition for DMAMUX_CxCR register **************/
2486+#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
2487+#define DMAMUX_CxCR_DMAREQ_ID_Msk (0x3FUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x0000003F */
2488+#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk /*!< DMA Request ID */
2489+#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */
2490+#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */
2491+#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */
2492+#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */
2493+#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */
2494+#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20U << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */
2495+#define DMAMUX_CxCR_SOIE_Pos (8U)
2496+#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */
2497+#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */
2498+#define DMAMUX_CxCR_EGE_Pos (9U)
2499+#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */
2500+#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk /*!< Event generation interrupt enable */
2501+#define DMAMUX_CxCR_SE_Pos (16U)
2502+#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */
2503+#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk /*!< Synchronization enable */
2504+#define DMAMUX_CxCR_SPOL_Pos (17U)
2505+#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */
2506+#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk /*!< Synchronization polarity */
2507+#define DMAMUX_CxCR_SPOL_0 (0x1U << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */
2508+#define DMAMUX_CxCR_SPOL_1 (0x2U << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */
2509+#define DMAMUX_CxCR_NBREQ_Pos (19U)
2510+#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */
2511+#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk /*!< Number of request */
2512+#define DMAMUX_CxCR_NBREQ_0 (0x01U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */
2513+#define DMAMUX_CxCR_NBREQ_1 (0x02U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */
2514+#define DMAMUX_CxCR_NBREQ_2 (0x04U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */
2515+#define DMAMUX_CxCR_NBREQ_3 (0x08U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */
2516+#define DMAMUX_CxCR_NBREQ_4 (0x10U << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */
2517+#define DMAMUX_CxCR_SYNC_ID_Pos (24U)
2518+#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */
2519+#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk /*!< Synchronization ID */
2520+#define DMAMUX_CxCR_SYNC_ID_0 (0x01U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */
2521+#define DMAMUX_CxCR_SYNC_ID_1 (0x02U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */
2522+#define DMAMUX_CxCR_SYNC_ID_2 (0x04U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */
2523+#define DMAMUX_CxCR_SYNC_ID_3 (0x08U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */
2524+#define DMAMUX_CxCR_SYNC_ID_4 (0x10U << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */
2525+
2526+/******************* Bits definition for DMAMUX_CSR register **************/
2527+#define DMAMUX_CSR_SOF0_Pos (0U)
2528+#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */
2529+#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk /*!< Synchronization Overrun Flag 0 */
2530+#define DMAMUX_CSR_SOF1_Pos (1U)
2531+#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */
2532+#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk /*!< Synchronization Overrun Flag 1 */
2533+#define DMAMUX_CSR_SOF2_Pos (2U)
2534+#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */
2535+#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk /*!< Synchronization Overrun Flag 2 */
2536+#define DMAMUX_CSR_SOF3_Pos (3U)
2537+#define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */
2538+#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk /*!< Synchronization Overrun Flag 3 */
2539+#define DMAMUX_CSR_SOF4_Pos (4U)
2540+#define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */
2541+#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk /*!< Synchronization Overrun Flag 4 */
2542+#define DMAMUX_CSR_SOF5_Pos (5U)
2543+#define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos) /*!< 0x00000020 */
2544+#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk /*!< Synchronization Overrun Flag 5 */
2545+#define DMAMUX_CSR_SOF6_Pos (6U)
2546+#define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos) /*!< 0x00000040 */
2547+#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk /*!< Synchronization Overrun Flag 6 */
2548+
2549+/******************** Bits definition for DMAMUX_CFR register **************/
2550+#define DMAMUX_CFR_CSOF0_Pos (0U)
2551+#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */
2552+#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk /*!< Clear Overrun Flag 0 */
2553+#define DMAMUX_CFR_CSOF1_Pos (1U)
2554+#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */
2555+#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk /*!< Clear Overrun Flag 1 */
2556+#define DMAMUX_CFR_CSOF2_Pos (2U)
2557+#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */
2558+#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk /*!< Clear Overrun Flag 2 */
2559+#define DMAMUX_CFR_CSOF3_Pos (3U)
2560+#define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */
2561+#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk /*!< Clear Overrun Flag 3 */
2562+#define DMAMUX_CFR_CSOF4_Pos (4U)
2563+#define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */
2564+#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk /*!< Clear Overrun Flag 4 */
2565+#define DMAMUX_CFR_CSOF5_Pos (5U)
2566+#define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */
2567+#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk /*!< Clear Overrun Flag 5 */
2568+#define DMAMUX_CFR_CSOF6_Pos (6U)
2569+#define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */
2570+#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk /*!< Clear Overrun Flag 6 */
2571+
2572+/******************** Bits definition for DMAMUX_RGxCR register ************/
2573+#define DMAMUX_RGxCR_SIG_ID_Pos (0U)
2574+#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */
2575+#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk /*!< Signal ID */
2576+#define DMAMUX_RGxCR_SIG_ID_0 (0x01U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */
2577+#define DMAMUX_RGxCR_SIG_ID_1 (0x02U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */
2578+#define DMAMUX_RGxCR_SIG_ID_2 (0x04U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */
2579+#define DMAMUX_RGxCR_SIG_ID_3 (0x08U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */
2580+#define DMAMUX_RGxCR_SIG_ID_4 (0x10U << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */
2581+#define DMAMUX_RGxCR_OIE_Pos (8U)
2582+#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */
2583+#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk /*!< Overrun interrupt enable */
2584+#define DMAMUX_RGxCR_GE_Pos (16U)
2585+#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */
2586+#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk /*!< Generation enable */
2587+#define DMAMUX_RGxCR_GPOL_Pos (17U)
2588+#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */
2589+#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk /*!< Generation polarity */
2590+#define DMAMUX_RGxCR_GPOL_0 (0x1U << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */
2591+#define DMAMUX_RGxCR_GPOL_1 (0x2U << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */
2592+#define DMAMUX_RGxCR_GNBREQ_Pos (19U)
2593+#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */
2594+#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk /*!< Number of request */
2595+#define DMAMUX_RGxCR_GNBREQ_0 (0x01U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */
2596+#define DMAMUX_RGxCR_GNBREQ_1 (0x02U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */
2597+#define DMAMUX_RGxCR_GNBREQ_2 (0x04U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */
2598+#define DMAMUX_RGxCR_GNBREQ_3 (0x08U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */
2599+#define DMAMUX_RGxCR_GNBREQ_4 (0x10U << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */
2600+
2601+/******************** Bits definition for DMAMUX_RGSR register **************/
2602+#define DMAMUX_RGSR_OF0_Pos (0U)
2603+#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */
2604+#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk /*!< Overrun flag 0 */
2605+#define DMAMUX_RGSR_OF1_Pos (1U)
2606+#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */
2607+#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk /*!< Overrun flag 1 */
2608+#define DMAMUX_RGSR_OF2_Pos (2U)
2609+#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */
2610+#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk /*!< Overrun flag 2 */
2611+#define DMAMUX_RGSR_OF3_Pos (3U)
2612+#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */
2613+#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk /*!< Overrun flag 3 */
2614+
2615+/******************** Bits definition for DMAMUX_RGCFR register **************/
2616+#define DMAMUX_RGCFR_COF0_Pos (0U)
2617+#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */
2618+#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk /*!< Clear Overrun flag 0 */
2619+#define DMAMUX_RGCFR_COF1_Pos (1U)
2620+#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */
2621+#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk /*!< Clear Overrun flag 1 */
2622+#define DMAMUX_RGCFR_COF2_Pos (2U)
2623+#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */
2624+#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk /*!< Clear Overrun flag 2 */
2625+#define DMAMUX_RGCFR_COF3_Pos (3U)
2626+#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */
2627+#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Clear Overrun flag 3 */
2628+
2629+/******************************************************************************/
2630+/* */
2631+/* External Interrupt/Event Controller */
2632+/* */
2633+/******************************************************************************/
2634+
2635+/****************** Bit definition for EXTI_RTSR1 register ******************/
2636+#define EXTI_RTSR1_RT_Pos (0U)
2637+#define EXTI_RTSR1_RT_Msk (0x803FFFFFUL << EXTI_RTSR1_RT_Pos) /*!< 0x803FFFFF */
2638+#define EXTI_RTSR1_RT EXTI_RTSR1_RT_Msk /*!< Rising trigger event configuration bit */
2639+#define EXTI_RTSR1_RT0_Pos (0U)
2640+#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */
2641+#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
2642+#define EXTI_RTSR1_RT1_Pos (1U)
2643+#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */
2644+#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
2645+#define EXTI_RTSR1_RT2_Pos (2U)
2646+#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */
2647+#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
2648+#define EXTI_RTSR1_RT3_Pos (3U)
2649+#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */
2650+#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
2651+#define EXTI_RTSR1_RT4_Pos (4U)
2652+#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */
2653+#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
2654+#define EXTI_RTSR1_RT5_Pos (5U)
2655+#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */
2656+#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
2657+#define EXTI_RTSR1_RT6_Pos (6U)
2658+#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */
2659+#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
2660+#define EXTI_RTSR1_RT7_Pos (7U)
2661+#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */
2662+#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
2663+#define EXTI_RTSR1_RT8_Pos (8U)
2664+#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */
2665+#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
2666+#define EXTI_RTSR1_RT9_Pos (9U)
2667+#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */
2668+#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
2669+#define EXTI_RTSR1_RT10_Pos (10U)
2670+#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */
2671+#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
2672+#define EXTI_RTSR1_RT11_Pos (11U)
2673+#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */
2674+#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
2675+#define EXTI_RTSR1_RT12_Pos (12U)
2676+#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */
2677+#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
2678+#define EXTI_RTSR1_RT13_Pos (13U)
2679+#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */
2680+#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
2681+#define EXTI_RTSR1_RT14_Pos (14U)
2682+#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */
2683+#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
2684+#define EXTI_RTSR1_RT15_Pos (15U)
2685+#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */
2686+#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
2687+#define EXTI_RTSR1_RT16_Pos (16U)
2688+#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */
2689+#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
2690+#define EXTI_RTSR1_RT17_Pos (17U)
2691+#define EXTI_RTSR1_RT17_Msk (0x1UL << EXTI_RTSR1_RT17_Pos) /*!< 0x00020000 */
2692+#define EXTI_RTSR1_RT17 EXTI_RTSR1_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */
2693+#define EXTI_RTSR1_RT18_Pos (18U)
2694+#define EXTI_RTSR1_RT18_Msk (0x1UL << EXTI_RTSR1_RT18_Pos) /*!< 0x00040000 */
2695+#define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk /*!< Rising trigger event configuration bit of line 18 */
2696+#define EXTI_RTSR1_RT19_Pos (19U)
2697+#define EXTI_RTSR1_RT19_Msk (0x1UL << EXTI_RTSR1_RT19_Pos) /*!< 0x00080000 */
2698+#define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
2699+
2700+/****************** Bit definition for EXTI_FTSR1 register ******************/
2701+#define EXTI_FTSR1_FT_Pos (0U)
2702+#define EXTI_FTSR1_FT_Msk (0x803FFFFFUL << EXTI_FTSR1_FT_Pos) /*!< 0x803FFFFF */
2703+#define EXTI_FTSR1_FT EXTI_FTSR1_FT_Msk /*!< Falling trigger event configuration bit */
2704+#define EXTI_FTSR1_FT0_Pos (0U)
2705+#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */
2706+#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
2707+#define EXTI_FTSR1_FT1_Pos (1U)
2708+#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */
2709+#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
2710+#define EXTI_FTSR1_FT2_Pos (2U)
2711+#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */
2712+#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
2713+#define EXTI_FTSR1_FT3_Pos (3U)
2714+#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */
2715+#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
2716+#define EXTI_FTSR1_FT4_Pos (4U)
2717+#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */
2718+#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
2719+#define EXTI_FTSR1_FT5_Pos (5U)
2720+#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */
2721+#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
2722+#define EXTI_FTSR1_FT6_Pos (6U)
2723+#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */
2724+#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
2725+#define EXTI_FTSR1_FT7_Pos (7U)
2726+#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */
2727+#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
2728+#define EXTI_FTSR1_FT8_Pos (8U)
2729+#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */
2730+#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
2731+#define EXTI_FTSR1_FT9_Pos (9U)
2732+#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */
2733+#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
2734+#define EXTI_FTSR1_FT10_Pos (10U)
2735+#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */
2736+#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
2737+#define EXTI_FTSR1_FT11_Pos (11U)
2738+#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */
2739+#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
2740+#define EXTI_FTSR1_FT12_Pos (12U)
2741+#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */
2742+#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
2743+#define EXTI_FTSR1_FT13_Pos (13U)
2744+#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */
2745+#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
2746+#define EXTI_FTSR1_FT14_Pos (14U)
2747+#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */
2748+#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
2749+#define EXTI_FTSR1_FT15_Pos (15U)
2750+#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */
2751+#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
2752+#define EXTI_FTSR1_FT16_Pos (16U)
2753+#define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */
2754+#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
2755+#define EXTI_FTSR1_FT17_Pos (17U)
2756+#define EXTI_FTSR1_FT17_Msk (0x1UL << EXTI_FTSR1_FT17_Pos) /*!< 0x00020000 */
2757+#define EXTI_FTSR1_FT17 EXTI_FTSR1_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */
2758+#define EXTI_FTSR1_FT18_Pos (18U)
2759+#define EXTI_FTSR1_FT18_Msk (0x1UL << EXTI_FTSR1_FT18_Pos) /*!< 0x00040000 */
2760+#define EXTI_FTSR1_FT18 EXTI_FTSR1_FT18_Msk /*!< Falling trigger event configuration bit of line 18 */
2761+#define EXTI_FTSR1_FT19_Pos (19U)
2762+#define EXTI_FTSR1_FT19_Msk (0x1UL << EXTI_FTSR1_FT19_Pos) /*!< 0x00080000 */
2763+#define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
2764+
2765+/****************** Bit definition for EXTI_SWIER1 register *****************/
2766+#define EXTI_SWIER1_SWI_Pos (0U)
2767+#define EXTI_SWIER1_SWI_Msk (0x803FFFFFUL << EXTI_SWIER1_SWI_Pos) /*!< 0x803FFFFF */
2768+#define EXTI_SWIER1_SWI EXTI_SWIER1_SWI_Msk /*!< Software interrupt */
2769+#define EXTI_SWIER1_SWI0_Pos (0U)
2770+#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */
2771+#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */
2772+#define EXTI_SWIER1_SWI1_Pos (1U)
2773+#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */
2774+#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */
2775+#define EXTI_SWIER1_SWI2_Pos (2U)
2776+#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */
2777+#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */
2778+#define EXTI_SWIER1_SWI3_Pos (3U)
2779+#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */
2780+#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */
2781+#define EXTI_SWIER1_SWI4_Pos (4U)
2782+#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */
2783+#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */
2784+#define EXTI_SWIER1_SWI5_Pos (5U)
2785+#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */
2786+#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */
2787+#define EXTI_SWIER1_SWI6_Pos (6U)
2788+#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */
2789+#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */
2790+#define EXTI_SWIER1_SWI7_Pos (7U)
2791+#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */
2792+#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */
2793+#define EXTI_SWIER1_SWI8_Pos (8U)
2794+#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */
2795+#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */
2796+#define EXTI_SWIER1_SWI9_Pos (9U)
2797+#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */
2798+#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */
2799+#define EXTI_SWIER1_SWI10_Pos (10U)
2800+#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */
2801+#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */
2802+#define EXTI_SWIER1_SWI11_Pos (11U)
2803+#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */
2804+#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */
2805+#define EXTI_SWIER1_SWI12_Pos (12U)
2806+#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */
2807+#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */
2808+#define EXTI_SWIER1_SWI13_Pos (13U)
2809+#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */
2810+#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */
2811+#define EXTI_SWIER1_SWI14_Pos (14U)
2812+#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */
2813+#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */
2814+#define EXTI_SWIER1_SWI15_Pos (15U)
2815+#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */
2816+#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */
2817+#define EXTI_SWIER1_SWI16_Pos (16U)
2818+#define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */
2819+#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */
2820+#define EXTI_SWIER1_SWI17_Pos (17U)
2821+#define EXTI_SWIER1_SWI17_Msk (0x1UL << EXTI_SWIER1_SWI17_Pos) /*!< 0x00020000 */
2822+#define EXTI_SWIER1_SWI17 EXTI_SWIER1_SWI17_Msk /*!< Software Interrupt on line 17 */
2823+#define EXTI_SWIER1_SWI18_Pos (18U)
2824+#define EXTI_SWIER1_SWI18_Msk (0x1UL << EXTI_SWIER1_SWI18_Pos) /*!< 0x00040000 */
2825+#define EXTI_SWIER1_SWI18 EXTI_SWIER1_SWI18_Msk /*!< Software Interrupt on line 18 */
2826+#define EXTI_SWIER1_SWI19_Pos (19U)
2827+#define EXTI_SWIER1_SWI19_Msk (0x1UL << EXTI_SWIER1_SWI19_Pos) /*!< 0x00080000 */
2828+#define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk /*!< Software Interrupt on line 19 */
2829+
2830+/******************* Bit definition for EXTI_PR1 register *******************/
2831+#define EXTI_PR1_PIF_Pos (0U)
2832+#define EXTI_PR1_PIF_Msk (0x803FFFFFUL << EXTI_PR1_PIF_Pos) /*!< 0x803FFFFF */
2833+#define EXTI_PR1_PIF EXTI_PR1_PIF_Msk /*!< Pending bit */
2834+#define EXTI_PR1_PIF0_Pos (0U)
2835+#define EXTI_PR1_PIF0_Msk (0x1UL << EXTI_PR1_PIF0_Pos) /*!< 0x00000001 */
2836+#define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk /*!< Pending bit for line 0 */
2837+#define EXTI_PR1_PIF1_Pos (1U)
2838+#define EXTI_PR1_PIF1_Msk (0x1UL << EXTI_PR1_PIF1_Pos) /*!< 0x00000002 */
2839+#define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk /*!< Pending bit for line 1 */
2840+#define EXTI_PR1_PIF2_Pos (2U)
2841+#define EXTI_PR1_PIF2_Msk (0x1UL << EXTI_PR1_PIF2_Pos) /*!< 0x00000004 */
2842+#define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk /*!< Pending bit for line 2 */
2843+#define EXTI_PR1_PIF3_Pos (3U)
2844+#define EXTI_PR1_PIF3_Msk (0x1UL << EXTI_PR1_PIF3_Pos) /*!< 0x00000008 */
2845+#define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk /*!< Pending bit for line 3 */
2846+#define EXTI_PR1_PIF4_Pos (4U)
2847+#define EXTI_PR1_PIF4_Msk (0x1UL << EXTI_PR1_PIF4_Pos) /*!< 0x00000010 */
2848+#define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk /*!< Pending bit for line 4 */
2849+#define EXTI_PR1_PIF5_Pos (5U)
2850+#define EXTI_PR1_PIF5_Msk (0x1UL << EXTI_PR1_PIF5_Pos) /*!< 0x00000020 */
2851+#define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk /*!< Pending bit for line 5 */
2852+#define EXTI_PR1_PIF6_Pos (6U)
2853+#define EXTI_PR1_PIF6_Msk (0x1UL << EXTI_PR1_PIF6_Pos) /*!< 0x00000040 */
2854+#define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk /*!< Pending bit for line 6 */
2855+#define EXTI_PR1_PIF7_Pos (7U)
2856+#define EXTI_PR1_PIF7_Msk (0x1UL << EXTI_PR1_PIF7_Pos) /*!< 0x00000080 */
2857+#define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk /*!< Pending bit for line 7 */
2858+#define EXTI_PR1_PIF8_Pos (8U)
2859+#define EXTI_PR1_PIF8_Msk (0x1UL << EXTI_PR1_PIF8_Pos) /*!< 0x00000100 */
2860+#define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk /*!< Pending bit for line 8 */
2861+#define EXTI_PR1_PIF9_Pos (9U)
2862+#define EXTI_PR1_PIF9_Msk (0x1UL << EXTI_PR1_PIF9_Pos) /*!< 0x00000200 */
2863+#define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk /*!< Pending bit for line 9 */
2864+#define EXTI_PR1_PIF10_Pos (10U)
2865+#define EXTI_PR1_PIF10_Msk (0x1UL << EXTI_PR1_PIF10_Pos) /*!< 0x00000400 */
2866+#define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk /*!< Pending bit for line 10 */
2867+#define EXTI_PR1_PIF11_Pos (11U)
2868+#define EXTI_PR1_PIF11_Msk (0x1UL << EXTI_PR1_PIF11_Pos) /*!< 0x00000800 */
2869+#define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk /*!< Pending bit for line 11 */
2870+#define EXTI_PR1_PIF12_Pos (12U)
2871+#define EXTI_PR1_PIF12_Msk (0x1UL << EXTI_PR1_PIF12_Pos) /*!< 0x00001000 */
2872+#define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk /*!< Pending bit for line 12 */
2873+#define EXTI_PR1_PIF13_Pos (13U)
2874+#define EXTI_PR1_PIF13_Msk (0x1UL << EXTI_PR1_PIF13_Pos) /*!< 0x00002000 */
2875+#define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk /*!< Pending bit for line 13 */
2876+#define EXTI_PR1_PIF14_Pos (14U)
2877+#define EXTI_PR1_PIF14_Msk (0x1UL << EXTI_PR1_PIF14_Pos) /*!< 0x00004000 */
2878+#define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk /*!< Pending bit for line 14 */
2879+#define EXTI_PR1_PIF15_Pos (15U)
2880+#define EXTI_PR1_PIF15_Msk (0x1UL << EXTI_PR1_PIF15_Pos) /*!< 0x00008000 */
2881+#define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk /*!< Pending bit for line 15 */
2882+#define EXTI_PR1_PIF16_Pos (16U)
2883+#define EXTI_PR1_PIF16_Msk (0x1UL << EXTI_PR1_PIF16_Pos) /*!< 0x00010000 */
2884+#define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk /*!< Pending bit for line 16 */
2885+#define EXTI_PR1_PIF17_Pos (17U)
2886+#define EXTI_PR1_PIF17_Msk (0x1UL << EXTI_PR1_PIF17_Pos) /*!< 0x00020000 */
2887+#define EXTI_PR1_PIF17 EXTI_PR1_PIF17_Msk /*!< Pending bit for line 17 */
2888+#define EXTI_PR1_PIF18_Pos (18U)
2889+#define EXTI_PR1_PIF18_Msk (0x1UL << EXTI_PR1_PIF18_Pos) /*!< 0x00040000 */
2890+#define EXTI_PR1_PIF18 EXTI_PR1_PIF18_Msk /*!< Pending bit for line 18 */
2891+#define EXTI_PR1_PIF19_Pos (19U)
2892+#define EXTI_PR1_PIF19_Msk (0x1UL << EXTI_PR1_PIF19_Pos) /*!< 0x00080000 */
2893+#define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk /*!< Pending bit for line 19 */
2894+
2895+/****************** Bit definition for EXTI_RTSR2 register ******************/
2896+#define EXTI_RTSR2_RT_Pos (0U)
2897+#define EXTI_RTSR2_RT_Msk (0x302UL << EXTI_RTSR2_RT_Pos) /*!< 0x00000302 */
2898+#define EXTI_RTSR2_RT EXTI_RTSR2_RT_Msk /*!< Rising trigger event configuration bit */
2899+#define EXTI_RTSR2_RT33_Pos (1U)
2900+#define EXTI_RTSR2_RT33_Msk (0x1UL << EXTI_RTSR2_RT33_Pos) /*!< 0x00000002 */
2901+#define EXTI_RTSR2_RT33 EXTI_RTSR2_RT33_Msk /*!< Rising trigger event configuration bit of line 33 */
2902+#define EXTI_RTSR2_RT40_Pos (8U)
2903+#define EXTI_RTSR2_RT40_Msk (0x1UL << EXTI_RTSR2_RT40_Pos) /*!< 0x00000100 */
2904+#define EXTI_RTSR2_RT40 EXTI_RTSR2_RT40_Msk /*!< Rising trigger event configuration bit of line 40 */
2905+#define EXTI_RTSR2_RT41_Pos (9U)
2906+#define EXTI_RTSR2_RT41_Msk (0x1UL << EXTI_RTSR2_RT41_Pos) /*!< 0x00000200 */
2907+#define EXTI_RTSR2_RT41 EXTI_RTSR2_RT41_Msk /*!< Rising trigger event configuration bit of line 41 */
2908+
2909+/****************** Bit definition for EXTI_FTSR2 register ******************/
2910+#define EXTI_FTSR2_FT_Pos (0U)
2911+#define EXTI_FTSR2_FT_Msk (0x302UL << EXTI_FTSR2_FT_Pos) /*!< 0x00000302 */
2912+#define EXTI_FTSR2_FT EXTI_FTSR2_FT_Msk /*!< Falling trigger event configuration bit */
2913+#define EXTI_FTSR2_FT33_Pos (1U)
2914+#define EXTI_FTSR2_FT33_Msk (0x1UL << EXTI_FTSR2_FT33_Pos) /*!< 0x00000002 */
2915+#define EXTI_FTSR2_FT33 EXTI_FTSR2_FT33_Msk /*!< Falling trigger event configuration bit of line 33 */
2916+#define EXTI_FTSR2_FT40_Pos (8U)
2917+#define EXTI_FTSR2_FT40_Msk (0x1UL << EXTI_FTSR2_FT40_Pos) /*!< 0x00000100 */
2918+#define EXTI_FTSR2_FT40 EXTI_FTSR2_FT40_Msk /*!< Falling trigger event configuration bit of line 40 */
2919+#define EXTI_FTSR2_FT41_Pos (9U)
2920+#define EXTI_FTSR2_FT41_Msk (0x1UL << EXTI_FTSR2_FT41_Pos) /*!< 0x00000200 */
2921+#define EXTI_FTSR2_FT41 EXTI_FTSR2_FT41_Msk /*!< Falling trigger event configuration bit of line 41 */
2922+
2923+/****************** Bit definition for EXTI_SWIER2 register *****************/
2924+#define EXTI_SWIER2_SWI_Pos (0U)
2925+#define EXTI_SWIER2_SWI_Msk (0x302UL << EXTI_SWIER2_SWI_Pos) /*!< 0x00000302 */
2926+#define EXTI_SWIER2_SWI EXTI_SWIER2_SWI_Msk /*!< Falling trigger event configuration bit */
2927+#define EXTI_SWIER2_SWI33_Pos (1U)
2928+#define EXTI_SWIER2_SWI33_Msk (0x1UL << EXTI_SWIER2_SWI33_Pos) /*!< 0x00000002 */
2929+#define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWI33_Msk /*!< Software Interrupt on line 33 */
2930+#define EXTI_SWIER2_SWI40_Pos (8U)
2931+#define EXTI_SWIER2_SWI40_Msk (0x1UL << EXTI_SWIER2_SWI40_Pos) /*!< 0x00000100 */
2932+#define EXTI_SWIER2_SWI40 EXTI_SWIER2_SWI40_Msk /*!< Software Interrupt on line 40 */
2933+#define EXTI_SWIER2_SWI41_Pos (9U)
2934+#define EXTI_SWIER2_SWI41_Msk (0x1UL << EXTI_SWIER2_SWI41_Pos) /*!< 0x00000200 */
2935+#define EXTI_SWIER2_SWI41 EXTI_SWIER2_SWI41_Msk /*!< Software Interrupt on line 41 */
2936+
2937+/******************* Bit definition for EXTI_PR2 register *******************/
2938+#define EXTI_PR2_PIF_Pos (0U)
2939+#define EXTI_PR2_PIF_Msk (0x302UL << EXTI_PR2_PIF_Pos) /*!< 0x00000302 */
2940+#define EXTI_PR2_PIF EXTI_PR2_PIF_Msk /*!< Pending bit */
2941+#define EXTI_PR2_PIF33_Pos (1U)
2942+#define EXTI_PR2_PIF33_Msk (0x1UL << EXTI_PR2_PIF33_Pos) /*!< 0x00000002 */
2943+#define EXTI_PR2_PIF33 EXTI_PR2_PIF33_Msk /*!< Pending bit for line 33 */
2944+#define EXTI_PR2_PIF40_Pos (8U)
2945+#define EXTI_PR2_PIF40_Msk (0x1UL << EXTI_PR2_PIF40_Pos) /*!< 0x00000100 */
2946+#define EXTI_PR2_PIF40 EXTI_PR2_PIF40_Msk /*!< Pending bit for line 40 */
2947+#define EXTI_PR2_PIF41_Pos (9U)
2948+#define EXTI_PR2_PIF41_Msk (0x1UL << EXTI_PR2_PIF41_Pos) /*!< 0x00000200 */
2949+#define EXTI_PR2_PIF41 EXTI_PR2_PIF41_Msk /*!< Pending bit for line 41 */
2950+
2951+/******************** Bits definition for EXTI_IMR1 register ****************/
2952+#define EXTI_IMR1_Pos (0U)
2953+#define EXTI_IMR1_Msk (0xFFFFFFFFUL << EXTI_IMR1_Pos) /*!< 0xFFFFFFFF */
2954+#define EXTI_IMR1_IM EXTI_IMR1_Msk /*!< CPU1 wakeup with interrupt Mask on Event */
2955+#define EXTI_IMR1_IM0_Pos (0U)
2956+#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
2957+#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< CPU1 Interrupt Mask on line 0 */
2958+#define EXTI_IMR1_IM1_Pos (1U)
2959+#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
2960+#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< CPU1 Interrupt Mask on line 1 */
2961+#define EXTI_IMR1_IM2_Pos (2U)
2962+#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
2963+#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< CPU1 Interrupt Mask on line 2 */
2964+#define EXTI_IMR1_IM3_Pos (3U)
2965+#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
2966+#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< CPU1 Interrupt Mask on line 3 */
2967+#define EXTI_IMR1_IM4_Pos (4U)
2968+#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
2969+#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< CPU1 Interrupt Mask on line 4 */
2970+#define EXTI_IMR1_IM5_Pos (5U)
2971+#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
2972+#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< CPU1 Interrupt Mask on line 5 */
2973+#define EXTI_IMR1_IM6_Pos (6U)
2974+#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
2975+#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< CPU1 Interrupt Mask on line 6 */
2976+#define EXTI_IMR1_IM7_Pos (7U)
2977+#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
2978+#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< CPU1 Interrupt Mask on line 7 */
2979+#define EXTI_IMR1_IM8_Pos (8U)
2980+#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
2981+#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< CPU1 Interrupt Mask on line 8 */
2982+#define EXTI_IMR1_IM9_Pos (9U)
2983+#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
2984+#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< CPU1 Interrupt Mask on line 9 */
2985+#define EXTI_IMR1_IM10_Pos (10U)
2986+#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
2987+#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< CPU1 Interrupt Mask on line 10 */
2988+#define EXTI_IMR1_IM11_Pos (11U)
2989+#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
2990+#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< CPU1 Interrupt Mask on line 11 */
2991+#define EXTI_IMR1_IM12_Pos (12U)
2992+#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
2993+#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< CPU1 Interrupt Mask on line 12 */
2994+#define EXTI_IMR1_IM13_Pos (13U)
2995+#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
2996+#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< CPU1 Interrupt Mask on line 13 */
2997+#define EXTI_IMR1_IM14_Pos (14U)
2998+#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
2999+#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< CPU1 Interrupt Mask on line 14 */
3000+#define EXTI_IMR1_IM15_Pos (15U)
3001+#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
3002+#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< CPU1 Interrupt Mask on line 15 */
3003+#define EXTI_IMR1_IM16_Pos (16U)
3004+#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */
3005+#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< CPU1 Interrupt Mask on line 16 */
3006+#define EXTI_IMR1_IM17_Pos (17U)
3007+#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */
3008+#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< CPU1 Interrupt Mask on line 17 */
3009+#define EXTI_IMR1_IM18_Pos (18U)
3010+#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */
3011+#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< CPU1 Interrupt Mask on line 18 */
3012+#define EXTI_IMR1_IM19_Pos (19U)
3013+#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
3014+#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< CPU1 Interrupt Mask on line 19 */
3015+#define EXTI_IMR1_IM22_Pos (22U)
3016+#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
3017+#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< CPU1 Interrupt Mask on line 22 */
3018+#define EXTI_IMR1_IM24_Pos (24U)
3019+#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
3020+#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< CPU1 Interrupt Mask on line 24 */
3021+#define EXTI_IMR1_IM29_Pos (29U)
3022+#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */
3023+#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< CPU1 Interrupt Mask on line 29 */
3024+#define EXTI_IMR1_IM30_Pos (30U)
3025+#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */
3026+#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< CPU1 Interrupt Mask on line 30 */
3027+
3028+/******************** Bits definition for EXTI_EMR1 register ****************/
3029+#define EXTI_EMR1_Pos (0U)
3030+#define EXTI_EMR1_Msk (0x003EFFFFUL << EXTI_EMR1_Pos) /*!< 0xFFFFFFFF */
3031+#define EXTI_EMR1_EM EXTI_EMR1_Msk /*!< CPU1 Event Mask */
3032+#define EXTI_EMR1_EM0_Pos (0U)
3033+#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
3034+#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< CPU1 Event Mask on line 0 */
3035+#define EXTI_EMR1_EM1_Pos (1U)
3036+#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
3037+#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< CPU1 Event Mask on line 1 */
3038+#define EXTI_EMR1_EM2_Pos (2U)
3039+#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
3040+#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< CPU1 Event Mask on line 2 */
3041+#define EXTI_EMR1_EM3_Pos (3U)
3042+#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
3043+#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< CPU1 Event Mask on line 3 */
3044+#define EXTI_EMR1_EM4_Pos (4U)
3045+#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
3046+#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< CPU1 Event Mask on line 4 */
3047+#define EXTI_EMR1_EM5_Pos (5U)
3048+#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
3049+#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< CPU1 Event Mask on line 5 */
3050+#define EXTI_EMR1_EM6_Pos (6U)
3051+#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
3052+#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< CPU1 Event Mask on line 6 */
3053+#define EXTI_EMR1_EM7_Pos (7U)
3054+#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
3055+#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< CPU1 Event Mask on line 7 */
3056+#define EXTI_EMR1_EM8_Pos (8U)
3057+#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
3058+#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< CPU1 Event Mask on line 8 */
3059+#define EXTI_EMR1_EM9_Pos (9U)
3060+#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
3061+#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< CPU1 Event Mask on line 9 */
3062+#define EXTI_EMR1_EM10_Pos (10U)
3063+#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
3064+#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< CPU1 Event Mask on line 10 */
3065+#define EXTI_EMR1_EM11_Pos (11U)
3066+#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
3067+#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< CPU1 Event Mask on line 11 */
3068+#define EXTI_EMR1_EM12_Pos (12U)
3069+#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
3070+#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< CPU1 Event Mask on line 12 */
3071+#define EXTI_EMR1_EM13_Pos (13U)
3072+#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
3073+#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< CPU1 Event Mask on line 13 */
3074+#define EXTI_EMR1_EM14_Pos (14U)
3075+#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
3076+#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< CPU1 Event Mask on line 14 */
3077+#define EXTI_EMR1_EM15_Pos (15U)
3078+#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
3079+#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< CPU1 Event Mask on line 15 */
3080+#define EXTI_EMR1_EM17_Pos (17U)
3081+#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */
3082+#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< CPU1 Event Mask on line 17 */
3083+#define EXTI_EMR1_EM18_Pos (18U)
3084+#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */
3085+#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< CPU1 Event Mask on line 18 */
3086+#define EXTI_EMR1_EM19_Pos (19U)
3087+#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */
3088+#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< CPU1 Event Mask on line 19 */
3089+
3090+/******************** Bits definition for EXTI_IMR2 register ****************/
3091+#define EXTI_IMR2_Pos (0U)
3092+#define EXTI_IMR2_Msk (0x0001FFFFUL << EXTI_IMR2_Pos) /*!< 0x0001FFFF */
3093+#define EXTI_IMR2_IM EXTI_IMR2_Msk /*!< CPU1 Interrupt Mask */
3094+#define EXTI_IMR2_IM33_Pos (1U)
3095+#define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
3096+#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< CPU1 Interrupt Mask on line 33 */
3097+#define EXTI_IMR2_IM36_Pos (4U)
3098+#define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
3099+#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< CPU1 Interrupt Mask on line 36 */
3100+#define EXTI_IMR2_IM37_Pos (5U)
3101+#define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
3102+#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< CPU1 Interrupt Mask on line 37 */
3103+#define EXTI_IMR2_IM38_Pos (6U)
3104+#define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
3105+#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< CPU1 Interrupt Mask on line 38 */
3106+#define EXTI_IMR2_IM39_Pos (7U)
3107+#define EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
3108+#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< CPU1 Interrupt Mask on line 39 */
3109+#define EXTI_IMR2_IM40_Pos (8U)
3110+#define EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */
3111+#define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< CPU1 Interrupt Mask on line 40 */
3112+#define EXTI_IMR2_IM41_Pos (9U)
3113+#define EXTI_IMR2_IM41_Msk (0x1UL << EXTI_IMR2_IM41_Pos) /*!< 0x00000200 */
3114+#define EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk /*!< CPU1 Interrupt Mask on line 41 */
3115+#define EXTI_IMR2_IM42_Pos (10U)
3116+#define EXTI_IMR2_IM42_Msk (0x1UL << EXTI_IMR2_IM42_Pos) /*!< 0x00000400 */
3117+#define EXTI_IMR2_IM42 EXTI_IMR2_IM42_Msk /*!< CPU1 Interrupt Mask on line 42 */
3118+#define EXTI_IMR2_IM44_Pos (12U)
3119+#define EXTI_IMR2_IM44_Msk (0x1UL << EXTI_IMR2_IM44_Pos) /*!< 0x00001000 */
3120+#define EXTI_IMR2_IM44 EXTI_IMR2_IM44_Msk /*!< CPU1 Interrupt Mask on line 44 */
3121+#define EXTI_IMR2_IM45_Pos (13U)
3122+#define EXTI_IMR2_IM45_Msk (0x1UL << EXTI_IMR2_IM45_Pos) /*!< 0x00002000 */
3123+#define EXTI_IMR2_IM45 EXTI_IMR2_IM45_Msk /*!< CPU1 Interrupt Mask on line 45 */
3124+#define EXTI_IMR2_IM46_Pos (14U)
3125+#define EXTI_IMR2_IM46_Msk (0x1UL << EXTI_IMR2_IM46_Pos) /*!< 0x00004000 */
3126+#define EXTI_IMR2_IM46 EXTI_IMR2_IM46_Msk /*!< CPU1 Interrupt Mask on line 46 */
3127+#define EXTI_IMR2_IM48_Pos (16U)
3128+#define EXTI_IMR2_IM48_Msk (0x1UL << EXTI_IMR2_IM48_Pos) /*!< 0x00010000 */
3129+#define EXTI_IMR2_IM48 EXTI_IMR2_IM48_Msk /*!< CPU1 Interrupt Mask on line 48 */
3130+
3131+/******************** Bits definition for EXTI_EMR2 register ****************/
3132+#define EXTI_EMR2_Pos (0U)
3133+#define EXTI_EMR2_Msk (0x00000300UL << EXTI_EMR2_Pos) /*!< 0x000003000 */
3134+#define EXTI_EMR2_EM EXTI_EMR2_Msk /*!< CPU1 Interrupt Mask */
3135+#define EXTI_EMR2_EM40_Pos (8U)
3136+#define EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */
3137+#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< CPU1 Event Mask on line 40 */
3138+#define EXTI_EMR2_EM41_Pos (9U)
3139+#define EXTI_EMR2_EM41_Msk (0x1UL << EXTI_EMR2_EM41_Pos) /*!< 0x00000200 */
3140+#define EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk /*!< CPU1 Event Mask on line 41 */
3141+
3142+/******************** Bits definition for EXTI_C2IMR1 register **************/
3143+#define EXTI_C2IMR1_Pos (0U)
3144+#define EXTI_C2IMR1_Msk (0xFFFFFFFFUL << EXTI_C2IMR1_Pos) /*!< 0xFFFFFFFF */
3145+#define EXTI_C2IMR1_IM EXTI_C2IMR1_Msk /*!< CPU2 wakeup with interrupt Mask on Event */
3146+#define EXTI_C2IMR1_IM0_Pos (0U)
3147+#define EXTI_C2IMR1_IM0_Msk (0x1UL << EXTI_C2IMR1_IM0_Pos) /*!< 0x00000001 */
3148+#define EXTI_C2IMR1_IM0 EXTI_C2IMR1_IM0_Msk /*!< CPU2 Interrupt Mask on line 0 */
3149+#define EXTI_C2IMR1_IM1_Pos (1U)
3150+#define EXTI_C2IMR1_IM1_Msk (0x1UL << EXTI_C2IMR1_IM1_Pos) /*!< 0x00000002 */
3151+#define EXTI_C2IMR1_IM1 EXTI_C2IMR1_IM1_Msk /*!< CPU2 Interrupt Mask on line 1 */
3152+#define EXTI_C2IMR1_IM2_Pos (2U)
3153+#define EXTI_C2IMR1_IM2_Msk (0x1UL << EXTI_C2IMR1_IM2_Pos) /*!< 0x00000004 */
3154+#define EXTI_C2IMR1_IM2 EXTI_C2IMR1_IM2_Msk /*!< CPU2 Interrupt Mask on line 2 */
3155+#define EXTI_C2IMR1_IM3_Pos (3U)
3156+#define EXTI_C2IMR1_IM3_Msk (0x1UL << EXTI_C2IMR1_IM3_Pos) /*!< 0x00000008 */
3157+#define EXTI_C2IMR1_IM3 EXTI_C2IMR1_IM3_Msk /*!< CPU2 Interrupt Mask on line 3 */
3158+#define EXTI_C2IMR1_IM4_Pos (4U)
3159+#define EXTI_C2IMR1_IM4_Msk (0x1UL << EXTI_C2IMR1_IM4_Pos) /*!< 0x00000010 */
3160+#define EXTI_C2IMR1_IM4 EXTI_C2IMR1_IM4_Msk /*!< CPU2 Interrupt Mask on line 4 */
3161+#define EXTI_C2IMR1_IM5_Pos (5U)
3162+#define EXTI_C2IMR1_IM5_Msk (0x1UL << EXTI_C2IMR1_IM5_Pos) /*!< 0x00000020 */
3163+#define EXTI_C2IMR1_IM5 EXTI_C2IMR1_IM5_Msk /*!< CPU2 Interrupt Mask on line 5 */
3164+#define EXTI_C2IMR1_IM6_Pos (6U)
3165+#define EXTI_C2IMR1_IM6_Msk (0x1UL << EXTI_C2IMR1_IM6_Pos) /*!< 0x00000040 */
3166+#define EXTI_C2IMR1_IM6 EXTI_C2IMR1_IM6_Msk /*!< CPU2 Interrupt Mask on line 6 */
3167+#define EXTI_C2IMR1_IM7_Pos (7U)
3168+#define EXTI_C2IMR1_IM7_Msk (0x1UL << EXTI_C2IMR1_IM7_Pos) /*!< 0x00000080 */
3169+#define EXTI_C2IMR1_IM7 EXTI_C2IMR1_IM7_Msk /*!< CPU2 Interrupt Mask on line 7 */
3170+#define EXTI_C2IMR1_IM8_Pos (8U)
3171+#define EXTI_C2IMR1_IM8_Msk (0x1UL << EXTI_C2IMR1_IM8_Pos) /*!< 0x00000100 */
3172+#define EXTI_C2IMR1_IM8 EXTI_C2IMR1_IM8_Msk /*!< CPU2 Interrupt Mask on line 8 */
3173+#define EXTI_C2IMR1_IM9_Pos (9U)
3174+#define EXTI_C2IMR1_IM9_Msk (0x1UL << EXTI_C2IMR1_IM9_Pos) /*!< 0x00000200 */
3175+#define EXTI_C2IMR1_IM9 EXTI_C2IMR1_IM9_Msk /*!< CPU2 Interrupt Mask on line 9 */
3176+#define EXTI_C2IMR1_IM10_Pos (10U)
3177+#define EXTI_C2IMR1_IM10_Msk (0x1UL << EXTI_C2IMR1_IM10_Pos) /*!< 0x00000400 */
3178+#define EXTI_C2IMR1_IM10 EXTI_C2IMR1_IM10_Msk /*!< CPU2 Interrupt Mask on line 10 */
3179+#define EXTI_C2IMR1_IM11_Pos (11U)
3180+#define EXTI_C2IMR1_IM11_Msk (0x1UL << EXTI_C2IMR1_IM11_Pos) /*!< 0x00000800 */
3181+#define EXTI_C2IMR1_IM11 EXTI_C2IMR1_IM11_Msk /*!< CPU2 Interrupt Mask on line 11 */
3182+#define EXTI_C2IMR1_IM12_Pos (12U)
3183+#define EXTI_C2IMR1_IM12_Msk (0x1UL << EXTI_C2IMR1_IM12_Pos) /*!< 0x00001000 */
3184+#define EXTI_C2IMR1_IM12 EXTI_C2IMR1_IM12_Msk /*!< CPU2 Interrupt Mask on line 12 */
3185+#define EXTI_C2IMR1_IM13_Pos (13U)
3186+#define EXTI_C2IMR1_IM13_Msk (0x1UL << EXTI_C2IMR1_IM13_Pos) /*!< 0x00002000 */
3187+#define EXTI_C2IMR1_IM13 EXTI_C2IMR1_IM13_Msk /*!< CPU2 Interrupt Mask on line 13 */
3188+#define EXTI_C2IMR1_IM14_Pos (14U)
3189+#define EXTI_C2IMR1_IM14_Msk (0x1UL << EXTI_C2IMR1_IM14_Pos) /*!< 0x00004000 */
3190+#define EXTI_C2IMR1_IM14 EXTI_C2IMR1_IM14_Msk /*!< CPU2 Interrupt Mask on line 14 */
3191+#define EXTI_C2IMR1_IM15_Pos (15U)
3192+#define EXTI_C2IMR1_IM15_Msk (0x1UL << EXTI_C2IMR1_IM15_Pos) /*!< 0x00008000 */
3193+#define EXTI_C2IMR1_IM15 EXTI_C2IMR1_IM15_Msk /*!< CPU2 Interrupt Mask on line 15 */
3194+#define EXTI_C2IMR1_IM16_Pos (16U)
3195+#define EXTI_C2IMR1_IM16_Msk (0x1UL << EXTI_C2IMR1_IM16_Pos) /*!< 0x00010000 */
3196+#define EXTI_C2IMR1_IM16 EXTI_C2IMR1_IM16_Msk /*!< CPU2 Interrupt Mask on line 16 */
3197+#define EXTI_C2IMR1_IM17_Pos (17U)
3198+#define EXTI_C2IMR1_IM17_Msk (0x1UL << EXTI_C2IMR1_IM17_Pos) /*!< 0x00020000 */
3199+#define EXTI_C2IMR1_IM17 EXTI_C2IMR1_IM17_Msk /*!< CPU2 Interrupt Mask on line 17 */
3200+#define EXTI_C2IMR1_IM18_Pos (18U)
3201+#define EXTI_C2IMR1_IM18_Msk (0x1UL << EXTI_C2IMR1_IM18_Pos) /*!< 0x00040000 */
3202+#define EXTI_C2IMR1_IM18 EXTI_C2IMR1_IM18_Msk /*!< CPU2 Interrupt Mask on line 18 */
3203+#define EXTI_C2IMR1_IM19_Pos (19U)
3204+#define EXTI_C2IMR1_IM19_Msk (0x1UL << EXTI_C2IMR1_IM19_Pos) /*!< 0x00080000 */
3205+#define EXTI_C2IMR1_IM19 EXTI_C2IMR1_IM19_Msk /*!< CPU2 Interrupt Mask on line 19 */
3206+#define EXTI_C2IMR1_IM22_Pos (22U)
3207+#define EXTI_C2IMR1_IM22_Msk (0x1UL << EXTI_C2IMR1_IM22_Pos) /*!< 0x00400000 */
3208+#define EXTI_C2IMR1_IM22 EXTI_C2IMR1_IM22_Msk /*!< CPU2 Interrupt Mask on line 22 */
3209+#define EXTI_C2IMR1_IM24_Pos (24U)
3210+#define EXTI_C2IMR1_IM24_Msk (0x1UL << EXTI_C2IMR1_IM24_Pos) /*!< 0x01000000 */
3211+#define EXTI_C2IMR1_IM24 EXTI_C2IMR1_IM24_Msk /*!< CPU2 Interrupt Mask on line 24 */
3212+#define EXTI_C2IMR1_IM29_Pos (29U)
3213+#define EXTI_C2IMR1_IM29_Msk (0x1UL << EXTI_C2IMR1_IM29_Pos) /*!< 0x20000000 */
3214+#define EXTI_C2IMR1_IM29 EXTI_C2IMR1_IM29_Msk /*!< CPU2 Interrupt Mask on line 29 */
3215+#define EXTI_C2IMR1_IM30_Pos (30U)
3216+#define EXTI_C2IMR1_IM30_Msk (0x1UL << EXTI_C2IMR1_IM30_Pos) /*!< 0x40000000 */
3217+#define EXTI_C2IMR1_IM30 EXTI_C2IMR1_IM30_Msk /*!< CPU2 Interrupt Mask on line 30 */
3218+
3219+/******************** Bits definition for EXTI_C2EMR1 register **************/
3220+#define EXTI_C2EMR1_Pos (0U)
3221+#define EXTI_C2EMR1_Msk (0x003EFFFFUL << EXTI_C2EMR1_Pos) /*!< 0xFFFFFFFF */
3222+#define EXTI_C2EMR1_EM EXTI_C2EMR1_Msk /*!< CPU2 Event Mask */
3223+#define EXTI_C2EMR1_EM0_Pos (0U)
3224+#define EXTI_C2EMR1_EM0_Msk (0x1UL << EXTI_C2EMR1_EM0_Pos) /*!< 0x00000001 */
3225+#define EXTI_C2EMR1_EM0 EXTI_C2EMR1_EM0_Msk /*!< CPU2 Event Mask on line 0 */
3226+#define EXTI_C2EMR1_EM1_Pos (1U)
3227+#define EXTI_C2EMR1_EM1_Msk (0x1UL << EXTI_C2EMR1_EM1_Pos) /*!< 0x00000002 */
3228+#define EXTI_C2EMR1_EM1 EXTI_C2EMR1_EM1_Msk /*!< CPU2 Event Mask on line 1 */
3229+#define EXTI_C2EMR1_EM2_Pos (2U)
3230+#define EXTI_C2EMR1_EM2_Msk (0x1UL << EXTI_C2EMR1_EM2_Pos) /*!< 0x00000004 */
3231+#define EXTI_C2EMR1_EM2 EXTI_C2EMR1_EM2_Msk /*!< CPU2 Event Mask on line 2 */
3232+#define EXTI_C2EMR1_EM3_Pos (3U)
3233+#define EXTI_C2EMR1_EM3_Msk (0x1UL << EXTI_C2EMR1_EM3_Pos) /*!< 0x00000008 */
3234+#define EXTI_C2EMR1_EM3 EXTI_C2EMR1_EM3_Msk /*!< CPU2 Event Mask on line 3 */
3235+#define EXTI_C2EMR1_EM4_Pos (4U)
3236+#define EXTI_C2EMR1_EM4_Msk (0x1UL << EXTI_C2EMR1_EM4_Pos) /*!< 0x00000010 */
3237+#define EXTI_C2EMR1_EM4 EXTI_C2EMR1_EM4_Msk /*!< CPU2 Event Mask on line 4 */
3238+#define EXTI_C2EMR1_EM5_Pos (5U)
3239+#define EXTI_C2EMR1_EM5_Msk (0x1UL << EXTI_C2EMR1_EM5_Pos) /*!< 0x00000020 */
3240+#define EXTI_C2EMR1_EM5 EXTI_C2EMR1_EM5_Msk /*!< CPU2 Event Mask on line 5 */
3241+#define EXTI_C2EMR1_EM6_Pos (6U)
3242+#define EXTI_C2EMR1_EM6_Msk (0x1UL << EXTI_C2EMR1_EM6_Pos) /*!< 0x00000040 */
3243+#define EXTI_C2EMR1_EM6 EXTI_C2EMR1_EM6_Msk /*!< CPU2 Event Mask on line 6 */
3244+#define EXTI_C2EMR1_EM7_Pos (7U)
3245+#define EXTI_C2EMR1_EM7_Msk (0x1UL << EXTI_C2EMR1_EM7_Pos) /*!< 0x00000080 */
3246+#define EXTI_C2EMR1_EM7 EXTI_C2EMR1_EM7_Msk /*!< CPU2 Event Mask on line 7 */
3247+#define EXTI_C2EMR1_EM8_Pos (8U)
3248+#define EXTI_C2EMR1_EM8_Msk (0x1UL << EXTI_C2EMR1_EM8_Pos) /*!< 0x00000100 */
3249+#define EXTI_C2EMR1_EM8 EXTI_C2EMR1_EM8_Msk /*!< CPU2 Event Mask on line 8 */
3250+#define EXTI_C2EMR1_EM9_Pos (9U)
3251+#define EXTI_C2EMR1_EM9_Msk (0x1UL << EXTI_C2EMR1_EM9_Pos) /*!< 0x00000200 */
3252+#define EXTI_C2EMR1_EM9 EXTI_C2EMR1_EM9_Msk /*!< CPU2 Event Mask on line 9 */
3253+#define EXTI_C2EMR1_EM10_Pos (10U)
3254+#define EXTI_C2EMR1_EM10_Msk (0x1UL << EXTI_C2EMR1_EM10_Pos) /*!< 0x00000400 */
3255+#define EXTI_C2EMR1_EM10 EXTI_C2EMR1_EM10_Msk /*!< CPU2 Event Mask on line 10 */
3256+#define EXTI_C2EMR1_EM11_Pos (11U)
3257+#define EXTI_C2EMR1_EM11_Msk (0x1UL << EXTI_C2EMR1_EM11_Pos) /*!< 0x00000800 */
3258+#define EXTI_C2EMR1_EM11 EXTI_C2EMR1_EM11_Msk /*!< CPU2 Event Mask on line 11 */
3259+#define EXTI_C2EMR1_EM12_Pos (12U)
3260+#define EXTI_C2EMR1_EM12_Msk (0x1UL << EXTI_C2EMR1_EM12_Pos) /*!< 0x00001000 */
3261+#define EXTI_C2EMR1_EM12 EXTI_C2EMR1_EM12_Msk /*!< CPU2 Event Mask on line 12 */
3262+#define EXTI_C2EMR1_EM13_Pos (13U)
3263+#define EXTI_C2EMR1_EM13_Msk (0x1UL << EXTI_C2EMR1_EM13_Pos) /*!< 0x00002000 */
3264+#define EXTI_C2EMR1_EM13 EXTI_C2EMR1_EM13_Msk /*!< CPU2 Event Mask on line 13 */
3265+#define EXTI_C2EMR1_EM14_Pos (14U)
3266+#define EXTI_C2EMR1_EM14_Msk (0x1UL << EXTI_C2EMR1_EM14_Pos) /*!< 0x00004000 */
3267+#define EXTI_C2EMR1_EM14 EXTI_C2EMR1_EM14_Msk /*!< CPU2 Event Mask on line 14 */
3268+#define EXTI_C2EMR1_EM15_Pos (15U)
3269+#define EXTI_C2EMR1_EM15_Msk (0x1UL << EXTI_C2EMR1_EM15_Pos) /*!< 0x00008000 */
3270+#define EXTI_C2EMR1_EM15 EXTI_C2EMR1_EM15_Msk /*!< CPU2 Event Mask on line 15 */
3271+#define EXTI_C2EMR1_EM17_Pos (17U)
3272+#define EXTI_C2EMR1_EM17_Msk (0x1UL << EXTI_C2EMR1_EM17_Pos) /*!< 0x00020000 */
3273+#define EXTI_C2EMR1_EM17 EXTI_C2EMR1_EM17_Msk /*!< CPU2 Event Mask on line 17 */
3274+#define EXTI_C2EMR1_EM18_Pos (18U)
3275+#define EXTI_C2EMR1_EM18_Msk (0x1UL << EXTI_C2EMR1_EM18_Pos) /*!< 0x00040000 */
3276+#define EXTI_C2EMR1_EM18 EXTI_C2EMR1_EM18_Msk /*!< CPU2 Event Mask on line 18 */
3277+#define EXTI_C2EMR1_EM19_Pos (19U)
3278+#define EXTI_C2EMR1_EM19_Msk (0x1UL << EXTI_C2EMR1_EM19_Pos) /*!< 0x00080000 */
3279+#define EXTI_C2EMR1_EM19 EXTI_C2EMR1_EM19_Msk /*!< CPU2 Event Mask on line 19 */
3280+
3281+/******************** Bits definition for EXTI_C2IMR2 register **************/
3282+#define EXTI_C2IMR2_Pos (0U)
3283+#define EXTI_C2IMR2_Msk (0x0001FFFFUL << EXTI_C2IMR2_Pos) /*!< 0x0001FFFF */
3284+#define EXTI_C2IMR2_IM EXTI_C2IMR2_Msk /*!< CPU2 Interrupt Mask */
3285+#define EXTI_C2IMR2_IM33_Pos (1U)
3286+#define EXTI_C2IMR2_IM33_Msk (0x1UL << EXTI_C2IMR2_IM33_Pos) /*!< 0x00000002 */
3287+#define EXTI_C2IMR2_IM33 EXTI_C2IMR2_IM33_Msk /*!< CPU2 Interrupt Mask on line 33 */
3288+#define EXTI_C2IMR2_IM36_Pos (4U)
3289+#define EXTI_C2IMR2_IM36_Msk (0x1UL << EXTI_C2IMR2_IM36_Pos) /*!< 0x00000010 */
3290+#define EXTI_C2IMR2_IM36 EXTI_C2IMR2_IM36_Msk /*!< CPU2 Interrupt Mask on line 36 */
3291+#define EXTI_C2IMR2_IM37_Pos (5U)
3292+#define EXTI_C2IMR2_IM37_Msk (0x1UL << EXTI_C2IMR2_IM37_Pos) /*!< 0x00000020 */
3293+#define EXTI_C2IMR2_IM37 EXTI_C2IMR2_IM37_Msk /*!< CPU2 Interrupt Mask on line 37 */
3294+#define EXTI_C2IMR2_IM38_Pos (6U)
3295+#define EXTI_C2IMR2_IM38_Msk (0x1UL << EXTI_C2IMR2_IM38_Pos) /*!< 0x00000040 */
3296+#define EXTI_C2IMR2_IM38 EXTI_C2IMR2_IM38_Msk /*!< CPU2 Interrupt Mask on line 38 */
3297+#define EXTI_C2IMR2_IM39_Pos (7U)
3298+#define EXTI_C2IMR2_IM39_Msk (0x1UL << EXTI_C2IMR2_IM39_Pos) /*!< 0x00000080 */
3299+#define EXTI_C2IMR2_IM39 EXTI_C2IMR2_IM39_Msk /*!< CPU2 Interrupt Mask on line 39 */
3300+#define EXTI_C2IMR2_IM40_Pos (8U)
3301+#define EXTI_C2IMR2_IM40_Msk (0x1UL << EXTI_C2IMR2_IM40_Pos) /*!< 0x00000100 */
3302+#define EXTI_C2IMR2_IM40 EXTI_C2IMR2_IM40_Msk /*!< CPU2 Interrupt Mask on line 40 */
3303+#define EXTI_C2IMR2_IM41_Pos (9U)
3304+#define EXTI_C2IMR2_IM41_Msk (0x1UL << EXTI_C2IMR2_IM41_Pos) /*!< 0x00000200 */
3305+#define EXTI_C2IMR2_IM41 EXTI_C2IMR2_IM41_Msk /*!< CPU2 Interrupt Mask on line 41 */
3306+#define EXTI_C2IMR2_IM42_Pos (10U)
3307+#define EXTI_C2IMR2_IM42_Msk (0x1UL << EXTI_C2IMR2_IM42_Pos) /*!< 0x00000400 */
3308+#define EXTI_C2IMR2_IM42 EXTI_C2IMR2_IM42_Msk /*!< CPU2 Interrupt Mask on line 42 */
3309+#define EXTI_C2IMR2_IM44_Pos (12U)
3310+#define EXTI_C2IMR2_IM44_Msk (0x1UL << EXTI_C2IMR2_IM44_Pos) /*!< 0x00001000 */
3311+#define EXTI_C2IMR2_IM44 EXTI_C2IMR2_IM44_Msk /*!< CPU2 Interrupt Mask on line 44 */
3312+#define EXTI_C2IMR2_IM45_Pos (13U)
3313+#define EXTI_C2IMR2_IM45_Msk (0x1UL << EXTI_C2IMR2_IM45_Pos) /*!< 0x00002000 */
3314+#define EXTI_C2IMR2_IM45 EXTI_C2IMR2_IM45_Msk /*!< CPU2 Interrupt Mask on line 45 */
3315+#define EXTI_C2IMR2_IM46_Pos (14U)
3316+#define EXTI_C2IMR2_IM46_Msk (0x1UL << EXTI_C2IMR2_IM46_Pos) /*!< 0x00004000 */
3317+#define EXTI_C2IMR2_IM46 EXTI_C2IMR2_IM46_Msk /*!< CPU2 Interrupt Mask on line 46 */
3318+#define EXTI_C2IMR2_IM48_Pos (16U)
3319+#define EXTI_C2IMR2_IM48_Msk (0x1UL << EXTI_C2IMR2_IM48_Pos) /*!< 0x00010000 */
3320+#define EXTI_C2IMR2_IM48 EXTI_C2IMR2_IM48_Msk /*!< CPU2 Interrupt Mask on line 48 */
3321+
3322+/******************** Bits definition for EXTI_C2EMR2 register **************/
3323+#define EXTI_C2EMR2_Pos (8U)
3324+#define EXTI_C2EMR2_Msk (0x00000300UL << EXTI_C2EMR2_Pos) /*!< 0x000003000 */
3325+#define EXTI_C2EMR2_EM EXTI_C2EMR2_Msk /*!< CPU2 Interrupt Mask */
3326+#define EXTI_C2EMR2_EM40_Pos (8U)
3327+#define EXTI_C2EMR2_EM40_Msk (0x1UL << EXTI_C2EMR2_EM40_Pos) /*!< 0x00000100 */
3328+#define EXTI_C2EMR2_EM40 EXTI_C2EMR2_EM40_Msk /*!< CPU2 Event Mask on line 40 */
3329+#define EXTI_C2EMR2_EM41_Pos (9U)
3330+#define EXTI_C2EMR2_EM41_Msk (0x1UL << EXTI_C2EMR2_EM41_Pos) /*!< 0x00000200 */
3331+#define EXTI_C2EMR2_EM41 EXTI_C2EMR2_EM41_Msk /*!< CPU2 Event Mask on line 41 */
3332+
3333+/******************************************************************************/
3334+/* */
3335+/* Public Key Accelerator (PKA) */
3336+/* */
3337+/******************************************************************************/
3338+
3339+/******************* Bits definition for PKA_CR register **************/
3340+#define PKA_CR_EN_Pos (0U)
3341+#define PKA_CR_EN_Msk (0x1UL << PKA_CR_EN_Pos) /*!< 0x00000001 */
3342+#define PKA_CR_EN PKA_CR_EN_Msk /*!< PKA enable */
3343+#define PKA_CR_START_Pos (1U)
3344+#define PKA_CR_START_Msk (0x1UL << PKA_CR_START_Pos) /*!< 0x00000002 */
3345+#define PKA_CR_START PKA_CR_START_Msk /*!< Start operation */
3346+#define PKA_CR_MODE_Pos (8U)
3347+#define PKA_CR_MODE_Msk (0x3FUL << PKA_CR_MODE_Pos) /*!< 0x00003F00 */
3348+#define PKA_CR_MODE PKA_CR_MODE_Msk /*!< MODE[5:0] PKA operation code */
3349+#define PKA_CR_MODE_0 (0x01U << PKA_CR_MODE_Pos) /*!< 0x00000100 */
3350+#define PKA_CR_MODE_1 (0x02U << PKA_CR_MODE_Pos) /*!< 0x00000200 */
3351+#define PKA_CR_MODE_2 (0x04U << PKA_CR_MODE_Pos) /*!< 0x00000400 */
3352+#define PKA_CR_MODE_3 (0x08U << PKA_CR_MODE_Pos) /*!< 0x00000800 */
3353+#define PKA_CR_MODE_4 (0x10U << PKA_CR_MODE_Pos) /*!< 0x00001000 */
3354+#define PKA_CR_MODE_5 (0x20U << PKA_CR_MODE_Pos) /*!< 0x00002000 */
3355+#define PKA_CR_PROCENDIE_Pos (17U)
3356+#define PKA_CR_PROCENDIE_Msk (0x1UL << PKA_CR_PROCENDIE_Pos) /*!< 0x00020000 */
3357+#define PKA_CR_PROCENDIE PKA_CR_PROCENDIE_Msk /*!< End of operation interrupt enable */
3358+#define PKA_CR_RAMERRIE_Pos (19U)
3359+#define PKA_CR_RAMERRIE_Msk (0x1UL << PKA_CR_RAMERRIE_Pos) /*!< 0x00080000 */
3360+#define PKA_CR_RAMERRIE PKA_CR_RAMERRIE_Msk /*!< RAM error interrupt enable */
3361+#define PKA_CR_ADDRERRIE_Pos (20U)
3362+#define PKA_CR_ADDRERRIE_Msk (0x1UL << PKA_CR_ADDRERRIE_Pos) /*!< 0x00100000 */
3363+#define PKA_CR_ADDRERRIE PKA_CR_ADDRERRIE_Msk /*!< RAM error interrupt enable */
3364+
3365+/******************* Bits definition for PKA_SR register **************/
3366+#define PKA_SR_BUSY_Pos (16U)
3367+#define PKA_SR_BUSY_Msk (0x1UL << PKA_SR_BUSY_Pos) /*!< 0x00010000 */
3368+#define PKA_SR_BUSY PKA_SR_BUSY_Msk /*!< PKA operation is in progress */
3369+#define PKA_SR_PROCENDF_Pos (17U)
3370+#define PKA_SR_PROCENDF_Msk (0x1UL << PKA_SR_PROCENDF_Pos) /*!< 0x00020000 */
3371+#define PKA_SR_PROCENDF PKA_SR_PROCENDF_Msk /*!< PKA end of operation flag */
3372+#define PKA_SR_RAMERRF_Pos (19U)
3373+#define PKA_SR_RAMERRF_Msk (0x1UL << PKA_SR_RAMERRF_Pos) /*!< 0x00080000 */
3374+#define PKA_SR_RAMERRF PKA_SR_RAMERRF_Msk /*!< PKA RAM error flag */
3375+#define PKA_SR_ADDRERRF_Pos (20U)
3376+#define PKA_SR_ADDRERRF_Msk (0x1UL << PKA_SR_ADDRERRF_Pos) /*!< 0x00100000 */
3377+#define PKA_SR_ADDRERRF PKA_SR_ADDRERRF_Msk /*!< Address error flag */
3378+
3379+/******************* Bits definition for PKA_CLRFR register **************/
3380+#define PKA_CLRFR_PROCENDFC_Pos (17U)
3381+#define PKA_CLRFR_PROCENDFC_Msk (0x1UL << PKA_CLRFR_PROCENDFC_Pos) /*!< 0x00020000 */
3382+#define PKA_CLRFR_PROCENDFC PKA_CLRFR_PROCENDFC_Msk /*!< Clear PKA end of operation flag */
3383+#define PKA_CLRFR_RAMERRFC_Pos (19U)
3384+#define PKA_CLRFR_RAMERRFC_Msk (0x1UL << PKA_CLRFR_RAMERRFC_Pos) /*!< 0x00080000 */
3385+#define PKA_CLRFR_RAMERRFC PKA_CLRFR_RAMERRFC_Msk /*!< Clear PKA RAM error flag */
3386+#define PKA_CLRFR_ADDRERRFC_Pos (20U)
3387+#define PKA_CLRFR_ADDRERRFC_Msk (0x1UL << PKA_CLRFR_ADDRERRFC_Pos) /*!< 0x00100000 */
3388+#define PKA_CLRFR_ADDRERRFC PKA_CLRFR_ADDRERRFC_Msk /*!< Clear address error flag */
3389+
3390+/******************* Bits definition for PKA RAM *************************/
3391+#define PKA_RAM_OFFSET 0x400U /*!< PKA RAM address offset */
3392+
3393+/* Compute Montgomery parameter input data */
3394+#define PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */
3395+#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modulus */
3396+
3397+/* Compute Montgomery parameter output data */
3398+#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */
3399+
3400+/* Compute modular exponentiation input data */
3401+#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */
3402+#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
3403+#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */
3404+#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */
3405+#define PKA_MODULAR_EXP_IN_EXPONENT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */
3406+#define PKA_MODULAR_EXP_IN_MODULUS ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modulus */
3407+
3408+/* Compute modular exponentiation output data */
3409+#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x594U - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */
3410+#define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC1 ((0x724U - PKA_RAM_OFFSET)>>2) /*!< Output SM algorithm accumulator 1 */
3411+#define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC2 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Output SM algorithm accumulator 2 */
3412+#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */
3413+#define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC3 ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Output SM algorithm accumulator 3 */
3414+
3415+/* Compute ECC scalar multiplication input data */
3416+#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */
3417+#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
3418+#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */
3419+#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */
3420+#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */
3421+#define PKA_ECC_SCALAR_MUL_IN_MONTGOMERY_PARAM ((0x4B4U - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */
3422+#define PKA_ECC_SCALAR_MUL_IN_K ((0x508U - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */
3423+#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */
3424+#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */
3425+
3426+/* Compute ECC scalar multiplication output data */
3427+#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */
3428+#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */
3429+#define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_X1 ((0xDE8U - PKA_RAM_OFFSET)>>2) /*!< Output last double X1 coordinate */
3430+#define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Y1 ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Output last double Y1 coordinate */
3431+#define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Z1 ((0xE90U - PKA_RAM_OFFSET)>>2) /*!< Output last double Z1 coordinate */
3432+#define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_X2 ((0xEE4U - PKA_RAM_OFFSET)>>2) /*!< Output check point X2 coordinate */
3433+#define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Y2 ((0xF38U - PKA_RAM_OFFSET)>>2) /*!< Output check point Y2 coordinate */
3434+#define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Z2 ((0xF8CU - PKA_RAM_OFFSET)>>2) /*!< Output check point Z2 coordinate */
3435+
3436+/* Point check input data */
3437+#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */
3438+#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */
3439+#define PKA_POINT_CHECK_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */
3440+#define PKA_POINT_CHECK_IN_B_COEFF ((0x7FCU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */
3441+#define PKA_POINT_CHECK_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */
3442+#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */
3443+#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */
3444+
3445+/* Point check output data */
3446+#define PKA_POINT_CHECK_OUT_ERROR ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Output error */
3447+
3448+/* ECDSA signature input data */
3449+#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */
3450+#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */
3451+#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x408U - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */
3452+#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x40CU - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */
3453+#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */
3454+#define PKA_ECDSA_SIGN_IN_K ((0x508U - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */
3455+#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x55CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */
3456+#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */
3457+#define PKA_ECDSA_SIGN_IN_HASH_E ((0xDE8U - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */
3458+#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0xE3CU - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */
3459+#define PKA_ECDSA_SIGN_IN_ORDER_N ((0xE94U - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */
3460+
3461+/* ECDSA signature output data */
3462+#define PKA_ECDSA_SIGN_OUT_ERROR ((0xEE8U - PKA_RAM_OFFSET)>>2) /*!< Output error */
3463+#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x700U - PKA_RAM_OFFSET)>>2) /*!< Output signature r */
3464+#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x754U - PKA_RAM_OFFSET)>>2) /*!< Output signature s */
3465+#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x103CU - PKA_RAM_OFFSET)>>2) /*!< Output final point kP X coordinate */
3466+#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1090U - PKA_RAM_OFFSET)>>2) /*!< Output final point kP Y coordinate */
3467+
3468+/* ECDSA verification input data */
3469+#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */
3470+#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x4B4U - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */
3471+#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x45CU - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */
3472+#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x460U - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */
3473+#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x4B8U - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */
3474+#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x5E8U - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */
3475+#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x63CU - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */
3476+#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0xF40U - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */
3477+#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0xF94U - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */
3478+#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x1098U - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */
3479+#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */
3480+#define PKA_ECDSA_VERIF_IN_HASH_E ((0xFE8U - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */
3481+#define PKA_ECDSA_VERIF_IN_ORDER_N ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */
3482+
3483+/* ECDSA verification output data */
3484+#define PKA_ECDSA_VERIF_OUT_RESULT ((0x5B0U - PKA_RAM_OFFSET)>>2) /*!< Output result */
3485+
3486+/* RSA CRT exponentiation input data */
3487+#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */
3488+#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x65CU - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */
3489+#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */
3490+#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x7ECU - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */
3491+#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x97CU - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */
3492+#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */
3493+#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0xEECU - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */
3494+
3495+/* RSA CRT exponentiation output data */
3496+#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x724U - PKA_RAM_OFFSET)>>2) /*!< Output result */
3497+
3498+/* Modular reduction input data */
3499+#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x400U - PKA_RAM_OFFSET)>>2) /*!< Input operand length */
3500+#define PKA_MODULAR_REDUC_IN_OPERAND ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand */
3501+#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */
3502+#define PKA_MODULAR_REDUC_IN_MODULUS ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input modulus */
3503+
3504+/* Modular reduction output data */
3505+#define PKA_MODULAR_REDUC_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */
3506+
3507+/* Arithmetic addition input data */
3508+#define PKA_ARITHMETIC_ADD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
3509+#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
3510+#define PKA_ARITHMETIC_ADD_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
3511+
3512+/* Arithmetic addition output data */
3513+#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */
3514+
3515+/* Arithmetic substraction input data */
3516+#define PKA_ARITHMETIC_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
3517+#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
3518+#define PKA_ARITHMETIC_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
3519+
3520+/* Arithmetic substraction output data */
3521+#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */
3522+
3523+/* Arithmetic multiplication input data */
3524+#define PKA_ARITHMETIC_MUL_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
3525+#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
3526+#define PKA_ARITHMETIC_MUL_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
3527+
3528+/* Arithmetic multiplication output data */
3529+#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */
3530+
3531+/* Comparison input data */
3532+#define PKA_COMPARISON_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
3533+#define PKA_COMPARISON_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
3534+#define PKA_COMPARISON_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
3535+
3536+/* Comparison output data */
3537+#define PKA_COMPARISON_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */
3538+
3539+/* Modular addition input data */
3540+#define PKA_MODULAR_ADD_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
3541+#define PKA_MODULAR_ADD_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
3542+#define PKA_MODULAR_ADD_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
3543+#define PKA_MODULAR_ADD_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */
3544+
3545+/* Modular addition output data */
3546+#define PKA_MODULAR_ADD_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */
3547+
3548+/* Modular inversion input data */
3549+#define PKA_MODULAR_INV_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
3550+#define PKA_MODULAR_INV_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
3551+#define PKA_MODULAR_INV_IN_OP2_MOD ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */
3552+
3553+/* Modular inversion output data */
3554+#define PKA_MODULAR_INV_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */
3555+
3556+/* Modular substraction input data */
3557+#define PKA_MODULAR_SUB_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
3558+#define PKA_MODULAR_SUB_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
3559+#define PKA_MODULAR_SUB_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
3560+#define PKA_MODULAR_SUB_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */
3561+
3562+/* Modular substraction output data */
3563+#define PKA_MODULAR_SUB_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */
3564+
3565+/* Montgomery multiplication input data */
3566+#define PKA_MONTGOMERY_MUL_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
3567+#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
3568+#define PKA_MONTGOMERY_MUL_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
3569+#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input modulus */
3570+
3571+/* Montgomery multiplication output data */
3572+#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */
3573+
3574+/* Generic Arithmetic input data */
3575+#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x404U - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
3576+#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x8B4U - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
3577+#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0xA44U - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
3578+#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0xD5CU - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
3579+
3580+/* Generic Arithmetic output data */
3581+#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0xBD0U - PKA_RAM_OFFSET)>>2) /*!< Output result */
3582+
3583+/******************************************************************************/
3584+/* */
3585+/* FLASH */
3586+/* */
3587+/******************************************************************************/
3588+/******************* Bits definition for FLASH_ACR register *****************/
3589+#define FLASH_ACR_LATENCY_Pos (0U)
3590+#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
3591+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */
3592+#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
3593+#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */
3594+#define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */
3595+#define FLASH_ACR_PRFTEN_Pos (8U)
3596+#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
3597+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */
3598+#define FLASH_ACR_ICEN_Pos (9U)
3599+#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
3600+#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk /*!< Instruction cache enable */
3601+#define FLASH_ACR_DCEN_Pos (10U)
3602+#define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
3603+#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk /*!< Data cache enable */
3604+#define FLASH_ACR_ICRST_Pos (11U)
3605+#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
3606+#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk /*!< Instruction cache reset */
3607+#define FLASH_ACR_DCRST_Pos (12U)
3608+#define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
3609+#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk /*!< Data cache reset */
3610+#define FLASH_ACR_PES_Pos (15U)
3611+#define FLASH_ACR_PES_Msk (0x1UL << FLASH_ACR_PES_Pos) /*!< 0x00008000 */
3612+#define FLASH_ACR_PES FLASH_ACR_PES_Msk /*!< Program/erase suspend request */
3613+#define FLASH_ACR_EMPTY_Pos (16U)
3614+#define FLASH_ACR_EMPTY_Msk (0x1UL << FLASH_ACR_EMPTY_Pos) /*!< 0x00010000 */
3615+#define FLASH_ACR_EMPTY FLASH_ACR_EMPTY_Msk /*!< Flash use area empty */
3616+
3617+#define FLASH_ACR_LATENCY_0WS (0x0UL << FLASH_ACR_LATENCY_Pos) /*!< FLASH Zero wait state */
3618+#define FLASH_ACR_LATENCY_1WS (FLASH_ACR_LATENCY_0 << FLASH_ACR_LATENCY_Pos) /*!< FLASH One wait state */
3619+#define FLASH_ACR_LATENCY_2WS (FLASH_ACR_LATENCY_1 << FLASH_ACR_LATENCY_Pos) /*!< FLASH Two wait states */
3620+#define FLASH_ACR_LATENCY_3WS ((FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0) << FLASH_ACR_LATENCY_Pos) /*!< FLASH Three wait states */
3621+
3622+/******************* Bits definition for FLASH_SR register ******************/
3623+#define FLASH_SR_EOP_Pos (0U)
3624+#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
3625+#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of Operation */
3626+#define FLASH_SR_OPERR_Pos (1U)
3627+#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */
3628+#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk /*!< Operation error */
3629+#define FLASH_SR_PROGERR_Pos (3U)
3630+#define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */
3631+#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk /*!< Programming error */
3632+#define FLASH_SR_WRPERR_Pos (4U)
3633+#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
3634+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */
3635+#define FLASH_SR_PGAERR_Pos (5U)
3636+#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
3637+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming alignment error */
3638+#define FLASH_SR_SIZERR_Pos (6U)
3639+#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */
3640+#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */
3641+#define FLASH_SR_PGSERR_Pos (7U)
3642+#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
3643+#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< Programming sequence error */
3644+#define FLASH_SR_MISERR_Pos (8U)
3645+#define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */
3646+#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk /*!< Fast programming data miss error */
3647+#define FLASH_SR_FASTERR_Pos (9U)
3648+#define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */
3649+#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk /*!< Fast programming error */
3650+#define FLASH_SR_OPTNV_Pos (13U)
3651+#define FLASH_SR_OPTNV_Msk (0x1UL << FLASH_SR_OPTNV_Pos) /*!< 0x00002000 */
3652+#define FLASH_SR_OPTNV FLASH_SR_OPTNV_Msk /*!< User option OPTVAL indication */
3653+#define FLASH_SR_RDERR_Pos (14U)
3654+#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */
3655+#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< PCROP read error */
3656+#define FLASH_SR_OPTVERR_Pos (15U)
3657+#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */
3658+#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option validity error */
3659+#define FLASH_SR_BSY_Pos (16U)
3660+#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
3661+#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Flash Busy */
3662+#define FLASH_SR_CFGBSY_Pos (18U)
3663+#define FLASH_SR_CFGBSY_Msk (0x1UL << FLASH_SR_CFGBSY_Pos) /*!< 0x00040000 */
3664+#define FLASH_SR_CFGBSY FLASH_SR_CFGBSY_Msk /*!< Programming or erase configuration busy */
3665+#define FLASH_SR_PESD_Pos (19U)
3666+#define FLASH_SR_PESD_Msk (0x1UL << FLASH_SR_PESD_Pos) /*!< 0x00080000 */
3667+#define FLASH_SR_PESD FLASH_SR_PESD_Msk /*!< Programming/erase operation suspended */
3668+
3669+/******************* Bits definition for FLASH_CR register ******************/
3670+#define FLASH_CR_PG_Pos (0U)
3671+#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */
3672+#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Flash programming */
3673+#define FLASH_CR_PER_Pos (1U)
3674+#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */
3675+#define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page erase */
3676+#define FLASH_CR_MER_Pos (2U)
3677+#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00000004 */
3678+#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass erase */
3679+#define FLASH_CR_PNB_Pos (3U)
3680+#define FLASH_CR_PNB_Msk (0xFFUL << FLASH_CR_PNB_Pos) /*!< 0x000007F8 */
3681+#define FLASH_CR_PNB FLASH_CR_PNB_Msk /*!< Page number selection mask */
3682+#define FLASH_CR_STRT_Pos (16U)
3683+#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
3684+#define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start an erase operation */
3685+#define FLASH_CR_OPTSTRT_Pos (17U)
3686+#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */
3687+#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk /*!< Options modification start */
3688+#define FLASH_CR_FSTPG_Pos (18U)
3689+#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */
3690+#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk /*!< Fast programming */
3691+#define FLASH_CR_EOPIE_Pos (24U)
3692+#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
3693+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */
3694+#define FLASH_CR_ERRIE_Pos (25U)
3695+#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */
3696+#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error interrupt enable */
3697+#define FLASH_CR_RDERRIE_Pos (26U)
3698+#define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */
3699+#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk /*!< PCROP read error interrupt enable */
3700+#define FLASH_CR_OBL_LAUNCH_Pos (27U)
3701+#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
3702+#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /*!< Force the option byte loading */
3703+#define FLASH_CR_OPTLOCK_Pos (30U)
3704+#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */
3705+#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk /*!< Options lock */
3706+#define FLASH_CR_LOCK_Pos (31U)
3707+#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
3708+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Flash control register lock */
3709+
3710+/******************* Bits definition for FLASH_ECCR register ****************/
3711+#define FLASH_ECCR_ADDR_ECC_Pos (0U)
3712+#define FLASH_ECCR_ADDR_ECC_Msk (0x1FFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0001FFFF */
3713+#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< double-word address ECC fail */
3714+#define FLASH_ECCR_SYSF_ECC_Pos (20U)
3715+#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */
3716+#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System flash ECC fail */
3717+#define FLASH_ECCR_ECCCIE_Pos (24U)
3718+#define FLASH_ECCR_ECCCIE_Msk (0x1UL << FLASH_ECCR_ECCCIE_Pos) /*!< 0x01000000 */
3719+#define FLASH_ECCR_ECCCIE FLASH_ECCR_ECCCIE_Msk /*!< ECC correction interrupt enable */
3720+#define FLASH_ECCR_CPUID_Pos (26U)
3721+#define FLASH_ECCR_CPUID_Msk (0x7UL << FLASH_ECCR_CPUID_Pos) /*!< 0x1C000000 */
3722+#define FLASH_ECCR_CPUID FLASH_ECCR_CPUID_Msk /*!< CPU identification */
3723+#define FLASH_ECCR_ECCC_Pos (30U)
3724+#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */
3725+#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */
3726+#define FLASH_ECCR_ECCD_Pos (31U)
3727+#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */
3728+#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */
3729+
3730+/******************* Bits definition for FLASH_OPTR register ****************/
3731+#define FLASH_OPTR_RDP_Pos (0U)
3732+#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */
3733+#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk /*!< Read protection level */
3734+#define FLASH_OPTR_ESE_Pos (8U)
3735+#define FLASH_OPTR_ESE_Msk (0x1UL << FLASH_OPTR_ESE_Pos) /*!< 0x00000100 */
3736+#define FLASH_OPTR_ESE FLASH_OPTR_ESE_Msk /*!< Security enable */
3737+#define FLASH_OPTR_BOR_LEV_Pos (9U)
3738+#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000E00 */
3739+#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR reset level mask */
3740+#define FLASH_OPTR_BOR_LEV_0 (0x1U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */
3741+#define FLASH_OPTR_BOR_LEV_1 (0x2U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */
3742+#define FLASH_OPTR_BOR_LEV_2 (0x4U << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000800 */
3743+#define FLASH_OPTR_nRST_STOP_Pos (12U)
3744+#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */
3745+#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< Reset option in Stop mode */
3746+#define FLASH_OPTR_nRST_STDBY_Pos (13U)
3747+#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */
3748+#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< Reset option in Standby mode */
3749+#define FLASH_OPTR_nRST_SHDW_Pos (14U)
3750+#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */
3751+#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk /*!< Reset option in Shutdown mode */
3752+#define FLASH_OPTR_IWDG_SW_Pos (16U)
3753+#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */
3754+#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */
3755+#define FLASH_OPTR_IWDG_STOP_Pos (17U)
3756+#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */
3757+#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk /*!< Independent watchdog counter option in Stop mode */
3758+#define FLASH_OPTR_IWDG_STDBY_Pos (18U)
3759+#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
3760+#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk /*!< Independent watchdog counter option in Standby mode */
3761+#define FLASH_OPTR_WWDG_SW_Pos (19U)
3762+#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */
3763+#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk /*!< Window watchdog selection */
3764+#define FLASH_OPTR_nBOOT1_Pos (23U)
3765+#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x00800000 */
3766+#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk /*!< Boot Configuration */
3767+#define FLASH_OPTR_SRAM2PE_Pos (24U)
3768+#define FLASH_OPTR_SRAM2PE_Msk (0x1UL << FLASH_OPTR_SRAM2PE_Pos) /*!< 0x01000000 */
3769+#define FLASH_OPTR_SRAM2PE FLASH_OPTR_SRAM2PE_Msk /*!< SRAM2 parity check enable */
3770+#define FLASH_OPTR_SRAM2RST_Pos (25U)
3771+#define FLASH_OPTR_SRAM2RST_Msk (0x1UL << FLASH_OPTR_SRAM2RST_Pos) /*!< 0x02000000 */
3772+#define FLASH_OPTR_SRAM2RST FLASH_OPTR_SRAM2RST_Msk /*!< SRAM2 erase option when system reset */
3773+#define FLASH_OPTR_nSWBOOT0_Pos (26U)
3774+#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */
3775+#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk /*!< Software BOOT0 */
3776+#define FLASH_OPTR_nBOOT0_Pos (27U)
3777+#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */
3778+#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk /*!< BOOT0 option bit */
3779+#define FLASH_OPTR_AGC_TRIM_Pos (29U)
3780+#define FLASH_OPTR_AGC_TRIM_Msk (0x7UL << FLASH_OPTR_AGC_TRIM_Pos) /*!< 0xE0000000 */
3781+#define FLASH_OPTR_AGC_TRIM FLASH_OPTR_AGC_TRIM_Msk /*!< Automatic Gain Control trimming mask */
3782+#define FLASH_OPTR_AGC_TRIM_0 (0x1U << FLASH_OPTR_AGC_TRIM_Pos) /*!< 0x20000000 */
3783+#define FLASH_OPTR_AGC_TRIM_1 (0x2U << FLASH_OPTR_AGC_TRIM_Pos) /*!< 0x40000000 */
3784+#define FLASH_OPTR_AGC_TRIM_2 (0x4U << FLASH_OPTR_AGC_TRIM_Pos) /*!< 0x80000000 */
3785+
3786+/****************** Bits definition for FLASH_PCROP1ASR register ************/
3787+#define FLASH_PCROP1ASR_PCROP1A_STRT_Pos (0U)
3788+#define FLASH_PCROP1ASR_PCROP1A_STRT_Msk (0x1FFUL << FLASH_PCROP1ASR_PCROP1A_STRT_Pos) /*!< 0x000001FF */
3789+#define FLASH_PCROP1ASR_PCROP1A_STRT FLASH_PCROP1ASR_PCROP1A_STRT_Msk /*!< PCROP area A start offset */
3790+
3791+/****************** Bits definition for FLASH_PCROP1AER register ************/
3792+#define FLASH_PCROP1AER_PCROP1A_END_Pos (0U)
3793+#define FLASH_PCROP1AER_PCROP1A_END_Msk (0x1FFUL << FLASH_PCROP1AER_PCROP1A_END_Pos) /*!< 0x000001FF */
3794+#define FLASH_PCROP1AER_PCROP1A_END FLASH_PCROP1AER_PCROP1A_END_Msk /*!< PCROP area A end offset */
3795+#define FLASH_PCROP1AER_PCROP_RDP_Pos (31U)
3796+#define FLASH_PCROP1AER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1AER_PCROP_RDP_Pos) /*!< 0x80000000 */
3797+#define FLASH_PCROP1AER_PCROP_RDP FLASH_PCROP1AER_PCROP_RDP_Msk /*!< PCROP area preserved when RDP level decreased */
3798+
3799+/****************** Bits definition for FLASH_WRP1AR register ***************/
3800+#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U)
3801+#define FLASH_WRP1AR_WRP1A_STRT_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */
3802+#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk /*!< WRP area A start offset */
3803+#define FLASH_WRP1AR_WRP1A_END_Pos (16U)
3804+#define FLASH_WRP1AR_WRP1A_END_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
3805+#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk /*!< WRP area A end offset */
3806+
3807+/****************** Bits definition for FLASH_WRP1BR register ***************/
3808+#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
3809+#define FLASH_WRP1BR_WRP1B_STRT_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */
3810+#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk /*!< WRP area B start offset */
3811+#define FLASH_WRP1BR_WRP1B_END_Pos (16U)
3812+#define FLASH_WRP1BR_WRP1B_END_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
3813+#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk /*!< WRP area B end offset */
3814+
3815+/****************** Bits definition for FLASH_PCROP1BSR register ************/
3816+#define FLASH_PCROP1BSR_PCROP1B_STRT_Pos (0U)
3817+#define FLASH_PCROP1BSR_PCROP1B_STRT_Msk (0x1FFUL << FLASH_PCROP1BSR_PCROP1B_STRT_Pos) /*!< 0x000001FF */
3818+#define FLASH_PCROP1BSR_PCROP1B_STRT FLASH_PCROP1BSR_PCROP1B_STRT_Msk /*!< PCROP area B start offset */
3819+
3820+/****************** Bits definition for FLASH_PCROP1BER register ************/
3821+#define FLASH_PCROP1BER_PCROP1B_END_Pos (0U)
3822+#define FLASH_PCROP1BER_PCROP1B_END_Msk (0x1FFUL << FLASH_PCROP1BER_PCROP1B_END_Pos) /*!< 0x000001FF */
3823+#define FLASH_PCROP1BER_PCROP1B_END FLASH_PCROP1BER_PCROP1B_END_Msk /*!< PCROP area B end offset */
3824+
3825+/****************** Bits definition for FLASH_IPCCBR register ************/
3826+#define FLASH_IPCCBR_IPCCDBA_Pos (0U)
3827+#define FLASH_IPCCBR_IPCCDBA_Msk (0x3FFFUL << FLASH_IPCCBR_IPCCDBA_Pos) /*!< 0x00003FFF */
3828+#define FLASH_IPCCBR_IPCCDBA FLASH_IPCCBR_IPCCDBA_Msk /*!< IPCC data buffer base address */
3829+
3830+/****************** Bits definition for FLASH_SFR register ************/
3831+#define FLASH_SFR_SFSA_Pos (0U)
3832+#define FLASH_SFR_SFSA_Msk (0xFFUL << FLASH_SFR_SFSA_Pos) /*!< 0x000000FF */
3833+#define FLASH_SFR_SFSA FLASH_SFR_SFSA_Msk /* Secure flash start address */
3834+#define FLASH_SFR_FSD_Pos (8U)
3835+#define FLASH_SFR_FSD_Msk (0x1UL << FLASH_SFR_FSD_Pos) /*!< 0x00000100 */
3836+#define FLASH_SFR_FSD FLASH_SFR_FSD_Msk /* Flash mode secure */
3837+#define FLASH_SFR_DDS_Pos (12U)
3838+#define FLASH_SFR_DDS_Msk (0x1UL << FLASH_SFR_DDS_Pos) /*!< 0x00001000 */
3839+#define FLASH_SFR_DDS FLASH_SFR_DDS_Msk /* Enabling and disabling CPU2 Debug access */
3840+
3841+/****************** Bits definition for FLASH_SRRVR register ************/
3842+#define FLASH_SRRVR_SBRV_Pos (0U)
3843+#define FLASH_SRRVR_SBRV_Msk (0x3FFFFUL << FLASH_SRRVR_SBRV_Pos) /*!< 0x0003FFFF */
3844+#define FLASH_SRRVR_SBRV FLASH_SRRVR_SBRV_Msk /* CPU2 boot reset vector memory offset */
3845+
3846+#define FLASH_SRRVR_SBRSA_Pos (18U)
3847+#define FLASH_SRRVR_SBRSA_Msk (0x1FUL << FLASH_SRRVR_SBRSA_Pos) /*!< 0x007C0000 */
3848+#define FLASH_SRRVR_SBRSA FLASH_SRRVR_SBRSA_Msk /* Secure backup SRAM2a start address */
3849+#define FLASH_SRRVR_BRSD_Pos (23U)
3850+#define FLASH_SRRVR_BRSD_Msk (0x1UL << FLASH_SRRVR_BRSD_Pos) /*!< 0x00800000 */
3851+#define FLASH_SRRVR_BRSD FLASH_SRRVR_BRSD_Msk /* Backup SRAM2A secure mode */
3852+
3853+#define FLASH_SRRVR_SNBRSA_Pos (25U)
3854+#define FLASH_SRRVR_SNBRSA_Msk (0x1FUL << FLASH_SRRVR_SNBRSA_Pos) /*!< 0x3E000000 */
3855+#define FLASH_SRRVR_SNBRSA FLASH_SRRVR_SNBRSA_Msk /* Secure non-backup SRAM2b start address */
3856+#define FLASH_SRRVR_NBRSD_Pos (30U)
3857+#define FLASH_SRRVR_NBRSD_Msk (0x1UL << FLASH_SRRVR_NBRSD_Pos) /*!< 0x40000000 */
3858+#define FLASH_SRRVR_NBRSD FLASH_SRRVR_NBRSD_Msk /* Non-backup SRAM2B secure mode */
3859+#define FLASH_SRRVR_C2OPT_Pos (31U)
3860+#define FLASH_SRRVR_C2OPT_Msk (0x1UL << FLASH_SRRVR_C2OPT_Pos) /*!< 0x80000000 */
3861+#define FLASH_SRRVR_C2OPT FLASH_SRRVR_C2OPT_Msk /* CPU2 boot reset vector memory selection */
3862+
3863+/****************** Bits definition for FLASH_C2ACR register ************/
3864+#define FLASH_C2ACR_PRFTEN_Pos (8U)
3865+#define FLASH_C2ACR_PRFTEN_Msk (0x1UL << FLASH_C2ACR_PRFTEN_Pos) /*!< 0x00000100 */
3866+#define FLASH_C2ACR_PRFTEN FLASH_C2ACR_PRFTEN_Msk /*!< CPU2 Prefetch enable */
3867+#define FLASH_C2ACR_ICEN_Pos (9U)
3868+#define FLASH_C2ACR_ICEN_Msk (0x1UL << FLASH_C2ACR_ICEN_Pos) /*!< 0x00000200 */
3869+#define FLASH_C2ACR_ICEN FLASH_C2ACR_ICEN_Msk /*!< CPU2 Instruction cache enable */
3870+#define FLASH_C2ACR_ICRST_Pos (11U)
3871+#define FLASH_C2ACR_ICRST_Msk (0x1UL << FLASH_C2ACR_ICRST_Pos) /*!< 0x00000800 */
3872+#define FLASH_C2ACR_ICRST FLASH_C2ACR_ICRST_Msk /*!< CPU2 Instruction cache reset */
3873+#define FLASH_C2ACR_PES_Pos (15U)
3874+#define FLASH_C2ACR_PES_Msk (0x1UL << FLASH_C2ACR_PES_Pos) /*!< 0x00008000 */
3875+#define FLASH_C2ACR_PES FLASH_C2ACR_PES_Msk /*!< CPU2 Program/erase suspend request */
3876+
3877+/****************** Bits definition for FLASH_C2SR register ************/
3878+#define FLASH_C2SR_EOP_Pos (0U)
3879+#define FLASH_C2SR_EOP_Msk (0x1UL << FLASH_C2SR_EOP_Pos) /*!< 0x00000001 */
3880+#define FLASH_C2SR_EOP FLASH_C2SR_EOP_Msk /*!< CPU2 End of operation */
3881+#define FLASH_C2SR_OPERR_Pos (1U)
3882+#define FLASH_C2SR_OPERR_Msk (0x1UL << FLASH_C2SR_OPERR_Pos) /*!< 0x00000002 */
3883+#define FLASH_C2SR_OPERR FLASH_C2SR_OPERR_Msk /*!< CPU2 Operation error */
3884+#define FLASH_C2SR_PROGERR_Pos (3U)
3885+#define FLASH_C2SR_PROGERR_Msk (0x1UL << FLASH_C2SR_PROGERR_Pos) /*!< 0x00000008 */
3886+#define FLASH_C2SR_PROGERR FLASH_C2SR_PROGERR_Msk /*!< CPU2 Programming error */
3887+#define FLASH_C2SR_WRPERR_Pos (4U)
3888+#define FLASH_C2SR_WRPERR_Msk (0x1UL << FLASH_C2SR_WRPERR_Pos) /*!< 0x00000010 */
3889+#define FLASH_C2SR_WRPERR FLASH_C2SR_WRPERR_Msk /*!< CPU2 Write protection error */
3890+#define FLASH_C2SR_PGAERR_Pos (5U)
3891+#define FLASH_C2SR_PGAERR_Msk (0x1UL << FLASH_C2SR_PGAERR_Pos) /*!< 0x00000020 */
3892+#define FLASH_C2SR_PGAERR FLASH_C2SR_PGAERR_Msk /*!< CPU2 Programming alignment error */
3893+#define FLASH_C2SR_SIZERR_Pos (6U)
3894+#define FLASH_C2SR_SIZERR_Msk (0x1UL << FLASH_C2SR_SIZERR_Pos) /*!< 0x00000040 */
3895+#define FLASH_C2SR_SIZERR FLASH_C2SR_SIZERR_Msk /*!< CPU2 Size error */
3896+#define FLASH_C2SR_PGSERR_Pos (7U)
3897+#define FLASH_C2SR_PGSERR_Msk (0x1UL << FLASH_C2SR_PGSERR_Pos) /*!< 0x00000080 */
3898+#define FLASH_C2SR_PGSERR FLASH_C2SR_PGSERR_Msk /*!< CPU2 Programming sequence error */
3899+#define FLASH_C2SR_MISERR_Pos (8U)
3900+#define FLASH_C2SR_MISERR_Msk (0x1UL << FLASH_C2SR_MISERR_Pos) /*!< 0x00000100 */
3901+#define FLASH_C2SR_MISERR FLASH_C2SR_MISERR_Msk /*!< CPU2 Fast programming data miss error */
3902+#define FLASH_C2SR_FASTERR_Pos (9U)
3903+#define FLASH_C2SR_FASTERR_Msk (0x1UL << FLASH_C2SR_FASTERR_Pos) /*!< 0x00000200 */
3904+#define FLASH_C2SR_FASTERR FLASH_C2SR_FASTERR_Msk /*!< CPU2 Fast programming error */
3905+#define FLASH_C2SR_RDERR_Pos (14U)
3906+#define FLASH_C2SR_RDERR_Msk (0x1UL << FLASH_C2SR_RDERR_Pos) /*!< 0x00004000 */
3907+#define FLASH_C2SR_RDERR FLASH_C2SR_RDERR_Msk /*!< CPU2 PCROP read error */
3908+#define FLASH_C2SR_BSY_Pos (16U)
3909+#define FLASH_C2SR_BSY_Msk (0x1UL << FLASH_C2SR_BSY_Pos) /*!< 0x00010000 */
3910+#define FLASH_C2SR_BSY FLASH_C2SR_BSY_Msk /*!< CPU2 Flash busy */
3911+#define FLASH_C2SR_CFGBSY_Pos (18U)
3912+#define FLASH_C2SR_CFGBSY_Msk (0x1UL << FLASH_C2SR_CFGBSY_Pos) /*!< 0x00040000 */
3913+#define FLASH_C2SR_CFGBSY FLASH_C2SR_CFGBSY_Msk /*!< CPU2 Programming or erase configuration busy */
3914+#define FLASH_C2SR_PESD_Pos (19U)
3915+#define FLASH_C2SR_PESD_Msk (0x1UL << FLASH_C2SR_PESD_Pos) /*!< 0x00080000 */
3916+#define FLASH_C2SR_PESD FLASH_C2SR_PESD_Msk /*!< CPU2 Programming/erase operation suspended */
3917+
3918+/****************** Bits definition for FLASH_C2CR register ************/
3919+#define FLASH_C2CR_PG_Pos (0U)
3920+#define FLASH_C2CR_PG_Msk (0x1UL << FLASH_C2CR_PG_Pos) /*!< 0x00000001 */
3921+#define FLASH_C2CR_PG FLASH_C2CR_PG_Msk /*!< CPU2 Flash programming */
3922+#define FLASH_C2CR_PER_Pos (1U)
3923+#define FLASH_C2CR_PER_Msk (0x1UL << FLASH_C2CR_PER_Pos) /*!< 0x00000002 */
3924+#define FLASH_C2CR_PER FLASH_C2CR_PER_Msk /*!< CPU2 Page erase */
3925+#define FLASH_C2CR_MER_Pos (2U)
3926+#define FLASH_C2CR_MER_Msk (0x1UL << FLASH_C2CR_MER_Pos) /*!< 0x00000004 */
3927+#define FLASH_C2CR_MER FLASH_C2CR_MER_Msk /*!< CPU2 Mass erase */
3928+#define FLASH_C2CR_PNB_Pos (3U)
3929+#define FLASH_C2CR_PNB_Msk (0xFFUL << FLASH_C2CR_PNB_Pos) /*!< 0x000007F8 */
3930+#define FLASH_C2CR_PNB FLASH_C2CR_PNB_Msk /*!< CPU2 Page number selection mask */
3931+#define FLASH_C2CR_STRT_Pos (16U)
3932+#define FLASH_C2CR_STRT_Msk (0x1UL << FLASH_C2CR_STRT_Pos) /*!< 0x00010000 */
3933+#define FLASH_C2CR_STRT FLASH_C2CR_STRT_Msk /*!< CPU2 Start an erase operation */
3934+#define FLASH_C2CR_FSTPG_Pos (18U)
3935+#define FLASH_C2CR_FSTPG_Msk (0x1UL << FLASH_C2CR_FSTPG_Pos) /*!< 0x00040000 */
3936+#define FLASH_C2CR_FSTPG FLASH_C2CR_FSTPG_Msk /*!< CPU2 Fast programming */
3937+#define FLASH_C2CR_EOPIE_Pos (24U)
3938+#define FLASH_C2CR_EOPIE_Msk (0x1UL << FLASH_C2CR_EOPIE_Pos) /*!< 0x01000000 */
3939+#define FLASH_C2CR_EOPIE FLASH_C2CR_EOPIE_Msk /*!< CPU2 End of operation interrupt enable */
3940+#define FLASH_C2CR_ERRIE_Pos (25U)
3941+#define FLASH_C2CR_ERRIE_Msk (0x1UL << FLASH_C2CR_ERRIE_Pos) /*!< 0x02000000 */
3942+#define FLASH_C2CR_ERRIE FLASH_C2CR_ERRIE_Msk /*!< CPU2 Error interrupt enable */
3943+#define FLASH_C2CR_RDERRIE_Pos (26U)
3944+#define FLASH_C2CR_RDERRIE_Msk (0x1UL << FLASH_C2CR_RDERRIE_Pos) /*!< 0x04000000 */
3945+#define FLASH_C2CR_RDERRIE FLASH_C2CR_RDERRIE_Msk /*!< CPU2 PCROP read error interrupt enable */
3946+
3947+/******************************************************************************/
3948+/* */
3949+/* General Purpose I/O */
3950+/* */
3951+/******************************************************************************/
3952+/****************** Bits definition for GPIO_MODER register *****************/
3953+#define GPIO_MODER_MODE0_Pos (0U)
3954+#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
3955+#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
3956+#define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
3957+#define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
3958+#define GPIO_MODER_MODE1_Pos (2U)
3959+#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
3960+#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
3961+#define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
3962+#define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
3963+#define GPIO_MODER_MODE2_Pos (4U)
3964+#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
3965+#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
3966+#define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
3967+#define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
3968+#define GPIO_MODER_MODE3_Pos (6U)
3969+#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
3970+#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
3971+#define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
3972+#define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
3973+#define GPIO_MODER_MODE4_Pos (8U)
3974+#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
3975+#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
3976+#define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
3977+#define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
3978+#define GPIO_MODER_MODE5_Pos (10U)
3979+#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
3980+#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
3981+#define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
3982+#define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
3983+#define GPIO_MODER_MODE6_Pos (12U)
3984+#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
3985+#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
3986+#define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
3987+#define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
3988+#define GPIO_MODER_MODE7_Pos (14U)
3989+#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
3990+#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
3991+#define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
3992+#define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
3993+#define GPIO_MODER_MODE8_Pos (16U)
3994+#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
3995+#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
3996+#define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
3997+#define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
3998+#define GPIO_MODER_MODE9_Pos (18U)
3999+#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
4000+#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
4001+#define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
4002+#define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
4003+#define GPIO_MODER_MODE10_Pos (20U)
4004+#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
4005+#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
4006+#define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
4007+#define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
4008+#define GPIO_MODER_MODE11_Pos (22U)
4009+#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
4010+#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
4011+#define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
4012+#define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
4013+#define GPIO_MODER_MODE12_Pos (24U)
4014+#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
4015+#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
4016+#define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
4017+#define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
4018+#define GPIO_MODER_MODE13_Pos (26U)
4019+#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
4020+#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
4021+#define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
4022+#define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
4023+#define GPIO_MODER_MODE14_Pos (28U)
4024+#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
4025+#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
4026+#define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
4027+#define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
4028+#define GPIO_MODER_MODE15_Pos (30U)
4029+#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
4030+#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
4031+#define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
4032+#define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
4033+
4034+/****************** Bits definition for GPIO_OTYPER register ****************/
4035+#define GPIO_OTYPER_OT0_Pos (0U)
4036+#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
4037+#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
4038+#define GPIO_OTYPER_OT1_Pos (1U)
4039+#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
4040+#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
4041+#define GPIO_OTYPER_OT2_Pos (2U)
4042+#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
4043+#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
4044+#define GPIO_OTYPER_OT3_Pos (3U)
4045+#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
4046+#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
4047+#define GPIO_OTYPER_OT4_Pos (4U)
4048+#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
4049+#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
4050+#define GPIO_OTYPER_OT5_Pos (5U)
4051+#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
4052+#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
4053+#define GPIO_OTYPER_OT6_Pos (6U)
4054+#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
4055+#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
4056+#define GPIO_OTYPER_OT7_Pos (7U)
4057+#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
4058+#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
4059+#define GPIO_OTYPER_OT8_Pos (8U)
4060+#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
4061+#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
4062+#define GPIO_OTYPER_OT9_Pos (9U)
4063+#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
4064+#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
4065+#define GPIO_OTYPER_OT10_Pos (10U)
4066+#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
4067+#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
4068+#define GPIO_OTYPER_OT11_Pos (11U)
4069+#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
4070+#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
4071+#define GPIO_OTYPER_OT12_Pos (12U)
4072+#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
4073+#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
4074+#define GPIO_OTYPER_OT13_Pos (13U)
4075+#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
4076+#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
4077+#define GPIO_OTYPER_OT14_Pos (14U)
4078+#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
4079+#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
4080+#define GPIO_OTYPER_OT15_Pos (15U)
4081+#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
4082+#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
4083+
4084+/****************** Bits definition for GPIO_OSPEEDR register ***************/
4085+#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
4086+#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
4087+#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
4088+#define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
4089+#define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
4090+#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
4091+#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
4092+#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
4093+#define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
4094+#define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
4095+#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
4096+#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
4097+#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
4098+#define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
4099+#define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
4100+#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
4101+#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
4102+#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
4103+#define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
4104+#define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
4105+#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
4106+#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
4107+#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
4108+#define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
4109+#define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
4110+#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
4111+#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
4112+#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
4113+#define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
4114+#define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
4115+#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
4116+#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
4117+#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
4118+#define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
4119+#define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
4120+#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
4121+#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
4122+#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
4123+#define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
4124+#define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
4125+#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
4126+#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
4127+#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
4128+#define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
4129+#define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
4130+#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
4131+#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
4132+#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
4133+#define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
4134+#define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
4135+#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
4136+#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
4137+#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
4138+#define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
4139+#define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
4140+#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
4141+#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
4142+#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
4143+#define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
4144+#define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
4145+#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
4146+#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
4147+#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
4148+#define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
4149+#define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
4150+#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
4151+#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
4152+#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
4153+#define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
4154+#define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
4155+#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
4156+#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
4157+#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
4158+#define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
4159+#define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
4160+#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
4161+#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
4162+#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
4163+#define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
4164+#define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
4165+
4166+/****************** Bits definition for GPIO_PUPDR register *****************/
4167+#define GPIO_PUPDR_PUPD0_Pos (0U)
4168+#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
4169+#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
4170+#define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
4171+#define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
4172+#define GPIO_PUPDR_PUPD1_Pos (2U)
4173+#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
4174+#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
4175+#define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
4176+#define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
4177+#define GPIO_PUPDR_PUPD2_Pos (4U)
4178+#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
4179+#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
4180+#define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
4181+#define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
4182+#define GPIO_PUPDR_PUPD3_Pos (6U)
4183+#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
4184+#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
4185+#define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
4186+#define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
4187+#define GPIO_PUPDR_PUPD4_Pos (8U)
4188+#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
4189+#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
4190+#define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
4191+#define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
4192+#define GPIO_PUPDR_PUPD5_Pos (10U)
4193+#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
4194+#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
4195+#define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
4196+#define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
4197+#define GPIO_PUPDR_PUPD6_Pos (12U)
4198+#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
4199+#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
4200+#define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
4201+#define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
4202+#define GPIO_PUPDR_PUPD7_Pos (14U)
4203+#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
4204+#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
4205+#define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
4206+#define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
4207+#define GPIO_PUPDR_PUPD8_Pos (16U)
4208+#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
4209+#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
4210+#define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
4211+#define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
4212+#define GPIO_PUPDR_PUPD9_Pos (18U)
4213+#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
4214+#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
4215+#define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
4216+#define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
4217+#define GPIO_PUPDR_PUPD10_Pos (20U)
4218+#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
4219+#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
4220+#define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
4221+#define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
4222+#define GPIO_PUPDR_PUPD11_Pos (22U)
4223+#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
4224+#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
4225+#define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
4226+#define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
4227+#define GPIO_PUPDR_PUPD12_Pos (24U)
4228+#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
4229+#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
4230+#define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
4231+#define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
4232+#define GPIO_PUPDR_PUPD13_Pos (26U)
4233+#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
4234+#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
4235+#define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
4236+#define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
4237+#define GPIO_PUPDR_PUPD14_Pos (28U)
4238+#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
4239+#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
4240+#define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
4241+#define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
4242+#define GPIO_PUPDR_PUPD15_Pos (30U)
4243+#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
4244+#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
4245+#define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
4246+#define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
4247+
4248+/****************** Bits definition for GPIO_IDR register *******************/
4249+#define GPIO_IDR_ID0_Pos (0U)
4250+#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
4251+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
4252+#define GPIO_IDR_ID1_Pos (1U)
4253+#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
4254+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
4255+#define GPIO_IDR_ID2_Pos (2U)
4256+#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
4257+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
4258+#define GPIO_IDR_ID3_Pos (3U)
4259+#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
4260+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
4261+#define GPIO_IDR_ID4_Pos (4U)
4262+#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
4263+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
4264+#define GPIO_IDR_ID5_Pos (5U)
4265+#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
4266+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
4267+#define GPIO_IDR_ID6_Pos (6U)
4268+#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
4269+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
4270+#define GPIO_IDR_ID7_Pos (7U)
4271+#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
4272+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
4273+#define GPIO_IDR_ID8_Pos (8U)
4274+#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
4275+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
4276+#define GPIO_IDR_ID9_Pos (9U)
4277+#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
4278+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
4279+#define GPIO_IDR_ID10_Pos (10U)
4280+#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
4281+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
4282+#define GPIO_IDR_ID11_Pos (11U)
4283+#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
4284+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
4285+#define GPIO_IDR_ID12_Pos (12U)
4286+#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
4287+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
4288+#define GPIO_IDR_ID13_Pos (13U)
4289+#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
4290+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
4291+#define GPIO_IDR_ID14_Pos (14U)
4292+#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
4293+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
4294+#define GPIO_IDR_ID15_Pos (15U)
4295+#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
4296+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
4297+
4298+/****************** Bits definition for GPIO_ODR register *******************/
4299+#define GPIO_ODR_OD0_Pos (0U)
4300+#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
4301+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
4302+#define GPIO_ODR_OD1_Pos (1U)
4303+#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
4304+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
4305+#define GPIO_ODR_OD2_Pos (2U)
4306+#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
4307+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
4308+#define GPIO_ODR_OD3_Pos (3U)
4309+#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
4310+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
4311+#define GPIO_ODR_OD4_Pos (4U)
4312+#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
4313+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
4314+#define GPIO_ODR_OD5_Pos (5U)
4315+#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
4316+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
4317+#define GPIO_ODR_OD6_Pos (6U)
4318+#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
4319+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
4320+#define GPIO_ODR_OD7_Pos (7U)
4321+#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
4322+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
4323+#define GPIO_ODR_OD8_Pos (8U)
4324+#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
4325+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
4326+#define GPIO_ODR_OD9_Pos (9U)
4327+#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
4328+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
4329+#define GPIO_ODR_OD10_Pos (10U)
4330+#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
4331+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
4332+#define GPIO_ODR_OD11_Pos (11U)
4333+#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
4334+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
4335+#define GPIO_ODR_OD12_Pos (12U)
4336+#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
4337+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
4338+#define GPIO_ODR_OD13_Pos (13U)
4339+#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
4340+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
4341+#define GPIO_ODR_OD14_Pos (14U)
4342+#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
4343+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
4344+#define GPIO_ODR_OD15_Pos (15U)
4345+#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
4346+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
4347+
4348+/****************** Bits definition for GPIO_BSRR register ******************/
4349+#define GPIO_BSRR_BS0_Pos (0U)
4350+#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
4351+#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
4352+#define GPIO_BSRR_BS1_Pos (1U)
4353+#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
4354+#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
4355+#define GPIO_BSRR_BS2_Pos (2U)
4356+#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
4357+#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
4358+#define GPIO_BSRR_BS3_Pos (3U)
4359+#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
4360+#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
4361+#define GPIO_BSRR_BS4_Pos (4U)
4362+#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
4363+#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
4364+#define GPIO_BSRR_BS5_Pos (5U)
4365+#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
4366+#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
4367+#define GPIO_BSRR_BS6_Pos (6U)
4368+#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
4369+#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
4370+#define GPIO_BSRR_BS7_Pos (7U)
4371+#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
4372+#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
4373+#define GPIO_BSRR_BS8_Pos (8U)
4374+#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
4375+#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
4376+#define GPIO_BSRR_BS9_Pos (9U)
4377+#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
4378+#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
4379+#define GPIO_BSRR_BS10_Pos (10U)
4380+#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
4381+#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
4382+#define GPIO_BSRR_BS11_Pos (11U)
4383+#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
4384+#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
4385+#define GPIO_BSRR_BS12_Pos (12U)
4386+#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
4387+#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
4388+#define GPIO_BSRR_BS13_Pos (13U)
4389+#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
4390+#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
4391+#define GPIO_BSRR_BS14_Pos (14U)
4392+#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
4393+#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
4394+#define GPIO_BSRR_BS15_Pos (15U)
4395+#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
4396+#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
4397+#define GPIO_BSRR_BR0_Pos (16U)
4398+#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
4399+#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
4400+#define GPIO_BSRR_BR1_Pos (17U)
4401+#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
4402+#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
4403+#define GPIO_BSRR_BR2_Pos (18U)
4404+#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
4405+#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
4406+#define GPIO_BSRR_BR3_Pos (19U)
4407+#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
4408+#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
4409+#define GPIO_BSRR_BR4_Pos (20U)
4410+#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
4411+#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
4412+#define GPIO_BSRR_BR5_Pos (21U)
4413+#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
4414+#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
4415+#define GPIO_BSRR_BR6_Pos (22U)
4416+#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
4417+#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
4418+#define GPIO_BSRR_BR7_Pos (23U)
4419+#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
4420+#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
4421+#define GPIO_BSRR_BR8_Pos (24U)
4422+#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
4423+#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
4424+#define GPIO_BSRR_BR9_Pos (25U)
4425+#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
4426+#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
4427+#define GPIO_BSRR_BR10_Pos (26U)
4428+#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
4429+#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
4430+#define GPIO_BSRR_BR11_Pos (27U)
4431+#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
4432+#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
4433+#define GPIO_BSRR_BR12_Pos (28U)
4434+#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
4435+#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
4436+#define GPIO_BSRR_BR13_Pos (29U)
4437+#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
4438+#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
4439+#define GPIO_BSRR_BR14_Pos (30U)
4440+#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
4441+#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
4442+#define GPIO_BSRR_BR15_Pos (31U)
4443+#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
4444+#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
4445+
4446+/****************** Bit definition for GPIO_LCKR register *********************/
4447+#define GPIO_LCKR_LCK0_Pos (0U)
4448+#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
4449+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
4450+#define GPIO_LCKR_LCK1_Pos (1U)
4451+#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
4452+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
4453+#define GPIO_LCKR_LCK2_Pos (2U)
4454+#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
4455+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
4456+#define GPIO_LCKR_LCK3_Pos (3U)
4457+#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
4458+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
4459+#define GPIO_LCKR_LCK4_Pos (4U)
4460+#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
4461+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
4462+#define GPIO_LCKR_LCK5_Pos (5U)
4463+#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
4464+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
4465+#define GPIO_LCKR_LCK6_Pos (6U)
4466+#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
4467+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
4468+#define GPIO_LCKR_LCK7_Pos (7U)
4469+#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
4470+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
4471+#define GPIO_LCKR_LCK8_Pos (8U)
4472+#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
4473+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
4474+#define GPIO_LCKR_LCK9_Pos (9U)
4475+#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
4476+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
4477+#define GPIO_LCKR_LCK10_Pos (10U)
4478+#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
4479+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
4480+#define GPIO_LCKR_LCK11_Pos (11U)
4481+#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
4482+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
4483+#define GPIO_LCKR_LCK12_Pos (12U)
4484+#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
4485+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
4486+#define GPIO_LCKR_LCK13_Pos (13U)
4487+#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
4488+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
4489+#define GPIO_LCKR_LCK14_Pos (14U)
4490+#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
4491+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
4492+#define GPIO_LCKR_LCK15_Pos (15U)
4493+#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
4494+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
4495+#define GPIO_LCKR_LCKK_Pos (16U)
4496+#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
4497+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
4498+
4499+/****************** Bit definition for GPIO_AFRL register *********************/
4500+#define GPIO_AFRL_AFSEL0_Pos (0U)
4501+#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
4502+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
4503+#define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
4504+#define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
4505+#define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
4506+#define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
4507+#define GPIO_AFRL_AFSEL1_Pos (4U)
4508+#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
4509+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
4510+#define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
4511+#define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
4512+#define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
4513+#define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
4514+#define GPIO_AFRL_AFSEL2_Pos (8U)
4515+#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
4516+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
4517+#define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
4518+#define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
4519+#define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
4520+#define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
4521+#define GPIO_AFRL_AFSEL3_Pos (12U)
4522+#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
4523+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
4524+#define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
4525+#define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
4526+#define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
4527+#define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
4528+#define GPIO_AFRL_AFSEL4_Pos (16U)
4529+#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
4530+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
4531+#define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
4532+#define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
4533+#define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
4534+#define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
4535+#define GPIO_AFRL_AFSEL5_Pos (20U)
4536+#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
4537+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
4538+#define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
4539+#define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
4540+#define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
4541+#define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
4542+#define GPIO_AFRL_AFSEL6_Pos (24U)
4543+#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
4544+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
4545+#define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
4546+#define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
4547+#define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
4548+#define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
4549+#define GPIO_AFRL_AFSEL7_Pos (28U)
4550+#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
4551+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
4552+#define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
4553+#define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
4554+#define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
4555+#define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
4556+
4557+/****************** Bit definition for GPIO_AFRH register *********************/
4558+#define GPIO_AFRH_AFSEL8_Pos (0U)
4559+#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
4560+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
4561+#define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
4562+#define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
4563+#define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
4564+#define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
4565+#define GPIO_AFRH_AFSEL9_Pos (4U)
4566+#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
4567+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
4568+#define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
4569+#define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
4570+#define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
4571+#define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
4572+#define GPIO_AFRH_AFSEL10_Pos (8U)
4573+#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
4574+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
4575+#define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
4576+#define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
4577+#define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
4578+#define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
4579+#define GPIO_AFRH_AFSEL11_Pos (12U)
4580+#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
4581+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
4582+#define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
4583+#define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
4584+#define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
4585+#define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
4586+#define GPIO_AFRH_AFSEL12_Pos (16U)
4587+#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
4588+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
4589+#define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
4590+#define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
4591+#define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
4592+#define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
4593+#define GPIO_AFRH_AFSEL13_Pos (20U)
4594+#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
4595+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
4596+#define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
4597+#define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
4598+#define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
4599+#define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
4600+#define GPIO_AFRH_AFSEL14_Pos (24U)
4601+#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
4602+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
4603+#define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
4604+#define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
4605+#define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
4606+#define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
4607+#define GPIO_AFRH_AFSEL15_Pos (28U)
4608+#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
4609+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
4610+#define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
4611+#define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
4612+#define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
4613+#define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
4614+
4615+/****************** Bits definition for GPIO_BRR register ******************/
4616+#define GPIO_BRR_BR0_Pos (0U)
4617+#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
4618+#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
4619+#define GPIO_BRR_BR1_Pos (1U)
4620+#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
4621+#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
4622+#define GPIO_BRR_BR2_Pos (2U)
4623+#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
4624+#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
4625+#define GPIO_BRR_BR3_Pos (3U)
4626+#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
4627+#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
4628+#define GPIO_BRR_BR4_Pos (4U)
4629+#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
4630+#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
4631+#define GPIO_BRR_BR5_Pos (5U)
4632+#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
4633+#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
4634+#define GPIO_BRR_BR6_Pos (6U)
4635+#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
4636+#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
4637+#define GPIO_BRR_BR7_Pos (7U)
4638+#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
4639+#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
4640+#define GPIO_BRR_BR8_Pos (8U)
4641+#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
4642+#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
4643+#define GPIO_BRR_BR9_Pos (9U)
4644+#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
4645+#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
4646+#define GPIO_BRR_BR10_Pos (10U)
4647+#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
4648+#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
4649+#define GPIO_BRR_BR11_Pos (11U)
4650+#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
4651+#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
4652+#define GPIO_BRR_BR12_Pos (12U)
4653+#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
4654+#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
4655+#define GPIO_BRR_BR13_Pos (13U)
4656+#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
4657+#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
4658+#define GPIO_BRR_BR14_Pos (14U)
4659+#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
4660+#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
4661+#define GPIO_BRR_BR15_Pos (15U)
4662+#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
4663+#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
4664+
4665+/******************************************************************************/
4666+/* */
4667+/* HSEM HW Semaphore */
4668+/* */
4669+/******************************************************************************/
4670+/******************** Bit definition for HSEM_R register ********************/
4671+#define HSEM_R_PROCID_Pos (0U)
4672+#define HSEM_R_PROCID_Msk (0xFFUL << HSEM_R_PROCID_Pos) /*!< 0x000000FF */
4673+#define HSEM_R_PROCID HSEM_R_PROCID_Msk /*!<Semaphore ProcessID */
4674+#define HSEM_R_COREID_Pos (8U)
4675+#define HSEM_R_COREID_Msk (0xFUL << HSEM_R_COREID_Pos) /*!< 0x00000F00 */
4676+#define HSEM_R_COREID HSEM_R_COREID_Msk /*!<Semaphore CoreID. */
4677+#define HSEM_R_LOCK_Pos (31U)
4678+#define HSEM_R_LOCK_Msk (0x1UL << HSEM_R_LOCK_Pos) /*!< 0x80000000 */
4679+#define HSEM_R_LOCK HSEM_R_LOCK_Msk /*!<Lock indication. */
4680+
4681+/******************** Bit definition for HSEM_RLR register ******************/
4682+#define HSEM_RLR_PROCID_Pos (0U)
4683+#define HSEM_RLR_PROCID_Msk (0xFFUL << HSEM_RLR_PROCID_Pos) /*!< 0x000000FF */
4684+#define HSEM_RLR_PROCID HSEM_RLR_PROCID_Msk /*!<Semaphore ProcessID */
4685+#define HSEM_RLR_COREID_Pos (8U)
4686+#define HSEM_RLR_COREID_Msk (0xFUL << HSEM_RLR_COREID_Pos) /*!< 0x00000F00 */
4687+#define HSEM_RLR_COREID HSEM_RLR_COREID_Msk /*!<Semaphore CoreID. */
4688+#define HSEM_RLR_LOCK_Pos (31U)
4689+#define HSEM_RLR_LOCK_Msk (0x1UL << HSEM_RLR_LOCK_Pos) /*!< 0x80000000 */
4690+#define HSEM_RLR_LOCK HSEM_RLR_LOCK_Msk /*!<Lock indication. */
4691+
4692+/******************** Bit definition for HSEM_C1IER register ****************/
4693+#define HSEM_C1IER_ISE0_Pos (0U)
4694+#define HSEM_C1IER_ISE0_Msk (0x1UL << HSEM_C1IER_ISE0_Pos) /*!< 0x00000001 */
4695+#define HSEM_C1IER_ISE0 HSEM_C1IER_ISE0_Msk /*!<semaphore 0 CPU1 interrupt enable bit. */
4696+#define HSEM_C1IER_ISE1_Pos (1U)
4697+#define HSEM_C1IER_ISE1_Msk (0x1UL << HSEM_C1IER_ISE1_Pos) /*!< 0x00000002 */
4698+#define HSEM_C1IER_ISE1 HSEM_C1IER_ISE1_Msk /*!<semaphore 1 CPU1 interrupt enable bit. */
4699+#define HSEM_C1IER_ISE2_Pos (2U)
4700+#define HSEM_C1IER_ISE2_Msk (0x1UL << HSEM_C1IER_ISE2_Pos) /*!< 0x00000004 */
4701+#define HSEM_C1IER_ISE2 HSEM_C1IER_ISE2_Msk /*!<semaphore 2 CPU1 interrupt enable bit. */
4702+#define HSEM_C1IER_ISE3_Pos (3U)
4703+#define HSEM_C1IER_ISE3_Msk (0x1UL << HSEM_C1IER_ISE3_Pos) /*!< 0x00000008 */
4704+#define HSEM_C1IER_ISE3 HSEM_C1IER_ISE3_Msk /*!<semaphore 3 CPU1 interrupt enable bit. */
4705+#define HSEM_C1IER_ISE4_Pos (4U)
4706+#define HSEM_C1IER_ISE4_Msk (0x1UL << HSEM_C1IER_ISE4_Pos) /*!< 0x00000010 */
4707+#define HSEM_C1IER_ISE4 HSEM_C1IER_ISE4_Msk /*!<semaphore 4 CPU1 interrupt enable bit. */
4708+#define HSEM_C1IER_ISE5_Pos (5U)
4709+#define HSEM_C1IER_ISE5_Msk (0x1UL << HSEM_C1IER_ISE5_Pos) /*!< 0x00000020 */
4710+#define HSEM_C1IER_ISE5 HSEM_C1IER_ISE5_Msk /*!<semaphore 5 CPU1 interrupt enable bit. */
4711+#define HSEM_C1IER_ISE6_Pos (6U)
4712+#define HSEM_C1IER_ISE6_Msk (0x1UL << HSEM_C1IER_ISE6_Pos) /*!< 0x00000040 */
4713+#define HSEM_C1IER_ISE6 HSEM_C1IER_ISE6_Msk /*!<semaphore 6 CPU1 interrupt enable bit. */
4714+#define HSEM_C1IER_ISE7_Pos (7U)
4715+#define HSEM_C1IER_ISE7_Msk (0x1UL << HSEM_C1IER_ISE7_Pos) /*!< 0x00000080 */
4716+#define HSEM_C1IER_ISE7 HSEM_C1IER_ISE7_Msk /*!<semaphore 7 CPU1 interrupt enable bit. */
4717+#define HSEM_C1IER_ISE8_Pos (8U)
4718+#define HSEM_C1IER_ISE8_Msk (0x1UL << HSEM_C1IER_ISE8_Pos) /*!< 0x00000100 */
4719+#define HSEM_C1IER_ISE8 HSEM_C1IER_ISE8_Msk /*!<semaphore 8 CPU1 interrupt enable bit. */
4720+#define HSEM_C1IER_ISE9_Pos (9U)
4721+#define HSEM_C1IER_ISE9_Msk (0x1UL << HSEM_C1IER_ISE9_Pos) /*!< 0x00000200 */
4722+#define HSEM_C1IER_ISE9 HSEM_C1IER_ISE9_Msk /*!<semaphore 9 CPU1 interrupt enable bit. */
4723+#define HSEM_C1IER_ISE10_Pos (10U)
4724+#define HSEM_C1IER_ISE10_Msk (0x1UL << HSEM_C1IER_ISE10_Pos) /*!< 0x00000400 */
4725+#define HSEM_C1IER_ISE10 HSEM_C1IER_ISE10_Msk /*!<semaphore 10 CPU1 interrupt enable bit. */
4726+#define HSEM_C1IER_ISE11_Pos (11U)
4727+#define HSEM_C1IER_ISE11_Msk (0x1UL << HSEM_C1IER_ISE11_Pos) /*!< 0x00000800 */
4728+#define HSEM_C1IER_ISE11 HSEM_C1IER_ISE11_Msk /*!<semaphore 11 CPU1 interrupt enable bit. */
4729+#define HSEM_C1IER_ISE12_Pos (12U)
4730+#define HSEM_C1IER_ISE12_Msk (0x1UL << HSEM_C1IER_ISE12_Pos) /*!< 0x00001000 */
4731+#define HSEM_C1IER_ISE12 HSEM_C1IER_ISE12_Msk /*!<semaphore 12 CPU1 interrupt enable bit. */
4732+#define HSEM_C1IER_ISE13_Pos (13U)
4733+#define HSEM_C1IER_ISE13_Msk (0x1UL << HSEM_C1IER_ISE13_Pos) /*!< 0x00002000 */
4734+#define HSEM_C1IER_ISE13 HSEM_C1IER_ISE13_Msk /*!<semaphore 13 CPU1 interrupt enable bit. */
4735+#define HSEM_C1IER_ISE14_Pos (14U)
4736+#define HSEM_C1IER_ISE14_Msk (0x1UL << HSEM_C1IER_ISE14_Pos) /*!< 0x00004000 */
4737+#define HSEM_C1IER_ISE14 HSEM_C1IER_ISE14_Msk /*!<semaphore 14 CPU1 interrupt enable bit. */
4738+#define HSEM_C1IER_ISE15_Pos (15U)
4739+#define HSEM_C1IER_ISE15_Msk (0x1UL << HSEM_C1IER_ISE15_Pos) /*!< 0x00008000 */
4740+#define HSEM_C1IER_ISE15 HSEM_C1IER_ISE15_Msk /*!<semaphore 15 CPU1 interrupt enable bit. */
4741+#define HSEM_C1IER_ISE16_Pos (16U)
4742+#define HSEM_C1IER_ISE16_Msk (0x1UL << HSEM_C1IER_ISE16_Pos) /*!< 0x00010000 */
4743+#define HSEM_C1IER_ISE16 HSEM_C1IER_ISE16_Msk /*!<semaphore 16 CPU1 interrupt enable bit. */
4744+#define HSEM_C1IER_ISE17_Pos (17U)
4745+#define HSEM_C1IER_ISE17_Msk (0x1UL << HSEM_C1IER_ISE17_Pos) /*!< 0x00020000 */
4746+#define HSEM_C1IER_ISE17 HSEM_C1IER_ISE17_Msk /*!<semaphore 17 CPU1 interrupt enable bit. */
4747+#define HSEM_C1IER_ISE18_Pos (18U)
4748+#define HSEM_C1IER_ISE18_Msk (0x1UL << HSEM_C1IER_ISE18_Pos) /*!< 0x00040000 */
4749+#define HSEM_C1IER_ISE18 HSEM_C1IER_ISE18_Msk /*!<semaphore 18 CPU1 interrupt enable bit. */
4750+#define HSEM_C1IER_ISE19_Pos (19U)
4751+#define HSEM_C1IER_ISE19_Msk (0x1UL << HSEM_C1IER_ISE19_Pos) /*!< 0x00080000 */
4752+#define HSEM_C1IER_ISE19 HSEM_C1IER_ISE19_Msk /*!<semaphore 19 CPU1 interrupt enable bit. */
4753+#define HSEM_C1IER_ISE20_Pos (20U)
4754+#define HSEM_C1IER_ISE20_Msk (0x1UL << HSEM_C1IER_ISE20_Pos) /*!< 0x00100000 */
4755+#define HSEM_C1IER_ISE20 HSEM_C1IER_ISE20_Msk /*!<semaphore 20 CPU1 interrupt enable bit. */
4756+#define HSEM_C1IER_ISE21_Pos (21U)
4757+#define HSEM_C1IER_ISE21_Msk (0x1UL << HSEM_C1IER_ISE21_Pos) /*!< 0x00200000 */
4758+#define HSEM_C1IER_ISE21 HSEM_C1IER_ISE21_Msk /*!<semaphore 21 CPU1 interrupt enable bit. */
4759+#define HSEM_C1IER_ISE22_Pos (22U)
4760+#define HSEM_C1IER_ISE22_Msk (0x1UL << HSEM_C1IER_ISE22_Pos) /*!< 0x00400000 */
4761+#define HSEM_C1IER_ISE22 HSEM_C1IER_ISE22_Msk /*!<semaphore 22 CPU1 interrupt enable bit. */
4762+#define HSEM_C1IER_ISE23_Pos (23U)
4763+#define HSEM_C1IER_ISE23_Msk (0x1UL << HSEM_C1IER_ISE23_Pos) /*!< 0x00800000 */
4764+#define HSEM_C1IER_ISE23 HSEM_C1IER_ISE23_Msk /*!<semaphore 23 CPU1 interrupt enable bit. */
4765+#define HSEM_C1IER_ISE24_Pos (24U)
4766+#define HSEM_C1IER_ISE24_Msk (0x1UL << HSEM_C1IER_ISE24_Pos) /*!< 0x01000000 */
4767+#define HSEM_C1IER_ISE24 HSEM_C1IER_ISE24_Msk /*!<semaphore 24 CPU1 interrupt enable bit. */
4768+#define HSEM_C1IER_ISE25_Pos (25U)
4769+#define HSEM_C1IER_ISE25_Msk (0x1UL << HSEM_C1IER_ISE25_Pos) /*!< 0x02000000 */
4770+#define HSEM_C1IER_ISE25 HSEM_C1IER_ISE25_Msk /*!<semaphore 25 CPU1 interrupt enable bit. */
4771+#define HSEM_C1IER_ISE26_Pos (26U)
4772+#define HSEM_C1IER_ISE26_Msk (0x1UL << HSEM_C1IER_ISE26_Pos) /*!< 0x04000000 */
4773+#define HSEM_C1IER_ISE26 HSEM_C1IER_ISE26_Msk /*!<semaphore 26 CPU1 interrupt enable bit. */
4774+#define HSEM_C1IER_ISE27_Pos (27U)
4775+#define HSEM_C1IER_ISE27_Msk (0x1UL << HSEM_C1IER_ISE27_Pos) /*!< 0x08000000 */
4776+#define HSEM_C1IER_ISE27 HSEM_C1IER_ISE27_Msk /*!<semaphore 27 CPU1 interrupt enable bit. */
4777+#define HSEM_C1IER_ISE28_Pos (28U)
4778+#define HSEM_C1IER_ISE28_Msk (0x1UL << HSEM_C1IER_ISE28_Pos) /*!< 0x10000000 */
4779+#define HSEM_C1IER_ISE28 HSEM_C1IER_ISE28_Msk /*!<semaphore 28 CPU1 interrupt enable bit. */
4780+#define HSEM_C1IER_ISE29_Pos (29U)
4781+#define HSEM_C1IER_ISE29_Msk (0x1UL << HSEM_C1IER_ISE29_Pos) /*!< 0x20000000 */
4782+#define HSEM_C1IER_ISE29 HSEM_C1IER_ISE29_Msk /*!<semaphore 29 CPU1 interrupt enable bit. */
4783+#define HSEM_C1IER_ISE30_Pos (30U)
4784+#define HSEM_C1IER_ISE30_Msk (0x1UL << HSEM_C1IER_ISE30_Pos) /*!< 0x40000000 */
4785+#define HSEM_C1IER_ISE30 HSEM_C1IER_ISE30_Msk /*!<semaphore 30 CPU1 interrupt enable bit. */
4786+#define HSEM_C1IER_ISE31_Pos (31U)
4787+#define HSEM_C1IER_ISE31_Msk (0x1UL << HSEM_C1IER_ISE31_Pos) /*!< 0x80000000 */
4788+#define HSEM_C1IER_ISE31 HSEM_C1IER_ISE31_Msk /*!<semaphore 31 CPU1 interrupt enable bit. */
4789+
4790+/******************** Bit definition for HSEM_C1ICR register *****************/
4791+#define HSEM_C1ICR_ISC0_Pos (0U)
4792+#define HSEM_C1ICR_ISC0_Msk (0x1UL << HSEM_C1ICR_ISC0_Pos) /*!< 0x00000001 */
4793+#define HSEM_C1ICR_ISC0 HSEM_C1ICR_ISC0_Msk /*!<semaphore 0 CPU1 interrupt clear bit. */
4794+#define HSEM_C1ICR_ISC1_Pos (1U)
4795+#define HSEM_C1ICR_ISC1_Msk (0x1UL << HSEM_C1ICR_ISC1_Pos) /*!< 0x00000002 */
4796+#define HSEM_C1ICR_ISC1 HSEM_C1ICR_ISC1_Msk /*!<semaphore 1 CPU1 interrupt clear bit. */
4797+#define HSEM_C1ICR_ISC2_Pos (2U)
4798+#define HSEM_C1ICR_ISC2_Msk (0x1UL << HSEM_C1ICR_ISC2_Pos) /*!< 0x00000004 */
4799+#define HSEM_C1ICR_ISC2 HSEM_C1ICR_ISC2_Msk /*!<semaphore 2 CPU1 interrupt clear bit. */
4800+#define HSEM_C1ICR_ISC3_Pos (3U)
4801+#define HSEM_C1ICR_ISC3_Msk (0x1UL << HSEM_C1ICR_ISC3_Pos) /*!< 0x00000008 */
4802+#define HSEM_C1ICR_ISC3 HSEM_C1ICR_ISC3_Msk /*!<semaphore 3 CPU1 interrupt clear bit. */
4803+#define HSEM_C1ICR_ISC4_Pos (4U)
4804+#define HSEM_C1ICR_ISC4_Msk (0x1UL << HSEM_C1ICR_ISC4_Pos) /*!< 0x00000010 */
4805+#define HSEM_C1ICR_ISC4 HSEM_C1ICR_ISC4_Msk /*!<semaphore 4 CPU1 interrupt clear bit. */
4806+#define HSEM_C1ICR_ISC5_Pos (5U)
4807+#define HSEM_C1ICR_ISC5_Msk (0x1UL << HSEM_C1ICR_ISC5_Pos) /*!< 0x00000020 */
4808+#define HSEM_C1ICR_ISC5 HSEM_C1ICR_ISC5_Msk /*!<semaphore 5 CPU1 interrupt clear bit. */
4809+#define HSEM_C1ICR_ISC6_Pos (6U)
4810+#define HSEM_C1ICR_ISC6_Msk (0x1UL << HSEM_C1ICR_ISC6_Pos) /*!< 0x00000040 */
4811+#define HSEM_C1ICR_ISC6 HSEM_C1ICR_ISC6_Msk /*!<semaphore 6 CPU1 interrupt clear bit. */
4812+#define HSEM_C1ICR_ISC7_Pos (7U)
4813+#define HSEM_C1ICR_ISC7_Msk (0x1UL << HSEM_C1ICR_ISC7_Pos) /*!< 0x00000080 */
4814+#define HSEM_C1ICR_ISC7 HSEM_C1ICR_ISC7_Msk /*!<semaphore 7 CPU1 interrupt clear bit. */
4815+#define HSEM_C1ICR_ISC8_Pos (8U)
4816+#define HSEM_C1ICR_ISC8_Msk (0x1UL << HSEM_C1ICR_ISC8_Pos) /*!< 0x00000100 */
4817+#define HSEM_C1ICR_ISC8 HSEM_C1ICR_ISC8_Msk /*!<semaphore 8 CPU1 interrupt clear bit. */
4818+#define HSEM_C1ICR_ISC9_Pos (9U)
4819+#define HSEM_C1ICR_ISC9_Msk (0x1UL << HSEM_C1ICR_ISC9_Pos) /*!< 0x00000200 */
4820+#define HSEM_C1ICR_ISC9 HSEM_C1ICR_ISC9_Msk /*!<semaphore 9 CPU1 interrupt clear bit. */
4821+#define HSEM_C1ICR_ISC10_Pos (10U)
4822+#define HSEM_C1ICR_ISC10_Msk (0x1UL << HSEM_C1ICR_ISC10_Pos) /*!< 0x00000400 */
4823+#define HSEM_C1ICR_ISC10 HSEM_C1ICR_ISC10_Msk /*!<semaphore 10 CPU1 interrupt clear bit. */
4824+#define HSEM_C1ICR_ISC11_Pos (11U)
4825+#define HSEM_C1ICR_ISC11_Msk (0x1UL << HSEM_C1ICR_ISC11_Pos) /*!< 0x00000800 */
4826+#define HSEM_C1ICR_ISC11 HSEM_C1ICR_ISC11_Msk /*!<semaphore 11 CPU1 interrupt clear bit. */
4827+#define HSEM_C1ICR_ISC12_Pos (12U)
4828+#define HSEM_C1ICR_ISC12_Msk (0x1UL << HSEM_C1ICR_ISC12_Pos) /*!< 0x00001000 */
4829+#define HSEM_C1ICR_ISC12 HSEM_C1ICR_ISC12_Msk /*!<semaphore 12 CPU1 interrupt clear bit. */
4830+#define HSEM_C1ICR_ISC13_Pos (13U)
4831+#define HSEM_C1ICR_ISC13_Msk (0x1UL << HSEM_C1ICR_ISC13_Pos) /*!< 0x00002000 */
4832+#define HSEM_C1ICR_ISC13 HSEM_C1ICR_ISC13_Msk /*!<semaphore 13 CPU1 interrupt clear bit. */
4833+#define HSEM_C1ICR_ISC14_Pos (14U)
4834+#define HSEM_C1ICR_ISC14_Msk (0x1UL << HSEM_C1ICR_ISC14_Pos) /*!< 0x00004000 */
4835+#define HSEM_C1ICR_ISC14 HSEM_C1ICR_ISC14_Msk /*!<semaphore 14 CPU1 interrupt clear bit. */
4836+#define HSEM_C1ICR_ISC15_Pos (15U)
4837+#define HSEM_C1ICR_ISC15_Msk (0x1UL << HSEM_C1ICR_ISC15_Pos) /*!< 0x00008000 */
4838+#define HSEM_C1ICR_ISC15 HSEM_C1ICR_ISC15_Msk /*!<semaphore 15 CPU1 interrupt clear bit. */
4839+#define HSEM_C1ICR_ISC16_Pos (16U)
4840+#define HSEM_C1ICR_ISC16_Msk (0x1UL << HSEM_C1ICR_ISC16_Pos) /*!< 0x00010000 */
4841+#define HSEM_C1ICR_ISC16 HSEM_C1ICR_ISC16_Msk /*!<semaphore 16 CPU1 interrupt clear bit. */
4842+#define HSEM_C1ICR_ISC17_Pos (17U)
4843+#define HSEM_C1ICR_ISC17_Msk (0x1UL << HSEM_C1ICR_ISC17_Pos) /*!< 0x00020000 */
4844+#define HSEM_C1ICR_ISC17 HSEM_C1ICR_ISC17_Msk /*!<semaphore 17 CPU1 interrupt clear bit. */
4845+#define HSEM_C1ICR_ISC18_Pos (18U)
4846+#define HSEM_C1ICR_ISC18_Msk (0x1UL << HSEM_C1ICR_ISC18_Pos) /*!< 0x00040000 */
4847+#define HSEM_C1ICR_ISC18 HSEM_C1ICR_ISC18_Msk /*!<semaphore 18 CPU1 interrupt clear bit. */
4848+#define HSEM_C1ICR_ISC19_Pos (19U)
4849+#define HSEM_C1ICR_ISC19_Msk (0x1UL << HSEM_C1ICR_ISC19_Pos) /*!< 0x00080000 */
4850+#define HSEM_C1ICR_ISC19 HSEM_C1ICR_ISC19_Msk /*!<semaphore 19 CPU1 interrupt clear bit. */
4851+#define HSEM_C1ICR_ISC20_Pos (20U)
4852+#define HSEM_C1ICR_ISC20_Msk (0x1UL << HSEM_C1ICR_ISC20_Pos) /*!< 0x00100000 */
4853+#define HSEM_C1ICR_ISC20 HSEM_C1ICR_ISC20_Msk /*!<semaphore 20 CPU1 interrupt clear bit. */
4854+#define HSEM_C1ICR_ISC21_Pos (21U)
4855+#define HSEM_C1ICR_ISC21_Msk (0x1UL << HSEM_C1ICR_ISC21_Pos) /*!< 0x00200000 */
4856+#define HSEM_C1ICR_ISC21 HSEM_C1ICR_ISC21_Msk /*!<semaphore 21 CPU1 interrupt clear bit. */
4857+#define HSEM_C1ICR_ISC22_Pos (22U)
4858+#define HSEM_C1ICR_ISC22_Msk (0x1UL << HSEM_C1ICR_ISC22_Pos) /*!< 0x00400000 */
4859+#define HSEM_C1ICR_ISC22 HSEM_C1ICR_ISC22_Msk /*!<semaphore 22 CPU1 interrupt clear bit. */
4860+#define HSEM_C1ICR_ISC23_Pos (23U)
4861+#define HSEM_C1ICR_ISC23_Msk (0x1UL << HSEM_C1ICR_ISC23_Pos) /*!< 0x00800000 */
4862+#define HSEM_C1ICR_ISC23 HSEM_C1ICR_ISC23_Msk /*!<semaphore 23 CPU1 interrupt clear bit. */
4863+#define HSEM_C1ICR_ISC24_Pos (24U)
4864+#define HSEM_C1ICR_ISC24_Msk (0x1UL << HSEM_C1ICR_ISC24_Pos) /*!< 0x01000000 */
4865+#define HSEM_C1ICR_ISC24 HSEM_C1ICR_ISC24_Msk /*!<semaphore 24 CPU1 interrupt clear bit. */
4866+#define HSEM_C1ICR_ISC25_Pos (25U)
4867+#define HSEM_C1ICR_ISC25_Msk (0x1UL << HSEM_C1ICR_ISC25_Pos) /*!< 0x02000000 */
4868+#define HSEM_C1ICR_ISC25 HSEM_C1ICR_ISC25_Msk /*!<semaphore 25 CPU1 interrupt clear bit. */
4869+#define HSEM_C1ICR_ISC26_Pos (26U)
4870+#define HSEM_C1ICR_ISC26_Msk (0x1UL << HSEM_C1ICR_ISC26_Pos) /*!< 0x04000000 */
4871+#define HSEM_C1ICR_ISC26 HSEM_C1ICR_ISC26_Msk /*!<semaphore 26 CPU1 interrupt clear bit. */
4872+#define HSEM_C1ICR_ISC27_Pos (27U)
4873+#define HSEM_C1ICR_ISC27_Msk (0x1UL << HSEM_C1ICR_ISC27_Pos) /*!< 0x08000000 */
4874+#define HSEM_C1ICR_ISC27 HSEM_C1ICR_ISC27_Msk /*!<semaphore 27 CPU1 interrupt clear bit. */
4875+#define HSEM_C1ICR_ISC28_Pos (28U)
4876+#define HSEM_C1ICR_ISC28_Msk (0x1UL << HSEM_C1ICR_ISC28_Pos) /*!< 0x10000000 */
4877+#define HSEM_C1ICR_ISC28 HSEM_C1ICR_ISC28_Msk /*!<semaphore 28 CPU1 interrupt clear bit. */
4878+#define HSEM_C1ICR_ISC29_Pos (29U)
4879+#define HSEM_C1ICR_ISC29_Msk (0x1UL << HSEM_C1ICR_ISC29_Pos) /*!< 0x20000000 */
4880+#define HSEM_C1ICR_ISC29 HSEM_C1ICR_ISC29_Msk /*!<semaphore 29 CPU1 interrupt clear bit. */
4881+#define HSEM_C1ICR_ISC30_Pos (30U)
4882+#define HSEM_C1ICR_ISC30_Msk (0x1UL << HSEM_C1ICR_ISC30_Pos) /*!< 0x40000000 */
4883+#define HSEM_C1ICR_ISC30 HSEM_C1ICR_ISC30_Msk /*!<semaphore 30 CPU1 interrupt clear bit. */
4884+#define HSEM_C1ICR_ISC31_Pos (31U)
4885+#define HSEM_C1ICR_ISC31_Msk (0x1UL << HSEM_C1ICR_ISC31_Pos) /*!< 0x80000000 */
4886+#define HSEM_C1ICR_ISC31 HSEM_C1ICR_ISC31_Msk /*!<semaphore 31 CPU1 interrupt clear bit. */
4887+
4888+/******************** Bit definition for HSEM_C1ISR register *****************/
4889+#define HSEM_C1ISR_ISF0_Pos (0U)
4890+#define HSEM_C1ISR_ISF0_Msk (0x1UL << HSEM_C1ISR_ISF0_Pos) /*!< 0x00000001 */
4891+#define HSEM_C1ISR_ISF0 HSEM_C1ISR_ISF0_Msk /*!<semaphore 0 CPU1 interrupt status bit. */
4892+#define HSEM_C1ISR_ISF1_Pos (1U)
4893+#define HSEM_C1ISR_ISF1_Msk (0x1UL << HSEM_C1ISR_ISF1_Pos) /*!< 0x00000002 */
4894+#define HSEM_C1ISR_ISF1 HSEM_C1ISR_ISF1_Msk /*!<semaphore 1 CPU1 interrupt status bit. */
4895+#define HSEM_C1ISR_ISF2_Pos (2U)
4896+#define HSEM_C1ISR_ISF2_Msk (0x1UL << HSEM_C1ISR_ISF2_Pos) /*!< 0x00000004 */
4897+#define HSEM_C1ISR_ISF2 HSEM_C1ISR_ISF2_Msk /*!<semaphore 2 CPU1 interrupt status bit. */
4898+#define HSEM_C1ISR_ISF3_Pos (3U)
4899+#define HSEM_C1ISR_ISF3_Msk (0x1UL << HSEM_C1ISR_ISF3_Pos) /*!< 0x00000008 */
4900+#define HSEM_C1ISR_ISF3 HSEM_C1ISR_ISF3_Msk /*!<semaphore 3 CPU1 interrupt status bit. */
4901+#define HSEM_C1ISR_ISF4_Pos (4U)
4902+#define HSEM_C1ISR_ISF4_Msk (0x1UL << HSEM_C1ISR_ISF4_Pos) /*!< 0x00000010 */
4903+#define HSEM_C1ISR_ISF4 HSEM_C1ISR_ISF4_Msk /*!<semaphore 4 CPU1 interrupt status bit. */
4904+#define HSEM_C1ISR_ISF5_Pos (5U)
4905+#define HSEM_C1ISR_ISF5_Msk (0x1UL << HSEM_C1ISR_ISF5_Pos) /*!< 0x00000020 */
4906+#define HSEM_C1ISR_ISF5 HSEM_C1ISR_ISF5_Msk /*!<semaphore 5 CPU1 interrupt status bit. */
4907+#define HSEM_C1ISR_ISF6_Pos (6U)
4908+#define HSEM_C1ISR_ISF6_Msk (0x1UL << HSEM_C1ISR_ISF6_Pos) /*!< 0x00000040 */
4909+#define HSEM_C1ISR_ISF6 HSEM_C1ISR_ISF6_Msk /*!<semaphore 6 CPU1 interrupt status bit. */
4910+#define HSEM_C1ISR_ISF7_Pos (7U)
4911+#define HSEM_C1ISR_ISF7_Msk (0x1UL << HSEM_C1ISR_ISF7_Pos) /*!< 0x00000080 */
4912+#define HSEM_C1ISR_ISF7 HSEM_C1ISR_ISF7_Msk /*!<semaphore 7 CPU1 interrupt status bit. */
4913+#define HSEM_C1ISR_ISF8_Pos (8U)
4914+#define HSEM_C1ISR_ISF8_Msk (0x1UL << HSEM_C1ISR_ISF8_Pos) /*!< 0x00000100 */
4915+#define HSEM_C1ISR_ISF8 HSEM_C1ISR_ISF8_Msk /*!<semaphore 8 CPU1 interrupt status bit. */
4916+#define HSEM_C1ISR_ISF9_Pos (9U)
4917+#define HSEM_C1ISR_ISF9_Msk (0x1UL << HSEM_C1ISR_ISF9_Pos) /*!< 0x00000200 */
4918+#define HSEM_C1ISR_ISF9 HSEM_C1ISR_ISF9_Msk /*!<semaphore 9 CPU1 interrupt status bit. */
4919+#define HSEM_C1ISR_ISF10_Pos (10U)
4920+#define HSEM_C1ISR_ISF10_Msk (0x1UL << HSEM_C1ISR_ISF10_Pos) /*!< 0x00000400 */
4921+#define HSEM_C1ISR_ISF10 HSEM_C1ISR_ISF10_Msk /*!<semaphore 10 CPU1 interrupt status bit. */
4922+#define HSEM_C1ISR_ISF11_Pos (11U)
4923+#define HSEM_C1ISR_ISF11_Msk (0x1UL << HSEM_C1ISR_ISF11_Pos) /*!< 0x00000800 */
4924+#define HSEM_C1ISR_ISF11 HSEM_C1ISR_ISF11_Msk /*!<semaphore 11 CPU1 interrupt status bit. */
4925+#define HSEM_C1ISR_ISF12_Pos (12U)
4926+#define HSEM_C1ISR_ISF12_Msk (0x1UL << HSEM_C1ISR_ISF12_Pos) /*!< 0x00001000 */
4927+#define HSEM_C1ISR_ISF12 HSEM_C1ISR_ISF12_Msk /*!<semaphore 12 CPU1 interrupt status bit. */
4928+#define HSEM_C1ISR_ISF13_Pos (13U)
4929+#define HSEM_C1ISR_ISF13_Msk (0x1UL << HSEM_C1ISR_ISF13_Pos) /*!< 0x00002000 */
4930+#define HSEM_C1ISR_ISF13 HSEM_C1ISR_ISF13_Msk /*!<semaphore 13 CPU1 interrupt status bit. */
4931+#define HSEM_C1ISR_ISF14_Pos (14U)
4932+#define HSEM_C1ISR_ISF14_Msk (0x1UL << HSEM_C1ISR_ISF14_Pos) /*!< 0x00004000 */
4933+#define HSEM_C1ISR_ISF14 HSEM_C1ISR_ISF14_Msk /*!<semaphore 14 CPU1 interrupt status bit. */
4934+#define HSEM_C1ISR_ISF15_Pos (15U)
4935+#define HSEM_C1ISR_ISF15_Msk (0x1UL << HSEM_C1ISR_ISF15_Pos) /*!< 0x00008000 */
4936+#define HSEM_C1ISR_ISF15 HSEM_C1ISR_ISF15_Msk /*!<semaphore 15 CPU1 interrupt status bit. */
4937+#define HSEM_C1ISR_ISF16_Pos (16U)
4938+#define HSEM_C1ISR_ISF16_Msk (0x1UL << HSEM_C1ISR_ISF16_Pos) /*!< 0x00010000 */
4939+#define HSEM_C1ISR_ISF16 HSEM_C1ISR_ISF16_Msk /*!<semaphore 16 CPU1 interrupt status bit. */
4940+#define HSEM_C1ISR_ISF17_Pos (17U)
4941+#define HSEM_C1ISR_ISF17_Msk (0x1UL << HSEM_C1ISR_ISF17_Pos) /*!< 0x00020000 */
4942+#define HSEM_C1ISR_ISF17 HSEM_C1ISR_ISF17_Msk /*!<semaphore 17 CPU1 interrupt status bit. */
4943+#define HSEM_C1ISR_ISF18_Pos (18U)
4944+#define HSEM_C1ISR_ISF18_Msk (0x1UL << HSEM_C1ISR_ISF18_Pos) /*!< 0x00040000 */
4945+#define HSEM_C1ISR_ISF18 HSEM_C1ISR_ISF18_Msk /*!<semaphore 18 CPU1 interrupt status bit. */
4946+#define HSEM_C1ISR_ISF19_Pos (19U)
4947+#define HSEM_C1ISR_ISF19_Msk (0x1UL << HSEM_C1ISR_ISF19_Pos) /*!< 0x00080000 */
4948+#define HSEM_C1ISR_ISF19 HSEM_C1ISR_ISF19_Msk /*!<semaphore 19 CPU1 interrupt status bit. */
4949+#define HSEM_C1ISR_ISF20_Pos (20U)
4950+#define HSEM_C1ISR_ISF20_Msk (0x1UL << HSEM_C1ISR_ISF20_Pos) /*!< 0x00100000 */
4951+#define HSEM_C1ISR_ISF20 HSEM_C1ISR_ISF20_Msk /*!<semaphore 20 CPU1 interrupt status bit. */
4952+#define HSEM_C1ISR_ISF21_Pos (21U)
4953+#define HSEM_C1ISR_ISF21_Msk (0x1UL << HSEM_C1ISR_ISF21_Pos) /*!< 0x00200000 */
4954+#define HSEM_C1ISR_ISF21 HSEM_C1ISR_ISF21_Msk /*!<semaphore 21 CPU1 interrupt status bit. */
4955+#define HSEM_C1ISR_ISF22_Pos (22U)
4956+#define HSEM_C1ISR_ISF22_Msk (0x1UL << HSEM_C1ISR_ISF22_Pos) /*!< 0x00400000 */
4957+#define HSEM_C1ISR_ISF22 HSEM_C1ISR_ISF22_Msk /*!<semaphore 22 CPU1 interrupt status bit. */
4958+#define HSEM_C1ISR_ISF23_Pos (23U)
4959+#define HSEM_C1ISR_ISF23_Msk (0x1UL << HSEM_C1ISR_ISF23_Pos) /*!< 0x00800000 */
4960+#define HSEM_C1ISR_ISF23 HSEM_C1ISR_ISF23_Msk /*!<semaphore 23 CPU1 interrupt status bit. */
4961+#define HSEM_C1ISR_ISF24_Pos (24U)
4962+#define HSEM_C1ISR_ISF24_Msk (0x1UL << HSEM_C1ISR_ISF24_Pos) /*!< 0x01000000 */
4963+#define HSEM_C1ISR_ISF24 HSEM_C1ISR_ISF24_Msk /*!<semaphore 24 CPU1 interrupt status bit. */
4964+#define HSEM_C1ISR_ISF25_Pos (25U)
4965+#define HSEM_C1ISR_ISF25_Msk (0x1UL << HSEM_C1ISR_ISF25_Pos) /*!< 0x02000000 */
4966+#define HSEM_C1ISR_ISF25 HSEM_C1ISR_ISF25_Msk /*!<semaphore 25 CPU1 interrupt status bit. */
4967+#define HSEM_C1ISR_ISF26_Pos (26U)
4968+#define HSEM_C1ISR_ISF26_Msk (0x1UL << HSEM_C1ISR_ISF26_Pos) /*!< 0x04000000 */
4969+#define HSEM_C1ISR_ISF26 HSEM_C1ISR_ISF26_Msk /*!<semaphore 26 CPU1 interrupt status bit. */
4970+#define HSEM_C1ISR_ISF27_Pos (27U)
4971+#define HSEM_C1ISR_ISF27_Msk (0x1UL << HSEM_C1ISR_ISF27_Pos) /*!< 0x08000000 */
4972+#define HSEM_C1ISR_ISF27 HSEM_C1ISR_ISF27_Msk /*!<semaphore 27 CPU1 interrupt status bit. */
4973+#define HSEM_C1ISR_ISF28_Pos (28U)
4974+#define HSEM_C1ISR_ISF28_Msk (0x1UL << HSEM_C1ISR_ISF28_Pos) /*!< 0x10000000 */
4975+#define HSEM_C1ISR_ISF28 HSEM_C1ISR_ISF28_Msk /*!<semaphore 28 CPU1 interrupt status bit. */
4976+#define HSEM_C1ISR_ISF29_Pos (29U)
4977+#define HSEM_C1ISR_ISF29_Msk (0x1UL << HSEM_C1ISR_ISF29_Pos) /*!< 0x20000000 */
4978+#define HSEM_C1ISR_ISF29 HSEM_C1ISR_ISF29_Msk /*!<semaphore 29 CPU1 interrupt status bit. */
4979+#define HSEM_C1ISR_ISF30_Pos (30U)
4980+#define HSEM_C1ISR_ISF30_Msk (0x1UL << HSEM_C1ISR_ISF30_Pos) /*!< 0x40000000 */
4981+#define HSEM_C1ISR_ISF30 HSEM_C1ISR_ISF30_Msk /*!<semaphore 30 CPU1 interrupt status bit. */
4982+#define HSEM_C1ISR_ISF31_Pos (31U)
4983+#define HSEM_C1ISR_ISF31_Msk (0x1UL << HSEM_C1ISR_ISF31_Pos) /*!< 0x80000000 */
4984+#define HSEM_C1ISR_ISF31 HSEM_C1ISR_ISF31_Msk /*!<semaphore 31 CPU1 interrupt status bit. */
4985+
4986+/******************** Bit definition for HSEM_C1MISR register *****************/
4987+#define HSEM_C1MISR_MISF0_Pos (0U)
4988+#define HSEM_C1MISR_MISF0_Msk (0x1UL << HSEM_C1MISR_MISF0_Pos) /*!< 0x00000001 */
4989+#define HSEM_C1MISR_MISF0 HSEM_C1MISR_MISF0_Msk /*!<semaphore 0 CPU1 interrupt masked status bit. */
4990+#define HSEM_C1MISR_MISF1_Pos (1U)
4991+#define HSEM_C1MISR_MISF1_Msk (0x1UL << HSEM_C1MISR_MISF1_Pos) /*!< 0x00000002 */
4992+#define HSEM_C1MISR_MISF1 HSEM_C1MISR_MISF1_Msk /*!<semaphore 1 CPU1 interrupt masked status bit. */
4993+#define HSEM_C1MISR_MISF2_Pos (2U)
4994+#define HSEM_C1MISR_MISF2_Msk (0x1UL << HSEM_C1MISR_MISF2_Pos) /*!< 0x00000004 */
4995+#define HSEM_C1MISR_MISF2 HSEM_C1MISR_MISF2_Msk /*!<semaphore 2 CPU1 interrupt masked status bit. */
4996+#define HSEM_C1MISR_MISF3_Pos (3U)
4997+#define HSEM_C1MISR_MISF3_Msk (0x1UL << HSEM_C1MISR_MISF3_Pos) /*!< 0x00000008 */
4998+#define HSEM_C1MISR_MISF3 HSEM_C1MISR_MISF3_Msk /*!<semaphore 3 CPU1 interrupt masked status bit. */
4999+#define HSEM_C1MISR_MISF4_Pos (4U)
5000+#define HSEM_C1MISR_MISF4_Msk (0x1UL << HSEM_C1MISR_MISF4_Pos) /*!< 0x00000010 */
5001+#define HSEM_C1MISR_MISF4 HSEM_C1MISR_MISF4_Msk /*!<semaphore 4 CPU1 interrupt masked status bit. */
5002+#define HSEM_C1MISR_MISF5_Pos (5U)
5003+#define HSEM_C1MISR_MISF5_Msk (0x1UL << HSEM_C1MISR_MISF5_Pos) /*!< 0x00000020 */
5004+#define HSEM_C1MISR_MISF5 HSEM_C1MISR_MISF5_Msk /*!<semaphore 5 CPU1 interrupt masked status bit. */
5005+#define HSEM_C1MISR_MISF6_Pos (6U)
5006+#define HSEM_C1MISR_MISF6_Msk (0x1UL << HSEM_C1MISR_MISF6_Pos) /*!< 0x00000040 */
5007+#define HSEM_C1MISR_MISF6 HSEM_C1MISR_MISF6_Msk /*!<semaphore 6 CPU1 interrupt masked status bit. */
5008+#define HSEM_C1MISR_MISF7_Pos (7U)
5009+#define HSEM_C1MISR_MISF7_Msk (0x1UL << HSEM_C1MISR_MISF7_Pos) /*!< 0x00000080 */
5010+#define HSEM_C1MISR_MISF7 HSEM_C1MISR_MISF7_Msk /*!<semaphore 7 CPU1 interrupt masked status bit. */
5011+#define HSEM_C1MISR_MISF8_Pos (8U)
5012+#define HSEM_C1MISR_MISF8_Msk (0x1UL << HSEM_C1MISR_MISF8_Pos) /*!< 0x00000100 */
5013+#define HSEM_C1MISR_MISF8 HSEM_C1MISR_MISF8_Msk /*!<semaphore 8 CPU1 interrupt masked status bit. */
5014+#define HSEM_C1MISR_MISF9_Pos (9U)
5015+#define HSEM_C1MISR_MISF9_Msk (0x1UL << HSEM_C1MISR_MISF9_Pos) /*!< 0x00000200 */
5016+#define HSEM_C1MISR_MISF9 HSEM_C1MISR_MISF9_Msk /*!<semaphore 9 CPU1 interrupt masked status bit. */
5017+#define HSEM_C1MISR_MISF10_Pos (10U)
5018+#define HSEM_C1MISR_MISF10_Msk (0x1UL << HSEM_C1MISR_MISF10_Pos) /*!< 0x00000400 */
5019+#define HSEM_C1MISR_MISF10 HSEM_C1MISR_MISF10_Msk /*!<semaphore 10 CPU1 interrupt masked status bit. */
5020+#define HSEM_C1MISR_MISF11_Pos (11U)
5021+#define HSEM_C1MISR_MISF11_Msk (0x1UL << HSEM_C1MISR_MISF11_Pos) /*!< 0x00000800 */
5022+#define HSEM_C1MISR_MISF11 HSEM_C1MISR_MISF11_Msk /*!<semaphore 11 CPU1 interrupt masked status bit. */
5023+#define HSEM_C1MISR_MISF12_Pos (12U)
5024+#define HSEM_C1MISR_MISF12_Msk (0x1UL << HSEM_C1MISR_MISF12_Pos) /*!< 0x00001000 */
5025+#define HSEM_C1MISR_MISF12 HSEM_C1MISR_MISF12_Msk /*!<semaphore 12 CPU1 interrupt masked status bit. */
5026+#define HSEM_C1MISR_MISF13_Pos (13U)
5027+#define HSEM_C1MISR_MISF13_Msk (0x1UL << HSEM_C1MISR_MISF13_Pos) /*!< 0x00002000 */
5028+#define HSEM_C1MISR_MISF13 HSEM_C1MISR_MISF13_Msk /*!<semaphore 13 CPU1 interrupt masked status bit. */
5029+#define HSEM_C1MISR_MISF14_Pos (14U)
5030+#define HSEM_C1MISR_MISF14_Msk (0x1UL << HSEM_C1MISR_MISF14_Pos) /*!< 0x00004000 */
5031+#define HSEM_C1MISR_MISF14 HSEM_C1MISR_MISF14_Msk /*!<semaphore 14 CPU1 interrupt masked status bit. */
5032+#define HSEM_C1MISR_MISF15_Pos (15U)
5033+#define HSEM_C1MISR_MISF15_Msk (0x1UL << HSEM_C1MISR_MISF15_Pos) /*!< 0x00008000 */
5034+#define HSEM_C1MISR_MISF15 HSEM_C1MISR_MISF15_Msk /*!<semaphore 15 CPU1 interrupt masked status bit. */
5035+#define HSEM_C1MISR_MISF16_Pos (16U)
5036+#define HSEM_C1MISR_MISF16_Msk (0x1UL << HSEM_C1MISR_MISF16_Pos) /*!< 0x00010000 */
5037+#define HSEM_C1MISR_MISF16 HSEM_C1MISR_MISF16_Msk /*!<semaphore 16 CPU1 interrupt masked status bit. */
5038+#define HSEM_C1MISR_MISF17_Pos (17U)
5039+#define HSEM_C1MISR_MISF17_Msk (0x1UL << HSEM_C1MISR_MISF17_Pos) /*!< 0x00020000 */
5040+#define HSEM_C1MISR_MISF17 HSEM_C1MISR_MISF17_Msk /*!<semaphore 17 CPU1 interrupt masked status bit. */
5041+#define HSEM_C1MISR_MISF18_Pos (18U)
5042+#define HSEM_C1MISR_MISF18_Msk (0x1UL << HSEM_C1MISR_MISF18_Pos) /*!< 0x00040000 */
5043+#define HSEM_C1MISR_MISF18 HSEM_C1MISR_MISF18_Msk /*!<semaphore 18 CPU1 interrupt masked status bit. */
5044+#define HSEM_C1MISR_MISF19_Pos (19U)
5045+#define HSEM_C1MISR_MISF19_Msk (0x1UL << HSEM_C1MISR_MISF19_Pos) /*!< 0x00080000 */
5046+#define HSEM_C1MISR_MISF19 HSEM_C1MISR_MISF19_Msk /*!<semaphore 19 CPU1 interrupt masked status bit. */
5047+#define HSEM_C1MISR_MISF20_Pos (20U)
5048+#define HSEM_C1MISR_MISF20_Msk (0x1UL << HSEM_C1MISR_MISF20_Pos) /*!< 0x00100000 */
5049+#define HSEM_C1MISR_MISF20 HSEM_C1MISR_MISF20_Msk /*!<semaphore 20 CPU1 interrupt masked status bit. */
5050+#define HSEM_C1MISR_MISF21_Pos (21U)
5051+#define HSEM_C1MISR_MISF21_Msk (0x1UL << HSEM_C1MISR_MISF21_Pos) /*!< 0x00200000 */
5052+#define HSEM_C1MISR_MISF21 HSEM_C1MISR_MISF21_Msk /*!<semaphore 21 CPU1 interrupt masked status bit. */
5053+#define HSEM_C1MISR_MISF22_Pos (22U)
5054+#define HSEM_C1MISR_MISF22_Msk (0x1UL << HSEM_C1MISR_MISF22_Pos) /*!< 0x00400000 */
5055+#define HSEM_C1MISR_MISF22 HSEM_C1MISR_MISF22_Msk /*!<semaphore 22 CPU1 interrupt masked status bit. */
5056+#define HSEM_C1MISR_MISF23_Pos (23U)
5057+#define HSEM_C1MISR_MISF23_Msk (0x1UL << HSEM_C1MISR_MISF23_Pos) /*!< 0x00800000 */
5058+#define HSEM_C1MISR_MISF23 HSEM_C1MISR_MISF23_Msk /*!<semaphore 23 CPU1 interrupt masked status bit. */
5059+#define HSEM_C1MISR_MISF24_Pos (24U)
5060+#define HSEM_C1MISR_MISF24_Msk (0x1UL << HSEM_C1MISR_MISF24_Pos) /*!< 0x01000000 */
5061+#define HSEM_C1MISR_MISF24 HSEM_C1MISR_MISF24_Msk /*!<semaphore 24 CPU1 interrupt masked status bit. */
5062+#define HSEM_C1MISR_MISF25_Pos (25U)
5063+#define HSEM_C1MISR_MISF25_Msk (0x1UL << HSEM_C1MISR_MISF25_Pos) /*!< 0x02000000 */
5064+#define HSEM_C1MISR_MISF25 HSEM_C1MISR_MISF25_Msk /*!<semaphore 25 CPU1 interrupt masked status bit. */
5065+#define HSEM_C1MISR_MISF26_Pos (26U)
5066+#define HSEM_C1MISR_MISF26_Msk (0x1UL << HSEM_C1MISR_MISF26_Pos) /*!< 0x04000000 */
5067+#define HSEM_C1MISR_MISF26 HSEM_C1MISR_MISF26_Msk /*!<semaphore 26 CPU1 interrupt masked status bit. */
5068+#define HSEM_C1MISR_MISF27_Pos (27U)
5069+#define HSEM_C1MISR_MISF27_Msk (0x1UL << HSEM_C1MISR_MISF27_Pos) /*!< 0x08000000 */
5070+#define HSEM_C1MISR_MISF27 HSEM_C1MISR_MISF27_Msk /*!<semaphore 27 CPU1 interrupt masked status bit. */
5071+#define HSEM_C1MISR_MISF28_Pos (28U)
5072+#define HSEM_C1MISR_MISF28_Msk (0x1UL << HSEM_C1MISR_MISF28_Pos) /*!< 0x10000000 */
5073+#define HSEM_C1MISR_MISF28 HSEM_C1MISR_MISF28_Msk /*!<semaphore 28 CPU1 interrupt masked status bit. */
5074+#define HSEM_C1MISR_MISF29_Pos (29U)
5075+#define HSEM_C1MISR_MISF29_Msk (0x1UL << HSEM_C1MISR_MISF29_Pos) /*!< 0x20000000 */
5076+#define HSEM_C1MISR_MISF29 HSEM_C1MISR_MISF29_Msk /*!<semaphore 29 CPU1 interrupt masked status bit. */
5077+#define HSEM_C1MISR_MISF30_Pos (30U)
5078+#define HSEM_C1MISR_MISF30_Msk (0x1UL << HSEM_C1MISR_MISF30_Pos) /*!< 0x40000000 */
5079+#define HSEM_C1MISR_MISF30 HSEM_C1MISR_MISF30_Msk /*!<semaphore 30 CPU1 interrupt masked status bit. */
5080+#define HSEM_C1MISR_MISF31_Pos (31U)
5081+#define HSEM_C1MISR_MISF31_Msk (0x1UL << HSEM_C1MISR_MISF31_Pos) /*!< 0x80000000 */
5082+#define HSEM_C1MISR_MISF31 HSEM_C1MISR_MISF31_Msk /*!<semaphore 31 CPU1 interrupt masked status bit. */
5083+
5084+/******************** Bit definition for HSEM_C2IER register *****************/
5085+#define HSEM_C2IER_ISE0_Pos (0U)
5086+#define HSEM_C2IER_ISE0_Msk (0x1UL << HSEM_C2IER_ISE0_Pos) /*!< 0x00000001 */
5087+#define HSEM_C2IER_ISE0 HSEM_C2IER_ISE0_Msk /*!<semaphore 0 CPU2 interrupt enable bit. */
5088+#define HSEM_C2IER_ISE1_Pos (1U)
5089+#define HSEM_C2IER_ISE1_Msk (0x1UL << HSEM_C2IER_ISE1_Pos) /*!< 0x00000002 */
5090+#define HSEM_C2IER_ISE1 HSEM_C2IER_ISE1_Msk /*!<semaphore 1 CPU2 interrupt enable bit. */
5091+#define HSEM_C2IER_ISE2_Pos (2U)
5092+#define HSEM_C2IER_ISE2_Msk (0x1UL << HSEM_C2IER_ISE2_Pos) /*!< 0x00000004 */
5093+#define HSEM_C2IER_ISE2 HSEM_C2IER_ISE2_Msk /*!<semaphore 2 CPU2 interrupt enable bit. */
5094+#define HSEM_C2IER_ISE3_Pos (3U)
5095+#define HSEM_C2IER_ISE3_Msk (0x1UL << HSEM_C2IER_ISE3_Pos) /*!< 0x00000008 */
5096+#define HSEM_C2IER_ISE3 HSEM_C2IER_ISE3_Msk /*!<semaphore 3 CPU2 interrupt enable bit. */
5097+#define HSEM_C2IER_ISE4_Pos (4U)
5098+#define HSEM_C2IER_ISE4_Msk (0x1UL << HSEM_C2IER_ISE4_Pos) /*!< 0x00000010 */
5099+#define HSEM_C2IER_ISE4 HSEM_C2IER_ISE4_Msk /*!<semaphore 4 CPU2 interrupt enable bit. */
5100+#define HSEM_C2IER_ISE5_Pos (5U)
5101+#define HSEM_C2IER_ISE5_Msk (0x1UL << HSEM_C2IER_ISE5_Pos) /*!< 0x00000020 */
5102+#define HSEM_C2IER_ISE5 HSEM_C2IER_ISE5_Msk /*!<semaphore 5 CPU2 interrupt enable bit. */
5103+#define HSEM_C2IER_ISE6_Pos (6U)
5104+#define HSEM_C2IER_ISE6_Msk (0x1UL << HSEM_C2IER_ISE6_Pos) /*!< 0x00000040 */
5105+#define HSEM_C2IER_ISE6 HSEM_C2IER_ISE6_Msk /*!<semaphore 6 CPU2 interrupt enable bit. */
5106+#define HSEM_C2IER_ISE7_Pos (7U)
5107+#define HSEM_C2IER_ISE7_Msk (0x1UL << HSEM_C2IER_ISE7_Pos) /*!< 0x00000080 */
5108+#define HSEM_C2IER_ISE7 HSEM_C2IER_ISE7_Msk /*!<semaphore 7 CPU2 interrupt enable bit. */
5109+#define HSEM_C2IER_ISE8_Pos (8U)
5110+#define HSEM_C2IER_ISE8_Msk (0x1UL << HSEM_C2IER_ISE8_Pos) /*!< 0x00000100 */
5111+#define HSEM_C2IER_ISE8 HSEM_C2IER_ISE8_Msk /*!<semaphore 8 CPU2 interrupt enable bit. */
5112+#define HSEM_C2IER_ISE9_Pos (9U)
5113+#define HSEM_C2IER_ISE9_Msk (0x1UL << HSEM_C2IER_ISE9_Pos) /*!< 0x00000200 */
5114+#define HSEM_C2IER_ISE9 HSEM_C2IER_ISE9_Msk /*!<semaphore 9 CPU2 interrupt enable bit. */
5115+#define HSEM_C2IER_ISE10_Pos (10U)
5116+#define HSEM_C2IER_ISE10_Msk (0x1UL << HSEM_C2IER_ISE10_Pos) /*!< 0x00000400 */
5117+#define HSEM_C2IER_ISE10 HSEM_C2IER_ISE10_Msk /*!<semaphore 10 CPU2 interrupt enable bit. */
5118+#define HSEM_C2IER_ISE11_Pos (11U)
5119+#define HSEM_C2IER_ISE11_Msk (0x1UL << HSEM_C2IER_ISE11_Pos) /*!< 0x00000800 */
5120+#define HSEM_C2IER_ISE11 HSEM_C2IER_ISE11_Msk /*!<semaphore 11 CPU2 interrupt enable bit. */
5121+#define HSEM_C2IER_ISE12_Pos (12U)
5122+#define HSEM_C2IER_ISE12_Msk (0x1UL << HSEM_C2IER_ISE12_Pos) /*!< 0x00001000 */
5123+#define HSEM_C2IER_ISE12 HSEM_C2IER_ISE12_Msk /*!<semaphore 12 CPU2 interrupt enable bit. */
5124+#define HSEM_C2IER_ISE13_Pos (13U)
5125+#define HSEM_C2IER_ISE13_Msk (0x1UL << HSEM_C2IER_ISE13_Pos) /*!< 0x00002000 */
5126+#define HSEM_C2IER_ISE13 HSEM_C2IER_ISE13_Msk /*!<semaphore 13 CPU2 interrupt enable bit. */
5127+#define HSEM_C2IER_ISE14_Pos (14U)
5128+#define HSEM_C2IER_ISE14_Msk (0x1UL << HSEM_C2IER_ISE14_Pos) /*!< 0x00004000 */
5129+#define HSEM_C2IER_ISE14 HSEM_C2IER_ISE14_Msk /*!<semaphore 14 CPU2 interrupt enable bit. */
5130+#define HSEM_C2IER_ISE15_Pos (15U)
5131+#define HSEM_C2IER_ISE15_Msk (0x1UL << HSEM_C2IER_ISE15_Pos) /*!< 0x00008000 */
5132+#define HSEM_C2IER_ISE15 HSEM_C2IER_ISE15_Msk /*!<semaphore 15 CPU2 interrupt enable bit. */
5133+#define HSEM_C2IER_ISE16_Pos (16U)
5134+#define HSEM_C2IER_ISE16_Msk (0x1UL << HSEM_C2IER_ISE16_Pos) /*!< 0x00010000 */
5135+#define HSEM_C2IER_ISE16 HSEM_C2IER_ISE16_Msk /*!<semaphore 16 CPU2 interrupt enable bit. */
5136+#define HSEM_C2IER_ISE17_Pos (17U)
5137+#define HSEM_C2IER_ISE17_Msk (0x1UL << HSEM_C2IER_ISE17_Pos) /*!< 0x00020000 */
5138+#define HSEM_C2IER_ISE17 HSEM_C2IER_ISE17_Msk /*!<semaphore 17 CPU2 interrupt enable bit. */
5139+#define HSEM_C2IER_ISE18_Pos (18U)
5140+#define HSEM_C2IER_ISE18_Msk (0x1UL << HSEM_C2IER_ISE18_Pos) /*!< 0x00040000 */
5141+#define HSEM_C2IER_ISE18 HSEM_C2IER_ISE18_Msk /*!<semaphore 18 CPU2 interrupt enable bit. */
5142+#define HSEM_C2IER_ISE19_Pos (19U)
5143+#define HSEM_C2IER_ISE19_Msk (0x1UL << HSEM_C2IER_ISE19_Pos) /*!< 0x00080000 */
5144+#define HSEM_C2IER_ISE19 HSEM_C2IER_ISE19_Msk /*!<semaphore 19 CPU2 interrupt enable bit. */
5145+#define HSEM_C2IER_ISE20_Pos (20U)
5146+#define HSEM_C2IER_ISE20_Msk (0x1UL << HSEM_C2IER_ISE20_Pos) /*!< 0x00100000 */
5147+#define HSEM_C2IER_ISE20 HSEM_C2IER_ISE20_Msk /*!<semaphore 20 CPU2 interrupt enable bit. */
5148+#define HSEM_C2IER_ISE21_Pos (21U)
5149+#define HSEM_C2IER_ISE21_Msk (0x1UL << HSEM_C2IER_ISE21_Pos) /*!< 0x00200000 */
5150+#define HSEM_C2IER_ISE21 HSEM_C2IER_ISE21_Msk /*!<semaphore 21 CPU2 interrupt enable bit. */
5151+#define HSEM_C2IER_ISE22_Pos (22U)
5152+#define HSEM_C2IER_ISE22_Msk (0x1UL << HSEM_C2IER_ISE22_Pos) /*!< 0x00400000 */
5153+#define HSEM_C2IER_ISE22 HSEM_C2IER_ISE22_Msk /*!<semaphore 22 CPU2 interrupt enable bit. */
5154+#define HSEM_C2IER_ISE23_Pos (23U)
5155+#define HSEM_C2IER_ISE23_Msk (0x1UL << HSEM_C2IER_ISE23_Pos) /*!< 0x00800000 */
5156+#define HSEM_C2IER_ISE23 HSEM_C2IER_ISE23_Msk /*!<semaphore 23 CPU2 interrupt enable bit. */
5157+#define HSEM_C2IER_ISE24_Pos (24U)
5158+#define HSEM_C2IER_ISE24_Msk (0x1UL << HSEM_C2IER_ISE24_Pos) /*!< 0x01000000 */
5159+#define HSEM_C2IER_ISE24 HSEM_C2IER_ISE24_Msk /*!<semaphore 24 CPU2 interrupt enable bit. */
5160+#define HSEM_C2IER_ISE25_Pos (25U)
5161+#define HSEM_C2IER_ISE25_Msk (0x1UL << HSEM_C2IER_ISE25_Pos) /*!< 0x02000000 */
5162+#define HSEM_C2IER_ISE25 HSEM_C2IER_ISE25_Msk /*!<semaphore 25 CPU2 interrupt enable bit. */
5163+#define HSEM_C2IER_ISE26_Pos (26U)
5164+#define HSEM_C2IER_ISE26_Msk (0x1UL << HSEM_C2IER_ISE26_Pos) /*!< 0x04000000 */
5165+#define HSEM_C2IER_ISE26 HSEM_C2IER_ISE26_Msk /*!<semaphore 26 CPU2 interrupt enable bit. */
5166+#define HSEM_C2IER_ISE27_Pos (27U)
5167+#define HSEM_C2IER_ISE27_Msk (0x1UL << HSEM_C2IER_ISE27_Pos) /*!< 0x08000000 */
5168+#define HSEM_C2IER_ISE27 HSEM_C2IER_ISE27_Msk /*!<semaphore 27 CPU2 interrupt enable bit. */
5169+#define HSEM_C2IER_ISE28_Pos (28U)
5170+#define HSEM_C2IER_ISE28_Msk (0x1UL << HSEM_C2IER_ISE28_Pos) /*!< 0x10000000 */
5171+#define HSEM_C2IER_ISE28 HSEM_C2IER_ISE28_Msk /*!<semaphore 28 CPU2 interrupt enable bit. */
5172+#define HSEM_C2IER_ISE29_Pos (29U)
5173+#define HSEM_C2IER_ISE29_Msk (0x1UL << HSEM_C2IER_ISE29_Pos) /*!< 0x20000000 */
5174+#define HSEM_C2IER_ISE29 HSEM_C2IER_ISE29_Msk /*!<semaphore 29 CPU2 interrupt enable bit. */
5175+#define HSEM_C2IER_ISE30_Pos (30U)
5176+#define HSEM_C2IER_ISE30_Msk (0x1UL << HSEM_C2IER_ISE30_Pos) /*!< 0x40000000 */
5177+#define HSEM_C2IER_ISE30 HSEM_C2IER_ISE30_Msk /*!<semaphore 30 CPU2 interrupt enable bit. */
5178+#define HSEM_C2IER_ISE31_Pos (31U)
5179+#define HSEM_C2IER_ISE31_Msk (0x1UL << HSEM_C2IER_ISE31_Pos) /*!< 0x80000000 */
5180+#define HSEM_C2IER_ISE31 HSEM_C2IER_ISE31_Msk /*!<semaphore 31 CPU2 interrupt enable bit. */
5181+
5182+/******************** Bit definition for HSEM_C2ICR register *****************/
5183+#define HSEM_C2ICR_ISC0_Pos (0U)
5184+#define HSEM_C2ICR_ISC0_Msk (0x1UL << HSEM_C2ICR_ISC0_Pos) /*!< 0x00000001 */
5185+#define HSEM_C2ICR_ISC0 HSEM_C2ICR_ISC0_Msk /*!<semaphore 0 CPU2 interrupt clear bit. */
5186+#define HSEM_C2ICR_ISC1_Pos (1U)
5187+#define HSEM_C2ICR_ISC1_Msk (0x1UL << HSEM_C2ICR_ISC1_Pos) /*!< 0x00000002 */
5188+#define HSEM_C2ICR_ISC1 HSEM_C2ICR_ISC1_Msk /*!<semaphore 1 CPU2 interrupt clear bit. */
5189+#define HSEM_C2ICR_ISC2_Pos (2U)
5190+#define HSEM_C2ICR_ISC2_Msk (0x1UL << HSEM_C2ICR_ISC2_Pos) /*!< 0x00000004 */
5191+#define HSEM_C2ICR_ISC2 HSEM_C2ICR_ISC2_Msk /*!<semaphore 2 CPU2 interrupt clear bit. */
5192+#define HSEM_C2ICR_ISC3_Pos (3U)
5193+#define HSEM_C2ICR_ISC3_Msk (0x1UL << HSEM_C2ICR_ISC3_Pos) /*!< 0x00000008 */
5194+#define HSEM_C2ICR_ISC3 HSEM_C2ICR_ISC3_Msk /*!<semaphore 3 CPU2 interrupt clear bit. */
5195+#define HSEM_C2ICR_ISC4_Pos (4U)
5196+#define HSEM_C2ICR_ISC4_Msk (0x1UL << HSEM_C2ICR_ISC4_Pos) /*!< 0x00000010 */
5197+#define HSEM_C2ICR_ISC4 HSEM_C2ICR_ISC4_Msk /*!<semaphore 4 CPU2 interrupt clear bit. */
5198+#define HSEM_C2ICR_ISC5_Pos (5U)
5199+#define HSEM_C2ICR_ISC5_Msk (0x1UL << HSEM_C2ICR_ISC5_Pos) /*!< 0x00000020 */
5200+#define HSEM_C2ICR_ISC5 HSEM_C2ICR_ISC5_Msk /*!<semaphore 5 CPU2 interrupt clear bit. */
5201+#define HSEM_C2ICR_ISC6_Pos (6U)
5202+#define HSEM_C2ICR_ISC6_Msk (0x1UL << HSEM_C2ICR_ISC6_Pos) /*!< 0x00000040 */
5203+#define HSEM_C2ICR_ISC6 HSEM_C2ICR_ISC6_Msk /*!<semaphore 6 CPU2 interrupt clear bit. */
5204+#define HSEM_C2ICR_ISC7_Pos (7U)
5205+#define HSEM_C2ICR_ISC7_Msk (0x1UL << HSEM_C2ICR_ISC7_Pos) /*!< 0x00000080 */
5206+#define HSEM_C2ICR_ISC7 HSEM_C2ICR_ISC7_Msk /*!<semaphore 7 CPU2 interrupt clear bit. */
5207+#define HSEM_C2ICR_ISC8_Pos (8U)
5208+#define HSEM_C2ICR_ISC8_Msk (0x1UL << HSEM_C2ICR_ISC8_Pos) /*!< 0x00000100 */
5209+#define HSEM_C2ICR_ISC8 HSEM_C2ICR_ISC8_Msk /*!<semaphore 8 CPU2 interrupt clear bit. */
5210+#define HSEM_C2ICR_ISC9_Pos (9U)
5211+#define HSEM_C2ICR_ISC9_Msk (0x1UL << HSEM_C2ICR_ISC9_Pos) /*!< 0x00000200 */
5212+#define HSEM_C2ICR_ISC9 HSEM_C2ICR_ISC9_Msk /*!<semaphore 9 CPU2 interrupt clear bit. */
5213+#define HSEM_C2ICR_ISC10_Pos (10U)
5214+#define HSEM_C2ICR_ISC10_Msk (0x1UL << HSEM_C2ICR_ISC10_Pos) /*!< 0x00000400 */
5215+#define HSEM_C2ICR_ISC10 HSEM_C2ICR_ISC10_Msk /*!<semaphore 10 CPU2 interrupt clear bit. */
5216+#define HSEM_C2ICR_ISC11_Pos (11U)
5217+#define HSEM_C2ICR_ISC11_Msk (0x1UL << HSEM_C2ICR_ISC11_Pos) /*!< 0x00000800 */
5218+#define HSEM_C2ICR_ISC11 HSEM_C2ICR_ISC11_Msk /*!<semaphore 11 CPU2 interrupt clear bit. */
5219+#define HSEM_C2ICR_ISC12_Pos (12U)
5220+#define HSEM_C2ICR_ISC12_Msk (0x1UL << HSEM_C2ICR_ISC12_Pos) /*!< 0x00001000 */
5221+#define HSEM_C2ICR_ISC12 HSEM_C2ICR_ISC12_Msk /*!<semaphore 12 CPU2 interrupt clear bit. */
5222+#define HSEM_C2ICR_ISC13_Pos (13U)
5223+#define HSEM_C2ICR_ISC13_Msk (0x1UL << HSEM_C2ICR_ISC13_Pos) /*!< 0x00002000 */
5224+#define HSEM_C2ICR_ISC13 HSEM_C2ICR_ISC13_Msk /*!<semaphore 13 CPU2 interrupt clear bit. */
5225+#define HSEM_C2ICR_ISC14_Pos (14U)
5226+#define HSEM_C2ICR_ISC14_Msk (0x1UL << HSEM_C2ICR_ISC14_Pos) /*!< 0x00004000 */
5227+#define HSEM_C2ICR_ISC14 HSEM_C2ICR_ISC14_Msk /*!<semaphore 14 CPU2 interrupt clear bit. */
5228+#define HSEM_C2ICR_ISC15_Pos (15U)
5229+#define HSEM_C2ICR_ISC15_Msk (0x1UL << HSEM_C2ICR_ISC15_Pos) /*!< 0x00008000 */
5230+#define HSEM_C2ICR_ISC15 HSEM_C2ICR_ISC15_Msk /*!<semaphore 15 CPU2 interrupt clear bit. */
5231+#define HSEM_C2ICR_ISC16_Pos (16U)
5232+#define HSEM_C2ICR_ISC16_Msk (0x1UL << HSEM_C2ICR_ISC16_Pos) /*!< 0x00010000 */
5233+#define HSEM_C2ICR_ISC16 HSEM_C2ICR_ISC16_Msk /*!<semaphore 16 CPU2 interrupt clear bit. */
5234+#define HSEM_C2ICR_ISC17_Pos (17U)
5235+#define HSEM_C2ICR_ISC17_Msk (0x1UL << HSEM_C2ICR_ISC17_Pos) /*!< 0x00020000 */
5236+#define HSEM_C2ICR_ISC17 HSEM_C2ICR_ISC17_Msk /*!<semaphore 17 CPU2 interrupt clear bit. */
5237+#define HSEM_C2ICR_ISC18_Pos (18U)
5238+#define HSEM_C2ICR_ISC18_Msk (0x1UL << HSEM_C2ICR_ISC18_Pos) /*!< 0x00040000 */
5239+#define HSEM_C2ICR_ISC18 HSEM_C2ICR_ISC18_Msk /*!<semaphore 18 CPU2 interrupt clear bit. */
5240+#define HSEM_C2ICR_ISC19_Pos (19U)
5241+#define HSEM_C2ICR_ISC19_Msk (0x1UL << HSEM_C2ICR_ISC19_Pos) /*!< 0x00080000 */
5242+#define HSEM_C2ICR_ISC19 HSEM_C2ICR_ISC19_Msk /*!<semaphore 19 CPU2 interrupt clear bit. */
5243+#define HSEM_C2ICR_ISC20_Pos (20U)
5244+#define HSEM_C2ICR_ISC20_Msk (0x1UL << HSEM_C2ICR_ISC20_Pos) /*!< 0x00100000 */
5245+#define HSEM_C2ICR_ISC20 HSEM_C2ICR_ISC20_Msk /*!<semaphore 20 CPU2 interrupt clear bit. */
5246+#define HSEM_C2ICR_ISC21_Pos (21U)
5247+#define HSEM_C2ICR_ISC21_Msk (0x1UL << HSEM_C2ICR_ISC21_Pos) /*!< 0x00200000 */
5248+#define HSEM_C2ICR_ISC21 HSEM_C2ICR_ISC21_Msk /*!<semaphore 21 CPU2 interrupt clear bit. */
5249+#define HSEM_C2ICR_ISC22_Pos (22U)
5250+#define HSEM_C2ICR_ISC22_Msk (0x1UL << HSEM_C2ICR_ISC22_Pos) /*!< 0x00400000 */
5251+#define HSEM_C2ICR_ISC22 HSEM_C2ICR_ISC22_Msk /*!<semaphore 22 CPU2 interrupt clear bit. */
5252+#define HSEM_C2ICR_ISC23_Pos (23U)
5253+#define HSEM_C2ICR_ISC23_Msk (0x1UL << HSEM_C2ICR_ISC23_Pos) /*!< 0x00800000 */
5254+#define HSEM_C2ICR_ISC23 HSEM_C2ICR_ISC23_Msk /*!<semaphore 23 CPU2 interrupt clear bit. */
5255+#define HSEM_C2ICR_ISC24_Pos (24U)
5256+#define HSEM_C2ICR_ISC24_Msk (0x1UL << HSEM_C2ICR_ISC24_Pos) /*!< 0x01000000 */
5257+#define HSEM_C2ICR_ISC24 HSEM_C2ICR_ISC24_Msk /*!<semaphore 24 CPU2 interrupt clear bit. */
5258+#define HSEM_C2ICR_ISC25_Pos (25U)
5259+#define HSEM_C2ICR_ISC25_Msk (0x1UL << HSEM_C2ICR_ISC25_Pos) /*!< 0x02000000 */
5260+#define HSEM_C2ICR_ISC25 HSEM_C2ICR_ISC25_Msk /*!<semaphore 25 CPU2 interrupt clear bit. */
5261+#define HSEM_C2ICR_ISC26_Pos (26U)
5262+#define HSEM_C2ICR_ISC26_Msk (0x1UL << HSEM_C2ICR_ISC26_Pos) /*!< 0x04000000 */
5263+#define HSEM_C2ICR_ISC26 HSEM_C2ICR_ISC26_Msk /*!<semaphore 26 CPU2 interrupt clear bit. */
5264+#define HSEM_C2ICR_ISC27_Pos (27U)
5265+#define HSEM_C2ICR_ISC27_Msk (0x1UL << HSEM_C2ICR_ISC27_Pos) /*!< 0x08000000 */
5266+#define HSEM_C2ICR_ISC27 HSEM_C2ICR_ISC27_Msk /*!<semaphore 27 CPU2 interrupt clear bit. */
5267+#define HSEM_C2ICR_ISC28_Pos (28U)
5268+#define HSEM_C2ICR_ISC28_Msk (0x1UL << HSEM_C2ICR_ISC28_Pos) /*!< 0x10000000 */
5269+#define HSEM_C2ICR_ISC28 HSEM_C2ICR_ISC28_Msk /*!<semaphore 28 CPU2 interrupt clear bit. */
5270+#define HSEM_C2ICR_ISC29_Pos (29U)
5271+#define HSEM_C2ICR_ISC29_Msk (0x1UL << HSEM_C2ICR_ISC29_Pos) /*!< 0x20000000 */
5272+#define HSEM_C2ICR_ISC29 HSEM_C2ICR_ISC29_Msk /*!<semaphore 29 CPU2 interrupt clear bit. */
5273+#define HSEM_C2ICR_ISC30_Pos (30U)
5274+#define HSEM_C2ICR_ISC30_Msk (0x1UL << HSEM_C2ICR_ISC30_Pos) /*!< 0x40000000 */
5275+#define HSEM_C2ICR_ISC30 HSEM_C2ICR_ISC30_Msk /*!<semaphore 30 CPU2 interrupt clear bit. */
5276+#define HSEM_C2ICR_ISC31_Pos (31U)
5277+#define HSEM_C2ICR_ISC31_Msk (0x1UL << HSEM_C2ICR_ISC31_Pos) /*!< 0x80000000 */
5278+#define HSEM_C2ICR_ISC31 HSEM_C2ICR_ISC31_Msk /*!<semaphore 31 CPU2 interrupt clear bit. */
5279+
5280+/******************** Bit definition for HSEM_C2ISR register *****************/
5281+#define HSEM_C2ISR_ISF0_Pos (0U)
5282+#define HSEM_C2ISR_ISF0_Msk (0x1UL << HSEM_C2ISR_ISF0_Pos) /*!< 0x00000001 */
5283+#define HSEM_C2ISR_ISF0 HSEM_C2ISR_ISF0_Msk /*!<semaphore 0 CPU2 interrupt status bit. */
5284+#define HSEM_C2ISR_ISF1_Pos (1U)
5285+#define HSEM_C2ISR_ISF1_Msk (0x1UL << HSEM_C2ISR_ISF1_Pos) /*!< 0x00000002 */
5286+#define HSEM_C2ISR_ISF1 HSEM_C2ISR_ISF1_Msk /*!<semaphore 1 CPU2 interrupt status bit. */
5287+#define HSEM_C2ISR_ISF2_Pos (2U)
5288+#define HSEM_C2ISR_ISF2_Msk (0x1UL << HSEM_C2ISR_ISF2_Pos) /*!< 0x00000004 */
5289+#define HSEM_C2ISR_ISF2 HSEM_C2ISR_ISF2_Msk /*!<semaphore 2 CPU2 interrupt status bit. */
5290+#define HSEM_C2ISR_ISF3_Pos (3U)
5291+#define HSEM_C2ISR_ISF3_Msk (0x1UL << HSEM_C2ISR_ISF3_Pos) /*!< 0x00000008 */
5292+#define HSEM_C2ISR_ISF3 HSEM_C2ISR_ISF3_Msk /*!<semaphore 3 CPU2 interrupt status bit. */
5293+#define HSEM_C2ISR_ISF4_Pos (4U)
5294+#define HSEM_C2ISR_ISF4_Msk (0x1UL << HSEM_C2ISR_ISF4_Pos) /*!< 0x00000010 */
5295+#define HSEM_C2ISR_ISF4 HSEM_C2ISR_ISF4_Msk /*!<semaphore 4 CPU2 interrupt status bit. */
5296+#define HSEM_C2ISR_ISF5_Pos (5U)
5297+#define HSEM_C2ISR_ISF5_Msk (0x1UL << HSEM_C2ISR_ISF5_Pos) /*!< 0x00000020 */
5298+#define HSEM_C2ISR_ISF5 HSEM_C2ISR_ISF5_Msk /*!<semaphore 5 CPU2 interrupt status bit. */
5299+#define HSEM_C2ISR_ISF6_Pos (6U)
5300+#define HSEM_C2ISR_ISF6_Msk (0x1UL << HSEM_C2ISR_ISF6_Pos) /*!< 0x00000040 */
5301+#define HSEM_C2ISR_ISF6 HSEM_C2ISR_ISF6_Msk /*!<semaphore 6 CPU2 interrupt status bit. */
5302+#define HSEM_C2ISR_ISF7_Pos (7U)
5303+#define HSEM_C2ISR_ISF7_Msk (0x1UL << HSEM_C2ISR_ISF7_Pos) /*!< 0x00000080 */
5304+#define HSEM_C2ISR_ISF7 HSEM_C2ISR_ISF7_Msk /*!<semaphore 7 CPU2 interrupt status bit. */
5305+#define HSEM_C2ISR_ISF8_Pos (8U)
5306+#define HSEM_C2ISR_ISF8_Msk (0x1UL << HSEM_C2ISR_ISF8_Pos) /*!< 0x00000100 */
5307+#define HSEM_C2ISR_ISF8 HSEM_C2ISR_ISF8_Msk /*!<semaphore 8 CPU2 interrupt status bit. */
5308+#define HSEM_C2ISR_ISF9_Pos (9U)
5309+#define HSEM_C2ISR_ISF9_Msk (0x1UL << HSEM_C2ISR_ISF9_Pos) /*!< 0x00000200 */
5310+#define HSEM_C2ISR_ISF9 HSEM_C2ISR_ISF9_Msk /*!<semaphore 9 CPU2 interrupt status bit. */
5311+#define HSEM_C2ISR_ISF10_Pos (10U)
5312+#define HSEM_C2ISR_ISF10_Msk (0x1UL << HSEM_C2ISR_ISF10_Pos) /*!< 0x00000400 */
5313+#define HSEM_C2ISR_ISF10 HSEM_C2ISR_ISF10_Msk /*!<semaphore 10 CPU2 interrupt status bit. */
5314+#define HSEM_C2ISR_ISF11_Pos (11U)
5315+#define HSEM_C2ISR_ISF11_Msk (0x1UL << HSEM_C2ISR_ISF11_Pos) /*!< 0x00000800 */
5316+#define HSEM_C2ISR_ISF11 HSEM_C2ISR_ISF11_Msk /*!<semaphore 11 CPU2 interrupt status bit. */
5317+#define HSEM_C2ISR_ISF12_Pos (12U)
5318+#define HSEM_C2ISR_ISF12_Msk (0x1UL << HSEM_C2ISR_ISF12_Pos) /*!< 0x00001000 */
5319+#define HSEM_C2ISR_ISF12 HSEM_C2ISR_ISF12_Msk /*!<semaphore 12 CPU2 interrupt status bit. */
5320+#define HSEM_C2ISR_ISF13_Pos (13U)
5321+#define HSEM_C2ISR_ISF13_Msk (0x1UL << HSEM_C2ISR_ISF13_Pos) /*!< 0x00002000 */
5322+#define HSEM_C2ISR_ISF13 HSEM_C2ISR_ISF13_Msk /*!<semaphore 13 CPU2 interrupt status bit. */
5323+#define HSEM_C2ISR_ISF14_Pos (14U)
5324+#define HSEM_C2ISR_ISF14_Msk (0x1UL << HSEM_C2ISR_ISF14_Pos) /*!< 0x00004000 */
5325+#define HSEM_C2ISR_ISF14 HSEM_C2ISR_ISF14_Msk /*!<semaphore 14 CPU2 interrupt status bit. */
5326+#define HSEM_C2ISR_ISF15_Pos (15U)
5327+#define HSEM_C2ISR_ISF15_Msk (0x1UL << HSEM_C2ISR_ISF15_Pos) /*!< 0x00008000 */
5328+#define HSEM_C2ISR_ISF15 HSEM_C2ISR_ISF15_Msk /*!<semaphore 15 CPU2 interrupt status bit. */
5329+#define HSEM_C2ISR_ISF16_Pos (16U)
5330+#define HSEM_C2ISR_ISF16_Msk (0x1UL << HSEM_C2ISR_ISF16_Pos) /*!< 0x00010000 */
5331+#define HSEM_C2ISR_ISF16 HSEM_C2ISR_ISF16_Msk /*!<semaphore 16 CPU2 interrupt status bit. */
5332+#define HSEM_C2ISR_ISF17_Pos (17U)
5333+#define HSEM_C2ISR_ISF17_Msk (0x1UL << HSEM_C2ISR_ISF17_Pos) /*!< 0x00020000 */
5334+#define HSEM_C2ISR_ISF17 HSEM_C2ISR_ISF17_Msk /*!<semaphore 17 CPU2 interrupt status bit. */
5335+#define HSEM_C2ISR_ISF18_Pos (18U)
5336+#define HSEM_C2ISR_ISF18_Msk (0x1UL << HSEM_C2ISR_ISF18_Pos) /*!< 0x00040000 */
5337+#define HSEM_C2ISR_ISF18 HSEM_C2ISR_ISF18_Msk /*!<semaphore 18 CPU2 interrupt status bit. */
5338+#define HSEM_C2ISR_ISF19_Pos (19U)
5339+#define HSEM_C2ISR_ISF19_Msk (0x1UL << HSEM_C2ISR_ISF19_Pos) /*!< 0x00080000 */
5340+#define HSEM_C2ISR_ISF19 HSEM_C2ISR_ISF19_Msk /*!<semaphore 19 CPU2 interrupt status bit. */
5341+#define HSEM_C2ISR_ISF20_Pos (20U)
5342+#define HSEM_C2ISR_ISF20_Msk (0x1UL << HSEM_C2ISR_ISF20_Pos) /*!< 0x00100000 */
5343+#define HSEM_C2ISR_ISF20 HSEM_C2ISR_ISF20_Msk /*!<semaphore 20 CPU2 interrupt status bit. */
5344+#define HSEM_C2ISR_ISF21_Pos (21U)
5345+#define HSEM_C2ISR_ISF21_Msk (0x1UL << HSEM_C2ISR_ISF21_Pos) /*!< 0x00200000 */
5346+#define HSEM_C2ISR_ISF21 HSEM_C2ISR_ISF21_Msk /*!<semaphore 21 CPU2 interrupt status bit. */
5347+#define HSEM_C2ISR_ISF22_Pos (22U)
5348+#define HSEM_C2ISR_ISF22_Msk (0x1UL << HSEM_C2ISR_ISF22_Pos) /*!< 0x00400000 */
5349+#define HSEM_C2ISR_ISF22 HSEM_C2ISR_ISF22_Msk /*!<semaphore 22 CPU2 interrupt status bit. */
5350+#define HSEM_C2ISR_ISF23_Pos (23U)
5351+#define HSEM_C2ISR_ISF23_Msk (0x1UL << HSEM_C2ISR_ISF23_Pos) /*!< 0x00800000 */
5352+#define HSEM_C2ISR_ISF23 HSEM_C2ISR_ISF23_Msk /*!<semaphore 23 CPU2 interrupt status bit. */
5353+#define HSEM_C2ISR_ISF24_Pos (24U)
5354+#define HSEM_C2ISR_ISF24_Msk (0x1UL << HSEM_C2ISR_ISF24_Pos) /*!< 0x01000000 */
5355+#define HSEM_C2ISR_ISF24 HSEM_C2ISR_ISF24_Msk /*!<semaphore 24 CPU2 interrupt status bit. */
5356+#define HSEM_C2ISR_ISF25_Pos (25U)
5357+#define HSEM_C2ISR_ISF25_Msk (0x1UL << HSEM_C2ISR_ISF25_Pos) /*!< 0x02000000 */
5358+#define HSEM_C2ISR_ISF25 HSEM_C2ISR_ISF25_Msk /*!<semaphore 25 CPU2 interrupt status bit. */
5359+#define HSEM_C2ISR_ISF26_Pos (26U)
5360+#define HSEM_C2ISR_ISF26_Msk (0x1UL << HSEM_C2ISR_ISF26_Pos) /*!< 0x04000000 */
5361+#define HSEM_C2ISR_ISF26 HSEM_C2ISR_ISF26_Msk /*!<semaphore 26 CPU2 interrupt status bit. */
5362+#define HSEM_C2ISR_ISF27_Pos (27U)
5363+#define HSEM_C2ISR_ISF27_Msk (0x1UL << HSEM_C2ISR_ISF27_Pos) /*!< 0x08000000 */
5364+#define HSEM_C2ISR_ISF27 HSEM_C2ISR_ISF27_Msk /*!<semaphore 27 CPU2 interrupt status bit. */
5365+#define HSEM_C2ISR_ISF28_Pos (28U)
5366+#define HSEM_C2ISR_ISF28_Msk (0x1UL << HSEM_C2ISR_ISF28_Pos) /*!< 0x10000000 */
5367+#define HSEM_C2ISR_ISF28 HSEM_C2ISR_ISF28_Msk /*!<semaphore 28 CPU2 interrupt status bit. */
5368+#define HSEM_C2ISR_ISF29_Pos (29U)
5369+#define HSEM_C2ISR_ISF29_Msk (0x1UL << HSEM_C2ISR_ISF29_Pos) /*!< 0x20000000 */
5370+#define HSEM_C2ISR_ISF29 HSEM_C2ISR_ISF29_Msk /*!<semaphore 29 CPU2 interrupt status bit. */
5371+#define HSEM_C2ISR_ISF30_Pos (30U)
5372+#define HSEM_C2ISR_ISF30_Msk (0x1UL << HSEM_C2ISR_ISF30_Pos) /*!< 0x40000000 */
5373+#define HSEM_C2ISR_ISF30 HSEM_C2ISR_ISF30_Msk /*!<semaphore 30 CPU2 interrupt status bit. */
5374+#define HSEM_C2ISR_ISF31_Pos (31U)
5375+#define HSEM_C2ISR_ISF31_Msk (0x1UL << HSEM_C2ISR_ISF31_Pos) /*!< 0x80000000 */
5376+#define HSEM_C2ISR_ISF31 HSEM_C2ISR_ISF31_Msk /*!<semaphore 31 CPU2 interrupt status bit. */
5377+
5378+/******************** Bit definition for HSEM_C2MISR register *****************/
5379+#define HSEM_C2MISR_MISF0_Pos (0U)
5380+#define HSEM_C2MISR_MISF0_Msk (0x1UL << HSEM_C2MISR_MISF0_Pos) /*!< 0x00000001 */
5381+#define HSEM_C2MISR_MISF0 HSEM_C2MISR_MISF0_Msk /*!<semaphore 0 CPU2 interrupt masked status bit. */
5382+#define HSEM_C2MISR_MISF1_Pos (1U)
5383+#define HSEM_C2MISR_MISF1_Msk (0x1UL << HSEM_C2MISR_MISF1_Pos) /*!< 0x00000002 */
5384+#define HSEM_C2MISR_MISF1 HSEM_C2MISR_MISF1_Msk /*!<semaphore 1 CPU2 interrupt masked status bit. */
5385+#define HSEM_C2MISR_MISF2_Pos (2U)
5386+#define HSEM_C2MISR_MISF2_Msk (0x1UL << HSEM_C2MISR_MISF2_Pos) /*!< 0x00000004 */
5387+#define HSEM_C2MISR_MISF2 HSEM_C2MISR_MISF2_Msk /*!<semaphore 2 CPU2 interrupt masked status bit. */
5388+#define HSEM_C2MISR_MISF3_Pos (3U)
5389+#define HSEM_C2MISR_MISF3_Msk (0x1UL << HSEM_C2MISR_MISF3_Pos) /*!< 0x00000008 */
5390+#define HSEM_C2MISR_MISF3 HSEM_C2MISR_MISF3_Msk /*!<semaphore 3 CPU2 interrupt masked status bit. */
5391+#define HSEM_C2MISR_MISF4_Pos (4U)
5392+#define HSEM_C2MISR_MISF4_Msk (0x1UL << HSEM_C2MISR_MISF4_Pos) /*!< 0x00000010 */
5393+#define HSEM_C2MISR_MISF4 HSEM_C2MISR_MISF4_Msk /*!<semaphore 4 CPU2 interrupt masked status bit. */
5394+#define HSEM_C2MISR_MISF5_Pos (5U)
5395+#define HSEM_C2MISR_MISF5_Msk (0x1UL << HSEM_C2MISR_MISF5_Pos) /*!< 0x00000020 */
5396+#define HSEM_C2MISR_MISF5 HSEM_C2MISR_MISF5_Msk /*!<semaphore 5 CPU2 interrupt masked status bit. */
5397+#define HSEM_C2MISR_MISF6_Pos (6U)
5398+#define HSEM_C2MISR_MISF6_Msk (0x1UL << HSEM_C2MISR_MISF6_Pos) /*!< 0x00000040 */
5399+#define HSEM_C2MISR_MISF6 HSEM_C2MISR_MISF6_Msk /*!<semaphore 6 CPU2 interrupt masked status bit. */
5400+#define HSEM_C2MISR_MISF7_Pos (7U)
5401+#define HSEM_C2MISR_MISF7_Msk (0x1UL << HSEM_C2MISR_MISF7_Pos) /*!< 0x00000080 */
5402+#define HSEM_C2MISR_MISF7 HSEM_C2MISR_MISF7_Msk /*!<semaphore 7 CPU2 interrupt masked status bit. */
5403+#define HSEM_C2MISR_MISF8_Pos (8U)
5404+#define HSEM_C2MISR_MISF8_Msk (0x1UL << HSEM_C2MISR_MISF8_Pos) /*!< 0x00000100 */
5405+#define HSEM_C2MISR_MISF8 HSEM_C2MISR_MISF8_Msk /*!<semaphore 8 CPU2 interrupt masked status bit. */
5406+#define HSEM_C2MISR_MISF9_Pos (9U)
5407+#define HSEM_C2MISR_MISF9_Msk (0x1UL << HSEM_C2MISR_MISF9_Pos) /*!< 0x00000200 */
5408+#define HSEM_C2MISR_MISF9 HSEM_C2MISR_MISF9_Msk /*!<semaphore 9 CPU2 interrupt masked status bit. */
5409+#define HSEM_C2MISR_MISF10_Pos (10U)
5410+#define HSEM_C2MISR_MISF10_Msk (0x1UL << HSEM_C2MISR_MISF10_Pos) /*!< 0x00000400 */
5411+#define HSEM_C2MISR_MISF10 HSEM_C2MISR_MISF10_Msk /*!<semaphore 10 CPU2 interrupt masked status bit. */
5412+#define HSEM_C2MISR_MISF11_Pos (11U)
5413+#define HSEM_C2MISR_MISF11_Msk (0x1UL << HSEM_C2MISR_MISF11_Pos) /*!< 0x00000800 */
5414+#define HSEM_C2MISR_MISF11 HSEM_C2MISR_MISF11_Msk /*!<semaphore 11 CPU2 interrupt masked status bit. */
5415+#define HSEM_C2MISR_MISF12_Pos (12U)
5416+#define HSEM_C2MISR_MISF12_Msk (0x1UL << HSEM_C2MISR_MISF12_Pos) /*!< 0x00001000 */
5417+#define HSEM_C2MISR_MISF12 HSEM_C2MISR_MISF12_Msk /*!<semaphore 12 CPU2 interrupt masked status bit. */
5418+#define HSEM_C2MISR_MISF13_Pos (13U)
5419+#define HSEM_C2MISR_MISF13_Msk (0x1UL << HSEM_C2MISR_MISF13_Pos) /*!< 0x00002000 */
5420+#define HSEM_C2MISR_MISF13 HSEM_C2MISR_MISF13_Msk /*!<semaphore 13 CPU2 interrupt masked status bit. */
5421+#define HSEM_C2MISR_MISF14_Pos (14U)
5422+#define HSEM_C2MISR_MISF14_Msk (0x1UL << HSEM_C2MISR_MISF14_Pos) /*!< 0x00004000 */
5423+#define HSEM_C2MISR_MISF14 HSEM_C2MISR_MISF14_Msk /*!<semaphore 14 CPU2 interrupt masked status bit. */
5424+#define HSEM_C2MISR_MISF15_Pos (15U)
5425+#define HSEM_C2MISR_MISF15_Msk (0x1UL << HSEM_C2MISR_MISF15_Pos) /*!< 0x00008000 */
5426+#define HSEM_C2MISR_MISF15 HSEM_C2MISR_MISF15_Msk /*!<semaphore 15 CPU2 interrupt masked status bit. */
5427+#define HSEM_C2MISR_MISF16_Pos (16U)
5428+#define HSEM_C2MISR_MISF16_Msk (0x1UL << HSEM_C2MISR_MISF16_Pos) /*!< 0x00010000 */
5429+#define HSEM_C2MISR_MISF16 HSEM_C2MISR_MISF16_Msk /*!<semaphore 16 CPU2 interrupt masked status bit. */
5430+#define HSEM_C2MISR_MISF17_Pos (17U)
5431+#define HSEM_C2MISR_MISF17_Msk (0x1UL << HSEM_C2MISR_MISF17_Pos) /*!< 0x00020000 */
5432+#define HSEM_C2MISR_MISF17 HSEM_C2MISR_MISF17_Msk /*!<semaphore 17 CPU2 interrupt masked status bit. */
5433+#define HSEM_C2MISR_MISF18_Pos (18U)
5434+#define HSEM_C2MISR_MISF18_Msk (0x1UL << HSEM_C2MISR_MISF18_Pos) /*!< 0x00040000 */
5435+#define HSEM_C2MISR_MISF18 HSEM_C2MISR_MISF18_Msk /*!<semaphore 18 CPU2 interrupt masked status bit. */
5436+#define HSEM_C2MISR_MISF19_Pos (19U)
5437+#define HSEM_C2MISR_MISF19_Msk (0x1UL << HSEM_C2MISR_MISF19_Pos) /*!< 0x00080000 */
5438+#define HSEM_C2MISR_MISF19 HSEM_C2MISR_MISF19_Msk /*!<semaphore 19 CPU2 interrupt masked status bit. */
5439+#define HSEM_C2MISR_MISF20_Pos (20U)
5440+#define HSEM_C2MISR_MISF20_Msk (0x1UL << HSEM_C2MISR_MISF20_Pos) /*!< 0x00100000 */
5441+#define HSEM_C2MISR_MISF20 HSEM_C2MISR_MISF20_Msk /*!<semaphore 20 CPU2 interrupt masked status bit. */
5442+#define HSEM_C2MISR_MISF21_Pos (21U)
5443+#define HSEM_C2MISR_MISF21_Msk (0x1UL << HSEM_C2MISR_MISF21_Pos) /*!< 0x00200000 */
5444+#define HSEM_C2MISR_MISF21 HSEM_C2MISR_MISF21_Msk /*!<semaphore 21 CPU2 interrupt masked status bit. */
5445+#define HSEM_C2MISR_MISF22_Pos (22U)
5446+#define HSEM_C2MISR_MISF22_Msk (0x1UL << HSEM_C2MISR_MISF22_Pos) /*!< 0x00400000 */
5447+#define HSEM_C2MISR_MISF22 HSEM_C2MISR_MISF22_Msk /*!<semaphore 22 CPU2 interrupt masked status bit. */
5448+#define HSEM_C2MISR_MISF23_Pos (23U)
5449+#define HSEM_C2MISR_MISF23_Msk (0x1UL << HSEM_C2MISR_MISF23_Pos) /*!< 0x00800000 */
5450+#define HSEM_C2MISR_MISF23 HSEM_C2MISR_MISF23_Msk /*!<semaphore 23 CPU2 interrupt masked status bit. */
5451+#define HSEM_C2MISR_MISF24_Pos (24U)
5452+#define HSEM_C2MISR_MISF24_Msk (0x1UL << HSEM_C2MISR_MISF24_Pos) /*!< 0x01000000 */
5453+#define HSEM_C2MISR_MISF24 HSEM_C2MISR_MISF24_Msk /*!<semaphore 24 CPU2 interrupt masked status bit. */
5454+#define HSEM_C2MISR_MISF25_Pos (25U)
5455+#define HSEM_C2MISR_MISF25_Msk (0x1UL << HSEM_C2MISR_MISF25_Pos) /*!< 0x02000000 */
5456+#define HSEM_C2MISR_MISF25 HSEM_C2MISR_MISF25_Msk /*!<semaphore 25 CPU2 interrupt masked status bit. */
5457+#define HSEM_C2MISR_MISF26_Pos (26U)
5458+#define HSEM_C2MISR_MISF26_Msk (0x1UL << HSEM_C2MISR_MISF26_Pos) /*!< 0x04000000 */
5459+#define HSEM_C2MISR_MISF26 HSEM_C2MISR_MISF26_Msk /*!<semaphore 26 CPU2 interrupt masked status bit. */
5460+#define HSEM_C2MISR_MISF27_Pos (27U)
5461+#define HSEM_C2MISR_MISF27_Msk (0x1UL << HSEM_C2MISR_MISF27_Pos) /*!< 0x08000000 */
5462+#define HSEM_C2MISR_MISF27 HSEM_C2MISR_MISF27_Msk /*!<semaphore 27 CPU2 interrupt masked status bit. */
5463+#define HSEM_C2MISR_MISF28_Pos (28U)
5464+#define HSEM_C2MISR_MISF28_Msk (0x1UL << HSEM_C2MISR_MISF28_Pos) /*!< 0x10000000 */
5465+#define HSEM_C2MISR_MISF28 HSEM_C2MISR_MISF28_Msk /*!<semaphore 28 CPU2 interrupt masked status bit. */
5466+#define HSEM_C2MISR_MISF29_Pos (29U)
5467+#define HSEM_C2MISR_MISF29_Msk (0x1UL << HSEM_C2MISR_MISF29_Pos) /*!< 0x20000000 */
5468+#define HSEM_C2MISR_MISF29 HSEM_C2MISR_MISF29_Msk /*!<semaphore 29 CPU2 interrupt masked status bit. */
5469+#define HSEM_C2MISR_MISF30_Pos (30U)
5470+#define HSEM_C2MISR_MISF30_Msk (0x1UL << HSEM_C2MISR_MISF30_Pos) /*!< 0x40000000 */
5471+#define HSEM_C2MISR_MISF30 HSEM_C2MISR_MISF30_Msk /*!<semaphore 30 CPU2 interrupt masked status bit. */
5472+#define HSEM_C2MISR_MISF31_Pos (31U)
5473+#define HSEM_C2MISR_MISF31_Msk (0x1UL << HSEM_C2MISR_MISF31_Pos) /*!< 0x80000000 */
5474+#define HSEM_C2MISR_MISF31 HSEM_C2MISR_MISF31_Msk /*!<semaphore 31 CPU2 interrupt masked status bit. */
5475+
5476+/******************** Bit definition for HSEM_CR register *****************/
5477+#define HSEM_CR_COREID_Pos (8U)
5478+#define HSEM_CR_COREID_Msk (0xFUL << HSEM_CR_COREID_Pos) /*!< 0x00000F00 */
5479+#define HSEM_CR_COREID HSEM_CR_COREID_Msk /*!<CoreID of semaphores to be cleared. */
5480+#define HSEM_CR_COREID_CPU1 (0x4U << HSEM_CR_COREID_Pos)
5481+#define HSEM_CR_COREID_CPU2 (0x8U << HSEM_CR_COREID_Pos)
5482+#define HSEM_CR_COREID_CURRENT HSEM_CR_COREID_CPU1
5483+#define HSEM_CR_KEY_Pos (16U)
5484+#define HSEM_CR_KEY_Msk (0xFFFFUL << HSEM_CR_KEY_Pos) /*!< 0xFFFF0000 */
5485+#define HSEM_CR_KEY HSEM_CR_KEY_Msk /*!<semaphores clear key. */
5486+
5487+/******************** Bit definition for HSEM_KEYR register *****************/
5488+#define HSEM_KEYR_KEY_Pos (16U)
5489+#define HSEM_KEYR_KEY_Msk (0xFFFFUL << HSEM_KEYR_KEY_Pos) /*!< 0xFFFF0000 */
5490+#define HSEM_KEYR_KEY HSEM_KEYR_KEY_Msk /*!<semaphores clear key. */
5491+
5492+/******************************************************************************/
5493+/* */
5494+/* Inter-integrated Circuit Interface (I2C) */
5495+/* */
5496+/******************************************************************************/
5497+/******************* Bit definition for I2C_CR1 register *******************/
5498+#define I2C_CR1_PE_Pos (0U)
5499+#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
5500+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
5501+#define I2C_CR1_TXIE_Pos (1U)
5502+#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
5503+#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
5504+#define I2C_CR1_RXIE_Pos (2U)
5505+#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
5506+#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
5507+#define I2C_CR1_ADDRIE_Pos (3U)
5508+#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
5509+#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
5510+#define I2C_CR1_NACKIE_Pos (4U)
5511+#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
5512+#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
5513+#define I2C_CR1_STOPIE_Pos (5U)
5514+#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
5515+#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
5516+#define I2C_CR1_TCIE_Pos (6U)
5517+#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
5518+#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
5519+#define I2C_CR1_ERRIE_Pos (7U)
5520+#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
5521+#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
5522+#define I2C_CR1_DNF_Pos (8U)
5523+#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
5524+#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
5525+#define I2C_CR1_ANFOFF_Pos (12U)
5526+#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
5527+#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
5528+#define I2C_CR1_SWRST_Pos (13U)
5529+#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
5530+#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
5531+#define I2C_CR1_TXDMAEN_Pos (14U)
5532+#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
5533+#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
5534+#define I2C_CR1_RXDMAEN_Pos (15U)
5535+#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
5536+#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
5537+#define I2C_CR1_SBC_Pos (16U)
5538+#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
5539+#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
5540+#define I2C_CR1_NOSTRETCH_Pos (17U)
5541+#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
5542+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
5543+#define I2C_CR1_WUPEN_Pos (18U)
5544+#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
5545+#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
5546+#define I2C_CR1_GCEN_Pos (19U)
5547+#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
5548+#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
5549+#define I2C_CR1_SMBHEN_Pos (20U)
5550+#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
5551+#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
5552+#define I2C_CR1_SMBDEN_Pos (21U)
5553+#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
5554+#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
5555+#define I2C_CR1_ALERTEN_Pos (22U)
5556+#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
5557+#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
5558+#define I2C_CR1_PECEN_Pos (23U)
5559+#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
5560+#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
5561+
5562+/****************** Bit definition for I2C_CR2 register ********************/
5563+#define I2C_CR2_SADD_Pos (0U)
5564+#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
5565+#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
5566+#define I2C_CR2_RD_WRN_Pos (10U)
5567+#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
5568+#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
5569+#define I2C_CR2_ADD10_Pos (11U)
5570+#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
5571+#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
5572+#define I2C_CR2_HEAD10R_Pos (12U)
5573+#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
5574+#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
5575+#define I2C_CR2_START_Pos (13U)
5576+#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
5577+#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
5578+#define I2C_CR2_STOP_Pos (14U)
5579+#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
5580+#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
5581+#define I2C_CR2_NACK_Pos (15U)
5582+#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
5583+#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
5584+#define I2C_CR2_NBYTES_Pos (16U)
5585+#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
5586+#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
5587+#define I2C_CR2_RELOAD_Pos (24U)
5588+#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
5589+#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
5590+#define I2C_CR2_AUTOEND_Pos (25U)
5591+#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
5592+#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
5593+#define I2C_CR2_PECBYTE_Pos (26U)
5594+#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
5595+#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
5596+
5597+/******************* Bit definition for I2C_OAR1 register ******************/
5598+#define I2C_OAR1_OA1_Pos (0U)
5599+#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
5600+#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
5601+#define I2C_OAR1_OA1MODE_Pos (10U)
5602+#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
5603+#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
5604+#define I2C_OAR1_OA1EN_Pos (15U)
5605+#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
5606+#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
5607+
5608+/******************* Bit definition for I2C_OAR2 register ******************/
5609+#define I2C_OAR2_OA2_Pos (1U)
5610+#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
5611+#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
5612+#define I2C_OAR2_OA2MSK_Pos (8U)
5613+#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
5614+#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
5615+#define I2C_OAR2_OA2NOMASK (0x00000000UL) /*!< No mask */
5616+#define I2C_OAR2_OA2MASK01_Pos (8U)
5617+#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
5618+#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
5619+#define I2C_OAR2_OA2MASK02_Pos (9U)
5620+#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
5621+#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
5622+#define I2C_OAR2_OA2MASK03_Pos (8U)
5623+#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
5624+#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
5625+#define I2C_OAR2_OA2MASK04_Pos (10U)
5626+#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
5627+#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
5628+#define I2C_OAR2_OA2MASK05_Pos (8U)
5629+#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
5630+#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
5631+#define I2C_OAR2_OA2MASK06_Pos (9U)
5632+#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
5633+#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
5634+#define I2C_OAR2_OA2MASK07_Pos (8U)
5635+#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
5636+#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
5637+#define I2C_OAR2_OA2EN_Pos (15U)
5638+#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
5639+#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
5640+
5641+/******************* Bit definition for I2C_TIMINGR register *******************/
5642+#define I2C_TIMINGR_SCLL_Pos (0U)
5643+#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
5644+#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
5645+#define I2C_TIMINGR_SCLH_Pos (8U)
5646+#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
5647+#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
5648+#define I2C_TIMINGR_SDADEL_Pos (16U)
5649+#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
5650+#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
5651+#define I2C_TIMINGR_SCLDEL_Pos (20U)
5652+#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
5653+#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
5654+#define I2C_TIMINGR_PRESC_Pos (28U)
5655+#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
5656+#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
5657+
5658+/******************* Bit definition for I2C_TIMEOUTR register *******************/
5659+#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
5660+#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
5661+#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
5662+#define I2C_TIMEOUTR_TIDLE_Pos (12U)
5663+#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
5664+#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
5665+#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
5666+#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
5667+#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
5668+#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
5669+#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
5670+#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
5671+#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
5672+#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
5673+#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
5674+
5675+/****************** Bit definition for I2C_ISR register *********************/
5676+#define I2C_ISR_TXE_Pos (0U)
5677+#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
5678+#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
5679+#define I2C_ISR_TXIS_Pos (1U)
5680+#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
5681+#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
5682+#define I2C_ISR_RXNE_Pos (2U)
5683+#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
5684+#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
5685+#define I2C_ISR_ADDR_Pos (3U)
5686+#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
5687+#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
5688+#define I2C_ISR_NACKF_Pos (4U)
5689+#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
5690+#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
5691+#define I2C_ISR_STOPF_Pos (5U)
5692+#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
5693+#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
5694+#define I2C_ISR_TC_Pos (6U)
5695+#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
5696+#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
5697+#define I2C_ISR_TCR_Pos (7U)
5698+#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
5699+#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
5700+#define I2C_ISR_BERR_Pos (8U)
5701+#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
5702+#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
5703+#define I2C_ISR_ARLO_Pos (9U)
5704+#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
5705+#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
5706+#define I2C_ISR_OVR_Pos (10U)
5707+#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
5708+#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
5709+#define I2C_ISR_PECERR_Pos (11U)
5710+#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
5711+#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
5712+#define I2C_ISR_TIMEOUT_Pos (12U)
5713+#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
5714+#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
5715+#define I2C_ISR_ALERT_Pos (13U)
5716+#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
5717+#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
5718+#define I2C_ISR_BUSY_Pos (15U)
5719+#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
5720+#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
5721+#define I2C_ISR_DIR_Pos (16U)
5722+#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
5723+#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
5724+#define I2C_ISR_ADDCODE_Pos (17U)
5725+#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
5726+#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
5727+
5728+/****************** Bit definition for I2C_ICR register *********************/
5729+#define I2C_ICR_ADDRCF_Pos (3U)
5730+#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
5731+#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
5732+#define I2C_ICR_NACKCF_Pos (4U)
5733+#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
5734+#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
5735+#define I2C_ICR_STOPCF_Pos (5U)
5736+#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
5737+#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
5738+#define I2C_ICR_BERRCF_Pos (8U)
5739+#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
5740+#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
5741+#define I2C_ICR_ARLOCF_Pos (9U)
5742+#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
5743+#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
5744+#define I2C_ICR_OVRCF_Pos (10U)
5745+#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
5746+#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
5747+#define I2C_ICR_PECCF_Pos (11U)
5748+#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
5749+#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
5750+#define I2C_ICR_TIMOUTCF_Pos (12U)
5751+#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
5752+#define I2C_ICR_TIMOUTCF I2C_