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chibios: Commit


Commit MetaInfo

Revision14017 (tree)
Time2021-01-12 17:42:33
Authorgdisirio

Log Message

More STM32WB-related patches.

Change Summary

Incremental Difference

--- trunk/demos/STM32/RT-STM32WB55RG-NUCLEO68/cfg/mcuconf.h (revision 14016)
+++ trunk/demos/STM32/RT-STM32WB55RG-NUCLEO68/cfg/mcuconf.h (revision 14017)
@@ -15,7 +15,7 @@
1515 */
1616
1717 /*
18- * STM32WBxx drivers configuration.
18+ * STM32WB55xx drivers configuration.
1919 * The following settings override the default settings present in
2020 * the various device driver implementation headers.
2121 * Note that the settings for each driver only have effect if the whole
@@ -42,6 +42,7 @@
4242 #define STM32_PVD_ENABLE FALSE
4343 #define STM32_PLS STM32_PLS_LEV0
4444 #define STM32_HSI16_ENABLED TRUE
45+#define STM32_HSI48_ENABLED FALSE
4546 #define STM32_LSI_ENABLED TRUE
4647 #define STM32_HSE_ENABLED TRUE
4748 #define STM32_LSE_ENABLED TRUE
@@ -57,6 +58,8 @@
5758 #define STM32_HPRE STM32_HPRE_DIV1
5859 #define STM32_PPRE1 STM32_PPRE1_DIV1
5960 #define STM32_PPRE2 STM32_PPRE2_DIV1
61+#define STM32_C2HPRE STM32_C2HPRE_DIV2
62+#define STM32_SHDHPRE STM32_SHDHPRE_DIV1
6063 #define STM32_STOPWUCK STM32_STOPWUCK_MSI
6164 #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
6265 #define STM32_MCOPRE STM32_MCOPRE_DIV1
@@ -78,7 +81,6 @@
7881 #define STM32_SAI1SEL STM32_SAI1SEL_OFF
7982 #define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
8083 #define STM32_ADCSEL STM32_ADCSEL_SYSCLK
81-#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
8284 #define STM32_RTCSEL STM32_RTCSEL_LSI
8385
8486 /*
@@ -102,6 +104,8 @@
102104 #define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7
103105 #define STM32_IRQ_TIM1_CC_PRIORITY 7
104106 #define STM32_IRQ_TIM2_PRIORITY 7
107+#define STM32_IRQ_TIM16_PRIORITY 7
108+#define STM32_IRQ_TIM17_PRIORITY 7
105109
106110 #define STM32_IRQ_USART1_PRIORITY 3
107111 #define STM32_IRQ_LPUART1_PRIORITY 3
@@ -109,14 +113,14 @@
109113 /*
110114 * ADC driver system settings.
111115 */
112-#define STM32_ADC_DUAL_MODE FALSE
113116 #define STM32_ADC_COMPACT_SAMPLES FALSE
114117 #define STM32_ADC_USE_ADC1 FALSE
115118 #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
116119 #define STM32_ADC_ADC1_DMA_PRIORITY 2
117-#define STM32_ADC_ADC12_IRQ_PRIORITY 5
120+#define STM32_ADC_ADC1_IRQ_PRIORITY 5
118121 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
119-#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
122+#define STM32_ADC_ADC1_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
123+#define STM32_ADC_ADC1_PRESC ADC_CCR_PRESC_DIV2
120124
121125 /*
122126 * GPT driver system settings.
@@ -174,6 +178,12 @@
174178 #define STM32_SERIAL_LPUART1_PRIORITY 12
175179
176180 /*
181+ * SIO driver system settings.
182+ */
183+#define STM32_SIO_USE_USART1 FALSE
184+#define STM32_SIO_USE_LPUART1 FALSE
185+
186+/*
177187 * SPI driver system settings.
178188 */
179189 #define STM32_SPI_USE_SPI1 FALSE
@@ -210,6 +220,14 @@
210220 #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
211221
212222 /*
223+ * USB driver system settings.
224+ */
225+#define STM32_USB_USE_USB1 FALSE
226+#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
227+#define STM32_USB_USB1_HP_IRQ_PRIORITY 12
228+#define STM32_USB_USB1_LP_IRQ_PRIORITY 12
229+
230+/*
213231 * WDG driver system settings.
214232 */
215233 #define STM32_WDG_USE_IWDG FALSE
--- trunk/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c (revision 14016)
+++ trunk/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c (revision 14017)
@@ -602,7 +602,7 @@
602602 #if STM32_ADC_USE_ADC1
603603 rccEnableADC1(true);
604604 rccResetADC1();
605- ADC1_COMMON->CCR = STM32_ADC_ADC1_CLOCK_MODE | ADC_DMA_MDMA;
605+ ADC1_COMMON->CCR = STM32_ADC_ADC1_PRESC | STM32_ADC_ADC1_CLOCK_MODE;
606606 rccDisableADC1();
607607 #endif
608608 #endif
--- trunk/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h (revision 14016)
+++ trunk/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h (revision 14017)
@@ -392,8 +392,15 @@
392392 * @brief ADC1 clock source and mode.
393393 */
394394 #if !defined(STM32_ADC_ADC1_CLOCK_MODE) || defined(__DOXYGEN__)
395-#define STM32_ADC_ADC1_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
395+#define STM32_ADC_ADC1_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
396396 #endif
397+
398+/**
399+ * @brief ADC1 clock prescaler.
400+ */
401+#if !defined(STM32_ADC_ADC1_PRESC) || defined(__DOXYGEN__)
402+#define STM32_ADC_ADC1_PRESC ADC_CCR_PRESC_DIV2
403+#endif
397404 #endif /* defined(STM32WBXX) */
398405
399406 /** @} */
--- trunk/os/hal/ports/STM32/LLD/ADCv3/notes.txt (revision 14016)
+++ trunk/os/hal/ports/STM32/LLD/ADCv3/notes.txt (revision 14017)
@@ -2,7 +2,7 @@
22
33 Driver capability:
44
5-- Supports the STM32 "fast" ADC found on F3, L4, L4+ and G4 sub-families.
5+- Supports the STM32 "fast" ADC found on F3, L4, L4+, G4 and WB sub-families.
66
77 The file registry must export:
88
--- trunk/os/hal/ports/STM32/LLD/USBv1/stm32_usb.h (revision 14016)
+++ trunk/os/hal/ports/STM32/LLD/USBv1/stm32_usb.h (revision 14017)
@@ -121,19 +121,23 @@
121121 /**
122122 * @brief USB registers block numeric address.
123123 */
124-#if defined(USB_BASE) || defined(__DOXYGEN__)
125-#define STM32_USB_BASE USB_BASE
124+#if defined(USB1_BASE) || defined(__DOXYGEN__)
125+ #define STM32_USB_BASE USB1_BASE
126+#elif defined(USB_BASE)
127+ #define STM32_USB_BASE USB_BASE
126128 #else
127-#define STM32_USB_BASE (APB1PERIPH_BASE + 0x5C00)
129+ #define STM32_USB_BASE (APB1PERIPH_BASE + 0x5C00)
128130 #endif
129131
130132 /**
131133 * @brief USB RAM numeric address.
132134 */
133-#if defined(USB_PMAADDR) || defined(__DOXYGEN__)
134-#define STM32_USBRAM_BASE USB_PMAADDR
135+#if defined(USB1_PMAADDR) || defined(__DOXYGEN__)
136+ #define STM32_USBRAM_BASE USB1_PMAADDR
137+#elif defined(USB_PMAADDR)
138+ #define STM32_USBRAM_BASE USB_PMAADDR
135139 #else
136-#define STM32_USBRAM_BASE (APB1PERIPH_BASE + 0x6000)
140+ #define STM32_USBRAM_BASE (APB1PERIPH_BASE + 0x6000)
137141 #endif
138142
139143 /**
--- trunk/os/hal/ports/STM32/STM32WBxx/hal_lld.c (revision 14016)
+++ trunk/os/hal/ports/STM32/STM32WBxx/hal_lld.c (revision 14017)
@@ -179,9 +179,11 @@
179179
180180 /* Core voltage setup.*/
181181 PWR->CR1 = STM32_VOS;
182- while ((PWR->SR2 & PWR_SR2_VOSF) != 0) /* Wait until regulator is */
183- ; /* stable. */
184182
183+ /* Wait until regulator is stable. */
184+ while ((PWR->SR2 & PWR_SR2_VOSF) != 0)
185+ ;
186+
185187 #if STM32_HSI16_ENABLED
186188 /* HSI activation.*/
187189 RCC->CR |= RCC_CR_HSION;
--- trunk/os/hal/ports/STM32/STM32WBxx/hal_lld.h (revision 14016)
+++ trunk/os/hal/ports/STM32/STM32WBxx/hal_lld.h (revision 14017)
@@ -211,7 +211,7 @@
211211 #define STM32_SHDHPRE_DIV5 (2 << 0) /**< SYSCLK divided by 5. */
212212 #define STM32_SHDHPRE_DIV6 (5 << 0) /**< SYSCLK divided by 6. */
213213 #define STM32_SHDHPRE_DIV8 (10 << 0) /**< SYSCLK divided by 8. */
214-#define STM32_SHDHPRE_DIV10 (6 << 0) /**< SYSCLK divided by 10. */
214+#define STM32_SHDHPRE_DIV10 (6 << 0) /**< SYSCLK divided by 10. */
215215 #define STM32_SHDHPRE_DIV16 (11 << 0) /**< SYSCLK divided by 16. */
216216 #define STM32_SHDHPRE_DIV32 (7 << 0) /**< SYSCLK divided by 32. */
217217 #define STM32_SHDHPRE_DIV64 (12 << 0) /**< SYSCLK divided by 64. */
@@ -243,7 +243,7 @@
243243 */
244244 #define STM32_RFCSS_MASK (1 << 20) /**< RFCSS field mask. */
245245 #define STM32_RFCSS_HSI16 (0 << 20) /**< HSI16 on HCLK5 and APB3. */
246-#define STM32_RFCSS_HSEDIV2 (1 << 20) /**< HSE/2 on HCLK5 and APB3. */
246+#define STM32_RFCSS_HSEDIV2 (1 << 20) /**< HSE/2 on HCLK5 and APB3. */
247247 /** @} */
248248
249249 /**
@@ -663,7 +663,7 @@
663663 * @brief ADCSEL value (ADCs clock source).
664664 */
665665 #if !defined(STM32_ADCSEL) || defined(__DOXYGEN__)
666-#define STM32_ADCSEL STM32_CLK48SEL_PLLSAI1
666+#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
667667 #endif
668668
669669 /**
--- trunk/testhal/STM32/multi/ADC/cfg/stm32wb55rg_nucleo68/mcuconf.h (revision 14016)
+++ trunk/testhal/STM32/multi/ADC/cfg/stm32wb55rg_nucleo68/mcuconf.h (revision 14017)
@@ -15,7 +15,7 @@
1515 */
1616
1717 /*
18- * STM32WBxx drivers configuration.
18+ * STM32WB55xx drivers configuration.
1919 * The following settings override the default settings present in
2020 * the various device driver implementation headers.
2121 * Note that the settings for each driver only have effect if the whole
@@ -42,6 +42,7 @@
4242 #define STM32_PVD_ENABLE FALSE
4343 #define STM32_PLS STM32_PLS_LEV0
4444 #define STM32_HSI16_ENABLED TRUE
45+#define STM32_HSI48_ENABLED FALSE
4546 #define STM32_LSI_ENABLED TRUE
4647 #define STM32_HSE_ENABLED TRUE
4748 #define STM32_LSE_ENABLED TRUE
@@ -57,6 +58,8 @@
5758 #define STM32_HPRE STM32_HPRE_DIV1
5859 #define STM32_PPRE1 STM32_PPRE1_DIV1
5960 #define STM32_PPRE2 STM32_PPRE2_DIV1
61+#define STM32_C2HPRE STM32_C2HPRE_DIV2
62+#define STM32_SHDHPRE STM32_SHDHPRE_DIV1
6063 #define STM32_STOPWUCK STM32_STOPWUCK_MSI
6164 #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
6265 #define STM32_MCOPRE STM32_MCOPRE_DIV1
@@ -78,7 +81,6 @@
7881 #define STM32_SAI1SEL STM32_SAI1SEL_OFF
7982 #define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
8083 #define STM32_ADCSEL STM32_ADCSEL_SYSCLK
81-#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
8284 #define STM32_RTCSEL STM32_RTCSEL_LSI
8385
8486 /*
@@ -102,6 +104,8 @@
102104 #define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7
103105 #define STM32_IRQ_TIM1_CC_PRIORITY 7
104106 #define STM32_IRQ_TIM2_PRIORITY 7
107+#define STM32_IRQ_TIM16_PRIORITY 7
108+#define STM32_IRQ_TIM17_PRIORITY 7
105109
106110 #define STM32_IRQ_USART1_PRIORITY 3
107111 #define STM32_IRQ_LPUART1_PRIORITY 3
@@ -109,16 +113,14 @@
109113 /*
110114 * ADC driver system settings.
111115 */
112-#define STM32_ADC_DUAL_MODE FALSE
113116 #define STM32_ADC_COMPACT_SAMPLES FALSE
114117 #define STM32_ADC_USE_ADC1 TRUE
115-#define STM32_ADC_USE_ADC2 FALSE
116-#define STM32_ADC_USE_ADC3 FALSE
117118 #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
118119 #define STM32_ADC_ADC1_DMA_PRIORITY 2
119120 #define STM32_ADC_ADC1_IRQ_PRIORITY 5
120121 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
121122 #define STM32_ADC_ADC1_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
123+#define STM32_ADC_ADC1_PRESC ADC_CCR_PRESC_DIV2
122124
123125 /*
124126 * GPT driver system settings.
@@ -149,8 +151,6 @@
149151 */
150152 #define STM32_ICU_USE_TIM1 FALSE
151153 #define STM32_ICU_USE_TIM2 FALSE
152-#define STM32_ICU_USE_TIM16 FALSE
153-#define STM32_ICU_USE_TIM17 FALSE
154154
155155 /*
156156 * PWM driver system settings.
@@ -178,6 +178,12 @@
178178 #define STM32_SERIAL_LPUART1_PRIORITY 12
179179
180180 /*
181+ * SIO driver system settings.
182+ */
183+#define STM32_SIO_USE_USART1 FALSE
184+#define STM32_SIO_USE_LPUART1 FALSE
185+
186+/*
181187 * SPI driver system settings.
182188 */
183189 #define STM32_SPI_USE_SPI1 FALSE
@@ -214,6 +220,14 @@
214220 #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
215221
216222 /*
223+ * USB driver system settings.
224+ */
225+#define STM32_USB_USE_USB1 FALSE
226+#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
227+#define STM32_USB_USB1_HP_IRQ_PRIORITY 12
228+#define STM32_USB_USB1_LP_IRQ_PRIORITY 12
229+
230+/*
217231 * WDG driver system settings.
218232 */
219233 #define STM32_WDG_USE_IWDG FALSE
--- trunk/testhal/STM32/multi/RTC/cfg/stm32wb55rg_nucleo68/mcuconf.h (revision 14016)
+++ trunk/testhal/STM32/multi/RTC/cfg/stm32wb55rg_nucleo68/mcuconf.h (revision 14017)
@@ -15,7 +15,7 @@
1515 */
1616
1717 /*
18- * STM32WBxx drivers configuration.
18+ * STM32WB55xx drivers configuration.
1919 * The following settings override the default settings present in
2020 * the various device driver implementation headers.
2121 * Note that the settings for each driver only have effect if the whole
@@ -42,6 +42,7 @@
4242 #define STM32_PVD_ENABLE FALSE
4343 #define STM32_PLS STM32_PLS_LEV0
4444 #define STM32_HSI16_ENABLED TRUE
45+#define STM32_HSI48_ENABLED FALSE
4546 #define STM32_LSI_ENABLED TRUE
4647 #define STM32_HSE_ENABLED TRUE
4748 #define STM32_LSE_ENABLED TRUE
@@ -57,6 +58,8 @@
5758 #define STM32_HPRE STM32_HPRE_DIV1
5859 #define STM32_PPRE1 STM32_PPRE1_DIV1
5960 #define STM32_PPRE2 STM32_PPRE2_DIV1
61+#define STM32_C2HPRE STM32_C2HPRE_DIV2
62+#define STM32_SHDHPRE STM32_SHDHPRE_DIV1
6063 #define STM32_STOPWUCK STM32_STOPWUCK_MSI
6164 #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
6265 #define STM32_MCOPRE STM32_MCOPRE_DIV1
@@ -78,7 +81,6 @@
7881 #define STM32_SAI1SEL STM32_SAI1SEL_OFF
7982 #define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
8083 #define STM32_ADCSEL STM32_ADCSEL_SYSCLK
81-#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
8284 #define STM32_RTCSEL STM32_RTCSEL_LSI
8385
8486 /*
@@ -102,6 +104,8 @@
102104 #define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7
103105 #define STM32_IRQ_TIM1_CC_PRIORITY 7
104106 #define STM32_IRQ_TIM2_PRIORITY 7
107+#define STM32_IRQ_TIM16_PRIORITY 7
108+#define STM32_IRQ_TIM17_PRIORITY 7
105109
106110 #define STM32_IRQ_USART1_PRIORITY 3
107111 #define STM32_IRQ_LPUART1_PRIORITY 3
@@ -109,16 +113,14 @@
109113 /*
110114 * ADC driver system settings.
111115 */
112-#define STM32_ADC_DUAL_MODE FALSE
113116 #define STM32_ADC_COMPACT_SAMPLES FALSE
114117 #define STM32_ADC_USE_ADC1 FALSE
115-#define STM32_ADC_USE_ADC2 FALSE
116-#define STM32_ADC_USE_ADC3 FALSE
117118 #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
118119 #define STM32_ADC_ADC1_DMA_PRIORITY 2
119120 #define STM32_ADC_ADC1_IRQ_PRIORITY 5
120121 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
121122 #define STM32_ADC_ADC1_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
123+#define STM32_ADC_ADC1_PRESC ADC_CCR_PRESC_DIV2
122124
123125 /*
124126 * GPT driver system settings.
@@ -149,8 +151,6 @@
149151 */
150152 #define STM32_ICU_USE_TIM1 FALSE
151153 #define STM32_ICU_USE_TIM2 FALSE
152-#define STM32_ICU_USE_TIM16 FALSE
153-#define STM32_ICU_USE_TIM17 FALSE
154154
155155 /*
156156 * PWM driver system settings.
@@ -178,6 +178,12 @@
178178 #define STM32_SERIAL_LPUART1_PRIORITY 12
179179
180180 /*
181+ * SIO driver system settings.
182+ */
183+#define STM32_SIO_USE_USART1 FALSE
184+#define STM32_SIO_USE_LPUART1 FALSE
185+
186+/*
181187 * SPI driver system settings.
182188 */
183189 #define STM32_SPI_USE_SPI1 FALSE
@@ -214,6 +220,14 @@
214220 #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
215221
216222 /*
223+ * USB driver system settings.
224+ */
225+#define STM32_USB_USE_USB1 FALSE
226+#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
227+#define STM32_USB_USB1_HP_IRQ_PRIORITY 12
228+#define STM32_USB_USB1_LP_IRQ_PRIORITY 12
229+
230+/*
217231 * WDG driver system settings.
218232 */
219233 #define STM32_WDG_USE_IWDG FALSE
--- trunk/testhal/STM32/multi/TRNG/cfg/stm32wb55rg_nucleo68/mcuconf.h (revision 14016)
+++ trunk/testhal/STM32/multi/TRNG/cfg/stm32wb55rg_nucleo68/mcuconf.h (revision 14017)
@@ -15,7 +15,7 @@
1515 */
1616
1717 /*
18- * STM32WBxx drivers configuration.
18+ * STM32WB55xx drivers configuration.
1919 * The following settings override the default settings present in
2020 * the various device driver implementation headers.
2121 * Note that the settings for each driver only have effect if the whole
@@ -42,6 +42,7 @@
4242 #define STM32_PVD_ENABLE FALSE
4343 #define STM32_PLS STM32_PLS_LEV0
4444 #define STM32_HSI16_ENABLED TRUE
45+#define STM32_HSI48_ENABLED FALSE
4546 #define STM32_LSI_ENABLED TRUE
4647 #define STM32_HSE_ENABLED TRUE
4748 #define STM32_LSE_ENABLED TRUE
@@ -57,6 +58,8 @@
5758 #define STM32_HPRE STM32_HPRE_DIV1
5859 #define STM32_PPRE1 STM32_PPRE1_DIV1
5960 #define STM32_PPRE2 STM32_PPRE2_DIV1
61+#define STM32_C2HPRE STM32_C2HPRE_DIV2
62+#define STM32_SHDHPRE STM32_SHDHPRE_DIV1
6063 #define STM32_STOPWUCK STM32_STOPWUCK_MSI
6164 #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
6265 #define STM32_MCOPRE STM32_MCOPRE_DIV1
@@ -78,7 +81,6 @@
7881 #define STM32_SAI1SEL STM32_SAI1SEL_OFF
7982 #define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
8083 #define STM32_ADCSEL STM32_ADCSEL_SYSCLK
81-#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
8284 #define STM32_RTCSEL STM32_RTCSEL_LSI
8385
8486 /*
@@ -102,6 +104,8 @@
102104 #define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7
103105 #define STM32_IRQ_TIM1_CC_PRIORITY 7
104106 #define STM32_IRQ_TIM2_PRIORITY 7
107+#define STM32_IRQ_TIM16_PRIORITY 7
108+#define STM32_IRQ_TIM17_PRIORITY 7
105109
106110 #define STM32_IRQ_USART1_PRIORITY 3
107111 #define STM32_IRQ_LPUART1_PRIORITY 3
@@ -109,16 +113,14 @@
109113 /*
110114 * ADC driver system settings.
111115 */
112-#define STM32_ADC_DUAL_MODE FALSE
113116 #define STM32_ADC_COMPACT_SAMPLES FALSE
114117 #define STM32_ADC_USE_ADC1 FALSE
115-#define STM32_ADC_USE_ADC2 FALSE
116-#define STM32_ADC_USE_ADC3 FALSE
117118 #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
118119 #define STM32_ADC_ADC1_DMA_PRIORITY 2
119120 #define STM32_ADC_ADC1_IRQ_PRIORITY 5
120121 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
121122 #define STM32_ADC_ADC1_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
123+#define STM32_ADC_ADC1_PRESC ADC_CCR_PRESC_DIV2
122124
123125 /*
124126 * GPT driver system settings.
@@ -149,8 +151,6 @@
149151 */
150152 #define STM32_ICU_USE_TIM1 FALSE
151153 #define STM32_ICU_USE_TIM2 FALSE
152-#define STM32_ICU_USE_TIM16 FALSE
153-#define STM32_ICU_USE_TIM17 FALSE
154154
155155 /*
156156 * PWM driver system settings.
@@ -178,6 +178,12 @@
178178 #define STM32_SERIAL_LPUART1_PRIORITY 12
179179
180180 /*
181+ * SIO driver system settings.
182+ */
183+#define STM32_SIO_USE_USART1 FALSE
184+#define STM32_SIO_USE_LPUART1 FALSE
185+
186+/*
181187 * SPI driver system settings.
182188 */
183189 #define STM32_SPI_USE_SPI1 FALSE
@@ -214,6 +220,14 @@
214220 #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
215221
216222 /*
223+ * USB driver system settings.
224+ */
225+#define STM32_USB_USE_USB1 FALSE
226+#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
227+#define STM32_USB_USB1_HP_IRQ_PRIORITY 12
228+#define STM32_USB_USB1_LP_IRQ_PRIORITY 12
229+
230+/*
217231 * WDG driver system settings.
218232 */
219233 #define STM32_WDG_USE_IWDG FALSE
--- trunk/testhal/STM32/multi/UART/cfg/stm32wb55rg_nucleo68/mcuconf.h (revision 14016)
+++ trunk/testhal/STM32/multi/UART/cfg/stm32wb55rg_nucleo68/mcuconf.h (revision 14017)
@@ -15,7 +15,7 @@
1515 */
1616
1717 /*
18- * STM32WBxx drivers configuration.
18+ * STM32WB55xx drivers configuration.
1919 * The following settings override the default settings present in
2020 * the various device driver implementation headers.
2121 * Note that the settings for each driver only have effect if the whole
@@ -42,6 +42,7 @@
4242 #define STM32_PVD_ENABLE FALSE
4343 #define STM32_PLS STM32_PLS_LEV0
4444 #define STM32_HSI16_ENABLED TRUE
45+#define STM32_HSI48_ENABLED FALSE
4546 #define STM32_LSI_ENABLED TRUE
4647 #define STM32_HSE_ENABLED TRUE
4748 #define STM32_LSE_ENABLED TRUE
@@ -57,6 +58,8 @@
5758 #define STM32_HPRE STM32_HPRE_DIV1
5859 #define STM32_PPRE1 STM32_PPRE1_DIV1
5960 #define STM32_PPRE2 STM32_PPRE2_DIV1
61+#define STM32_C2HPRE STM32_C2HPRE_DIV2
62+#define STM32_SHDHPRE STM32_SHDHPRE_DIV1
6063 #define STM32_STOPWUCK STM32_STOPWUCK_MSI
6164 #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
6265 #define STM32_MCOPRE STM32_MCOPRE_DIV1
@@ -78,7 +81,6 @@
7881 #define STM32_SAI1SEL STM32_SAI1SEL_OFF
7982 #define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
8083 #define STM32_ADCSEL STM32_ADCSEL_SYSCLK
81-#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
8284 #define STM32_RTCSEL STM32_RTCSEL_LSI
8385
8486 /*
@@ -102,6 +104,8 @@
102104 #define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7
103105 #define STM32_IRQ_TIM1_CC_PRIORITY 7
104106 #define STM32_IRQ_TIM2_PRIORITY 7
107+#define STM32_IRQ_TIM16_PRIORITY 7
108+#define STM32_IRQ_TIM17_PRIORITY 7
105109
106110 #define STM32_IRQ_USART1_PRIORITY 12
107111 #define STM32_IRQ_LPUART1_PRIORITY 12
@@ -109,16 +113,14 @@
109113 /*
110114 * ADC driver system settings.
111115 */
112-#define STM32_ADC_DUAL_MODE FALSE
113116 #define STM32_ADC_COMPACT_SAMPLES FALSE
114117 #define STM32_ADC_USE_ADC1 FALSE
115-#define STM32_ADC_USE_ADC2 FALSE
116-#define STM32_ADC_USE_ADC3 FALSE
117118 #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
118119 #define STM32_ADC_ADC1_DMA_PRIORITY 2
119120 #define STM32_ADC_ADC1_IRQ_PRIORITY 5
120121 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
121122 #define STM32_ADC_ADC1_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
123+#define STM32_ADC_ADC1_PRESC ADC_CCR_PRESC_DIV2
122124
123125 /*
124126 * GPT driver system settings.
@@ -149,8 +151,6 @@
149151 */
150152 #define STM32_ICU_USE_TIM1 FALSE
151153 #define STM32_ICU_USE_TIM2 FALSE
152-#define STM32_ICU_USE_TIM16 FALSE
153-#define STM32_ICU_USE_TIM17 FALSE
154154
155155 /*
156156 * PWM driver system settings.
@@ -178,6 +178,12 @@
178178 #define STM32_SERIAL_LPUART1_PRIORITY 12
179179
180180 /*
181+ * SIO driver system settings.
182+ */
183+#define STM32_SIO_USE_USART1 FALSE
184+#define STM32_SIO_USE_LPUART1 FALSE
185+
186+/*
181187 * SPI driver system settings.
182188 */
183189 #define STM32_SPI_USE_SPI1 FALSE
@@ -214,6 +220,14 @@
214220 #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
215221
216222 /*
223+ * USB driver system settings.
224+ */
225+#define STM32_USB_USE_USB1 FALSE
226+#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
227+#define STM32_USB_USB1_HP_IRQ_PRIORITY 12
228+#define STM32_USB_USB1_LP_IRQ_PRIORITY 12
229+
230+/*
217231 * WDG driver system settings.
218232 */
219233 #define STM32_WDG_USE_IWDG FALSE
--- trunk/testhal/STM32/multi/USB_CDC/cfg/stm32wb55rg_nucleo68/mcuconf.h (revision 14016)
+++ trunk/testhal/STM32/multi/USB_CDC/cfg/stm32wb55rg_nucleo68/mcuconf.h (revision 14017)
@@ -1,5 +1,5 @@
11 /*
2- ChibiOS - Copyright (C) 2006..2020 Ilya Kharin
2+ ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
33
44 Licensed under the Apache License, Version 2.0 (the "License");
55 you may not use this file except in compliance with the License.
@@ -15,7 +15,7 @@
1515 */
1616
1717 /*
18- * STM32WBxx drivers configuration.
18+ * STM32WB55xx drivers configuration.
1919 * The following settings override the default settings present in
2020 * the various device driver implementation headers.
2121 * Note that the settings for each driver only have effect if the whole
@@ -42,21 +42,24 @@
4242 #define STM32_PVD_ENABLE FALSE
4343 #define STM32_PLS STM32_PLS_LEV0
4444 #define STM32_HSI16_ENABLED TRUE
45-#define STM32_LSI_ENABLED TRUE
45+#define STM32_HSI48_ENABLED TRUE
46+#define STM32_LSI_ENABLED FALSE
4647 #define STM32_HSE_ENABLED FALSE
47-#define STM32_LSE_ENABLED FALSE
48-#define STM32_MSIPLL_ENABLED FALSE
48+#define STM32_LSE_ENABLED TRUE
49+#define STM32_MSIPLL_ENABLED TRUE
4950 #define STM32_MSIRANGE STM32_MSIRANGE_4M
5051 #define STM32_SW STM32_SW_PLL
5152 #define STM32_PLLSRC STM32_PLLSRC_MSI
5253 #define STM32_PLLM_VALUE 1
5354 #define STM32_PLLN_VALUE 32
54-#define STM32_PLLP_VALUE 2
55-#define STM32_PLLQ_VALUE 2
55+#define STM32_PLLP_VALUE 5
56+#define STM32_PLLQ_VALUE 4
5657 #define STM32_PLLR_VALUE 2
5758 #define STM32_HPRE STM32_HPRE_DIV1
5859 #define STM32_PPRE1 STM32_PPRE1_DIV1
5960 #define STM32_PPRE2 STM32_PPRE2_DIV1
61+#define STM32_C2HPRE STM32_C2HPRE_DIV2
62+#define STM32_SHDHPRE STM32_SHDHPRE_DIV1
6063 #define STM32_STOPWUCK STM32_STOPWUCK_MSI
6164 #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
6265 #define STM32_MCOPRE STM32_MCOPRE_DIV1
@@ -76,10 +79,9 @@
7679 #define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
7780 #define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
7881 #define STM32_SAI1SEL STM32_SAI1SEL_OFF
79-#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
80-#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
81-#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
82-#define STM32_RTCSEL STM32_RTCSEL_LSI
82+#define STM32_CLK48SEL STM32_CLK48SEL_HSI48
83+#define STM32_ADCSEL STM32_ADCSEL_NOCLK
84+#define STM32_RTCSEL STM32_RTCSEL_NOCLOCK
8385
8486 /*
8587 * IRQ system settings.
@@ -102,6 +104,8 @@
102104 #define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7
103105 #define STM32_IRQ_TIM1_CC_PRIORITY 7
104106 #define STM32_IRQ_TIM2_PRIORITY 7
107+#define STM32_IRQ_TIM16_PRIORITY 7
108+#define STM32_IRQ_TIM17_PRIORITY 7
105109
106110 #define STM32_IRQ_USART1_PRIORITY 3
107111 #define STM32_IRQ_LPUART1_PRIORITY 3
@@ -109,7 +113,6 @@
109113 /*
110114 * ADC driver system settings.
111115 */
112-#define STM32_ADC_DUAL_MODE FALSE
113116 #define STM32_ADC_COMPACT_SAMPLES FALSE
114117 #define STM32_ADC_USE_ADC1 FALSE
115118 #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
@@ -117,6 +120,7 @@
117120 #define STM32_ADC_ADC1_IRQ_PRIORITY 5
118121 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
119122 #define STM32_ADC_ADC1_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
123+#define STM32_ADC_ADC1_PRESC ADC_CCR_PRESC_DIV2
120124
121125 /*
122126 * GPT driver system settings.
@@ -174,6 +178,12 @@
174178 #define STM32_SERIAL_LPUART1_PRIORITY 12
175179
176180 /*
181+ * SIO driver system settings.
182+ */
183+#define STM32_SIO_USE_USART1 FALSE
184+#define STM32_SIO_USE_LPUART1 FALSE
185+
186+/*
177187 * SPI driver system settings.
178188 */
179189 #define STM32_SPI_USE_SPI1 FALSE
--- trunk/testhal/STM32/multi/USB_CDC/Makefile (revision 14016)
+++ trunk/testhal/STM32/multi/USB_CDC/Makefile (revision 14017)
@@ -28,7 +28,7 @@
2828 +@make --no-print-directory -f ./make/stm32h743_nucleo144.make all
2929 @echo ====================================================================
3030 @echo
31- @echo === Building for STM32WB55RG_Nucleo64 =============================
31+ @echo === Building for STM32WB55RG_Nucleo68 =============================
3232 +@make --no-print-directory -f ./make/stm32wb55rg_nucleo68.make all
3333 @echo ====================================================================
3434 @echo
--- trunk/tools/ftl/schema/boards/stm32wbxx_board.xsd (revision 14016)
+++ trunk/tools/ftl/schema/boards/stm32wbxx_board.xsd (revision 14017)
@@ -20,24 +20,24 @@
2020 </xs:element>
2121 <xs:element name="clocks" maxOccurs="1" minOccurs="1">
2222 <xs:complexType>
23- <xs:attribute name="HSEBypass" use="required">
23+ <xs:attribute name="HSEFrequency" use="required">
2424 <xs:simpleType>
25- <xs:restriction base="xs:string">
25+ <xs:restriction base="xs:int">
2626 <xs:whiteSpace value="collapse"></xs:whiteSpace>
27- <xs:enumeration value="false"></xs:enumeration>
28- <xs:enumeration value="true"></xs:enumeration>
27+ <xs:minInclusive value="0"></xs:minInclusive>
2928 </xs:restriction>
3029 </xs:simpleType>
3130 </xs:attribute>
32- <xs:attribute name="HSEFrequency" use="required">
31+ <xs:attribute name="LSEBypass" use="required">
3332 <xs:simpleType>
34- <xs:restriction base="xs:int">
35- <xs:whiteSpace value="collapse"></xs:whiteSpace>
36- <xs:minInclusive value="0"></xs:minInclusive>
33+ <xs:restriction base="xs:string">
34+ <xs:whiteSpace value="collapse">
35+ </xs:whiteSpace>
36+ <xs:enumeration value="false"></xs:enumeration>
37+ <xs:enumeration value="true"></xs:enumeration>
3738 </xs:restriction>
3839 </xs:simpleType>
39- </xs:attribute> -
40+ </xs:attribute>
4041 <xs:attribute name="LSEDrive" use="required">
4142 <xs:simpleType>
4243 <xs:restriction base="xs:string">
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