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chibios: Commit


Commit MetaInfo

Revision14146 (tree)
Time2021-04-07 21:26:38
Authorgdisirio

Log Message

Added DMA definitions.

Change Summary

Incremental Difference

--- trunk/os/common/ext/RP/RP2040/rp2040.h (revision 14145)
+++ trunk/os/common/ext/RP/RP2040/rp2040.h (revision 14146)
@@ -86,6 +86,36 @@
8686 */
8787 typedef struct {
8888 struct {
89+ __IO uint32_t READ_ADDR;
90+ __IO uint32_t WRITE_ADDR;
91+ __IO uint32_t TRANS_COUNT;
92+ __IO uint32_t CTRL_TRIG;
93+ __I uint32_t resvd10[12];
94+ } CH[12];
95+ __I uint32_t resvd300[64];
96+ __IO uint32_t INTR;
97+ struct {
98+ __IO uint32_t INTE;
99+ __IO uint32_t INTF;
100+ __IO uint32_t INTS;
101+ } C[2];
102+ __IO uint32_t TIMER[4];
103+ __IO uint32_t MULTI_CHAN_TRIGGER;
104+ __IO uint32_t SNIFF_CTRL;
105+ __IO uint32_t SNIFF_DATA;
106+ __I uint32_t FIFO_LEVELS;
107+ __IO uint32_t CHAN_ABORT;
108+ __I uint32_t N_CHANNELS;
109+ __I uint32_t resvd44C[237];
110+ struct {
111+ __I uint32_t CTDREQ;
112+ __I uint32_t TCR;
113+ __I uint32_t resvd8[56];
114+ } CH_DBG[12];
115+} DMA_TypeDef;
116+
117+typedef struct {
118+ struct {
89119 __I uint32_t STATUS;
90120 __IO uint32_t CTRL;
91121 } GPIO[30];
@@ -254,6 +284,7 @@
254284 #define __APBPERIPH_BASE 0x40000000U
255285 #define __AHBPERIPH_BASE 0x50000000U
256286 #define __IOPORT_BASE 0xD0000000U
287+#define __DMA_BASE (__APBPERIPH_BASE + 0x00000000U)
257288 #define __IOUSER0_BASE (__APBPERIPH_BASE + 0x00014000U)
258289 #define __IOQSPI_BASE (__APBPERIPH_BASE + 0x00018000U)
259290 #define __PADSUSER0_BASE (__APBPERIPH_BASE + 0x0001C000U)
@@ -270,6 +301,7 @@
270301 * @name Peripherals
271302 * @{
272303 */
304+#define DMA ((DMA_TypeDef *) __DMA_BASE)
273305 #define IO_BANK0 ((IOUSER_TypeDef *) __IOUSER0_BASE)
274306 #define IO_QSPI ((IOUSER_TypeDef *) __IOQSPI_BASE)
275307 #define PADS_BANK0 ((PADS_TypeDef *) __PADSUSER0_BASE)
@@ -283,7 +315,46 @@
283315 /** @} */
284316
285317 /**
318+ * @name DMA bits definitions
319+ * @{
320+ */
321+#define DMA_CTRL_TRIG_AHB_ERROR (1U << 31)
322+#define DMA_CTRL_TRIG_READ_ERROR (1U << 30)
323+#define DMA_CTRL_TRIG_WRITE_ERROR (1U << 29)
324+#define DMA_CTRL_TRIG_BUSY (1U << 24)
325+#define DMA_CTRL_TRIG_SNIFF_EN (1U << 23)
326+#define DMA_CTRL_TRIG_BSWAP (1U << 22)
327+#define DMA_CTRL_TRIG_IRQ_QUIET (1U << 21)
328+#define DMA_CTRL_TRIG_TREQ_SEL_Pos 15U
329+#define DMA_CTRL_TRIG_TREQ_SEL_Msk (0x3FU << DMA_CTRL_TRIG_TREQ_SEL_Pos)
330+#define DMA_CTRL_TRIG_TREQ_SEL(n) ((n) << DMA_CTRL_TRIG_TREQ_SEL_Pos)
331+#define DMA_CTRL_TRIG_TREQ_TIMER0 DMA_CTRL_TRIG_TREQ_SEL(0x3BU)
332+#define DMA_CTRL_TRIG_TREQ_TIMER1 DMA_CTRL_TRIG_TREQ_SEL(0x3CU)
333+#define DMA_CTRL_TRIG_TREQ_TIMER2 DMA_CTRL_TRIG_TREQ_SEL(0x3DU)
334+#define DMA_CTRL_TRIG_TREQ_TIMER3 DMA_CTRL_TRIG_TREQ_SEL(0x3EU)
335+#define DMA_CTRL_TRIG_TREQ_PERMANENT DMA_CTRL_TRIG_TREQ_SEL(0x3FU)
336+#define DMA_CTRL_TRIG_CHAIN_TO_Pos 11U
337+#define DMA_CTRL_TRIG_CHAIN_TO_Msk (15U << DMA_CTRL_TRIG_CHAIN_TO_Pos)
338+#define DMA_CTRL_TRIG_CHAIN_TO(n) ((n) << DMA_CTRL_TRIG_CHAIN_TO_Pos)
339+#define DMA_CTRL_TRIG_RING_SEL (1U << 10)
340+#define DMA_CTRL_TRIG_RING_SIZE_Pos 6U
341+#define DMA_CTRL_TRIG_RING_SIZE_Msk (15U << DMA_CTRL_TRIG_RING_SIZE_Pos)
342+#define DMA_CTRL_TRIG_RING_SIZE(n) ((n) << DMA_CTRL_TRIG_RING_SIZE_Pos)
343+#define DMA_CTRL_TRIG_INCR_WRITE (1U << 5)
344+#define DMA_CTRL_TRIG_INCR_READ (1U << 4)
345+#define DMA_CTRL_TRIG_DATA_SIZE_Pos 2U
346+#define DMA_CTRL_TRIG_DATA_SIZE_Msk (3U << DMA_CTRL_TRIG_DATA_SIZE_Pos)
347+#define DMA_CTRL_TRIG_DATA_SIZE(n) ((n) << DMA_CTRL_TRIG_DATA_SIZE_Pos)
348+#define DMA_CTRL_TRIG_DATA_SIZE_BYTE DMA_CTRL_TRIG_DATA_SIZE(0U)
349+#define DMA_CTRL_TRIG_DATA_SIZE_HWORD DMA_CTRL_TRIG_DATA_SIZE(1U)
350+#define DMA_CTRL_TRIG_DATA_SIZE_WORD DMA_CTRL_TRIG_DATA_SIZE(2U)
351+#define DMA_CTRL_TRIG_HIGH_PRIORITY (1U << 1)
352+#define DMA_CTRL_TRIG_EN (1U << 0)
353+/** @} */
354+
355+/**
286356 * @name RESETS bits definitions
357+ * @{
287358 */
288359 #define RESETS_ALLREG_USBCTRL (1U << 24)
289360 #define RESETS_ALLREG_UART1 (1U << 23)
@@ -314,6 +385,7 @@
314385
315386 /**
316387 * @name SIO bits definitions
388+ * @{
317389 */
318390 #define SIO_FIFO_ST_VLD_Pos 0U
319391 #define SIO_FIFO_ST_VLD_Msk (1U << SIO_FIFO_ST_VLD_Pos)
@@ -331,6 +403,7 @@
331403
332404 /**
333405 * @name TIMER bits definitions
406+ * @{
334407 */
335408 #define TIMER_ARMED_ALARM0_Pos 0U
336409 #define TIMER_ARMED_ALARM0_Msk (1U << TIMER_ARMED_ALARM0_Pos)
@@ -411,6 +484,7 @@
411484
412485 /**
413486 * @name UART bits definitions
487+ * @{
414488 */
415489 #define UART_UARTDR_OE_Pos 11U
416490 #define UART_UARTDR_OE_Msk (1U << UART_UARTDR_OE_Pos)
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