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chibios: Commit


Commit MetaInfo

Revision14148 (tree)
Time2021-04-08 14:50:22
Authorcinsights

Log Message

Add RP RTC bit definitions + driver WIP

Change Summary

Incremental Difference

--- trunk/os/common/ext/RP/RP2040/rp2040.h (revision 14147)
+++ trunk/os/common/ext/RP/RP2040/rp2040.h (revision 14148)
@@ -281,20 +281,20 @@
281281 * @name Base addresses
282282 * @{
283283 */
284-#define __APBPERIPH_BASE 0x40000000U
285-#define __AHBPERIPH_BASE 0x50000000U
286-#define __IOPORT_BASE 0xD0000000U
287-#define __DMA_BASE (__APBPERIPH_BASE + 0x00000000U)
288-#define __IOUSER0_BASE (__APBPERIPH_BASE + 0x00014000U)
289-#define __IOQSPI_BASE (__APBPERIPH_BASE + 0x00018000U)
290-#define __PADSUSER0_BASE (__APBPERIPH_BASE + 0x0001C000U)
291-#define __PADSQSPI_BASE (__APBPERIPH_BASE + 0x00020000U)
292-#define __RESETS_BASE (__APBPERIPH_BASE + 0x0000C000U)
293-#define __TIMER_BASE (__APBPERIPH_BASE + 0x00054000U)
294-#define __UART0_BASE (__APBPERIPH_BASE + 0x00034000U)
295-#define __UART1_BASE (__APBPERIPH_BASE + 0x00038000U)
296-#define __SIO_BASE (__IOPORT_BASE + 0x00000000U)
297-#define __RTC_BASE (__APBPERIPH_BASE + 0x0005c000U)
284+#define __APBPERIPH_BASE 0x40000000U
285+#define __AHBPERIPH_BASE 0x50000000U
286+#define __IOPORT_BASE 0xD0000000U
287+#define __DMA_BASE (__APBPERIPH_BASE + 0x00000000U)
288+#define __IOUSER0_BASE (__APBPERIPH_BASE + 0x00014000U)
289+#define __IOQSPI_BASE (__APBPERIPH_BASE + 0x00018000U)
290+#define __PADSUSER0_BASE (__APBPERIPH_BASE + 0x0001C000U)
291+#define __PADSQSPI_BASE (__APBPERIPH_BASE + 0x00020000U)
292+#define __RESETS_BASE (__APBPERIPH_BASE + 0x0000C000U)
293+#define __TIMER_BASE (__APBPERIPH_BASE + 0x00054000U)
294+#define __UART0_BASE (__APBPERIPH_BASE + 0x00034000U)
295+#define __UART1_BASE (__APBPERIPH_BASE + 0x00038000U)
296+#define __SIO_BASE (__IOPORT_BASE + 0x00000000U)
297+#define __RTC_BASE (__APBPERIPH_BASE + 0x0005C000U)
298298 /** @} */
299299
300300 /**
@@ -301,17 +301,17 @@
301301 * @name Peripherals
302302 * @{
303303 */
304-#define DMA ((DMA_TypeDef *) __DMA_BASE)
305-#define IO_BANK0 ((IOUSER_TypeDef *) __IOUSER0_BASE)
306-#define IO_QSPI ((IOUSER_TypeDef *) __IOQSPI_BASE)
307-#define PADS_BANK0 ((PADS_TypeDef *) __PADSUSER0_BASE)
308-#define PADS_QSPI ((PADS_TypeDef *) __PADSQSPI_BASE)
309-#define RESETS ((RESETS_TypeDef *) __RESETS_BASE)
310-#define SIO ((SIO_TypeDef *) __SIO_BASE)
311-#define TIMER ((TIMER_TypeDef *) __TIMER_BASE)
312-#define UART0 ((UART_TypeDef *) __UART0_BASE)
313-#define UART1 ((UART_TypeDef *) __UART1_BASE)
314-#define RTC ((RTC_TypeDef *) __RTC_BASE)
304+#define DMA ((DMA_TypeDef *) __DMA_BASE)
305+#define IO_BANK0 ((IOUSER_TypeDef *) __IOUSER0_BASE)
306+#define IO_QSPI ((IOUSER_TypeDef *) __IOQSPI_BASE)
307+#define PADS_BANK0 ((PADS_TypeDef *) __PADSUSER0_BASE)
308+#define PADS_QSPI ((PADS_TypeDef *) __PADSQSPI_BASE)
309+#define RESETS ((RESETS_TypeDef *) __RESETS_BASE)
310+#define SIO ((SIO_TypeDef *) __SIO_BASE)
311+#define TIMER ((TIMER_TypeDef *) __TIMER_BASE)
312+#define UART0 ((UART_TypeDef *) __UART0_BASE)
313+#define UART1 ((UART_TypeDef *) __UART1_BASE)
314+#define RTC ((RTC_TypeDef *) __RTC_BASE)
315315 /** @} */
316316
317317 /**
@@ -318,38 +318,38 @@
318318 * @name DMA bits definitions
319319 * @{
320320 */
321-#define DMA_CTRL_TRIG_AHB_ERROR (1U << 31)
322-#define DMA_CTRL_TRIG_READ_ERROR (1U << 30)
323-#define DMA_CTRL_TRIG_WRITE_ERROR (1U << 29)
324-#define DMA_CTRL_TRIG_BUSY (1U << 24)
325-#define DMA_CTRL_TRIG_SNIFF_EN (1U << 23)
326-#define DMA_CTRL_TRIG_BSWAP (1U << 22)
327-#define DMA_CTRL_TRIG_IRQ_QUIET (1U << 21)
328-#define DMA_CTRL_TRIG_TREQ_SEL_Pos 15U
329-#define DMA_CTRL_TRIG_TREQ_SEL_Msk (0x3FU << DMA_CTRL_TRIG_TREQ_SEL_Pos)
330-#define DMA_CTRL_TRIG_TREQ_SEL(n) ((n) << DMA_CTRL_TRIG_TREQ_SEL_Pos)
331-#define DMA_CTRL_TRIG_TREQ_TIMER0 DMA_CTRL_TRIG_TREQ_SEL(0x3BU)
332-#define DMA_CTRL_TRIG_TREQ_TIMER1 DMA_CTRL_TRIG_TREQ_SEL(0x3CU)
333-#define DMA_CTRL_TRIG_TREQ_TIMER2 DMA_CTRL_TRIG_TREQ_SEL(0x3DU)
334-#define DMA_CTRL_TRIG_TREQ_TIMER3 DMA_CTRL_TRIG_TREQ_SEL(0x3EU)
335-#define DMA_CTRL_TRIG_TREQ_PERMANENT DMA_CTRL_TRIG_TREQ_SEL(0x3FU)
336-#define DMA_CTRL_TRIG_CHAIN_TO_Pos 11U
337-#define DMA_CTRL_TRIG_CHAIN_TO_Msk (15U << DMA_CTRL_TRIG_CHAIN_TO_Pos)
338-#define DMA_CTRL_TRIG_CHAIN_TO(n) ((n) << DMA_CTRL_TRIG_CHAIN_TO_Pos)
339-#define DMA_CTRL_TRIG_RING_SEL (1U << 10)
340-#define DMA_CTRL_TRIG_RING_SIZE_Pos 6U
341-#define DMA_CTRL_TRIG_RING_SIZE_Msk (15U << DMA_CTRL_TRIG_RING_SIZE_Pos)
342-#define DMA_CTRL_TRIG_RING_SIZE(n) ((n) << DMA_CTRL_TRIG_RING_SIZE_Pos)
343-#define DMA_CTRL_TRIG_INCR_WRITE (1U << 5)
344-#define DMA_CTRL_TRIG_INCR_READ (1U << 4)
345-#define DMA_CTRL_TRIG_DATA_SIZE_Pos 2U
346-#define DMA_CTRL_TRIG_DATA_SIZE_Msk (3U << DMA_CTRL_TRIG_DATA_SIZE_Pos)
347-#define DMA_CTRL_TRIG_DATA_SIZE(n) ((n) << DMA_CTRL_TRIG_DATA_SIZE_Pos)
348-#define DMA_CTRL_TRIG_DATA_SIZE_BYTE DMA_CTRL_TRIG_DATA_SIZE(0U)
349-#define DMA_CTRL_TRIG_DATA_SIZE_HWORD DMA_CTRL_TRIG_DATA_SIZE(1U)
350-#define DMA_CTRL_TRIG_DATA_SIZE_WORD DMA_CTRL_TRIG_DATA_SIZE(2U)
351-#define DMA_CTRL_TRIG_HIGH_PRIORITY (1U << 1)
352-#define DMA_CTRL_TRIG_EN (1U << 0)
321+#define DMA_CTRL_TRIG_AHB_ERROR (1U << 31)
322+#define DMA_CTRL_TRIG_READ_ERROR (1U << 30)
323+#define DMA_CTRL_TRIG_WRITE_ERROR (1U << 29)
324+#define DMA_CTRL_TRIG_BUSY (1U << 24)
325+#define DMA_CTRL_TRIG_SNIFF_EN (1U << 23)
326+#define DMA_CTRL_TRIG_BSWAP (1U << 22)
327+#define DMA_CTRL_TRIG_IRQ_QUIET (1U << 21)
328+#define DMA_CTRL_TRIG_TREQ_SEL_Pos 15U
329+#define DMA_CTRL_TRIG_TREQ_SEL_Msk (0x3FU << DMA_CTRL_TRIG_TREQ_SEL_Pos)
330+#define DMA_CTRL_TRIG_TREQ_SEL(n) ((n) << DMA_CTRL_TRIG_TREQ_SEL_Pos)
331+#define DMA_CTRL_TRIG_TREQ_TIMER0 DMA_CTRL_TRIG_TREQ_SEL(0x3BU)
332+#define DMA_CTRL_TRIG_TREQ_TIMER1 DMA_CTRL_TRIG_TREQ_SEL(0x3CU)
333+#define DMA_CTRL_TRIG_TREQ_TIMER2 DMA_CTRL_TRIG_TREQ_SEL(0x3DU)
334+#define DMA_CTRL_TRIG_TREQ_TIMER3 DMA_CTRL_TRIG_TREQ_SEL(0x3EU)
335+#define DMA_CTRL_TRIG_TREQ_PERMANENT DMA_CTRL_TRIG_TREQ_SEL(0x3FU)
336+#define DMA_CTRL_TRIG_CHAIN_TO_Pos 11U
337+#define DMA_CTRL_TRIG_CHAIN_TO_Msk (15U << DMA_CTRL_TRIG_CHAIN_TO_Pos)
338+#define DMA_CTRL_TRIG_CHAIN_TO(n) ((n) << DMA_CTRL_TRIG_CHAIN_TO_Pos)
339+#define DMA_CTRL_TRIG_RING_SEL (1U << 10)
340+#define DMA_CTRL_TRIG_RING_SIZE_Pos 6U
341+#define DMA_CTRL_TRIG_RING_SIZE_Msk (15U << DMA_CTRL_TRIG_RING_SIZE_Pos)
342+#define DMA_CTRL_TRIG_RING_SIZE(n) ((n) << DMA_CTRL_TRIG_RING_SIZE_Pos)
343+#define DMA_CTRL_TRIG_INCR_WRITE (1U << 5)
344+#define DMA_CTRL_TRIG_INCR_READ (1U << 4)
345+#define DMA_CTRL_TRIG_DATA_SIZE_Pos 2U
346+#define DMA_CTRL_TRIG_DATA_SIZE_Msk (3U << DMA_CTRL_TRIG_DATA_SIZE_Pos)
347+#define DMA_CTRL_TRIG_DATA_SIZE(n) ((n) << DMA_CTRL_TRIG_DATA_SIZE_Pos)
348+#define DMA_CTRL_TRIG_DATA_SIZE_BYTE DMA_CTRL_TRIG_DATA_SIZE(0U)
349+#define DMA_CTRL_TRIG_DATA_SIZE_HWORD DMA_CTRL_TRIG_DATA_SIZE(1U)
350+#define DMA_CTRL_TRIG_DATA_SIZE_WORD DMA_CTRL_TRIG_DATA_SIZE(2U)
351+#define DMA_CTRL_TRIG_HIGH_PRIORITY (1U << 1)
352+#define DMA_CTRL_TRIG_EN (1U << 0)
353353 /** @} */
354354
355355 /**
@@ -356,31 +356,31 @@
356356 * @name RESETS bits definitions
357357 * @{
358358 */
359-#define RESETS_ALLREG_USBCTRL (1U << 24)
360-#define RESETS_ALLREG_UART1 (1U << 23)
361-#define RESETS_ALLREG_UART0 (1U << 22)
362-#define RESETS_ALLREG_TIMER (1U << 21)
363-#define RESETS_ALLREG_TBMAN (1U << 20)
364-#define RESETS_ALLREG_SYSINFO (1U << 19)
365-#define RESETS_ALLREG_SYSCFG (1U << 18)
366-#define RESETS_ALLREG_SPI1 (1U << 17)
367-#define RESETS_ALLREG_SPI0 (1U << 16)
368-#define RESETS_ALLREG_RTC (1U << 15)
369-#define RESETS_ALLREG_PWM (1U << 14)
370-#define RESETS_ALLREG_PLL_USB (1U << 13)
371-#define RESETS_ALLREG_PLL_SYS (1U << 12)
372-#define RESETS_ALLREG_PIO1 (1U << 11)
373-#define RESETS_ALLREG_PIO0 (1U << 10)
374-#define RESETS_ALLREG_PADS_QSPI (1U << 9)
375-#define RESETS_ALLREG_PADS_BANK0 (1U << 8)
376-#define RESETS_ALLREG_JTAG (1U << 7)
377-#define RESETS_ALLREG_IO_QSPI (1U << 6)
378-#define RESETS_ALLREG_IO_BANK0 (1U << 5)
379-#define RESETS_ALLREG_I2C1 (1U << 4)
380-#define RESETS_ALLREG_I2C0 (1U << 3)
381-#define RESETS_ALLREG_DMA (1U << 2)
382-#define RESETS_ALLREG_BUSCTRL (1U << 1)
383-#define RESETS_ALLREG_ADC (1U << 0)
359+#define RESETS_ALLREG_USBCTRL (1U << 24)
360+#define RESETS_ALLREG_UART1 (1U << 23)
361+#define RESETS_ALLREG_UART0 (1U << 22)
362+#define RESETS_ALLREG_TIMER (1U << 21)
363+#define RESETS_ALLREG_TBMAN (1U << 20)
364+#define RESETS_ALLREG_SYSINFO (1U << 19)
365+#define RESETS_ALLREG_SYSCFG (1U << 18)
366+#define RESETS_ALLREG_SPI1 (1U << 17)
367+#define RESETS_ALLREG_SPI0 (1U << 16)
368+#define RESETS_ALLREG_RTC (1U << 15)
369+#define RESETS_ALLREG_PWM (1U << 14)
370+#define RESETS_ALLREG_PLL_USB (1U << 13)
371+#define RESETS_ALLREG_PLL_SYS (1U << 12)
372+#define RESETS_ALLREG_PIO1 (1U << 11)
373+#define RESETS_ALLREG_PIO0 (1U << 10)
374+#define RESETS_ALLREG_PADS_QSPI (1U << 9)
375+#define RESETS_ALLREG_PADS_BANK0 (1U << 8)
376+#define RESETS_ALLREG_JTAG (1U << 7)
377+#define RESETS_ALLREG_IO_QSPI (1U << 6)
378+#define RESETS_ALLREG_IO_BANK0 (1U << 5)
379+#define RESETS_ALLREG_I2C1 (1U << 4)
380+#define RESETS_ALLREG_I2C0 (1U << 3)
381+#define RESETS_ALLREG_DMA (1U << 2)
382+#define RESETS_ALLREG_BUSCTRL (1U << 1)
383+#define RESETS_ALLREG_ADC (1U << 0)
384384 /** @} */
385385
386386 /**
@@ -387,18 +387,18 @@
387387 * @name SIO bits definitions
388388 * @{
389389 */
390-#define SIO_FIFO_ST_VLD_Pos 0U
391-#define SIO_FIFO_ST_VLD_Msk (1U << SIO_FIFO_ST_VLD_Pos)
392-#define SIO_FIFO_ST_VLD SIO_FIFO_ST_VLD_Msk
393-#define SIO_FIFO_ST_RDY_Pos 1U
394-#define SIO_FIFO_ST_RDY_Msk (1U << SIO_FIFO_ST_RDY_Pos)
395-#define SIO_FIFO_ST_RDY SIO_FIFO_ST_RDY_Msk
396-#define SIO_FIFO_ST_WOF_Pos 2U
397-#define SIO_FIFO_ST_WOF_Msk (1U << SIO_FIFO_ST_WOF_Pos)
398-#define SIO_FIFO_ST_WOF SIO_FIFO_ST_WOF_Msk
399-#define SIO_FIFO_ST_ROE_Pos 3U
400-#define SIO_FIFO_ST_ROE_Msk (1U << SIO_FIFO_ST_ROE_Pos)
401-#define SIO_FIFO_ST_ROE SIO_FIFO_ST_ROE_Msk
390+#define SIO_FIFO_ST_VLD_Pos 0U
391+#define SIO_FIFO_ST_VLD_Msk (1U << SIO_FIFO_ST_VLD_Pos)
392+#define SIO_FIFO_ST_VLD SIO_FIFO_ST_VLD_Msk
393+#define SIO_FIFO_ST_RDY_Pos 1U
394+#define SIO_FIFO_ST_RDY_Msk (1U << SIO_FIFO_ST_RDY_Pos)
395+#define SIO_FIFO_ST_RDY SIO_FIFO_ST_RDY_Msk
396+#define SIO_FIFO_ST_WOF_Pos 2U
397+#define SIO_FIFO_ST_WOF_Msk (1U << SIO_FIFO_ST_WOF_Pos)
398+#define SIO_FIFO_ST_WOF SIO_FIFO_ST_WOF_Msk
399+#define SIO_FIFO_ST_ROE_Pos 3U
400+#define SIO_FIFO_ST_ROE_Msk (1U << SIO_FIFO_ST_ROE_Pos)
401+#define SIO_FIFO_ST_ROE SIO_FIFO_ST_ROE_Msk
402402 /** @} */
403403
404404 /**
@@ -405,81 +405,81 @@
405405 * @name TIMER bits definitions
406406 * @{
407407 */
408-#define TIMER_ARMED_ALARM0_Pos 0U
409-#define TIMER_ARMED_ALARM0_Msk (1U << TIMER_ARMED_ALARM0_Pos)
410-#define TIMER_ARMED_ALARM0 TIMER_ARMED_ALARM0_Msk
411-#define TIMER_ARMED_ALARM1_Pos 1U
412-#define TIMER_ARMED_ALARM1_Msk (1U << TIMER_ARMED_ALARM1_Pos)
413-#define TIMER_ARMED_ALARM1 TIMER_ARMED_ALARM1_Msk
414-#define TIMER_ARMED_ALARM2_Pos 2U
415-#define TIMER_ARMED_ALARM2_Msk (1U << TIMER_ARMED_ALARM2_Pos)
416-#define TIMER_ARMED_ALARM2 TIMER_ARMED_ALARM2_Msk
417-#define TIMER_ARMED_ALARM3_Pos 3U
418-#define TIMER_ARMED_ALARM3_Msk (1U << TIMER_ARMED_ALARM3_Pos)
419-#define TIMER_ARMED_ALARM3 TIMER_ARMED_ALARM3_Msk
408+#define TIMER_ARMED_ALARM0_Pos 0U
409+#define TIMER_ARMED_ALARM0_Msk (1U << TIMER_ARMED_ALARM0_Pos)
410+#define TIMER_ARMED_ALARM0 TIMER_ARMED_ALARM0_Msk
411+#define TIMER_ARMED_ALARM1_Pos 1U
412+#define TIMER_ARMED_ALARM1_Msk (1U << TIMER_ARMED_ALARM1_Pos)
413+#define TIMER_ARMED_ALARM1 TIMER_ARMED_ALARM1_Msk
414+#define TIMER_ARMED_ALARM2_Pos 2U
415+#define TIMER_ARMED_ALARM2_Msk (1U << TIMER_ARMED_ALARM2_Pos)
416+#define TIMER_ARMED_ALARM2 TIMER_ARMED_ALARM2_Msk
417+#define TIMER_ARMED_ALARM3_Pos 3U
418+#define TIMER_ARMED_ALARM3_Msk (1U << TIMER_ARMED_ALARM3_Pos)
419+#define TIMER_ARMED_ALARM3 TIMER_ARMED_ALARM3_Msk
420420
421-#define TIMER_DBGPAUSE_DBG0_Pos 1U
422-#define TIMER_DBGPAUSE_DBG0_Msk (1U << TIMER_DBGPAUSE_DBG0_Pos)
423-#define TIMER_DBGPAUSE_DBG0 TIMER_DBGPAUSE_DBG0_Msk
424-#define TIMER_DBGPAUSE_DBG1_Pos 2U
425-#define TIMER_DBGPAUSE_DBG1_Msk (1U << TIMER_DBGPAUSE_DBG1_Pos)
426-#define TIMER_DBGPAUSE_DBG1 TIMER_DBGPAUSE_DBG1_Msk
421+#define TIMER_DBGPAUSE_DBG0_Pos 1U
422+#define TIMER_DBGPAUSE_DBG0_Msk (1U << TIMER_DBGPAUSE_DBG0_Pos)
423+#define TIMER_DBGPAUSE_DBG0 TIMER_DBGPAUSE_DBG0_Msk
424+#define TIMER_DBGPAUSE_DBG1_Pos 2U
425+#define TIMER_DBGPAUSE_DBG1_Msk (1U << TIMER_DBGPAUSE_DBG1_Pos)
426+#define TIMER_DBGPAUSE_DBG1 TIMER_DBGPAUSE_DBG1_Msk
427427
428-#define TIMER_PAUSE_PAUSE_Pos 0U
429-#define TIMER_PAUSE_PAUSE_Msk (1U << TIMER_PAUSE_PAUSE_Pos)
430-#define TIMER_PAUSE_PAUSE TIMER_PAUSE_PAUSE_Msk
428+#define TIMER_PAUSE_PAUSE_Pos 0U
429+#define TIMER_PAUSE_PAUSE_Msk (1U << TIMER_PAUSE_PAUSE_Pos)
430+#define TIMER_PAUSE_PAUSE TIMER_PAUSE_PAUSE_Msk
431431
432-#define TIMER_INTR_ALARM0_Pos 0U
433-#define TIMER_INTR_ALARM0_Msk (1U << TIMER_INTR_ALARM0_Pos)
434-#define TIMER_INTR_ALARM0 TIMER_INTR_ALARM0_Msk
435-#define TIMER_INTR_ALARM1_Pos 1U
436-#define TIMER_INTR_ALARM1_Msk (1U << TIMER_INTR_ALARM1_Pos)
437-#define TIMER_INTR_ALARM1 TIMER_INTR_ALARM1_Msk
438-#define TIMER_INTR_ALARM2_Pos 2U
439-#define TIMER_INTR_ALARM2_Msk (1U << TIMER_INTR_ALARM2_Pos)
440-#define TIMER_INTR_ALARM2 TIMER_INTR_ALARM2_Msk
441-#define TIMER_INTR_ALARM3_Pos 3U
442-#define TIMER_INTR_ALARM3_Msk (1U << TIMER_INTR_ALARM3_Pos)
443-#define TIMER_INTR_ALARM3 TIMER_INTR_ALARM3_Msk
432+#define TIMER_INTR_ALARM0_Pos 0U
433+#define TIMER_INTR_ALARM0_Msk (1U << TIMER_INTR_ALARM0_Pos)
434+#define TIMER_INTR_ALARM0 TIMER_INTR_ALARM0_Msk
435+#define TIMER_INTR_ALARM1_Pos 1U
436+#define TIMER_INTR_ALARM1_Msk (1U << TIMER_INTR_ALARM1_Pos)
437+#define TIMER_INTR_ALARM1 TIMER_INTR_ALARM1_Msk
438+#define TIMER_INTR_ALARM2_Pos 2U
439+#define TIMER_INTR_ALARM2_Msk (1U << TIMER_INTR_ALARM2_Pos)
440+#define TIMER_INTR_ALARM2 TIMER_INTR_ALARM2_Msk
441+#define TIMER_INTR_ALARM3_Pos 3U
442+#define TIMER_INTR_ALARM3_Msk (1U << TIMER_INTR_ALARM3_Pos)
443+#define TIMER_INTR_ALARM3 TIMER_INTR_ALARM3_Msk
444444
445-#define TIMER_INTE_ALARM0_Pos 0U
446-#define TIMER_INTE_ALARM0_Msk (1U << TIMER_INTE_ALARM0_Pos)
447-#define TIMER_INTE_ALARM0 TIMER_INTE_ALARM0_Msk
448-#define TIMER_INTE_ALARM1_Pos 1U
449-#define TIMER_INTE_ALARM1_Msk (1U << TIMER_INTE_ALARM1_Pos)
450-#define TIMER_INTE_ALARM1 TIMER_INTE_ALARM1_Msk
451-#define TIMER_INTE_ALARM2_Pos 2U
452-#define TIMER_INTE_ALARM2_Msk (1U << TIMER_INTE_ALARM2_Pos)
453-#define TIMER_INTE_ALARM2 TIMER_INTE_ALARM2_Msk
454-#define TIMER_INTE_ALARM3_Pos 3U
455-#define TIMER_INTE_ALARM3_Msk (1U << TIMER_INTE_ALARM3_Pos)
456-#define TIMER_INTE_ALARM3 TIMER_INTE_ALARM3_Msk
445+#define TIMER_INTE_ALARM0_Pos 0U
446+#define TIMER_INTE_ALARM0_Msk (1U << TIMER_INTE_ALARM0_Pos)
447+#define TIMER_INTE_ALARM0 TIMER_INTE_ALARM0_Msk
448+#define TIMER_INTE_ALARM1_Pos 1U
449+#define TIMER_INTE_ALARM1_Msk (1U << TIMER_INTE_ALARM1_Pos)
450+#define TIMER_INTE_ALARM1 TIMER_INTE_ALARM1_Msk
451+#define TIMER_INTE_ALARM2_Pos 2U
452+#define TIMER_INTE_ALARM2_Msk (1U << TIMER_INTE_ALARM2_Pos)
453+#define TIMER_INTE_ALARM2 TIMER_INTE_ALARM2_Msk
454+#define TIMER_INTE_ALARM3_Pos 3U
455+#define TIMER_INTE_ALARM3_Msk (1U << TIMER_INTE_ALARM3_Pos)
456+#define TIMER_INTE_ALARM3 TIMER_INTE_ALARM3_Msk
457457
458-#define TIMER_INTF_ALARM0_Pos 0U
459-#define TIMER_INTF_ALARM0_Msk (1U << TIMER_INTF_ALARM0_Pos)
460-#define TIMER_INTF_ALARM0 TIMER_INTF_ALARM0_Msk
461-#define TIMER_INTF_ALARM1_Pos 1U
462-#define TIMER_INTF_ALARM1_Msk (1U << TIMER_INTF_ALARM1_Pos)
463-#define TIMER_INTF_ALARM1 TIMER_INTF_ALARM1_Msk
464-#define TIMER_INTF_ALARM2_Pos 2U
465-#define TIMER_INTF_ALARM2_Msk (1U << TIMER_INTF_ALARM2_Pos)
466-#define TIMER_INTF_ALARM2 TIMER_INTF_ALARM2_Msk
467-#define TIMER_INTF_ALARM3_Pos 3U
468-#define TIMER_INTF_ALARM3_Msk (1U << TIMER_INTF_ALARM3_Pos)
469-#define TIMER_INTF_ALARM3 TIMER_INTF_ALARM3_Msk
458+#define TIMER_INTF_ALARM0_Pos 0U
459+#define TIMER_INTF_ALARM0_Msk (1U << TIMER_INTF_ALARM0_Pos)
460+#define TIMER_INTF_ALARM0 TIMER_INTF_ALARM0_Msk
461+#define TIMER_INTF_ALARM1_Pos 1U
462+#define TIMER_INTF_ALARM1_Msk (1U << TIMER_INTF_ALARM1_Pos)
463+#define TIMER_INTF_ALARM1 TIMER_INTF_ALARM1_Msk
464+#define TIMER_INTF_ALARM2_Pos 2U
465+#define TIMER_INTF_ALARM2_Msk (1U << TIMER_INTF_ALARM2_Pos)
466+#define TIMER_INTF_ALARM2 TIMER_INTF_ALARM2_Msk
467+#define TIMER_INTF_ALARM3_Pos 3U
468+#define TIMER_INTF_ALARM3_Msk (1U << TIMER_INTF_ALARM3_Pos)
469+#define TIMER_INTF_ALARM3 TIMER_INTF_ALARM3_Msk
470470
471-#define TIMER_INTS_ALARM0_Pos 0U
472-#define TIMER_INTS_ALARM0_Msk (1U << TIMER_INTS_ALARM0_Pos)
473-#define TIMER_INTS_ALARM0 TIMER_INTS_ALARM0_Msk
474-#define TIMER_INTS_ALARM1_Pos 1U
475-#define TIMER_INTS_ALARM1_Msk (1U << TIMER_INTS_ALARM1_Pos)
476-#define TIMER_INTS_ALARM1 TIMER_INTS_ALARM1_Msk
477-#define TIMER_INTS_ALARM2_Pos 2U
478-#define TIMER_INTS_ALARM2_Msk (1U << TIMER_INTS_ALARM2_Pos)
479-#define TIMER_INTS_ALARM2 TIMER_INTS_ALARM2_Msk
480-#define TIMER_INTS_ALARM3_Pos 3U
481-#define TIMER_INTS_ALARM3_Msk (1U << TIMER_INTS_ALARM3_Pos)
482-#define TIMER_INTS_ALARM3 TIMER_INTS_ALARM3_Msk
471+#define TIMER_INTS_ALARM0_Pos 0U
472+#define TIMER_INTS_ALARM0_Msk (1U << TIMER_INTS_ALARM0_Pos)
473+#define TIMER_INTS_ALARM0 TIMER_INTS_ALARM0_Msk
474+#define TIMER_INTS_ALARM1_Pos 1U
475+#define TIMER_INTS_ALARM1_Msk (1U << TIMER_INTS_ALARM1_Pos)
476+#define TIMER_INTS_ALARM1 TIMER_INTS_ALARM1_Msk
477+#define TIMER_INTS_ALARM2_Pos 2U
478+#define TIMER_INTS_ALARM2_Msk (1U << TIMER_INTS_ALARM2_Pos)
479+#define TIMER_INTS_ALARM2 TIMER_INTS_ALARM2_Msk
480+#define TIMER_INTS_ALARM3_Pos 3U
481+#define TIMER_INTS_ALARM3_Msk (1U << TIMER_INTS_ALARM3_Pos)
482+#define TIMER_INTS_ALARM3 TIMER_INTS_ALARM3_Msk
483483 /** @} */
484484
485485 /**
@@ -486,300 +486,446 @@
486486 * @name UART bits definitions
487487 * @{
488488 */
489-#define UART_UARTDR_OE_Pos 11U
490-#define UART_UARTDR_OE_Msk (1U << UART_UARTDR_OE_Pos)
491-#define UART_UARTDR_OE UART_UARTDR_OE_Msk
492-#define UART_UARTDR_BE_Pos 10U
493-#define UART_UARTDR_BE_Msk (1U << UART_UARTDR_BE_Pos)
494-#define UART_UARTDR_BE UART_UARTDR_BE_Msk
495-#define UART_UARTDR_PE_Pos 9U
496-#define UART_UARTDR_PE_Msk (1U << UART_UARTDR_PE_Pos)
497-#define UART_UARTDR_PE UART_UARTDR_PE_Msk
498-#define UART_UARTDR_FE_Pos 8U
499-#define UART_UARTDR_FE_Msk (1U << UART_UARTDR_FE_Pos)
500-#define UART_UARTDR_FE UART_UARTDR_FE_Msk
489+#define UART_UARTDR_OE_Pos 11U
490+#define UART_UARTDR_OE_Msk (1U << UART_UARTDR_OE_Pos)
491+#define UART_UARTDR_OE UART_UARTDR_OE_Msk
492+#define UART_UARTDR_BE_Pos 10U
493+#define UART_UARTDR_BE_Msk (1U << UART_UARTDR_BE_Pos)
494+#define UART_UARTDR_BE UART_UARTDR_BE_Msk
495+#define UART_UARTDR_PE_Pos 9U
496+#define UART_UARTDR_PE_Msk (1U << UART_UARTDR_PE_Pos)
497+#define UART_UARTDR_PE UART_UARTDR_PE_Msk
498+#define UART_UARTDR_FE_Pos 8U
499+#define UART_UARTDR_FE_Msk (1U << UART_UARTDR_FE_Pos)
500+#define UART_UARTDR_FE UART_UARTDR_FE_Msk
501501
502-#define UART_UARTRSR_OE_Pos 3U
503-#define UART_UARTRSR_OE_Msk (1U << UART_UARTRSR_OE_Pos)
504-#define UART_UARTRSR_OE UART_UARTRSR_OE_Msk
505-#define UART_UARTRSR_BE_Pos 2U
506-#define UART_UARTRSR_BE_Msk (1U << UART_UARTRSR_BE_Pos)
507-#define UART_UARTRSR_BE UART_UARTRSR_BE_Msk
508-#define UART_UARTRSR_PE_Pos 1U
509-#define UART_UARTRSR_PE_Msk (1U << UART_UARTRSR_PE_Pos)
510-#define UART_UARTRSR_PE UART_UARTRSR_PE_Msk
511-#define UART_UARTRSR_FE_Pos 0U
512-#define UART_UARTRSR_FE_Msk (1U << UART_UARTRSR_FE_Pos)
513-#define UART_UARTRSR_FE UART_UARTRSR_FE_Msk
502+#define UART_UARTRSR_OE_Pos 3U
503+#define UART_UARTRSR_OE_Msk (1U << UART_UARTRSR_OE_Pos)
504+#define UART_UARTRSR_OE UART_UARTRSR_OE_Msk
505+#define UART_UARTRSR_BE_Pos 2U
506+#define UART_UARTRSR_BE_Msk (1U << UART_UARTRSR_BE_Pos)
507+#define UART_UARTRSR_BE UART_UARTRSR_BE_Msk
508+#define UART_UARTRSR_PE_Pos 1U
509+#define UART_UARTRSR_PE_Msk (1U << UART_UARTRSR_PE_Pos)
510+#define UART_UARTRSR_PE UART_UARTRSR_PE_Msk
511+#define UART_UARTRSR_FE_Pos 0U
512+#define UART_UARTRSR_FE_Msk (1U << UART_UARTRSR_FE_Pos)
513+#define UART_UARTRSR_FE UART_UARTRSR_FE_Msk
514514
515-#define UART_UARTFR_RI_Pos 8U
516-#define UART_UARTFR_RI_Msk (1U << UART_UARTFR_RI_Pos)
517-#define UART_UARTFR_RI UART_UARTFR_RI_Msk
518-#define UART_UARTFR_TXFE_Pos 7U
519-#define UART_UARTFR_TXFE_Msk (1U << UART_UARTFR_TXFE_Pos)
520-#define UART_UARTFR_TXFE UART_UARTFR_TXFE_Msk
521-#define UART_UARTFR_RXFF_Pos 6U
522-#define UART_UARTFR_RXFF_Msk (1U << UART_UARTFR_RXFF_Pos)
523-#define UART_UARTFR_RXFF UART_UARTFR_RXFF_Msk
524-#define UART_UARTFR_TXFF_Pos 5U
525-#define UART_UARTFR_TXFF_Msk (1U << UART_UARTFR_TXFF_Pos)
526-#define UART_UARTFR_TXFF UART_UARTFR_TXFF_Msk
527-#define UART_UARTFR_RXFE_Pos 4U
528-#define UART_UARTFR_RXFE_Msk (1U << UART_UARTFR_RXFE_Pos)
529-#define UART_UARTFR_RXFE UART_UARTFR_RXFE_Msk
530-#define UART_UARTFR_BUSY_Pos 3U
531-#define UART_UARTFR_BUSY_Msk (1U << UART_UARTFR_BUSY_Pos)
532-#define UART_UARTFR_BUSY UART_UARTFR_BUSY_Msk
533-#define UART_UARTFR_DCD_Pos 2U
534-#define UART_UARTFR_DCD_Msk (1U << UART_UARTFR_DCD_Pos)
535-#define UART_UARTFR_DCD UART_UARTFR_DCD_Msk
536-#define UART_UARTFR_DSR_Pos 1U
537-#define UART_UARTFR_DSR_Msk (1U << UART_UARTFR_DSR_Pos)
538-#define UART_UARTFR_DSR UART_UARTFR_DSR_Msk
539-#define UART_UARTFR_CTS_Pos 0U
540-#define UART_UARTFR_CTS_Msk (1U << UART_UARTFR_CTS_Pos)
541-#define UART_UARTFR_CTS UART_UARTFR_CTS_Msk
515+#define UART_UARTFR_RI_Pos 8U
516+#define UART_UARTFR_RI_Msk (1U << UART_UARTFR_RI_Pos)
517+#define UART_UARTFR_RI UART_UARTFR_RI_Msk
518+#define UART_UARTFR_TXFE_Pos 7U
519+#define UART_UARTFR_TXFE_Msk (1U << UART_UARTFR_TXFE_Pos)
520+#define UART_UARTFR_TXFE UART_UARTFR_TXFE_Msk
521+#define UART_UARTFR_RXFF_Pos 6U
522+#define UART_UARTFR_RXFF_Msk (1U << UART_UARTFR_RXFF_Pos)
523+#define UART_UARTFR_RXFF UART_UARTFR_RXFF_Msk
524+#define UART_UARTFR_TXFF_Pos 5U
525+#define UART_UARTFR_TXFF_Msk (1U << UART_UARTFR_TXFF_Pos)
526+#define UART_UARTFR_TXFF UART_UARTFR_TXFF_Msk
527+#define UART_UARTFR_RXFE_Pos 4U
528+#define UART_UARTFR_RXFE_Msk (1U << UART_UARTFR_RXFE_Pos)
529+#define UART_UARTFR_RXFE UART_UARTFR_RXFE_Msk
530+#define UART_UARTFR_BUSY_Pos 3U
531+#define UART_UARTFR_BUSY_Msk (1U << UART_UARTFR_BUSY_Pos)
532+#define UART_UARTFR_BUSY UART_UARTFR_BUSY_Msk
533+#define UART_UARTFR_DCD_Pos 2U
534+#define UART_UARTFR_DCD_Msk (1U << UART_UARTFR_DCD_Pos)
535+#define UART_UARTFR_DCD UART_UARTFR_DCD_Msk
536+#define UART_UARTFR_DSR_Pos 1U
537+#define UART_UARTFR_DSR_Msk (1U << UART_UARTFR_DSR_Pos)
538+#define UART_UARTFR_DSR UART_UARTFR_DSR_Msk
539+#define UART_UARTFR_CTS_Pos 0U
540+#define UART_UARTFR_CTS_Msk (1U << UART_UARTFR_CTS_Pos)
541+#define UART_UARTFR_CTS UART_UARTFR_CTS_Msk
542542
543-#define UART_UARTILPR_ILPDVSR_Pos 0U
544-#define UART_UARTILPR_ILPDVSR_Msk (255U << UART_UARTILPR_ILPDVSR_Pos)
545-#define UART_UARTILPR_ILPDVSR(n) ((n) << UART_UARTILPR_ILPDVSR_Pos)
543+#define UART_UARTILPR_ILPDVSR_Pos 0U
544+#define UART_UARTILPR_ILPDVSR_Msk (255U << UART_UARTILPR_ILPDVSR_Pos)
545+#define UART_UARTILPR_ILPDVSR(n) ((n) << UART_UARTILPR_ILPDVSR_Pos)
546546
547-#define UART_UARTIBRD_BAUD_DIVINT_Pos 0U
548-#define UART_UARTIBRD_BAUD_DIVINT_Msk (0xFFFFU << UART_UARTIBRD_BAUD_DIVINT_Pos)
549-#define UART_UARTIBRD_BAUD_DIVINT(n) ((n) << UART_UARTIBRD_BAUD_DIVINT_Pos)
547+#define UART_UARTIBRD_BAUD_DIVINT_Pos 0U
548+#define UART_UARTIBRD_BAUD_DIVINT_Msk (0xFFFFU << UART_UARTIBRD_BAUD_DIVINT_Pos)
549+#define UART_UARTIBRD_BAUD_DIVINT(n) ((n) << UART_UARTIBRD_BAUD_DIVINT_Pos)
550550
551-#define UART_UARTFBRD_BAUD_DIVFRAC_Pos 0U
552-#define UART_UARTFBRD_BAUD_DIVFRAC_Msk (63U << UART_UARTFBRD_BAUD_DIVFRAC_Pos)
553-#define UART_UARTFBRD_BAUD_DIVFRAC(n) ((n) << UART_UARTFBRD_BAUD_DIVFRAC_Pos)
551+#define UART_UARTFBRD_BAUD_DIVFRAC_Pos 0U
552+#define UART_UARTFBRD_BAUD_DIVFRAC_Msk (63U << UART_UARTFBRD_BAUD_DIVFRAC_Pos)
553+#define UART_UARTFBRD_BAUD_DIVFRAC(n) ((n) << UART_UARTFBRD_BAUD_DIVFRAC_Pos)
554554
555-#define UART_UARTLCR_H_SPS_Pos 7U
556-#define UART_UARTLCR_H_SPS_Msk (1U << UART_UARTLCR_H_SPS_Pos)
557-#define UART_UARTLCR_H_SPS UART_UARTLCR_H_SPS_Msk
558-#define UART_UARTLCR_H_WLEN_Pos 5U
559-#define UART_UARTLCR_H_WLEN_Msk (1U << UART_UARTLCR_H_WLEN_Pos)
560-#define UART_UARTLCR_H_WLEN(n) ((n) << UART_UARTLCR_H_WLEN_Pos)
561-#define UART_UARTLCR_H_WLEN_5BITS UART_UARTLCR_H_WLEN(0U)
562-#define UART_UARTLCR_H_WLEN_6BITS UART_UARTLCR_H_WLEN(1U)
563-#define UART_UARTLCR_H_WLEN_7BITS UART_UARTLCR_H_WLEN(2U)
564-#define UART_UARTLCR_H_WLEN_8BITS UART_UARTLCR_H_WLEN(3U)
565-#define UART_UARTLCR_H_FEN_Pos 4U
566-#define UART_UARTLCR_H_FEN_Msk (1U << UART_UARTLCR_H_FEN_Pos)
567-#define UART_UARTLCR_H_FEN UART_UARTLCR_H_FEN_Msk
568-#define UART_UARTLCR_H_STP2_Pos 3U
569-#define UART_UARTLCR_H_STP2_Msk (1U << UART_UARTLCR_H_STP2_Pos)
570-#define UART_UARTLCR_H_STP2 UART_UARTLCR_H_STP2_Msk
571-#define UART_UARTLCR_H_EPS_Pos 2U
572-#define UART_UARTLCR_H_EPS_Msk (1U << UART_UARTLCR_H_EPS_Pos)
573-#define UART_UARTLCR_H_EPS UART_UARTLCR_H_EPS_Msk
574-#define UART_UARTLCR_H_PEN_Pos 1U
575-#define UART_UARTLCR_H_PEN_Msk (1U << UART_UARTLCR_H_PEN_Pos)
576-#define UART_UARTLCR_H_PEN UART_UARTLCR_H_PEN_Msk
577-#define UART_UARTLCR_H_BRK_Pos 0U
578-#define UART_UARTLCR_H_BRK_Msk (1U << UART_UARTLCR_H_BRK_Pos)
579-#define UART_UARTLCR_H_BRK UART_UARTLCR_H_BRK_Msk
555+#define UART_UARTLCR_H_SPS_Pos 7U
556+#define UART_UARTLCR_H_SPS_Msk (1U << UART_UARTLCR_H_SPS_Pos)
557+#define UART_UARTLCR_H_SPS UART_UARTLCR_H_SPS_Msk
558+#define UART_UARTLCR_H_WLEN_Pos 5U
559+#define UART_UARTLCR_H_WLEN_Msk (1U << UART_UARTLCR_H_WLEN_Pos)
560+#define UART_UARTLCR_H_WLEN(n) ((n) << UART_UARTLCR_H_WLEN_Pos)
561+#define UART_UARTLCR_H_WLEN_5BITS UART_UARTLCR_H_WLEN(0U)
562+#define UART_UARTLCR_H_WLEN_6BITS UART_UARTLCR_H_WLEN(1U)
563+#define UART_UARTLCR_H_WLEN_7BITS UART_UARTLCR_H_WLEN(2U)
564+#define UART_UARTLCR_H_WLEN_8BITS UART_UARTLCR_H_WLEN(3U)
565+#define UART_UARTLCR_H_FEN_Pos 4U
566+#define UART_UARTLCR_H_FEN_Msk (1U << UART_UARTLCR_H_FEN_Pos)
567+#define UART_UARTLCR_H_FEN UART_UARTLCR_H_FEN_Msk
568+#define UART_UARTLCR_H_STP2_Pos 3U
569+#define UART_UARTLCR_H_STP2_Msk (1U << UART_UARTLCR_H_STP2_Pos)
570+#define UART_UARTLCR_H_STP2 UART_UARTLCR_H_STP2_Msk
571+#define UART_UARTLCR_H_EPS_Pos 2U
572+#define UART_UARTLCR_H_EPS_Msk (1U << UART_UARTLCR_H_EPS_Pos)
573+#define UART_UARTLCR_H_EPS UART_UARTLCR_H_EPS_Msk
574+#define UART_UARTLCR_H_PEN_Pos 1U
575+#define UART_UARTLCR_H_PEN_Msk (1U << UART_UARTLCR_H_PEN_Pos)
576+#define UART_UARTLCR_H_PEN UART_UARTLCR_H_PEN_Msk
577+#define UART_UARTLCR_H_BRK_Pos 0U
578+#define UART_UARTLCR_H_BRK_Msk (1U << UART_UARTLCR_H_BRK_Pos)
579+#define UART_UARTLCR_H_BRK UART_UARTLCR_H_BRK_Msk
580580
581-#define UART_UARTCR_CTSEN_Pos 15U
582-#define UART_UARTCR_CTSEN_Msk (1U << UART_UARTCR_CTSEN_Pos)
583-#define UART_UARTCR_CTSEN UART_UARTCR_CTSEN_Msk
584-#define UART_UARTCR_RTSEN_Pos 14U
585-#define UART_UARTCR_RTSEN_Msk (1U << UART_UARTCR_RTSEN_Pos)
586-#define UART_UARTCR_RTSEN UART_UARTCR_RTSEN_Msk
587-#define UART_UARTCR_OUT2_Pos 13U
588-#define UART_UARTCR_OUT2_Msk (1U << UART_UARTCR_OUT2_Pos)
589-#define UART_UARTCR_OUT2 UART_UARTCR_OUT2_Msk
590-#define UART_UARTCR_OUT1_Pos 12U
591-#define UART_UARTCR_OUT1_Msk (1U << UART_UARTCR_OUT1_Pos)
592-#define UART_UARTCR_OUT1 UART_UARTCR_OUT1_Msk
593-#define UART_UARTCR_RTS_Pos 11U
594-#define UART_UARTCR_RTS_Msk (1U << UART_UARTCR_RTS_Pos)
595-#define UART_UARTCR_RTS UART_UARTCR_RTS_Msk
596-#define UART_UARTCR_DTR_Pos 10U
597-#define UART_UARTCR_DTR_Msk (1U << UART_UARTCR_DTR_Pos)
598-#define UART_UARTCR_DTR UART_UARTCR_DTR_Msk
599-#define UART_UARTCR_RXE_Pos 9U
600-#define UART_UARTCR_RXE_Msk (1U << UART_UARTCR_RXE_Pos)
601-#define UART_UARTCR_RXE UART_UARTCR_RXE_Msk
602-#define UART_UARTCR_TXE_Pos 8U
603-#define UART_UARTCR_TXE_Msk (1U << UART_UARTCR_TXE_Pos)
604-#define UART_UARTCR_TXE UART_UARTCR_TXE_Msk
605-#define UART_UARTCR_LBE_Pos 7U
606-#define UART_UARTCR_LBE_Msk (1U << UART_UARTCR_LBE_Pos)
607-#define UART_UARTCR_LBE UART_UARTCR_LBE_Msk
608-#define UART_UARTCR_SIRLP_Pos 2U
609-#define UART_UARTCR_SIRLP_Msk (1U << UART_UARTCR_SIRLP_Pos)
610-#define UART_UARTCR_SIRLP UART_UARTCR_SIRLP_Msk
611-#define UART_UARTCR_SIREN_Pos 1U
612-#define UART_UARTCR_SIREN_Msk (1U << UART_UARTCR_SIREN_Pos)
613-#define UART_UARTCR_SIREN UART_UARTCR_SIREN_Msk
614-#define UART_UARTCR_UARTEN_Pos 0U
615-#define UART_UARTCR_UARTEN_Msk (1U << UART_UARTCR_UARTEN_Pos)
616-#define UART_UARTCR_UARTEN UART_UARTCR_UARTEN_Msk
581+#define UART_UARTCR_CTSEN_Pos 15U
582+#define UART_UARTCR_CTSEN_Msk (1U << UART_UARTCR_CTSEN_Pos)
583+#define UART_UARTCR_CTSEN UART_UARTCR_CTSEN_Msk
584+#define UART_UARTCR_RTSEN_Pos 14U
585+#define UART_UARTCR_RTSEN_Msk (1U << UART_UARTCR_RTSEN_Pos)
586+#define UART_UARTCR_RTSEN UART_UARTCR_RTSEN_Msk
587+#define UART_UARTCR_OUT2_Pos 13U
588+#define UART_UARTCR_OUT2_Msk (1U << UART_UARTCR_OUT2_Pos)
589+#define UART_UARTCR_OUT2 UART_UARTCR_OUT2_Msk
590+#define UART_UARTCR_OUT1_Pos 12U
591+#define UART_UARTCR_OUT1_Msk (1U << UART_UARTCR_OUT1_Pos)
592+#define UART_UARTCR_OUT1 UART_UARTCR_OUT1_Msk
593+#define UART_UARTCR_RTS_Pos 11U
594+#define UART_UARTCR_RTS_Msk (1U << UART_UARTCR_RTS_Pos)
595+#define UART_UARTCR_RTS UART_UARTCR_RTS_Msk
596+#define UART_UARTCR_DTR_Pos 10U
597+#define UART_UARTCR_DTR_Msk (1U << UART_UARTCR_DTR_Pos)
598+#define UART_UARTCR_DTR UART_UARTCR_DTR_Msk
599+#define UART_UARTCR_RXE_Pos 9U
600+#define UART_UARTCR_RXE_Msk (1U << UART_UARTCR_RXE_Pos)
601+#define UART_UARTCR_RXE UART_UARTCR_RXE_Msk
602+#define UART_UARTCR_TXE_Pos 8U
603+#define UART_UARTCR_TXE_Msk (1U << UART_UARTCR_TXE_Pos)
604+#define UART_UARTCR_TXE UART_UARTCR_TXE_Msk
605+#define UART_UARTCR_LBE_Pos 7U
606+#define UART_UARTCR_LBE_Msk (1U << UART_UARTCR_LBE_Pos)
607+#define UART_UARTCR_LBE UART_UARTCR_LBE_Msk
608+#define UART_UARTCR_SIRLP_Pos 2U
609+#define UART_UARTCR_SIRLP_Msk (1U << UART_UARTCR_SIRLP_Pos)
610+#define UART_UARTCR_SIRLP UART_UARTCR_SIRLP_Msk
611+#define UART_UARTCR_SIREN_Pos 1U
612+#define UART_UARTCR_SIREN_Msk (1U << UART_UARTCR_SIREN_Pos)
613+#define UART_UARTCR_SIREN UART_UARTCR_SIREN_Msk
614+#define UART_UARTCR_UARTEN_Pos 0U
615+#define UART_UARTCR_UARTEN_Msk (1U << UART_UARTCR_UARTEN_Pos)
616+#define UART_UARTCR_UARTEN UART_UARTCR_UARTEN_Msk
617617
618-#define UART_UARTIFLS_RXIFLSEL_Pos 3U
619-#define UART_UARTIFLS_RXIFLSEL_Msk (1U << UART_UARTIFLS_RXIFLSEL_Pos)
620-#define UART_UARTIFLS_RXIFLSEL(n) ((n) << UART_UARTIFLS_RXIFLSEL_Pos)
621-#define UART_UARTIFLS_RXIFLSEL_1_8F UART_UARTIFLS_RXIFLSEL(0U)
622-#define UART_UARTIFLS_RXIFLSEL_1_4F UART_UARTIFLS_RXIFLSEL(1U)
623-#define UART_UARTIFLS_RXIFLSEL_1_2F UART_UARTIFLS_RXIFLSEL(2U)
624-#define UART_UARTIFLS_RXIFLSEL_3_4F UART_UARTIFLS_RXIFLSEL(3U)
625-#define UART_UARTIFLS_RXIFLSEL_7_8F UART_UARTIFLS_RXIFLSEL(4U)
618+#define UART_UARTIFLS_RXIFLSEL_Pos 3U
619+#define UART_UARTIFLS_RXIFLSEL_Msk (1U << UART_UARTIFLS_RXIFLSEL_Pos)
620+#define UART_UARTIFLS_RXIFLSEL(n) ((n) << UART_UARTIFLS_RXIFLSEL_Pos)
621+#define UART_UARTIFLS_RXIFLSEL_1_8F UART_UARTIFLS_RXIFLSEL(0U)
622+#define UART_UARTIFLS_RXIFLSEL_1_4F UART_UARTIFLS_RXIFLSEL(1U)
623+#define UART_UARTIFLS_RXIFLSEL_1_2F UART_UARTIFLS_RXIFLSEL(2U)
624+#define UART_UARTIFLS_RXIFLSEL_3_4F UART_UARTIFLS_RXIFLSEL(3U)
625+#define UART_UARTIFLS_RXIFLSEL_7_8F UART_UARTIFLS_RXIFLSEL(4U)
626626
627-#define UART_UARTIFLS_TXIFLSEL_Pos 3U
628-#define UART_UARTIFLS_TXIFLSEL_Msk (1U << UART_UARTIFLS_TXIFLSEL_Pos)
629-#define UART_UARTIFLS_TXIFLSEL(n) ((n) << UART_UARTIFLS_TXIFLSEL_Pos)
630-#define UART_UARTIFLS_TXIFLSEL_1_8E UART_UARTIFLS_TXIFLSEL(0U)
631-#define UART_UARTIFLS_TXIFLSEL_1_4E UART_UARTIFLS_TXIFLSEL(1U)
632-#define UART_UARTIFLS_TXIFLSEL_1_2E UART_UARTIFLS_TXIFLSEL(2U)
633-#define UART_UARTIFLS_TXIFLSEL_3_4E UART_UARTIFLS_TXIFLSEL(3U)
634-#define UART_UARTIFLS_TXIFLSEL_7_8E UART_UARTIFLS_TXIFLSEL(4U)
627+#define UART_UARTIFLS_TXIFLSEL_Pos 3U
628+#define UART_UARTIFLS_TXIFLSEL_Msk (1U << UART_UARTIFLS_TXIFLSEL_Pos)
629+#define UART_UARTIFLS_TXIFLSEL(n) ((n) << UART_UARTIFLS_TXIFLSEL_Pos)
630+#define UART_UARTIFLS_TXIFLSEL_1_8E UART_UARTIFLS_TXIFLSEL(0U)
631+#define UART_UARTIFLS_TXIFLSEL_1_4E UART_UARTIFLS_TXIFLSEL(1U)
632+#define UART_UARTIFLS_TXIFLSEL_1_2E UART_UARTIFLS_TXIFLSEL(2U)
633+#define UART_UARTIFLS_TXIFLSEL_3_4E UART_UARTIFLS_TXIFLSEL(3U)
634+#define UART_UARTIFLS_TXIFLSEL_7_8E UART_UARTIFLS_TXIFLSEL(4U)
635635
636-#define UART_UARTIMSC_OEIM_Pos 10U
637-#define UART_UARTIMSC_OEIM_Msk (1U << UART_UARTIMSC_OEIM_Pos)
638-#define UART_UARTIMSC_OEIM UART_UARTIMSC_OEIM_Msk
639-#define UART_UARTIMSC_BEIM_Pos 9U
640-#define UART_UARTIMSC_BEIM_Msk (1U << UART_UARTIMSC_BEIM_Pos)
641-#define UART_UARTIMSC_BEIM UART_UARTIMSC_BEIM_Msk
642-#define UART_UARTIMSC_PEIM_Pos 8U
643-#define UART_UARTIMSC_PEIM_Msk (1U << UART_UARTIMSC_PEIM_Pos)
644-#define UART_UARTIMSC_PEIM UART_UARTIMSC_PEIM_Msk
645-#define UART_UARTIMSC_FEIM_Pos 7U
646-#define UART_UARTIMSC_FEIM_Msk (1U << UART_UARTIMSC_FEIM_Pos)
647-#define UART_UARTIMSC_FEIM UART_UARTIMSC_FEIM_Msk
648-#define UART_UARTIMSC_RTIM_Pos 6U
649-#define UART_UARTIMSC_RTIM_Msk (1U << UART_UARTIMSC_RTIM_Pos)
650-#define UART_UARTIMSC_RTIM UART_UARTIMSC_RTIM_Msk
651-#define UART_UARTIMSC_TXIM_Pos 5U
652-#define UART_UARTIMSC_TXIM_Msk (1U << UART_UARTIMSC_TXIM_Pos)
653-#define UART_UARTIMSC_TXIM UART_UARTIMSC_TXIM_Msk
654-#define UART_UARTIMSC_RXIM_Pos 4U
655-#define UART_UARTIMSC_RXIM_Msk (1U << UART_UARTIMSC_RXIM_Pos)
656-#define UART_UARTIMSC_RXIM UART_UARTIMSC_RXIM_Msk
657-#define UART_UARTIMSC_DSRMIM_Pos 3U
658-#define UART_UARTIMSC_DSRMIM_Msk (1U << UART_UARTIMSC_DSRMIM_Pos)
659-#define UART_UARTIMSC_DSRMIM UART_UARTIMSC_DSRMIM_Msk
660-#define UART_UARTIMSC_DCDMIM_Pos 2U
661-#define UART_UARTIMSC_DCDMIM_Msk (1U << UART_UARTIMSC_DCDMIM_Pos)
662-#define UART_UARTIMSC_DCDMIM UART_UARTIMSC_DCDMIM_Msk
663-#define UART_UARTIMSC_CTSMIM_Pos 1U
664-#define UART_UARTIMSC_CTSMIM_Msk (1U << UART_UARTIMSC_CTSMIM_Pos)
665-#define UART_UARTIMSC_CTSMIM UART_UARTIMSC_CTSMIM_Msk
666-#define UART_UARTIMSC_RIMIM_Pos 0U
667-#define UART_UARTIMSC_RIMIM_Msk (1U << UART_UARTIMSC_RIMIM_Pos)
668-#define UART_UARTIMSC_RIMIM UART_UARTIMSC_RIMIM_Msk
636+#define UART_UARTIMSC_OEIM_Pos 10U
637+#define UART_UARTIMSC_OEIM_Msk (1U << UART_UARTIMSC_OEIM_Pos)
638+#define UART_UARTIMSC_OEIM UART_UARTIMSC_OEIM_Msk
639+#define UART_UARTIMSC_BEIM_Pos 9U
640+#define UART_UARTIMSC_BEIM_Msk (1U << UART_UARTIMSC_BEIM_Pos)
641+#define UART_UARTIMSC_BEIM UART_UARTIMSC_BEIM_Msk
642+#define UART_UARTIMSC_PEIM_Pos 8U
643+#define UART_UARTIMSC_PEIM_Msk (1U << UART_UARTIMSC_PEIM_Pos)
644+#define UART_UARTIMSC_PEIM UART_UARTIMSC_PEIM_Msk
645+#define UART_UARTIMSC_FEIM_Pos 7U
646+#define UART_UARTIMSC_FEIM_Msk (1U << UART_UARTIMSC_FEIM_Pos)
647+#define UART_UARTIMSC_FEIM UART_UARTIMSC_FEIM_Msk
648+#define UART_UARTIMSC_RTIM_Pos 6U
649+#define UART_UARTIMSC_RTIM_Msk (1U << UART_UARTIMSC_RTIM_Pos)
650+#define UART_UARTIMSC_RTIM UART_UARTIMSC_RTIM_Msk
651+#define UART_UARTIMSC_TXIM_Pos 5U
652+#define UART_UARTIMSC_TXIM_Msk (1U << UART_UARTIMSC_TXIM_Pos)
653+#define UART_UARTIMSC_TXIM UART_UARTIMSC_TXIM_Msk
654+#define UART_UARTIMSC_RXIM_Pos 4U
655+#define UART_UARTIMSC_RXIM_Msk (1U << UART_UARTIMSC_RXIM_Pos)
656+#define UART_UARTIMSC_RXIM UART_UARTIMSC_RXIM_Msk
657+#define UART_UARTIMSC_DSRMIM_Pos 3U
658+#define UART_UARTIMSC_DSRMIM_Msk (1U << UART_UARTIMSC_DSRMIM_Pos)
659+#define UART_UARTIMSC_DSRMIM UART_UARTIMSC_DSRMIM_Msk
660+#define UART_UARTIMSC_DCDMIM_Pos 2U
661+#define UART_UARTIMSC_DCDMIM_Msk (1U << UART_UARTIMSC_DCDMIM_Pos)
662+#define UART_UARTIMSC_DCDMIM UART_UARTIMSC_DCDMIM_Msk
663+#define UART_UARTIMSC_CTSMIM_Pos 1U
664+#define UART_UARTIMSC_CTSMIM_Msk (1U << UART_UARTIMSC_CTSMIM_Pos)
665+#define UART_UARTIMSC_CTSMIM UART_UARTIMSC_CTSMIM_Msk
666+#define UART_UARTIMSC_RIMIM_Pos 0U
667+#define UART_UARTIMSC_RIMIM_Msk (1U << UART_UARTIMSC_RIMIM_Pos)
668+#define UART_UARTIMSC_RIMIM UART_UARTIMSC_RIMIM_Msk
669669
670-#define UART_UARTRIS_OERIS_Pos 10U
671-#define UART_UARTRIS_OERIS_Msk (1U << UART_UARTRIS_OERIS_Pos)
672-#define UART_UARTRIS_OERIS UART_UARTRIS_OERIS_Msk
673-#define UART_UARTRIS_BERIS_Pos 9U
674-#define UART_UARTRIS_BERIS_Msk (1U << UART_UARTRIS_BERIS_Pos)
675-#define UART_UARTRIS_BERIS UART_UARTRIS_BERIS_Msk
676-#define UART_UARTRIS_PERIS_Pos 8U
677-#define UART_UARTRIS_PERIS_Msk (1U << UART_UARTRIS_PERIS_Pos)
678-#define UART_UARTRIS_PERIS UART_UARTRIS_PERIS_Msk
679-#define UART_UARTRIS_FERIS_Pos 7U
680-#define UART_UARTRIS_FERIS_Msk (1U << UART_UARTRIS_FERIS_Pos)
681-#define UART_UARTRIS_FERIS UART_UARTRIS_FERIS_Msk
682-#define UART_UARTRIS_RTRIS_Pos 6U
683-#define UART_UARTRIS_RTRIS_Msk (1U << UART_UARTRIS_RTRIS_Pos)
684-#define UART_UARTRIS_RTRIS UART_UARTRIS_RTRIS_Msk
685-#define UART_UARTRIS_TXRIS_Pos 5U
686-#define UART_UARTRIS_TXRIS_Msk (1U << UART_UARTRIS_TXRIS_Pos)
687-#define UART_UARTRIS_TXRIS UART_UARTRIS_TXRIS_Msk
688-#define UART_UARTRIS_RXRIS_Pos 4U
689-#define UART_UARTRIS_RXRIS_Msk (1U << UART_UARTRIS_RXRIS_Pos)
690-#define UART_UARTRIS_RXRIS UART_UARTRIS_RXRIS_Msk
691-#define UART_UARTRIS_DSRRMIS_Pos 3U
692-#define UART_UARTRIS_DSRRMIS_Msk (1U << UART_UARTRIS_DSRRMIS_Pos)
693-#define UART_UARTRIS_DSRRMIS UART_UARTRIS_DSRRMIS_Msk
694-#define UART_UARTRIS_DCDRMIS_Pos 2U
695-#define UART_UARTRIS_DCDRMIS_Msk (1U << UART_UARTRIS_DCDRMIS_Pos)
696-#define UART_UARTRIS_DCDRMIS UART_UARTRIS_DCDRMIS_Msk
697-#define UART_UARTRIS_CTSRMIS_Pos 1U
698-#define UART_UARTRIS_CTSRMIS_Msk (1U << UART_UARTRIS_CTSRMIS_Pos)
699-#define UART_UARTRIS_CTSRMIS UART_UARTRIS_CTSRMIS_Msk
700-#define UART_UARTRIS_RIRMIS_Pos 0U
701-#define UART_UARTRIS_RIRMIS_Msk (1U << UART_UARTRIS_RIRMIS_Pos)
702-#define UART_UARTRIS_RIRMIS UART_UARTIMSC_RIRMIS_Msk
670+#define UART_UARTRIS_OERIS_Pos 10U
671+#define UART_UARTRIS_OERIS_Msk (1U << UART_UARTRIS_OERIS_Pos)
672+#define UART_UARTRIS_OERIS UART_UARTRIS_OERIS_Msk
673+#define UART_UARTRIS_BERIS_Pos 9U
674+#define UART_UARTRIS_BERIS_Msk (1U << UART_UARTRIS_BERIS_Pos)
675+#define UART_UARTRIS_BERIS UART_UARTRIS_BERIS_Msk
676+#define UART_UARTRIS_PERIS_Pos 8U
677+#define UART_UARTRIS_PERIS_Msk (1U << UART_UARTRIS_PERIS_Pos)
678+#define UART_UARTRIS_PERIS UART_UARTRIS_PERIS_Msk
679+#define UART_UARTRIS_FERIS_Pos 7U
680+#define UART_UARTRIS_FERIS_Msk (1U << UART_UARTRIS_FERIS_Pos)
681+#define UART_UARTRIS_FERIS UART_UARTRIS_FERIS_Msk
682+#define UART_UARTRIS_RTRIS_Pos 6U
683+#define UART_UARTRIS_RTRIS_Msk (1U << UART_UARTRIS_RTRIS_Pos)
684+#define UART_UARTRIS_RTRIS UART_UARTRIS_RTRIS_Msk
685+#define UART_UARTRIS_TXRIS_Pos 5U
686+#define UART_UARTRIS_TXRIS_Msk (1U << UART_UARTRIS_TXRIS_Pos)
687+#define UART_UARTRIS_TXRIS UART_UARTRIS_TXRIS_Msk
688+#define UART_UARTRIS_RXRIS_Pos 4U
689+#define UART_UARTRIS_RXRIS_Msk (1U << UART_UARTRIS_RXRIS_Pos)
690+#define UART_UARTRIS_RXRIS UART_UARTRIS_RXRIS_Msk
691+#define UART_UARTRIS_DSRRMIS_Pos 3U
692+#define UART_UARTRIS_DSRRMIS_Msk (1U << UART_UARTRIS_DSRRMIS_Pos)
693+#define UART_UARTRIS_DSRRMIS UART_UARTRIS_DSRRMIS_Msk
694+#define UART_UARTRIS_DCDRMIS_Pos 2U
695+#define UART_UARTRIS_DCDRMIS_Msk (1U << UART_UARTRIS_DCDRMIS_Pos)
696+#define UART_UARTRIS_DCDRMIS UART_UARTRIS_DCDRMIS_Msk
697+#define UART_UARTRIS_CTSRMIS_Pos 1U
698+#define UART_UARTRIS_CTSRMIS_Msk (1U << UART_UARTRIS_CTSRMIS_Pos)
699+#define UART_UARTRIS_CTSRMIS UART_UARTRIS_CTSRMIS_Msk
700+#define UART_UARTRIS_RIRMIS_Pos 0U
701+#define UART_UARTRIS_RIRMIS_Msk (1U << UART_UARTRIS_RIRMIS_Pos)
702+#define UART_UARTRIS_RIRMIS UART_UARTIMSC_RIRMIS_Msk
703703
704-#define UART_UARTMIS_OEMIS_Pos 10U
705-#define UART_UARTMIS_OEMIS_Msk (1U << UART_UARTMIS_OEMIS_Pos)
706-#define UART_UARTMIS_OEMIS UART_UARTMIS_OEMIS_Msk
707-#define UART_UARTMIS_BEMIS_Pos 9U
708-#define UART_UARTMIS_BEMIS_Msk (1U << UART_UARTMIS_BEMIS_Pos)
709-#define UART_UARTMIS_BEMIS UART_UARTMIS_BEMIS_Msk
710-#define UART_UARTMIS_PEMIS_Pos 8U
711-#define UART_UARTMIS_PEMIS_Msk (1U << UART_UARTMIS_PEMIS_Pos)
712-#define UART_UARTMIS_PEMIS UART_UARTMIS_PEMIS_Msk
713-#define UART_UARTMIS_FEMIS_Pos 7U
714-#define UART_UARTMIS_FEMIS_Msk (1U << UART_UARTMIS_FEMIS_Pos)
715-#define UART_UARTMIS_FEMIS UART_UARTMIS_FEMIS_Msk
716-#define UART_UARTMIS_RTMIS_Pos 6U
717-#define UART_UARTMIS_RTMIS_Msk (1U << UART_UARTMIS_RTMIS_Pos)
718-#define UART_UARTMIS_RTMIS UART_UARTMIS_RTMIS_Msk
719-#define UART_UARTMIS_TXMIS_Pos 5U
720-#define UART_UARTMIS_TXMIS_Msk (1U << UART_UARTMIS_TXMIS_Pos)
721-#define UART_UARTMIS_TXMIS UART_UARTMIS_TXMIS_Msk
722-#define UART_UARTMIS_RXMIS_Pos 4U
723-#define UART_UARTMIS_RXMIS_Msk (1U << UART_UARTMIS_RXMIS_Pos)
724-#define UART_UARTMIS_RXMIS UART_UARTMIS_RXMIS_Msk
725-#define UART_UARTMIS_DSRMMIS_Pos 3U
726-#define UART_UARTMIS_DSRMMIS_Msk (1U << UART_UARTMIS_DSRMMIS_Pos)
727-#define UART_UARTMIS_DSRRMIS UART_UARTMIS_DSRMMIS_Msk
728-#define UART_UARTMIS_DCDMMIS_Pos 2U
729-#define UART_UARTMIS_DCDMMIS_Msk (1U << UART_UARTMIS_DCDMMIS_Pos)
730-#define UART_UARTMIS_DCDMMIS UART_UARTMIS_DCDMMIS_Msk
731-#define UART_UARTMIS_CTSMMIS_Pos 1U
732-#define UART_UARTMIS_CTSMMIS_Msk (1U << UART_UARTMIS_CTSMMIS_Pos)
733-#define UART_UARTMIS_CTSMMIS UART_UARTMIS_CTSMMIS_Msk
734-#define UART_UARTMIS_RIMMIS_Pos 0U
735-#define UART_UARTMIS_RIMMIS_Msk (1U << UART_UARTMIS_RIMMIS_Pos)
736-#define UART_UARTMIS_RIMMIS UART_UARTIMSC_RIMMIS_Msk
704+#define UART_UARTMIS_OEMIS_Pos 10U
705+#define UART_UARTMIS_OEMIS_Msk (1U << UART_UARTMIS_OEMIS_Pos)
706+#define UART_UARTMIS_OEMIS UART_UARTMIS_OEMIS_Msk
707+#define UART_UARTMIS_BEMIS_Pos 9U
708+#define UART_UARTMIS_BEMIS_Msk (1U << UART_UARTMIS_BEMIS_Pos)
709+#define UART_UARTMIS_BEMIS UART_UARTMIS_BEMIS_Msk
710+#define UART_UARTMIS_PEMIS_Pos 8U
711+#define UART_UARTMIS_PEMIS_Msk (1U << UART_UARTMIS_PEMIS_Pos)
712+#define UART_UARTMIS_PEMIS UART_UARTMIS_PEMIS_Msk
713+#define UART_UARTMIS_FEMIS_Pos 7U
714+#define UART_UARTMIS_FEMIS_Msk (1U << UART_UARTMIS_FEMIS_Pos)
715+#define UART_UARTMIS_FEMIS UART_UARTMIS_FEMIS_Msk
716+#define UART_UARTMIS_RTMIS_Pos 6U
717+#define UART_UARTMIS_RTMIS_Msk (1U << UART_UARTMIS_RTMIS_Pos)
718+#define UART_UARTMIS_RTMIS UART_UARTMIS_RTMIS_Msk
719+#define UART_UARTMIS_TXMIS_Pos 5U
720+#define UART_UARTMIS_TXMIS_Msk (1U << UART_UARTMIS_TXMIS_Pos)
721+#define UART_UARTMIS_TXMIS UART_UARTMIS_TXMIS_Msk
722+#define UART_UARTMIS_RXMIS_Pos 4U
723+#define UART_UARTMIS_RXMIS_Msk (1U << UART_UARTMIS_RXMIS_Pos)
724+#define UART_UARTMIS_RXMIS UART_UARTMIS_RXMIS_Msk
725+#define UART_UARTMIS_DSRMMIS_Pos 3U
726+#define UART_UARTMIS_DSRMMIS_Msk (1U << UART_UARTMIS_DSRMMIS_Pos)
727+#define UART_UARTMIS_DSRRMIS UART_UARTMIS_DSRMMIS_Msk
728+#define UART_UARTMIS_DCDMMIS_Pos 2U
729+#define UART_UARTMIS_DCDMMIS_Msk (1U << UART_UARTMIS_DCDMMIS_Pos)
730+#define UART_UARTMIS_DCDMMIS UART_UARTMIS_DCDMMIS_Msk
731+#define UART_UARTMIS_CTSMMIS_Pos 1U
732+#define UART_UARTMIS_CTSMMIS_Msk (1U << UART_UARTMIS_CTSMMIS_Pos)
733+#define UART_UARTMIS_CTSMMIS UART_UARTMIS_CTSMMIS_Msk
734+#define UART_UARTMIS_RIMMIS_Pos 0U
735+#define UART_UARTMIS_RIMMIS_Msk (1U << UART_UARTMIS_RIMMIS_Pos)
736+#define UART_UARTMIS_RIMMIS UART_UARTIMSC_RIMMIS_Msk
737737
738-#define UART_UARTICR_OEIC_Pos 10U
739-#define UART_UARTICR_OEIC_Msk (1U << UART_UARTICR_OEIC_Pos)
740-#define UART_UARTICR_OEIC UART_UARTICR_OEIC_Msk
741-#define UART_UARTICR_BEIC_Pos 9U
742-#define UART_UARTICR_BEIC_Msk (1U << UART_UARTICR_BEIC_Pos)
743-#define UART_UARTICR_BEIC UART_UARTICR_BEIC_Msk
744-#define UART_UARTICR_PEIC_Pos 8U
745-#define UART_UARTICR_PEIC_Msk (1U << UART_UARTICR_PEIC_Pos)
746-#define UART_UARTICR_PEIC UART_UARTICR_PEIC_Msk
747-#define UART_UARTICR_FEIC_Pos 7U
748-#define UART_UARTICR_FEIC_Msk (1U << UART_UARTICR_FEIC_Pos)
749-#define UART_UARTICR_FEIC UART_UARTICR_FEIC_Msk
750-#define UART_UARTICR_RTIC_Pos 6U
751-#define UART_UARTICR_RTIC_Msk (1U << UART_UARTICR_RTIC_Pos)
752-#define UART_UARTICR_RTIC UART_UARTICR_RTIC_Msk
753-#define UART_UARTICR_TXIC_Pos 5U
754-#define UART_UARTICR_TXIC_Msk (1U << UART_UARTICR_TXIC_Pos)
755-#define UART_UARTICR_TXIC UART_UARTICR_TXIC_Msk
756-#define UART_UARTICR_RXIC_Pos 4U
757-#define UART_UARTICR_RXIC_Msk (1U << UART_UARTICR_RXIC_Pos)
758-#define UART_UARTICR_RXIC UART_UARTICR_RXIC_Msk
759-#define UART_UARTICR_DSRMIC_Pos 3U
760-#define UART_UARTICR_DSRMIC_Msk (1U << UART_UARTICR_DSRMIC_Pos)
761-#define UART_UARTICR_DSRMIC UART_UARTICR_DSRMIC_Msk
762-#define UART_UARTICR_DCDMIC_Pos 2U
763-#define UART_UARTICR_DCDMIC_Msk (1U << UART_UARTICR_DCDMIC_Pos)
764-#define UART_UARTICR_DCDMIC UART_UARTICR_DCDMIC_Msk
765-#define UART_UARTICR_CTSMIC_Pos 1U
766-#define UART_UARTICR_CTSMIC_Msk (1U << UART_UARTICR_CTSMIC_Pos)
767-#define UART_UARTICR_CTSMIC UART_UARTICR_CTSMIC_Msk
768-#define UART_UARTICR_RIMIC_Pos 0U
769-#define UART_UARTICR_RIMIC_Msk (1U << UART_UARTICR_RIMIC_Pos)
770-#define UART_UARTICR_RIMIC UART_UARTICR_RIMIC_Msk
738+#define UART_UARTICR_OEIC_Pos 10U
739+#define UART_UARTICR_OEIC_Msk (1U << UART_UARTICR_OEIC_Pos)
740+#define UART_UARTICR_OEIC UART_UARTICR_OEIC_Msk
741+#define UART_UARTICR_BEIC_Pos 9U
742+#define UART_UARTICR_BEIC_Msk (1U << UART_UARTICR_BEIC_Pos)
743+#define UART_UARTICR_BEIC UART_UARTICR_BEIC_Msk
744+#define UART_UARTICR_PEIC_Pos 8U
745+#define UART_UARTICR_PEIC_Msk (1U << UART_UARTICR_PEIC_Pos)
746+#define UART_UARTICR_PEIC UART_UARTICR_PEIC_Msk
747+#define UART_UARTICR_FEIC_Pos 7U
748+#define UART_UARTICR_FEIC_Msk (1U << UART_UARTICR_FEIC_Pos)
749+#define UART_UARTICR_FEIC UART_UARTICR_FEIC_Msk
750+#define UART_UARTICR_RTIC_Pos 6U
751+#define UART_UARTICR_RTIC_Msk (1U << UART_UARTICR_RTIC_Pos)
752+#define UART_UARTICR_RTIC UART_UARTICR_RTIC_Msk
753+#define UART_UARTICR_TXIC_Pos 5U
754+#define UART_UARTICR_TXIC_Msk (1U << UART_UARTICR_TXIC_Pos)
755+#define UART_UARTICR_TXIC UART_UARTICR_TXIC_Msk
756+#define UART_UARTICR_RXIC_Pos 4U
757+#define UART_UARTICR_RXIC_Msk (1U << UART_UARTICR_RXIC_Pos)
758+#define UART_UARTICR_RXIC UART_UARTICR_RXIC_Msk
759+#define UART_UARTICR_DSRMIC_Pos 3U
760+#define UART_UARTICR_DSRMIC_Msk (1U << UART_UARTICR_DSRMIC_Pos)
761+#define UART_UARTICR_DSRMIC UART_UARTICR_DSRMIC_Msk
762+#define UART_UARTICR_DCDMIC_Pos 2U
763+#define UART_UARTICR_DCDMIC_Msk (1U << UART_UARTICR_DCDMIC_Pos)
764+#define UART_UARTICR_DCDMIC UART_UARTICR_DCDMIC_Msk
765+#define UART_UARTICR_CTSMIC_Pos 1U
766+#define UART_UARTICR_CTSMIC_Msk (1U << UART_UARTICR_CTSMIC_Pos)
767+#define UART_UARTICR_CTSMIC UART_UARTICR_CTSMIC_Msk
768+#define UART_UARTICR_RIMIC_Pos 0U
769+#define UART_UARTICR_RIMIC_Msk (1U << UART_UARTICR_RIMIC_Pos)
770+#define UART_UARTICR_RIMIC UART_UARTICR_RIMIC_Msk
771771
772-#define UART_UARTDMACR_DMAONERR_Pos 2U
773-#define UART_UARTDMACR_DMAONERR_Msk (1U << UART_UARTDMACR_DMAONERR_Pos)
774-#define UART_UARTDMACR_DMAONERR UART_UARTDMACR_DMAONERR_Msk
775-#define UART_UARTDMACR_TXDMAE_Pos 1U
776-#define UART_UARTDMACR_TXDMAE_Msk (1U << UART_UARTDMACR_TXDMAE_Pos)
777-#define UART_UARTDMACR_TXDMAE UART_UARTDMACR_TXDMAE_Msk
778-#define UART_UARTDMACR_RXDMAE_Pos 0U
779-#define UART_UARTDMACR_RXDMAE_Msk (1U << UART_UARTDMACR_RXDMAE_Pos)
780-#define UART_UARTDMACR_RXDMAE UART_UARTDMACR_RXDMAE_Msk
772+#define UART_UARTDMACR_DMAONERR_Pos 2U
773+#define UART_UARTDMACR_DMAONERR_Msk (1U << UART_UARTDMACR_DMAONERR_Pos)
774+#define UART_UARTDMACR_DMAONERR UART_UARTDMACR_DMAONERR_Msk
775+#define UART_UARTDMACR_TXDMAE_Pos 1U
776+#define UART_UARTDMACR_TXDMAE_Msk (1U << UART_UARTDMACR_TXDMAE_Pos)
777+#define UART_UARTDMACR_TXDMAE UART_UARTDMACR_TXDMAE_Msk
778+#define UART_UARTDMACR_RXDMAE_Pos 0U
779+#define UART_UARTDMACR_RXDMAE_Msk (1U << UART_UARTDMACR_RXDMAE_Pos)
780+#define UART_UARTDMACR_RXDMAE UART_UARTDMACR_RXDMAE_Msk
781781 /** @} */
782782
783+/**
784+ * @name RTC bits definitions
785+ * @{
786+ */
787+#define RTC_CLKDIV_M1_Pos 0U
788+#define RTC_CLKDIV_M1_Msk (0xFFFFU << RTC_CLKDIV_M1_Pos)
789+#define RTC_CLKDIV_M1 RTC_CLKDIV_M1_Msk
790+
791+#define RTC_SETUP_0_YEAR_Pos 12U
792+#define RTC_SETUP_0_YEAR_Msk (0xFFFU << RTC_SETUP_0_YEAR_Pos)
793+#define RTC_SETUP_0_YEAR(n) ((n) << RTC_SETUP_0_YEAR_Pos)
794+#define RTC_SETUP_0_MONTH_Pos 8U
795+#define RTC_SETUP_0_MONTH_Msk (0xFU << RTC_SETUP_0_MONTH_Pos)
796+#define RTC_SETUP_0_MONTH(n) ((n) << RTC_SETUP_0_MONTH_Pos)
797+#define RTC_SETUP_0_DAY_Pos 4U
798+#define RTC_SETUP_0_DAY_Msk (0x1FU << RTC_SETUP_0_DAY_Pos)
799+#define RTC_SETUP_0_DAY(n) ((n) << RTC_SETUP_0_DAY_Pos)
800+
801+#define RTC_SETUP_1_DOTW_Pos 24U
802+#define RTC_SETUP_1_DOTW_Msk (0x7U << RTC_SETUP_1_DOTW_Pos)
803+#define RTC_SETUP_1_DOTW(n) ((n) << RTC_SETUP_1_DOTW_Pos)
804+#define RTC_SETUP_1_HOUR_Pos 16U
805+#define RTC_SETUP_1_HOUR_Msk (0x1FU << RTC_SETUP_1_HOUR_Pos)
806+#define RTC_SETUP_1_HOUR(n) ((n) << RTC_SETUP_1_HOUR_Pos)
807+#define RTC_SETUP_1_MIN_Pos 8U
808+#define RTC_SETUP_1_MIN_Msk (0x3FU << RTC_SETUP_1_MIN_Pos)
809+#define RTC_SETUP_1_MIN(n) ((n) << RTC_SETUP_1_MIN_Pos)
810+#define RTC_SETUP_1_SEC_Pos 0U
811+#define RTC_SETUP_1_SEC_Msk (0x3FU << RTC_SETUP_1_SEC_Pos)
812+#define RTC_SETUP_1_SEC(n) ((n) << RTC_SETUP_1_SEC_Pos)
813+
814+#define RTC_CTRL_FORCE_NOTLEAPYEAR_Pos 8U
815+#define RTC_CTRL_FORCE_NOTLEAPYEAR_Msk (1U << RTC_CTRL_FORCE_NOTLEAPYEAR_Pos)
816+#define RTC_CTRL_FORCE_NOTLEAPYEAR RTC_CTRL_FORCE_NOTLEAPYEAR_Msk
817+
818+#define RTC_CTRL_LOAD_Pos 4U
819+#define RTC_CTRL_LOAD_Msk (1U << RTC_CTRL_LOAD_Pos)
820+#define RTC_CTRL_LOAD RTC_CTRL_LOAD_Msk
821+
822+#define RTC_CTRL_RTC_ACTIVE_Pos 1U
823+#define RTC_CTRL_RTC_ACTIVE_Msk (1U << RTC_CTRL_RTC_ACTIVE_Pos)
824+#define RTC_CTRL_RTC_ACTIVE RTC_CTRL_RTC_ACTIVE_Msk
825+
826+#define RTC_CTRL_RTC_ENABLE_Pos 0U
827+#define RTC_CTRL_RTC_ENABLE_Msk (1U << RTC_CTRL_RTC_ENABLE_Pos)
828+#define RTC_CTRL_RTC_ENABLE RTC_CTRL_RTC_ENABLE_Msk
829+
830+#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_Pos 29U
831+#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_Msk (1U << RTC_IRQ_SETUP_0_MATCH_ACTIVE_Pos)
832+#define RTC_IRQ_SETUP_0_MATCH_ACTIVE RTC_IRQ_SETUP_0_MATCH_ACTIVE_Msk
833+#define RTC_IRQ_SETUP_0_MATCH_ENA_Pos 28U
834+#define RTC_IRQ_SETUP_0_MATCH_ENA_Msk (1U << RTC_IRQ_SETUP_0_MATCH_ENA_Pos)
835+#define RTC_IRQ_SETUP_0_MATCH_ENA RTC_IRQ_SETUP_0_MATCH_ENA_Msk
836+#define RTC_IRQ_SETUP_0_YEAR_ENA_Pos 26U
837+#define RTC_IRQ_SETUP_0_YEAR_ENA_Msk (1U << RTC_IRQ_SETUP_0_YEAR_ENA_Pos)
838+#define RTC_IRQ_SETUP_0_YEAR_ENA RTC_IRQ_SETUP_0_YEAR_ENA_Msk
839+#define RTC_IRQ_SETUP_0_MONTH_ENA_Pos 25U
840+#define RTC_IRQ_SETUP_0_MONTH_ENA_Msk (1U << RTC_IRQ_SETUP_0_MONTH_ENA_Pos)
841+#define RTC_IRQ_SETUP_0_MONTH_ENA RTC_IRQ_SETUP_0_MONTH_ENA_Msk
842+#define RTC_IRQ_SETUP_0_DAY_ENA_Pos 24U
843+#define RTC_IRQ_SETUP_0_DAY_ENA_Msk (1U << RTC_IRQ_SETUP_0_DAY_ENA_Pos)
844+#define RTC_IRQ_SETUP_0_DAY_ENA RTC_IRQ_SETUP_0_DAY_ENA_Msk
845+
846+#define RTC_IRQ_SETUP_0_YEAR_Pos 12U
847+#define RTC_IRQ_SETUP_0_YEAR_Msk (0xFFFU << RTC_IRQ_SETUP_0_YEAR_Pos)
848+#define RTC_IRQ_SETUP_0_YEAR(n) ((n) << RTC_IRQ_SETUP_0_YEAR_Pos)
849+#define RTC_IRQ_SETUP_0_MONTH_Pos 8U
850+#define RTC_IRQ_SETUP_0_MONTH_Msk (0xFU << RTC_IRQ_SETUP_0_MONTH_Pos)
851+#define RTC_IRQ_SETUP_0_MONTH(n) ((n) << RTC_IRQ_SETUP_0_MONTH_Pos)
852+#define RTC_IRQ_SETUP_0_DAY_Pos 4U
853+#define RTC_IRQ_SETUP_0_DAY_Msk (0x1FU << RTC_IRQ_SETUP_0_DAY_Pos)
854+#define RTC_IRQ_SETUP_0_DAY(n) ((n) << RTC_IRQ_SETUP_0_DAY_Pos)
855+
856+#define RTC_IRQ_SETUP_1_DOTW_ENA_Pos 31U
857+#define RTC_IRQ_SETUP_1_DOTW_ENA_Msk (1U << RTC_IRQ_SETUP_1_DOTW_ENA_Pos)
858+#define RTC_IRQ_SETUP_1_DOTW_ENA RTC_IRQ_SETUP_1_DOTW_ENA_Msk
859+#define RTC_IRQ_SETUP_1_HOUR_ENA_Pos 30U
860+#define RTC_IRQ_SETUP_1_HOUR_ENA_Msk (1U << RTC_IRQ_SETUP_1_HOUR_ENA_Pos)
861+#define RTC_IRQ_SETUP_1_HOUR_ENA RTC_IRQ_SETUP_1_HOUR_ENA_Msk
862+#define RTC_IRQ_SETUP_1_MIN_ENA_Pos 29U
863+#define RTC_IRQ_SETUP_1_MIN_ENA_Msk (1U << RTC_IRQ_SETUP_1_MIN_ENA_Pos)
864+#define RTC_IRQ_SETUP_1_MIN_ENA RTC_IRQ_SETUP_1_MIN_ENA_Msk
865+#define RTC_IRQ_SETUP_1_SEC_ENA_Pos 28U
866+#define RTC_IRQ_SETUP_1_SEC_ENA_Msk (1U << RTC_IRQ_SETUP_1_SEC_ENA_Pos)
867+#define RTC_IRQ_SETUP_1_SEC_ENA RTC_IRQ_SETUP_1_SEC_ENA_Msk
868+
869+#define RTC_IRQ_SETUP_1_DOTW_Pos 24U
870+#define RTC_IRQ_SETUP_1_DOTW_Msk (0x7U << RTC_IRQ_SETUP_1_DOTW_Pos)
871+#define RTC_IRQ_SETUP_1_DOTW(n) ((n) << RTC_IRQ_SETUP_1_DOTW_Pos)
872+#define RTC_IRQ_SETUP_1_HOUR_Pos 16U
873+#define RTC_IRQ_SETUP_1_HOUR_Msk (0x1FU << RTC_IRQ_SETUP_1_HOUR_Pos)
874+#define RTC_IRQ_SETUP_1_HOUR(n) ((n) << RTC_IRQ_SETUP_1_HOUR_Pos)
875+#define RTC_IRQ_SETUP_1_MIN_Pos 8U
876+#define RTC_IRQ_SETUP_1_MIN_Msk (0x3FU << RTC_IRQ_SETUP_1_MIN_Pos)
877+#define RTC_IRQ_SETUP_1_MIN(n) ((n) << RTC_IRQ_SETUP_1_MIN_Pos)
878+#define RTC_IRQ_SETUP_1_SEC_Pos 0U
879+#define RTC_IRQ_SETUP_1_SEC_Msk (0x3FU << RTC_IRQ_SETUP_1_SEC_Pos)
880+#define RTC_IRQ_SETUP_1_SEC(n) ((n) << RTC_IRQ_SETUP_1_SEC_Pos)
881+
882+#define RTC_INTR_RTC_Pos 0U
883+#define RTC_INTR_RTC_Msk (1U << RTC_INTR_RTC_Pos)
884+#define RTC_INTR_RTC RTC_INTR_RTC_Msk
885+
886+#define RTC_INTE_RTC_Pos 0U
887+#define RTC_INTE_RTC_Msk (1U << RTC_INTE_RTC_Pos)
888+#define RTC_INTE_RTC RTC_INTE_RTC_Msk
889+
890+#define RTC_INTF_RTC_Pos 0U
891+#define RTC_INTF_RTC_Msk (1U << RTC_INTF_RTC_Pos)
892+#define RTC_INTF_RTC RTC_INTF_RTC_Msk
893+
894+#define RTC_INTS_RTC_Pos 0U
895+#define RTC_INTS_RTC_Msk (1U << RTC_INTS_RTC_Pos)
896+#define RTC_INTS_RTC RTC_INTS_RTC_Msk
897+
898+/* Normalisation of RTC0 & RTC1 fields read from RTC. */
899+#define RTC_RTC_1_YEAR_Pos 12U
900+#define RTC_RTC_1_YEAR_Msk (0xFFFU << RTC_RTC_1_YEAR_Pos)
901+#define RTC_RTC_1_YEAR(n) ((n & RTC_RTC_1_YEAR_Msk) >> \
902+ RTC_RTC_1_YEAR_Pos)
903+#define RTC_RTC_1_MONTH_Pos 8U
904+#define RTC_RTC_1_MONTH_Msk (0xFU << RTC_RTC_1_MONTH_Pos)
905+#define RTC_RTC_1_MONTH(n) ((n & RTC_RTC_1_MONTH_Msk) >> \
906+ RTC_RTC_1_DAY_Pos)
907+#define RTC_RTC_1_DAY_Pos 0U
908+#define RTC_RTC_1_DAY_Msk (0x1FU << RTC_RTC_1_DAY_Pos)
909+#define RTC_RTC_1_DAY(n) ((n & RTC_RTC_1_DAY_Msk) >> \
910+ RTC_RTC_1_DAY_Pos)
911+#define RTC_RTC_0_DOTW_Pos 24U
912+#define RTC_RTC_0_DOTW_Msk (0x7U << RTC_RTC_0_DOTW_Pos)
913+#define RTC_RTC_0_DOTW(n) ((n & RTC_RTC_0_DOTW_Msk) >> \
914+ RTC_RTC_0_DOTW_Pos)
915+#define RTC_RTC_0_HOUR_Pos 16U
916+#define RTC_RTC_0_HOUR_Msk (0x1FU << RTC_RTC_0_HOUR_Pos)
917+#define RTC_RTC_0_HOUR(n) ((n & RTC_RTC_0_HOUR_Msk) >> \
918+ RTC_RTC_0_HOUR_Pos)
919+#define RTC_RTC_0_MIN_Pos 8U
920+#define RTC_RTC_0_MIN_Msk (0x3FU << RTC_RTC_0_MIN_Pos)
921+#define RTC_RTC_0_MIN(n) ((n & RTC_RTC_0_MIN_Msk) >> \
922+ RTC_RTC_0_MIN_Pos)
923+#define RTC_RTC_0_SEC_Pos 0U
924+#define RTC_RTC_0_SEC_Msk (0x3FU << RTC_RTC_0_SEC_Pos)
925+#define RTC_RTC_0_SEC(n) ((n & RTC_RTC_0_SEC_Msk) >> \
926+ RTC_RTC_0_SEC_Pos)
927+/** @} */
928+
783929 #ifdef __cplusplus
784930 extern "C" {
785931 #endif
--- trunk/os/hal/ports/RP/LLD/RTCv1/hal_rtc_lld.c (revision 14147)
+++ trunk/os/hal/ports/RP/LLD/RTCv1/hal_rtc_lld.c (revision 14148)
@@ -48,6 +48,20 @@
4848 /* Driver local functions. */
4949 /*===========================================================================*/
5050
51+static void rtc_enable_alarm(RTCDriver *rtcp) {
52+ /* Enable matching and wait for it to be activated. */
53+ rtcp->rtc->IRQSETUP0 |= RTC_IRQ_SETUP_0_MATCH_ENA;
54+ while (!(rtcp->rtc->IRQSETUP0 & RTC_IRQ_SETUP_0_MATCH_ACTIVE))
55+ ;
56+}
57+
58+static void rtc_disable_alarm(RTCDriver *rtcp) {
59+ /* Disable alarm matching and wait until deactivated. */
60+ rtcp->rtc->IRQSETUP0 &= ~RTC_IRQ_SETUP_0_MATCH_ENA;
61+ while (rtcp->rtc->IRQSETUP0 & RTC_IRQ_SETUP_0_MATCH_ACTIVE)
62+ ;
63+}
64+
5165 /*===========================================================================*/
5266 /* Driver interrupt handlers. */
5367 /*===========================================================================*/
@@ -107,7 +121,7 @@
107121 rtcp->rtc->CTRL = 0;
108122
109123 /* Wait for RTC to go inactive. */
110- while ((rtcp->rtc->CTRL & RTC_CTRL_RTC_ACTIVE_BITS) != 0)
124+ while ((rtcp->rtc->CTRL & RTC_CTRL_RTC_ACTIVE) != 0)
111125 ;
112126
113127 /* Entering a reentrant critical zone.*/
@@ -114,26 +128,24 @@
114128 syssts_t sts = osalSysGetStatusAndLockX();
115129
116130 /* Write setup to pre-load registers. */
117- rtcp->rtc->SETUP0 =
118- ((timespec->year + 1980) << RTC_SETUP_0_YEAR_LSB) |
119- (timespec->month << RTC_SETUP_0_MONTH_LSB) |
120- (timespec->day << RTC_SETUP_0_DAY_LSB);
121- rtcp->rtc->SETUP1 =
122- ((timespec->dayofweek - 1) << RTC_SETUP_1_DOTW_LSB) |
123- (hour << RTC_SETUP_1_HOUR_LSB) |
124- (min << RTC_SETUP_1_MIN_LSB) |
125- (sec << RTC_SETUP_1_SEC_LSB);
131+ rtcp->rtc->SETUP0 = (RTC_SETUP_0_YEAR(timespec->year + 1980)) |
132+ (RTC_SETUP_0_MONTH(timespec->month)) |
133+ (RTC_SETUP_0_DAY(timespec->day));
134+ rtcp->rtc->SETUP1 = (RTC_SETUP_1_DOTW(timespec->dayofweek - 1)) |
135+ (RTC_SETUP_1_HOUR(hour)) |
136+ (RTC_SETUP_1_MIN(min)) |
137+ (RTC_SETUP_1_SEC(sec);
126138
127139 /* Move setup values into RTC clock domain. */
128- rtcp->rtc->CTRL = RTC_CTRL_LOAD_BITS;
140+ rtcp->rtc->CTRL = RTC_CTRL_LOAD;
129141
130142 /* Enable RTC and wait for active. */
131- rtcp->rtc->CTRL = RTC_CTRL_RTC_ENABLE_BITS;
143+ rtcp->rtc->CTRL = RTC_CTRL_RTC_ENABLE;
132144
133145 /* Leaving a reentrant critical zone.*/
134146 osalSysRestoreStatusX(sts);
135147
136- while ((rtcp->rtc->CTRL & RTC_CTRL_RTC_ACTIVE_BITS) == 0)
148+ while ((rtcp->rtc->CTRL & RTC_CTRL_RTC_ACTIVE) == 0)
137149 ;
138150 }
139151
@@ -159,20 +171,15 @@
159171 osalSysRestoreStatusX(sts);
160172
161173 /* Calculate and set milliseconds since midnight field. */
162- timespec->millisecond =
163- ((((rtc_0 & RTC_RTC_0_HOUR_BITS) >> RTC_RTC_0_HOUR_LSB) * 3600)
164- + (((rtc_0 & RTC_RTC_0_MIN_BITS) >> RTC_RTC_0_MIN_LSB) * 60)
165- + (((rtc_0 & RTC_RTC_0_SEC_BITS) >> RTC_RTC_0_SEC_LSB))) * 1000;
174+ timespec->millisecond = (RTC_RTC_0_HOUR(rtc_0) * 3600) +
175+ (RTC_RTC_0_MIN(rtc_0) * 60) +
176+ (RTC_RTC_0_SEC(rtc_0) * 1000);
166177
167- /* Set fields with adjustments. */
168- timespec->dayofweek =
169- ((rtc_0 & RTC_RTC_0_DOTW_BITS) >> RTC_RTC_0_DOTW_LSB) + 1;
170- timespec->year =
171- ((rtc_1 & RTC_RTC_1_YEAR_BITS) >> RTC_RTC_1_YEAR_LSB) - 1980;
172- timespec->month =
173- ((rtc_1 & RTC_RTC_1_MONTH_BITS) >> RTC_RTC_1_MONTH_LSB);
174- timespec->day =
175- ((rtc_1 & RTC_RTC_1_DAY_BITS) >> RTC_RTC_1_DAY_LSB);
178+ /* Set RTCDateTime fields with adjustments from RTC data. */
179+ timespec->dayofweek = RTC_RTC_0_DOTW(rtc_0) + 1;
180+ timespec->year = RTC_RTC_1_YEAR(rtc_1) - 1980;
181+ timespec->month = RTC_RTC_1_MONTH(rtc_1);
182+ timespec->day = RTC_RTC_1_DAY(rtc_1);
176183 }
177184
178185 #if (RTC_ALARMS > 0) || defined(__DOXYGEN__)
@@ -183,7 +190,7 @@
183190 * @note The function can be called from any context.
184191 *
185192 * @param[in] rtcp pointer to RTC driver structure.
186- * @param[in] alarm alarm identifier. Can be 1 or 2.
193+ * @param[in] alarm alarm identifier. Can be 1.
187194 * @param[in] alarmspec pointer to a @p RTCAlarm structure.
188195 *
189196 * @notapi
@@ -193,48 +200,63 @@
193200 const RTCAlarm *alarmspec) {
194201
195202 (void)alarm;
196- RTCDateTime *t = &alarmspec->alarm;
197- uint32_t sec = (uint32_t)t->millisecond / 1000;
198- uint32_t hour = sec / 3600;
203+ uint32_t sec, min, hour, day, month, year, dotw, setup0, setup1;
204+ RTCDateTime *timespec = &alarmspec->alarm;
205+ sec = (uint32_t)timespec->millisecond / 1000;
206+ hour = sec / 3600;
199207 sec %= 3600;
200- uint32_t min = sec / 60;
208+ min = sec / 60;
201209 sec %= 60;
210+ day = timespec->day;
211+ month = timespec->month;
202212
203- rtc_disable_alarm();
213+ /* Normalise and setup for non-zero checking. */
214+ year = timespec->year == 0 ? 0 : timespec->year + 1980;
215+ dotw = timespec->dayofweek;
204216
205- // Only add to setup if it isn't -1
206- rtcp->rtc->IRQSETUP0 = ((t->year < 0) ? 0 : (((uint)t->year) << RTC_IRQ_SETUP_0_YEAR_LSB )) |
207- ((t->month < 0) ? 0 : (((uint)t->month) << RTC_IRQ_SETUP_0_MONTH_LSB)) |
208- ((t->day < 0) ? 0 : (((uint)t->day) << RTC_IRQ_SETUP_0_DAY_LSB ));
209- rtcp->rtc->IRQSETUP1 = ((t->dotw == 0) ? 0 : (((uint)t->dotw) << RTC_IRQ_SETUP_1_DOTW_LSB)) |
210- (t->hour << RTC_IRQ_SETUP_1_HOUR_LSB)) |
211- (t->min << RTC_IRQ_SETUP_1_MIN_LSB )) |
212- (t->sec << RTC_IRQ_SETUP_1_SEC_LSB ));
217+ /* Write all registers regardless. */
218+ setup0 = (RTC_IRQ_SETUP_0_YEAR(year)) |
219+ (RTC_IRQ_SETUP_0_MONTH(month)) |
220+ (RTC_IRQ_SETUP_0_DAY(day));
221+ setup1 = (RTC_IRQ_SETUP_1_DOTW(dotw - 1)) |
222+ (RTC_IRQ_SETUP_1_HOUR(hour)) |
223+ (RTC_IRQ_SETUP_1_MIN(min)) |
224+ (RTC_IRQ_SETUP_1_SEC(sec);
213225
214- // Set the match enable bits for things we care about
215- if (t->year >= 0) hw_set_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_YEAR_ENA_BITS);
216- if (t->month >= 0) hw_set_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_MONTH_ENA_BITS);
217- if (t->day >= 0) hw_set_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_DAY_ENA_BITS);
218- if (t->dotw >= 0) hw_set_bits(&rtc_hw->irq_setup_1, RTC_IRQ_SETUP_1_DOTW_ENA_BITS);
219- if (t->hour >= 0) hw_set_bits(&rtc_hw->irq_setup_1, RTC_IRQ_SETUP_1_HOUR_ENA_BITS);
220- if (t->min >= 0) hw_set_bits(&rtc_hw->irq_setup_1, RTC_IRQ_SETUP_1_MIN_ENA_BITS);
221- if (t->sec >= 0) hw_set_bits(&rtc_hw->irq_setup_1, RTC_IRQ_SETUP_1_SEC_ENA_BITS);
226+ /* Check and set match enable bits for non-zero */
227+ if (year > 0) setup0 |= RTC_IRQ_SETUP_0_YEAR_ENA;
228+ if (month > 0) setup0 |= RTC_IRQ_SETUP_0_MONTH_ENA;
229+ if (day > 0) setup0 |= RTC_IRQ_SETUP_0_DAY_ENA;
230+ if (dotw > 0) setup1 |= RTC_IRQ_SETUP_1_DOTW_ENA;
231+ if (hour > 0) setup1 |= RTC_IRQ_SETUP_1_HOUR_ENA;
232+ if (min > 0) setup1 |= RTC_IRQ_SETUP_1_MIN_ENA;
233+ if (sec > 0) setup1 |= RTC_IRQ_SETUP_1_SEC_ENA;
222234
235+ /* Entering a reentrant critical zone.*/
236+ syssts_t sts = osalSysGetStatusAndLockX();
237+
238+ rtc_disable_alarm(rtcp);
239+ rtcp->rtc->IRQSETUP0 = setup0;
240+ rtcp->rtc->IRQSETUP1 = setup1;
241+
223242 // Does it repeat? I.e. do we not match on any of the bits
224- _alarm_repeats = rtc_alarm_repeats(t);
243+ //_alarm_repeats = rtc_alarm_repeats(t);
225244
226245 // Store function pointer we can call later
227- _callback = user_callback;
246+ //_callback = user_callback;
228247
229- irq_set_exclusive_handler(RTC_IRQ, rtc_irq_handler);
248+ //irq_set_exclusive_handler(RTC_IRQ, rtc_irq_handler);
230249
231250 // Enable the IRQ at the peri
232- rtc_hw->inte = RTC_INTE_RTC_BITS;
251+ //rtc_hw->inte = RTC_INTE_RTC_BITS;
233252
234253 // Enable the IRQ at the proc
235- irq_set_enabled(RTC_IRQ, true);
254+ //irq_set_enabled(RTC_IRQ, true);
236255
237- rtc_enable_alarm();
256+ rtc_enable_alarm(rtcp);
257+
258+ /* Leaving a reentrant critical zone.*/
259+ osalSysRestoreStatusX(sts);
238260 }
239261
240262 /**
@@ -257,6 +279,22 @@
257279 }
258280 #endif /* RTC_ALARMS > 0 */
259281
282+/**
283+ * @brief Enables or disables RTC callbacks.
284+ * @details This function enables or disables callbacks, use a @p NULL pointer
285+ * in order to disable a callback.
286+ * @note The function can be called from any context.
287+ *
288+ * @param[in] rtcp pointer to RTC driver structure
289+ * @param[in] callback callback function pointer or @p NULL
290+ *
291+ * @notapi
292+ */
293+void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback) {
294+
295+ rtcp->callback = callback;
296+}
297+
260298 #endif /* HAL_USE_RTC */
261299
262300 /** @} */
--- trunk/os/hal/ports/RP/LLD/RTCv1/hal_rtc_lld.h (revision 14147)
+++ trunk/os/hal/ports/RP/LLD/RTCv1/hal_rtc_lld.h (revision 14148)
@@ -89,7 +89,6 @@
8989 */
9090 typedef void (*rtccb_t)(RTCDriver *rtcp, rtcevent_t event);
9191
92-
9392 /**
9493 * @brief Type of a structure representing an RTC alarm time stamp.
9594 */
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