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chibios: Commit


Commit MetaInfo

Revision14604 (tree)
Time2021-07-16 13:22:53
Authorgdisirio

Log Message

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Change Summary

Incremental Difference

--- branches/stable_21.6.x/os/hal/ports/STM32/STM32G0xx/hal_lld.c (revision 14603)
+++ branches/stable_21.6.x/os/hal/ports/STM32/STM32G0xx/hal_lld.c (revision 14604)
@@ -643,7 +643,7 @@
643643 rccEnableAPBR2(RCC_APBENR2_SYSCFGEN, false);
644644
645645 #if defined(HAL_USE_RTC) && defined(RCC_APBENR1_RTCAPBEN)
646- rccEnableAPBR1(RCC_APBENR1_RTCAPBEN, false);
646+ rccEnableAPBR1(RCC_APBENR1_RTCAPBEN, true);
647647 #endif
648648
649649 /* Static PWR configurations.*/
@@ -686,7 +686,7 @@
686686 rccEnableAPBR2(RCC_APBENR2_SYSCFGEN, false);
687687
688688 #if defined(HAL_USE_RTC) && defined(RCC_APBENR1_RTCAPBEN)
689- rccEnableAPBR1(RCC_APBENR1_RTCAPBEN, false);
689+ rccEnableAPBR1(RCC_APBENR1_RTCAPBEN, true);
690690 #endif
691691
692692 /* Static PWR configurations.*/
--- branches/stable_21.6.x/os/hal/ports/STM32/STM32L4xx/hal_lld.c (revision 14603)
+++ branches/stable_21.6.x/os/hal/ports/STM32/STM32L4xx/hal_lld.c (revision 14604)
@@ -106,6 +106,11 @@
106106 /* PWR clock enabled.*/
107107 rccEnablePWRInterface(false);
108108
109+ /* RTC APB clock enable.*/
110+#if (HAL_USE_RTC == TRUE) && defined(RCC_APBENR1_RTCAPBEN)
111+ rccEnableAPB1R1(RCC_APB1ENR1_RTCAPBEN, true)
112+#endif
113+
109114 /* Core voltage setup, backup domain access enabled and left open.*/
110115 PWR->CR1 = STM32_VOS | PWR_CR1_DBP;
111116 while ((PWR->SR2 & PWR_SR2_VOSF) != 0) /* Wait until regulator is */
--- branches/stable_21.6.x/os/hal/ports/STM32/STM32L4xx+/hal_lld.c (revision 14603)
+++ branches/stable_21.6.x/os/hal/ports/STM32/STM32L4xx+/hal_lld.c (revision 14604)
@@ -780,6 +780,11 @@
780780 among multiple drivers.*/
781781 rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, false);
782782
783+ /* RTC APB clock enable.*/
784+#if (HAL_USE_RTC == TRUE) && defined(RCC_APBENR1_RTCAPBEN)
785+ rccEnableAPB1R1(RCC_APB1ENR1_RTCAPBEN, true)
786+#endif
787+
783788 /* Static PWR configurations.*/
784789 hal_lld_set_static_pwr();
785790
@@ -839,6 +844,11 @@
839844 among multiple drivers.*/
840845 rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, false);
841846
847+ /* RTC APB clock enable.*/
848+#if (HAL_USE_RTC == TRUE) && defined(RCC_APBENR1_RTCAPBEN)
849+ rccEnableAPB1R1(RCC_APB1ENR1_RTCAPBEN, true)
850+#endif
851+
842852 /* Static PWR configurations.*/
843853 hal_lld_set_static_pwr();
844854
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