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chibios: Commit


Commit MetaInfo

Revision14606 (tree)
Time2021-07-22 18:38:28
Authorcinsights

Log Message

Adding STM32L4P/Q5

Change Summary

Incremental Difference

--- trunk/demos/STM32/RT-STM32L4P5ZG-NUCLEO144/cfg/chconf.h (nonexistent)
+++ trunk/demos/STM32/RT-STM32L4P5ZG-NUCLEO144/cfg/chconf.h (revision 14606)
@@ -0,0 +1,818 @@
1+/*
2+ ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
3+
4+ Licensed under the Apache License, Version 2.0 (the "License");
5+ you may not use this file except in compliance with the License.
6+ You may obtain a copy of the License at
7+
8+ http://www.apache.org/licenses/LICENSE-2.0
9+
10+ Unless required by applicable law or agreed to in writing, software
11+ distributed under the License is distributed on an "AS IS" BASIS,
12+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13+ See the License for the specific language governing permissions and
14+ limitations under the License.
15+*/
16+
17+/**
18+ * @file rt/templates/chconf.h
19+ * @brief Configuration file template.
20+ * @details A copy of this file must be placed in each project directory, it
21+ * contains the application specific kernel settings.
22+ *
23+ * @addtogroup config
24+ * @details Kernel related settings and hooks.
25+ * @{
26+ */
27+
28+#ifndef CHCONF_H
29+#define CHCONF_H
30+
31+#define _CHIBIOS_RT_CONF_
32+#define _CHIBIOS_RT_CONF_VER_7_0_
33+
34+/*===========================================================================*/
35+/**
36+ * @name System settings
37+ * @{
38+ */
39+/*===========================================================================*/
40+
41+/**
42+ * @brief Handling of instances.
43+ * @note If enabled then threads assigned to various instances can
44+ * interact each other using the same synchronization objects.
45+ * If disabled then each OS instance is a separate world, no
46+ * direct interactions are handled by the OS.
47+ */
48+#if !defined(CH_CFG_SMP_MODE)
49+#define CH_CFG_SMP_MODE FALSE
50+#endif
51+
52+/** @} */
53+
54+/*===========================================================================*/
55+/**
56+ * @name System timers settings
57+ * @{
58+ */
59+/*===========================================================================*/
60+
61+/**
62+ * @brief System time counter resolution.
63+ * @note Allowed values are 16, 32 or 64 bits.
64+ */
65+#if !defined(CH_CFG_ST_RESOLUTION)
66+#define CH_CFG_ST_RESOLUTION 32
67+#endif
68+
69+/**
70+ * @brief System tick frequency.
71+ * @details Frequency of the system timer that drives the system ticks. This
72+ * setting also defines the system tick time unit.
73+ */
74+#if !defined(CH_CFG_ST_FREQUENCY)
75+#define CH_CFG_ST_FREQUENCY 10000
76+#endif
77+
78+/**
79+ * @brief Time intervals data size.
80+ * @note Allowed values are 16, 32 or 64 bits.
81+ */
82+#if !defined(CH_CFG_INTERVALS_SIZE)
83+#define CH_CFG_INTERVALS_SIZE 32
84+#endif
85+
86+/**
87+ * @brief Time types data size.
88+ * @note Allowed values are 16 or 32 bits.
89+ */
90+#if !defined(CH_CFG_TIME_TYPES_SIZE)
91+#define CH_CFG_TIME_TYPES_SIZE 32
92+#endif
93+
94+/**
95+ * @brief Time delta constant for the tick-less mode.
96+ * @note If this value is zero then the system uses the classic
97+ * periodic tick. This value represents the minimum number
98+ * of ticks that is safe to specify in a timeout directive.
99+ * The value one is not valid, timeouts are rounded up to
100+ * this value.
101+ */
102+#if !defined(CH_CFG_ST_TIMEDELTA)
103+#define CH_CFG_ST_TIMEDELTA 2
104+#endif
105+
106+/** @} */
107+
108+/*===========================================================================*/
109+/**
110+ * @name Kernel parameters and options
111+ * @{
112+ */
113+/*===========================================================================*/
114+
115+/**
116+ * @brief Round robin interval.
117+ * @details This constant is the number of system ticks allowed for the
118+ * threads before preemption occurs. Setting this value to zero
119+ * disables the preemption for threads with equal priority and the
120+ * round robin becomes cooperative. Note that higher priority
121+ * threads can still preempt, the kernel is always preemptive.
122+ * @note Disabling the round robin preemption makes the kernel more compact
123+ * and generally faster.
124+ * @note The round robin preemption is not supported in tickless mode and
125+ * must be set to zero in that case.
126+ */
127+#if !defined(CH_CFG_TIME_QUANTUM)
128+#define CH_CFG_TIME_QUANTUM 0
129+#endif
130+
131+/**
132+ * @brief Idle thread automatic spawn suppression.
133+ * @details When this option is activated the function @p chSysInit()
134+ * does not spawn the idle thread. The application @p main()
135+ * function becomes the idle thread and must implement an
136+ * infinite loop.
137+ */
138+#if !defined(CH_CFG_NO_IDLE_THREAD)
139+#define CH_CFG_NO_IDLE_THREAD FALSE
140+#endif
141+
142+/** @} */
143+
144+/*===========================================================================*/
145+/**
146+ * @name Performance options
147+ * @{
148+ */
149+/*===========================================================================*/
150+
151+/**
152+ * @brief OS optimization.
153+ * @details If enabled then time efficient rather than space efficient code
154+ * is used when two possible implementations exist.
155+ *
156+ * @note This is not related to the compiler optimization options.
157+ * @note The default is @p TRUE.
158+ */
159+#if !defined(CH_CFG_OPTIMIZE_SPEED)
160+#define CH_CFG_OPTIMIZE_SPEED TRUE
161+#endif
162+
163+/** @} */
164+
165+/*===========================================================================*/
166+/**
167+ * @name Subsystem options
168+ * @{
169+ */
170+/*===========================================================================*/
171+
172+/**
173+ * @brief Time Measurement APIs.
174+ * @details If enabled then the time measurement APIs are included in
175+ * the kernel.
176+ *
177+ * @note The default is @p TRUE.
178+ */
179+#if !defined(CH_CFG_USE_TM)
180+#define CH_CFG_USE_TM TRUE
181+#endif
182+
183+/**
184+ * @brief Time Stamps APIs.
185+ * @details If enabled then the time time stamps APIs are included in
186+ * the kernel.
187+ *
188+ * @note The default is @p TRUE.
189+ */
190+#if !defined(CH_CFG_USE_TIMESTAMP)
191+#define CH_CFG_USE_TIMESTAMP TRUE
192+#endif
193+
194+/**
195+ * @brief Threads registry APIs.
196+ * @details If enabled then the registry APIs are included in the kernel.
197+ *
198+ * @note The default is @p TRUE.
199+ */
200+#if !defined(CH_CFG_USE_REGISTRY)
201+#define CH_CFG_USE_REGISTRY TRUE
202+#endif
203+
204+/**
205+ * @brief Threads synchronization APIs.
206+ * @details If enabled then the @p chThdWait() function is included in
207+ * the kernel.
208+ *
209+ * @note The default is @p TRUE.
210+ */
211+#if !defined(CH_CFG_USE_WAITEXIT)
212+#define CH_CFG_USE_WAITEXIT TRUE
213+#endif
214+
215+/**
216+ * @brief Semaphores APIs.
217+ * @details If enabled then the Semaphores APIs are included in the kernel.
218+ *
219+ * @note The default is @p TRUE.
220+ */
221+#if !defined(CH_CFG_USE_SEMAPHORES)
222+#define CH_CFG_USE_SEMAPHORES TRUE
223+#endif
224+
225+/**
226+ * @brief Semaphores queuing mode.
227+ * @details If enabled then the threads are enqueued on semaphores by
228+ * priority rather than in FIFO order.
229+ *
230+ * @note The default is @p FALSE. Enable this if you have special
231+ * requirements.
232+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
233+ */
234+#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY)
235+#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
236+#endif
237+
238+/**
239+ * @brief Mutexes APIs.
240+ * @details If enabled then the mutexes APIs are included in the kernel.
241+ *
242+ * @note The default is @p TRUE.
243+ */
244+#if !defined(CH_CFG_USE_MUTEXES)
245+#define CH_CFG_USE_MUTEXES TRUE
246+#endif
247+
248+/**
249+ * @brief Enables recursive behavior on mutexes.
250+ * @note Recursive mutexes are heavier and have an increased
251+ * memory footprint.
252+ *
253+ * @note The default is @p FALSE.
254+ * @note Requires @p CH_CFG_USE_MUTEXES.
255+ */
256+#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE)
257+#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
258+#endif
259+
260+/**
261+ * @brief Conditional Variables APIs.
262+ * @details If enabled then the conditional variables APIs are included
263+ * in the kernel.
264+ *
265+ * @note The default is @p TRUE.
266+ * @note Requires @p CH_CFG_USE_MUTEXES.
267+ */
268+#if !defined(CH_CFG_USE_CONDVARS)
269+#define CH_CFG_USE_CONDVARS TRUE
270+#endif
271+
272+/**
273+ * @brief Conditional Variables APIs with timeout.
274+ * @details If enabled then the conditional variables APIs with timeout
275+ * specification are included in the kernel.
276+ *
277+ * @note The default is @p TRUE.
278+ * @note Requires @p CH_CFG_USE_CONDVARS.
279+ */
280+#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT)
281+#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
282+#endif
283+
284+/**
285+ * @brief Events Flags APIs.
286+ * @details If enabled then the event flags APIs are included in the kernel.
287+ *
288+ * @note The default is @p TRUE.
289+ */
290+#if !defined(CH_CFG_USE_EVENTS)
291+#define CH_CFG_USE_EVENTS TRUE
292+#endif
293+
294+/**
295+ * @brief Events Flags APIs with timeout.
296+ * @details If enabled then the events APIs with timeout specification
297+ * are included in the kernel.
298+ *
299+ * @note The default is @p TRUE.
300+ * @note Requires @p CH_CFG_USE_EVENTS.
301+ */
302+#if !defined(CH_CFG_USE_EVENTS_TIMEOUT)
303+#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
304+#endif
305+
306+/**
307+ * @brief Synchronous Messages APIs.
308+ * @details If enabled then the synchronous messages APIs are included
309+ * in the kernel.
310+ *
311+ * @note The default is @p TRUE.
312+ */
313+#if !defined(CH_CFG_USE_MESSAGES)
314+#define CH_CFG_USE_MESSAGES TRUE
315+#endif
316+
317+/**
318+ * @brief Synchronous Messages queuing mode.
319+ * @details If enabled then messages are served by priority rather than in
320+ * FIFO order.
321+ *
322+ * @note The default is @p FALSE. Enable this if you have special
323+ * requirements.
324+ * @note Requires @p CH_CFG_USE_MESSAGES.
325+ */
326+#if !defined(CH_CFG_USE_MESSAGES_PRIORITY)
327+#define CH_CFG_USE_MESSAGES_PRIORITY FALSE
328+#endif
329+
330+/**
331+ * @brief Dynamic Threads APIs.
332+ * @details If enabled then the dynamic threads creation APIs are included
333+ * in the kernel.
334+ *
335+ * @note The default is @p TRUE.
336+ * @note Requires @p CH_CFG_USE_WAITEXIT.
337+ * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
338+ */
339+#if !defined(CH_CFG_USE_DYNAMIC)
340+#define CH_CFG_USE_DYNAMIC TRUE
341+#endif
342+
343+/** @} */
344+
345+/*===========================================================================*/
346+/**
347+ * @name OSLIB options
348+ * @{
349+ */
350+/*===========================================================================*/
351+
352+/**
353+ * @brief Mailboxes APIs.
354+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
355+ * included in the kernel.
356+ *
357+ * @note The default is @p TRUE.
358+ * @note Requires @p CH_CFG_USE_SEMAPHORES.
359+ */
360+#if !defined(CH_CFG_USE_MAILBOXES)
361+#define CH_CFG_USE_MAILBOXES TRUE
362+#endif
363+
364+/**
365+ * @brief Core Memory Manager APIs.
366+ * @details If enabled then the core memory manager APIs are included
367+ * in the kernel.
368+ *
369+ * @note The default is @p TRUE.
370+ */
371+#if !defined(CH_CFG_USE_MEMCORE)
372+#define CH_CFG_USE_MEMCORE TRUE
373+#endif
374+
375+/**
376+ * @brief Managed RAM size.
377+ * @details Size of the RAM area to be managed by the OS. If set to zero
378+ * then the whole available RAM is used. The core memory is made
379+ * available to the heap allocator and/or can be used directly through
380+ * the simplified core memory allocator.
381+ *
382+ * @note In order to let the OS manage the whole RAM the linker script must
383+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
384+ * @note Requires @p CH_CFG_USE_MEMCORE.
385+ */
386+#if !defined(CH_CFG_MEMCORE_SIZE)
387+#define CH_CFG_MEMCORE_SIZE 0
388+#endif
389+
390+/**
391+ * @brief Heap Allocator APIs.
392+ * @details If enabled then the memory heap allocator APIs are included
393+ * in the kernel.
394+ *
395+ * @note The default is @p TRUE.
396+ * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or
397+ * @p CH_CFG_USE_SEMAPHORES.
398+ * @note Mutexes are recommended.
399+ */
400+#if !defined(CH_CFG_USE_HEAP)
401+#define CH_CFG_USE_HEAP TRUE
402+#endif
403+
404+/**
405+ * @brief Memory Pools Allocator APIs.
406+ * @details If enabled then the memory pools allocator APIs are included
407+ * in the kernel.
408+ *
409+ * @note The default is @p TRUE.
410+ */
411+#if !defined(CH_CFG_USE_MEMPOOLS)
412+#define CH_CFG_USE_MEMPOOLS TRUE
413+#endif
414+
415+/**
416+ * @brief Objects FIFOs APIs.
417+ * @details If enabled then the objects FIFOs APIs are included
418+ * in the kernel.
419+ *
420+ * @note The default is @p TRUE.
421+ */
422+#if !defined(CH_CFG_USE_OBJ_FIFOS)
423+#define CH_CFG_USE_OBJ_FIFOS TRUE
424+#endif
425+
426+/**
427+ * @brief Pipes APIs.
428+ * @details If enabled then the pipes APIs are included
429+ * in the kernel.
430+ *
431+ * @note The default is @p TRUE.
432+ */
433+#if !defined(CH_CFG_USE_PIPES)
434+#define CH_CFG_USE_PIPES TRUE
435+#endif
436+
437+/**
438+ * @brief Objects Caches APIs.
439+ * @details If enabled then the objects caches APIs are included
440+ * in the kernel.
441+ *
442+ * @note The default is @p TRUE.
443+ */
444+#if !defined(CH_CFG_USE_OBJ_CACHES)
445+#define CH_CFG_USE_OBJ_CACHES TRUE
446+#endif
447+
448+/**
449+ * @brief Delegate threads APIs.
450+ * @details If enabled then the delegate threads APIs are included
451+ * in the kernel.
452+ *
453+ * @note The default is @p TRUE.
454+ */
455+#if !defined(CH_CFG_USE_DELEGATES)
456+#define CH_CFG_USE_DELEGATES TRUE
457+#endif
458+
459+/**
460+ * @brief Jobs Queues APIs.
461+ * @details If enabled then the jobs queues APIs are included
462+ * in the kernel.
463+ *
464+ * @note The default is @p TRUE.
465+ */
466+#if !defined(CH_CFG_USE_JOBS)
467+#define CH_CFG_USE_JOBS TRUE
468+#endif
469+
470+/** @} */
471+
472+/*===========================================================================*/
473+/**
474+ * @name Objects factory options
475+ * @{
476+ */
477+/*===========================================================================*/
478+
479+/**
480+ * @brief Objects Factory APIs.
481+ * @details If enabled then the objects factory APIs are included in the
482+ * kernel.
483+ *
484+ * @note The default is @p FALSE.
485+ */
486+#if !defined(CH_CFG_USE_FACTORY)
487+#define CH_CFG_USE_FACTORY TRUE
488+#endif
489+
490+/**
491+ * @brief Maximum length for object names.
492+ * @details If the specified length is zero then the name is stored by
493+ * pointer but this could have unintended side effects.
494+ */
495+#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH)
496+#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8
497+#endif
498+
499+/**
500+ * @brief Enables the registry of generic objects.
501+ */
502+#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY)
503+#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE
504+#endif
505+
506+/**
507+ * @brief Enables factory for generic buffers.
508+ */
509+#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS)
510+#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE
511+#endif
512+
513+/**
514+ * @brief Enables factory for semaphores.
515+ */
516+#if !defined(CH_CFG_FACTORY_SEMAPHORES)
517+#define CH_CFG_FACTORY_SEMAPHORES TRUE
518+#endif
519+
520+/**
521+ * @brief Enables factory for mailboxes.
522+ */
523+#if !defined(CH_CFG_FACTORY_MAILBOXES)
524+#define CH_CFG_FACTORY_MAILBOXES TRUE
525+#endif
526+
527+/**
528+ * @brief Enables factory for objects FIFOs.
529+ */
530+#if !defined(CH_CFG_FACTORY_OBJ_FIFOS)
531+#define CH_CFG_FACTORY_OBJ_FIFOS TRUE
532+#endif
533+
534+/**
535+ * @brief Enables factory for Pipes.
536+ */
537+#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__)
538+#define CH_CFG_FACTORY_PIPES TRUE
539+#endif
540+
541+/** @} */
542+
543+/*===========================================================================*/
544+/**
545+ * @name Debug options
546+ * @{
547+ */
548+/*===========================================================================*/
549+
550+/**
551+ * @brief Debug option, kernel statistics.
552+ *
553+ * @note The default is @p FALSE.
554+ */
555+#if !defined(CH_DBG_STATISTICS)
556+#define CH_DBG_STATISTICS FALSE
557+#endif
558+
559+/**
560+ * @brief Debug option, system state check.
561+ * @details If enabled the correct call protocol for system APIs is checked
562+ * at runtime.
563+ *
564+ * @note The default is @p FALSE.
565+ */
566+#if !defined(CH_DBG_SYSTEM_STATE_CHECK)
567+#define CH_DBG_SYSTEM_STATE_CHECK FALSE
568+#endif
569+
570+/**
571+ * @brief Debug option, parameters checks.
572+ * @details If enabled then the checks on the API functions input
573+ * parameters are activated.
574+ *
575+ * @note The default is @p FALSE.
576+ */
577+#if !defined(CH_DBG_ENABLE_CHECKS)
578+#define CH_DBG_ENABLE_CHECKS FALSE
579+#endif
580+
581+/**
582+ * @brief Debug option, consistency checks.
583+ * @details If enabled then all the assertions in the kernel code are
584+ * activated. This includes consistency checks inside the kernel,
585+ * runtime anomalies and port-defined checks.
586+ *
587+ * @note The default is @p FALSE.
588+ */
589+#if !defined(CH_DBG_ENABLE_ASSERTS)
590+#define CH_DBG_ENABLE_ASSERTS FALSE
591+#endif
592+
593+/**
594+ * @brief Debug option, trace buffer.
595+ * @details If enabled then the trace buffer is activated.
596+ *
597+ * @note The default is @p CH_DBG_TRACE_MASK_DISABLED.
598+ */
599+#if !defined(CH_DBG_TRACE_MASK)
600+#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED
601+#endif
602+
603+/**
604+ * @brief Trace buffer entries.
605+ * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is
606+ * different from @p CH_DBG_TRACE_MASK_DISABLED.
607+ */
608+#if !defined(CH_DBG_TRACE_BUFFER_SIZE)
609+#define CH_DBG_TRACE_BUFFER_SIZE 128
610+#endif
611+
612+/**
613+ * @brief Debug option, stack checks.
614+ * @details If enabled then a runtime stack check is performed.
615+ *
616+ * @note The default is @p FALSE.
617+ * @note The stack check is performed in a architecture/port dependent way.
618+ * It may not be implemented or some ports.
619+ * @note The default failure mode is to halt the system with the global
620+ * @p panic_msg variable set to @p NULL.
621+ */
622+#if !defined(CH_DBG_ENABLE_STACK_CHECK)
623+#define CH_DBG_ENABLE_STACK_CHECK FALSE
624+#endif
625+
626+/**
627+ * @brief Debug option, stacks initialization.
628+ * @details If enabled then the threads working area is filled with a byte
629+ * value when a thread is created. This can be useful for the
630+ * runtime measurement of the used stack.
631+ *
632+ * @note The default is @p FALSE.
633+ */
634+#if !defined(CH_DBG_FILL_THREADS)
635+#define CH_DBG_FILL_THREADS FALSE
636+#endif
637+
638+/**
639+ * @brief Debug option, threads profiling.
640+ * @details If enabled then a field is added to the @p thread_t structure that
641+ * counts the system ticks occurred while executing the thread.
642+ *
643+ * @note The default is @p FALSE.
644+ * @note This debug option is not currently compatible with the
645+ * tickless mode.
646+ */
647+#if !defined(CH_DBG_THREADS_PROFILING)
648+#define CH_DBG_THREADS_PROFILING FALSE
649+#endif
650+
651+/** @} */
652+
653+/*===========================================================================*/
654+/**
655+ * @name Kernel hooks
656+ * @{
657+ */
658+/*===========================================================================*/
659+
660+/**
661+ * @brief System structure extension.
662+ * @details User fields added to the end of the @p ch_system_t structure.
663+ */
664+#define CH_CFG_SYSTEM_EXTRA_FIELDS \
665+ /* Add system custom fields here.*/
666+
667+/**
668+ * @brief System initialization hook.
669+ * @details User initialization code added to the @p chSysInit() function
670+ * just before interrupts are enabled globally.
671+ */
672+#define CH_CFG_SYSTEM_INIT_HOOK() { \
673+ /* Add system initialization code here.*/ \
674+}
675+
676+/**
677+ * @brief OS instance structure extension.
678+ * @details User fields added to the end of the @p os_instance_t structure.
679+ */
680+#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \
681+ /* Add OS instance custom fields here.*/
682+
683+/**
684+ * @brief OS instance initialization hook.
685+ *
686+ * @param[in] oip pointer to the @p os_instance_t structure
687+ */
688+#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \
689+ /* Add OS instance initialization code here.*/ \
690+}
691+
692+/**
693+ * @brief Threads descriptor structure extension.
694+ * @details User fields added to the end of the @p thread_t structure.
695+ */
696+#define CH_CFG_THREAD_EXTRA_FIELDS \
697+ /* Add threads custom fields here.*/
698+
699+/**
700+ * @brief Threads initialization hook.
701+ * @details User initialization code added to the @p _thread_init() function.
702+ *
703+ * @note It is invoked from within @p _thread_init() and implicitly from all
704+ * the threads creation APIs.
705+ *
706+ * @param[in] tp pointer to the @p thread_t structure
707+ */
708+#define CH_CFG_THREAD_INIT_HOOK(tp) { \
709+ /* Add threads initialization code here.*/ \
710+}
711+
712+/**
713+ * @brief Threads finalization hook.
714+ * @details User finalization code added to the @p chThdExit() API.
715+ *
716+ * @param[in] tp pointer to the @p thread_t structure
717+ */
718+#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
719+ /* Add threads finalization code here.*/ \
720+}
721+
722+/**
723+ * @brief Context switch hook.
724+ * @details This hook is invoked just before switching between threads.
725+ *
726+ * @param[in] ntp thread being switched in
727+ * @param[in] otp thread being switched out
728+ */
729+#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
730+ /* Context switch code here.*/ \
731+}
732+
733+/**
734+ * @brief ISR enter hook.
735+ */
736+#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
737+ /* IRQ prologue code here.*/ \
738+}
739+
740+/**
741+ * @brief ISR exit hook.
742+ */
743+#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
744+ /* IRQ epilogue code here.*/ \
745+}
746+
747+/**
748+ * @brief Idle thread enter hook.
749+ * @note This hook is invoked within a critical zone, no OS functions
750+ * should be invoked from here.
751+ * @note This macro can be used to activate a power saving mode.
752+ */
753+#define CH_CFG_IDLE_ENTER_HOOK() { \
754+ /* Idle-enter code here.*/ \
755+}
756+
757+/**
758+ * @brief Idle thread leave hook.
759+ * @note This hook is invoked within a critical zone, no OS functions
760+ * should be invoked from here.
761+ * @note This macro can be used to deactivate a power saving mode.
762+ */
763+#define CH_CFG_IDLE_LEAVE_HOOK() { \
764+ /* Idle-leave code here.*/ \
765+}
766+
767+/**
768+ * @brief Idle Loop hook.
769+ * @details This hook is continuously invoked by the idle thread loop.
770+ */
771+#define CH_CFG_IDLE_LOOP_HOOK() { \
772+ /* Idle loop code here.*/ \
773+}
774+
775+/**
776+ * @brief System tick event hook.
777+ * @details This hook is invoked in the system tick handler immediately
778+ * after processing the virtual timers queue.
779+ */
780+#define CH_CFG_SYSTEM_TICK_HOOK() { \
781+ /* System tick event code here.*/ \
782+}
783+
784+/**
785+ * @brief System halt hook.
786+ * @details This hook is invoked in case to a system halting error before
787+ * the system is halted.
788+ */
789+#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
790+ /* System halt code here.*/ \
791+}
792+
793+/**
794+ * @brief Trace hook.
795+ * @details This hook is invoked each time a new record is written in the
796+ * trace buffer.
797+ */
798+#define CH_CFG_TRACE_HOOK(tep) { \
799+ /* Trace code here.*/ \
800+}
801+
802+/**
803+ * @brief Runtime Faults Collection Unit hook.
804+ * @details This hook is invoked each time new faults are collected and stored.
805+ */
806+#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \
807+ /* Faults handling code here.*/ \
808+}
809+
810+/** @} */
811+
812+/*===========================================================================*/
813+/* Port-specific settings (override port settings defaulted in chcore.h). */
814+/*===========================================================================*/
815+
816+#endif /* CHCONF_H */
817+
818+/** @} */
--- trunk/demos/STM32/RT-STM32L4P5ZG-NUCLEO144/cfg/halconf.h (nonexistent)
+++ trunk/demos/STM32/RT-STM32L4P5ZG-NUCLEO144/cfg/halconf.h (revision 14606)
@@ -0,0 +1,551 @@
1+/*
2+ ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
3+
4+ Licensed under the Apache License, Version 2.0 (the "License");
5+ you may not use this file except in compliance with the License.
6+ You may obtain a copy of the License at
7+
8+ http://www.apache.org/licenses/LICENSE-2.0
9+
10+ Unless required by applicable law or agreed to in writing, software
11+ distributed under the License is distributed on an "AS IS" BASIS,
12+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13+ See the License for the specific language governing permissions and
14+ limitations under the License.
15+*/
16+
17+/**
18+ * @file templates/halconf.h
19+ * @brief HAL configuration header.
20+ * @details HAL configuration file, this file allows to enable or disable the
21+ * various device drivers from your application. You may also use
22+ * this file in order to override the device drivers default settings.
23+ *
24+ * @addtogroup HAL_CONF
25+ * @{
26+ */
27+
28+#ifndef HALCONF_H
29+#define HALCONF_H
30+
31+#define _CHIBIOS_HAL_CONF_
32+#define _CHIBIOS_HAL_CONF_VER_7_1_
33+
34+#include "mcuconf.h"
35+
36+/**
37+ * @brief Enables the PAL subsystem.
38+ */
39+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
40+#define HAL_USE_PAL TRUE
41+#endif
42+
43+/**
44+ * @brief Enables the ADC subsystem.
45+ */
46+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
47+#define HAL_USE_ADC FALSE
48+#endif
49+
50+/**
51+ * @brief Enables the CAN subsystem.
52+ */
53+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
54+#define HAL_USE_CAN FALSE
55+#endif
56+
57+/**
58+ * @brief Enables the cryptographic subsystem.
59+ */
60+#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__)
61+#define HAL_USE_CRY FALSE
62+#endif
63+
64+/**
65+ * @brief Enables the DAC subsystem.
66+ */
67+#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
68+#define HAL_USE_DAC FALSE
69+#endif
70+
71+/**
72+ * @brief Enables the EFlash subsystem.
73+ */
74+#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__)
75+#define HAL_USE_EFL FALSE
76+#endif
77+
78+/**
79+ * @brief Enables the GPT subsystem.
80+ */
81+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
82+#define HAL_USE_GPT FALSE
83+#endif
84+
85+/**
86+ * @brief Enables the I2C subsystem.
87+ */
88+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
89+#define HAL_USE_I2C FALSE
90+#endif
91+
92+/**
93+ * @brief Enables the I2S subsystem.
94+ */
95+#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
96+#define HAL_USE_I2S FALSE
97+#endif
98+
99+/**
100+ * @brief Enables the ICU subsystem.
101+ */
102+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
103+#define HAL_USE_ICU FALSE
104+#endif
105+
106+/**
107+ * @brief Enables the MAC subsystem.
108+ */
109+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
110+#define HAL_USE_MAC FALSE
111+#endif
112+
113+/**
114+ * @brief Enables the MMC_SPI subsystem.
115+ */
116+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
117+#define HAL_USE_MMC_SPI FALSE
118+#endif
119+
120+/**
121+ * @brief Enables the PWM subsystem.
122+ */
123+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
124+#define HAL_USE_PWM FALSE
125+#endif
126+
127+/**
128+ * @brief Enables the RTC subsystem.
129+ */
130+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
131+#define HAL_USE_RTC FALSE
132+#endif
133+
134+/**
135+ * @brief Enables the SDC subsystem.
136+ */
137+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
138+#define HAL_USE_SDC FALSE
139+#endif
140+
141+/**
142+ * @brief Enables the SERIAL subsystem.
143+ */
144+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
145+#define HAL_USE_SERIAL TRUE
146+#endif
147+
148+/**
149+ * @brief Enables the SERIAL over USB subsystem.
150+ */
151+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
152+#define HAL_USE_SERIAL_USB FALSE
153+#endif
154+
155+/**
156+ * @brief Enables the SIO subsystem.
157+ */
158+#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__)
159+#define HAL_USE_SIO FALSE
160+#endif
161+
162+/**
163+ * @brief Enables the SPI subsystem.
164+ */
165+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
166+#define HAL_USE_SPI FALSE
167+#endif
168+
169+/**
170+ * @brief Enables the TRNG subsystem.
171+ */
172+#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__)
173+#define HAL_USE_TRNG FALSE
174+#endif
175+
176+/**
177+ * @brief Enables the UART subsystem.
178+ */
179+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
180+#define HAL_USE_UART FALSE
181+#endif
182+
183+/**
184+ * @brief Enables the USB subsystem.
185+ */
186+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
187+#define HAL_USE_USB FALSE
188+#endif
189+
190+/**
191+ * @brief Enables the WDG subsystem.
192+ */
193+#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
194+#define HAL_USE_WDG FALSE
195+#endif
196+
197+/**
198+ * @brief Enables the WSPI subsystem.
199+ */
200+#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__)
201+#define HAL_USE_WSPI FALSE
202+#endif
203+
204+/*===========================================================================*/
205+/* PAL driver related settings. */
206+/*===========================================================================*/
207+
208+/**
209+ * @brief Enables synchronous APIs.
210+ * @note Disabling this option saves both code and data space.
211+ */
212+#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__)
213+#define PAL_USE_CALLBACKS FALSE
214+#endif
215+
216+/**
217+ * @brief Enables synchronous APIs.
218+ * @note Disabling this option saves both code and data space.
219+ */
220+#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__)
221+#define PAL_USE_WAIT FALSE
222+#endif
223+
224+/*===========================================================================*/
225+/* ADC driver related settings. */
226+/*===========================================================================*/
227+
228+/**
229+ * @brief Enables synchronous APIs.
230+ * @note Disabling this option saves both code and data space.
231+ */
232+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
233+#define ADC_USE_WAIT TRUE
234+#endif
235+
236+/**
237+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
238+ * @note Disabling this option saves both code and data space.
239+ */
240+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
241+#define ADC_USE_MUTUAL_EXCLUSION TRUE
242+#endif
243+
244+/*===========================================================================*/
245+/* CAN driver related settings. */
246+/*===========================================================================*/
247+
248+/**
249+ * @brief Sleep mode related APIs inclusion switch.
250+ */
251+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
252+#define CAN_USE_SLEEP_MODE TRUE
253+#endif
254+
255+/**
256+ * @brief Enforces the driver to use direct callbacks rather than OSAL events.
257+ */
258+#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__)
259+#define CAN_ENFORCE_USE_CALLBACKS FALSE
260+#endif
261+
262+/*===========================================================================*/
263+/* CRY driver related settings. */
264+/*===========================================================================*/
265+
266+/**
267+ * @brief Enables the SW fall-back of the cryptographic driver.
268+ * @details When enabled, this option, activates a fall-back software
269+ * implementation for algorithms not supported by the underlying
270+ * hardware.
271+ * @note Fall-back implementations may not be present for all algorithms.
272+ */
273+#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__)
274+#define HAL_CRY_USE_FALLBACK FALSE
275+#endif
276+
277+/**
278+ * @brief Makes the driver forcibly use the fall-back implementations.
279+ */
280+#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__)
281+#define HAL_CRY_ENFORCE_FALLBACK FALSE
282+#endif
283+
284+/*===========================================================================*/
285+/* DAC driver related settings. */
286+/*===========================================================================*/
287+
288+/**
289+ * @brief Enables synchronous APIs.
290+ * @note Disabling this option saves both code and data space.
291+ */
292+#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__)
293+#define DAC_USE_WAIT TRUE
294+#endif
295+
296+/**
297+ * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs.
298+ * @note Disabling this option saves both code and data space.
299+ */
300+#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
301+#define DAC_USE_MUTUAL_EXCLUSION TRUE
302+#endif
303+
304+/*===========================================================================*/
305+/* I2C driver related settings. */
306+/*===========================================================================*/
307+
308+/**
309+ * @brief Enables the mutual exclusion APIs on the I2C bus.
310+ */
311+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
312+#define I2C_USE_MUTUAL_EXCLUSION TRUE
313+#endif
314+
315+/*===========================================================================*/
316+/* MAC driver related settings. */
317+/*===========================================================================*/
318+
319+/**
320+ * @brief Enables the zero-copy API.
321+ */
322+#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
323+#define MAC_USE_ZERO_COPY FALSE
324+#endif
325+
326+/**
327+ * @brief Enables an event sources for incoming packets.
328+ */
329+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
330+#define MAC_USE_EVENTS TRUE
331+#endif
332+
333+/*===========================================================================*/
334+/* MMC_SPI driver related settings. */
335+/*===========================================================================*/
336+
337+/**
338+ * @brief Delays insertions.
339+ * @details If enabled this options inserts delays into the MMC waiting
340+ * routines releasing some extra CPU time for the threads with
341+ * lower priority, this may slow down the driver a bit however.
342+ * This option is recommended also if the SPI driver does not
343+ * use a DMA channel and heavily loads the CPU.
344+ */
345+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
346+#define MMC_NICE_WAITING TRUE
347+#endif
348+
349+/*===========================================================================*/
350+/* SDC driver related settings. */
351+/*===========================================================================*/
352+
353+/**
354+ * @brief Number of initialization attempts before rejecting the card.
355+ * @note Attempts are performed at 10mS intervals.
356+ */
357+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
358+#define SDC_INIT_RETRY 100
359+#endif
360+
361+/**
362+ * @brief Include support for MMC cards.
363+ * @note MMC support is not yet implemented so this option must be kept
364+ * at @p FALSE.
365+ */
366+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
367+#define SDC_MMC_SUPPORT FALSE
368+#endif
369+
370+/**
371+ * @brief Delays insertions.
372+ * @details If enabled this options inserts delays into the MMC waiting
373+ * routines releasing some extra CPU time for the threads with
374+ * lower priority, this may slow down the driver a bit however.
375+ */
376+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
377+#define SDC_NICE_WAITING TRUE
378+#endif
379+
380+/**
381+ * @brief OCR initialization constant for V20 cards.
382+ */
383+#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__)
384+#define SDC_INIT_OCR_V20 0x50FF8000U
385+#endif
386+
387+/**
388+ * @brief OCR initialization constant for non-V20 cards.
389+ */
390+#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__)
391+#define SDC_INIT_OCR 0x80100000U
392+#endif
393+
394+/*===========================================================================*/
395+/* SERIAL driver related settings. */
396+/*===========================================================================*/
397+
398+/**
399+ * @brief Default bit rate.
400+ * @details Configuration parameter, this is the baud rate selected for the
401+ * default configuration.
402+ */
403+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
404+#define SERIAL_DEFAULT_BITRATE 38400
405+#endif
406+
407+/**
408+ * @brief Serial buffers size.
409+ * @details Configuration parameter, you can change the depth of the queue
410+ * buffers depending on the requirements of your application.
411+ * @note The default is 16 bytes for both the transmission and receive
412+ * buffers.
413+ */
414+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
415+#define SERIAL_BUFFERS_SIZE 16
416+#endif
417+
418+/*===========================================================================*/
419+/* SIO driver related settings. */
420+/*===========================================================================*/
421+
422+/**
423+ * @brief Default bit rate.
424+ * @details Configuration parameter, this is the baud rate selected for the
425+ * default configuration.
426+ */
427+#if !defined(SIO_DEFAULT_BITRATE) || defined(__DOXYGEN__)
428+#define SIO_DEFAULT_BITRATE 38400
429+#endif
430+
431+/**
432+ * @brief Support for thread synchronization API.
433+ */
434+#if !defined(SIO_USE_SYNCHRONIZATION) || defined(__DOXYGEN__)
435+#define SIO_USE_SYNCHRONIZATION TRUE
436+#endif
437+
438+/*===========================================================================*/
439+/* SERIAL_USB driver related setting. */
440+/*===========================================================================*/
441+
442+/**
443+ * @brief Serial over USB buffers size.
444+ * @details Configuration parameter, the buffer size must be a multiple of
445+ * the USB data endpoint maximum packet size.
446+ * @note The default is 256 bytes for both the transmission and receive
447+ * buffers.
448+ */
449+#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
450+#define SERIAL_USB_BUFFERS_SIZE 256
451+#endif
452+
453+/**
454+ * @brief Serial over USB number of buffers.
455+ * @note The default is 2 buffers.
456+ */
457+#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)
458+#define SERIAL_USB_BUFFERS_NUMBER 2
459+#endif
460+
461+/*===========================================================================*/
462+/* SPI driver related settings. */
463+/*===========================================================================*/
464+
465+/**
466+ * @brief Enables synchronous APIs.
467+ * @note Disabling this option saves both code and data space.
468+ */
469+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
470+#define SPI_USE_WAIT TRUE
471+#endif
472+
473+/**
474+ * @brief Enables circular transfers APIs.
475+ * @note Disabling this option saves both code and data space.
476+ */
477+#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__)
478+#define SPI_USE_CIRCULAR FALSE
479+#endif
480+
481+/**
482+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
483+ * @note Disabling this option saves both code and data space.
484+ */
485+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
486+#define SPI_USE_MUTUAL_EXCLUSION TRUE
487+#endif
488+
489+/**
490+ * @brief Handling method for SPI CS line.
491+ * @note Disabling this option saves both code and data space.
492+ */
493+#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__)
494+#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD
495+#endif
496+
497+/*===========================================================================*/
498+/* UART driver related settings. */
499+/*===========================================================================*/
500+
501+/**
502+ * @brief Enables synchronous APIs.
503+ * @note Disabling this option saves both code and data space.
504+ */
505+#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)
506+#define UART_USE_WAIT FALSE
507+#endif
508+
509+/**
510+ * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.
511+ * @note Disabling this option saves both code and data space.
512+ */
513+#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
514+#define UART_USE_MUTUAL_EXCLUSION FALSE
515+#endif
516+
517+/*===========================================================================*/
518+/* USB driver related settings. */
519+/*===========================================================================*/
520+
521+/**
522+ * @brief Enables synchronous APIs.
523+ * @note Disabling this option saves both code and data space.
524+ */
525+#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
526+#define USB_USE_WAIT FALSE
527+#endif
528+
529+/*===========================================================================*/
530+/* WSPI driver related settings. */
531+/*===========================================================================*/
532+
533+/**
534+ * @brief Enables synchronous APIs.
535+ * @note Disabling this option saves both code and data space.
536+ */
537+#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__)
538+#define WSPI_USE_WAIT TRUE
539+#endif
540+
541+/**
542+ * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs.
543+ * @note Disabling this option saves both code and data space.
544+ */
545+#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
546+#define WSPI_USE_MUTUAL_EXCLUSION TRUE
547+#endif
548+
549+#endif /* HALCONF_H */
550+
551+/** @} */
--- trunk/demos/STM32/RT-STM32L4P5ZG-NUCLEO144/cfg/mcuconf.h (nonexistent)
+++ trunk/demos/STM32/RT-STM32L4P5ZG-NUCLEO144/cfg/mcuconf.h (revision 14606)
@@ -0,0 +1,395 @@
1+/*
2+ ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
3+
4+ Licensed under the Apache License, Version 2.0 (the "License");
5+ you may not use this file except in compliance with the License.
6+ You may obtain a copy of the License at
7+
8+ http://www.apache.org/licenses/LICENSE-2.0
9+
10+ Unless required by applicable law or agreed to in writing, software
11+ distributed under the License is distributed on an "AS IS" BASIS,
12+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13+ See the License for the specific language governing permissions and
14+ limitations under the License.
15+*/
16+
17+/*
18+ * STM32L4xx drivers configuration.
19+ * The following settings override the default settings present in
20+ * the various device driver implementation headers.
21+ * Note that the settings for each driver only have effect if the whole
22+ * driver is enabled in halconf.h.
23+ *
24+ * IRQ priorities:
25+ * 15...0 Lowest...Highest.
26+ *
27+ * DMA priorities:
28+ * 0...3 Lowest...Highest.
29+ */
30+
31+#ifndef MCUCONF_H
32+#define MCUCONF_H
33+
34+#define STM32L4xx_MCUCONF
35+#define STM32L4P5_MCUCONF
36+#define STM32L4Q5_MCUCONF
37+#define STM32L4R5_MCUCONF
38+#define STM32L4S5_MCUCONF
39+#define STM32L4R7_MCUCONF
40+#define STM32L4S7_MCUCONF
41+#define STM32L4R9_MCUCONF
42+#define STM32L4S9_MCUCONF
43+
44+/*
45+ * HAL driver system settings.
46+ */
47+#define STM32_NO_INIT FALSE
48+#define STM32_CLOCK_DYNAMIC TRUE
49+#define STM32_VOS STM32_VOS_RANGE1
50+#define STM32_PWR_BOOST TRUE
51+#define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0 | PWR_CR2_IOSV)
52+#define STM32_PWR_CR3 (PWR_CR3_EIWF)
53+#define STM32_PWR_CR4 (0U)
54+#define STM32_PWR_PUCRA (0U)
55+#define STM32_PWR_PDCRA (0U)
56+#define STM32_PWR_PUCRB (0U)
57+#define STM32_PWR_PDCRB (0U)
58+#define STM32_PWR_PUCRC (0U)
59+#define STM32_PWR_PDCRC (0U)
60+#define STM32_PWR_PUCRD (0U)
61+#define STM32_PWR_PDCRD (0U)
62+#define STM32_PWR_PUCRE (0U)
63+#define STM32_PWR_PDCRE (0U)
64+#define STM32_PWR_PUCRF (0U)
65+#define STM32_PWR_PDCRF (0U)
66+#define STM32_PWR_PUCRG (0U)
67+#define STM32_PWR_PDCRG (0U)
68+#define STM32_PWR_PUCRH (0U)
69+#define STM32_PWR_PDCRH (0U)
70+#define STM32_PWR_PUCRI (0U)
71+#define STM32_PWR_PDCRI (0U)
72+#define STM32_HSI16_ENABLED FALSE
73+#define STM32_HSI48_ENABLED FALSE
74+#define STM32_LSI_ENABLED TRUE
75+#define STM32_HSE_ENABLED FALSE
76+#define STM32_LSE_ENABLED FALSE
77+#define STM32_MSIPLL_ENABLED FALSE
78+#define STM32_MSIRANGE STM32_MSIRANGE_4M
79+#define STM32_MSISRANGE STM32_MSISRANGE_4M
80+#define STM32_SW STM32_SW_PLL
81+#define STM32_PLLSRC STM32_PLLSRC_MSI
82+#define STM32_PLLM_VALUE 1
83+#define STM32_PLLN_VALUE 60
84+#define STM32_PLLPDIV_VALUE 0
85+#define STM32_PLLP_VALUE 7
86+#define STM32_PLLQ_VALUE 4
87+#define STM32_PLLR_VALUE 2
88+#define STM32_HPRE STM32_HPRE_DIV1
89+#define STM32_PPRE1 STM32_PPRE1_DIV1
90+#define STM32_PPRE2 STM32_PPRE2_DIV1
91+#define STM32_STOPWUCK STM32_STOPWUCK_MSI
92+#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
93+#define STM32_MCOPRE STM32_MCOPRE_DIV1
94+#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
95+#define STM32_PLLSAI1M_VALUE 1
96+#define STM32_PLLSAI1N_VALUE 72
97+#define STM32_PLLSAI1PDIV_VALUE 6
98+#define STM32_PLLSAI1P_VALUE 7
99+#define STM32_PLLSAI1Q_VALUE 6
100+#define STM32_PLLSAI1R_VALUE 6
101+#define STM32_PLLSAI2M_VALUE 1
102+#define STM32_PLLSAI2N_VALUE 72
103+#define STM32_PLLSAI2PDIV_VALUE 6
104+#define STM32_PLLSAI2P_VALUE 7
105+#define STM32_PLLSAI2Q_VALUE 6
106+#define STM32_PLLSAI2R_VALUE 6
107+#define STM32_PLLSAI2DIVR STM32_PLLSAI2DIVR_DIV16
108+
109+/*
110+ * Peripherals clock sources.
111+ */
112+#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
113+#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
114+#define STM32_USART3SEL STM32_USART3SEL_SYSCLK
115+#define STM32_UART4SEL STM32_UART4SEL_SYSCLK
116+#define STM32_UART5SEL STM32_UART5SEL_SYSCLK
117+#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
118+#define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK
119+#define STM32_I2C2SEL STM32_I2C2SEL_SYSCLK
120+#define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK
121+#define STM32_I2C4SEL STM32_I2C4SEL_SYSCLK
122+#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
123+#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
124+#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1
125+#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
126+#define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK2
127+#define STM32_ADFSDMSEL STM32_ADFSDMSEL_SAI1CLK
128+#define STM32_SAI1SEL STM32_SAI1SEL_OFF
129+#define STM32_SAI2SEL STM32_SAI2SEL_OFF
130+#define STM32_DSISEL STM32_DSISEL_DSIPHY
131+#define STM32_SDMMCSEL STM32_SDMMCSEL_48CLK
132+#define STM32_OSPISEL STM32_OSPISEL_SYSCLK
133+#define STM32_RTCSEL STM32_RTCSEL_LSI
134+
135+/*
136+ * IRQ system settings.
137+ */
138+#define STM32_IRQ_EXTI0_PRIORITY 6
139+#define STM32_IRQ_EXTI1_PRIORITY 6
140+#define STM32_IRQ_EXTI2_PRIORITY 6
141+#define STM32_IRQ_EXTI3_PRIORITY 6
142+#define STM32_IRQ_EXTI4_PRIORITY 6
143+#define STM32_IRQ_EXTI5_9_PRIORITY 6
144+#define STM32_IRQ_EXTI10_15_PRIORITY 6
145+#define STM32_IRQ_EXTI1635_38_PRIORITY 6
146+#define STM32_IRQ_EXTI18_PRIORITY 6
147+#define STM32_IRQ_EXTI19_PRIORITY 6
148+#define STM32_IRQ_EXTI20_PRIORITY 6
149+#define STM32_IRQ_EXTI21_22_PRIORITY 6
150+
151+#define STM32_IRQ_SDMMC1_PRIORITY 9
152+
153+#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY 7
154+#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY 7
155+#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7
156+#define STM32_IRQ_TIM1_CC_PRIORITY 7
157+#define STM32_IRQ_TIM2_PRIORITY 7
158+#define STM32_IRQ_TIM3_PRIORITY 7
159+#define STM32_IRQ_TIM4_PRIORITY 7
160+#define STM32_IRQ_TIM5_PRIORITY 7
161+#define STM32_IRQ_TIM6_PRIORITY 7
162+#define STM32_IRQ_TIM7_PRIORITY 7
163+#define STM32_IRQ_TIM8_UP_PRIORITY 7
164+#define STM32_IRQ_TIM8_CC_PRIORITY 7
165+
166+#define STM32_IRQ_USART1_PRIORITY 12
167+#define STM32_IRQ_USART2_PRIORITY 12
168+#define STM32_IRQ_USART3_PRIORITY 12
169+#define STM32_IRQ_UART4_PRIORITY 12
170+#define STM32_IRQ_UART5_PRIORITY 12
171+#define STM32_IRQ_LPUART1_PRIORITY 12
172+
173+/*
174+ * ADC driver system settings.
175+ */
176+#define STM32_ADC_COMPACT_SAMPLES FALSE
177+#define STM32_ADC_USE_ADC1 FALSE
178+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
179+#define STM32_ADC_ADC1_DMA_PRIORITY 2
180+#define STM32_ADC_ADC12_IRQ_PRIORITY 5
181+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
182+#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV2
183+#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
184+
185+/*
186+ * CAN driver system settings.
187+ */
188+#define STM32_CAN_USE_CAN1 FALSE
189+#define STM32_CAN_CAN1_IRQ_PRIORITY 11
190+
191+/*
192+ * DAC driver system settings.
193+ */
194+#define STM32_DAC_DUAL_MODE FALSE
195+#define STM32_DAC_USE_DAC1_CH1 FALSE
196+#define STM32_DAC_USE_DAC1_CH2 FALSE
197+#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
198+#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
199+#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
200+#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
201+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
202+#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
203+
204+/*
205+ * GPT driver system settings.
206+ */
207+#define STM32_GPT_USE_TIM1 FALSE
208+#define STM32_GPT_USE_TIM2 FALSE
209+#define STM32_GPT_USE_TIM3 FALSE
210+#define STM32_GPT_USE_TIM4 FALSE
211+#define STM32_GPT_USE_TIM5 FALSE
212+#define STM32_GPT_USE_TIM6 FALSE
213+#define STM32_GPT_USE_TIM7 FALSE
214+#define STM32_GPT_USE_TIM8 FALSE
215+#define STM32_GPT_USE_TIM15 FALSE
216+#define STM32_GPT_USE_TIM16 FALSE
217+#define STM32_GPT_USE_TIM17 FALSE
218+
219+/*
220+ * I2C driver system settings.
221+ */
222+#define STM32_I2C_USE_I2C1 FALSE
223+#define STM32_I2C_USE_I2C2 FALSE
224+#define STM32_I2C_USE_I2C3 FALSE
225+#define STM32_I2C_USE_I2C4 FALSE
226+#define STM32_I2C_BUSY_TIMEOUT 50
227+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
228+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
229+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
230+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
231+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
232+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
233+#define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
234+#define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
235+#define STM32_I2C_I2C1_IRQ_PRIORITY 5
236+#define STM32_I2C_I2C2_IRQ_PRIORITY 5
237+#define STM32_I2C_I2C3_IRQ_PRIORITY 5
238+#define STM32_I2C_I2C4_IRQ_PRIORITY 5
239+#define STM32_I2C_I2C1_DMA_PRIORITY 3
240+#define STM32_I2C_I2C2_DMA_PRIORITY 3
241+#define STM32_I2C_I2C3_DMA_PRIORITY 3
242+#define STM32_I2C_I2C4_DMA_PRIORITY 3
243+#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
244+
245+/*
246+ * ICU driver system settings.
247+ */
248+#define STM32_ICU_USE_TIM1 FALSE
249+#define STM32_ICU_USE_TIM2 FALSE
250+#define STM32_ICU_USE_TIM3 FALSE
251+#define STM32_ICU_USE_TIM4 FALSE
252+#define STM32_ICU_USE_TIM5 FALSE
253+#define STM32_ICU_USE_TIM8 FALSE
254+#define STM32_ICU_USE_TIM15 FALSE
255+#define STM32_ICU_USE_TIM16 FALSE
256+#define STM32_ICU_USE_TIM17 FALSE
257+
258+/*
259+ * PWM driver system settings.
260+ */
261+#define STM32_PWM_USE_TIM1 FALSE
262+#define STM32_PWM_USE_TIM2 FALSE
263+#define STM32_PWM_USE_TIM3 FALSE
264+#define STM32_PWM_USE_TIM4 FALSE
265+#define STM32_PWM_USE_TIM5 FALSE
266+#define STM32_PWM_USE_TIM8 FALSE
267+#define STM32_PWM_USE_TIM15 FALSE
268+#define STM32_PWM_USE_TIM16 FALSE
269+#define STM32_PWM_USE_TIM17 FALSE
270+
271+/*
272+ * RTC driver system settings.
273+ */
274+#define STM32_RTC_PRESA_VALUE 32
275+#define STM32_RTC_PRESS_VALUE 1024
276+#define STM32_RTC_CR_INIT 0
277+#define STM32_RTC_TAMPCR_INIT 0
278+
279+/*
280+ * SDC driver system settings.
281+ */
282+#define STM32_SDC_USE_SDMMC1 FALSE
283+#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE
284+#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000000
285+#define STM32_SDC_SDMMC_READ_TIMEOUT 1000000
286+#define STM32_SDC_SDMMC_CLOCK_DELAY 10
287+#define STM32_SDC_SDMMC_PWRSAV TRUE
288+#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9
289+
290+/*
291+ * SERIAL driver system settings.
292+ */
293+#define STM32_SERIAL_USE_USART1 FALSE
294+#define STM32_SERIAL_USE_USART2 FALSE
295+#define STM32_SERIAL_USE_USART3 FALSE
296+#define STM32_SERIAL_USE_UART4 FALSE
297+#define STM32_SERIAL_USE_UART5 FALSE
298+#define STM32_SERIAL_USE_LPUART1 TRUE
299+
300+/*
301+ * SIO driver system settings.
302+ */
303+#define STM32_SIO_USE_USART1 FALSE
304+#define STM32_SIO_USE_USART2 FALSE
305+#define STM32_SIO_USE_USART3 FALSE
306+#define STM32_SIO_USE_UART4 FALSE
307+#define STM32_SIO_USE_UART5 FALSE
308+#define STM32_SIO_USE_LPUART1 FALSE
309+
310+/*
311+ * SPI driver system settings.
312+ */
313+#define STM32_SPI_USE_SPI1 FALSE
314+#define STM32_SPI_USE_SPI2 FALSE
315+#define STM32_SPI_USE_SPI3 FALSE
316+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
317+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
318+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
319+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
320+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
321+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
322+#define STM32_SPI_SPI1_DMA_PRIORITY 1
323+#define STM32_SPI_SPI2_DMA_PRIORITY 1
324+#define STM32_SPI_SPI3_DMA_PRIORITY 1
325+#define STM32_SPI_SPI1_IRQ_PRIORITY 10
326+#define STM32_SPI_SPI2_IRQ_PRIORITY 10
327+#define STM32_SPI_SPI3_IRQ_PRIORITY 10
328+#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
329+
330+/*
331+ * ST driver system settings.
332+ */
333+#define STM32_ST_IRQ_PRIORITY 8
334+#define STM32_ST_USE_TIMER 2
335+
336+/*
337+ * TRNG driver system settings.
338+ */
339+#define STM32_TRNG_USE_RNG1 FALSE
340+
341+/*
342+ * UART driver system settings.
343+ */
344+#define STM32_UART_USE_USART1 FALSE
345+#define STM32_UART_USE_USART2 FALSE
346+#define STM32_UART_USE_USART3 FALSE
347+#define STM32_UART_USE_UART4 FALSE
348+#define STM32_UART_USE_UART5 FALSE
349+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
350+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
351+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
352+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
353+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
354+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
355+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
356+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
357+#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
358+#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
359+#define STM32_UART_USART1_DMA_PRIORITY 0
360+#define STM32_UART_USART2_DMA_PRIORITY 0
361+#define STM32_UART_USART3_DMA_PRIORITY 0
362+#define STM32_UART_UART4_DMA_PRIORITY 0
363+#define STM32_UART_UART5_DMA_PRIORITY 0
364+#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
365+
366+/*
367+ * USB driver system settings.
368+ */
369+#define STM32_USB_USE_OTG1 FALSE
370+#define STM32_USB_OTG1_IRQ_PRIORITY 14
371+#define STM32_USB_OTG1_RX_FIFO_SIZE 512
372+
373+/*
374+ * WDG driver system settings.
375+ */
376+#define STM32_WDG_USE_IWDG FALSE
377+
378+/*
379+ * WSPI driver system settings.
380+ */
381+#define STM32_WSPI_USE_OCTOSPI1 TRUE
382+#define STM32_WSPI_USE_OCTOSPI2 TRUE
383+#define STM32_WSPI_OCTOSPI1_PRESCALER_VALUE 1
384+#define STM32_WSPI_OCTOSPI2_PRESCALER_VALUE 1
385+#define STM32_WSPI_OCTOSPI1_IRQ_PRIORITY 10
386+#define STM32_WSPI_OCTOSPI2_IRQ_PRIORITY 10
387+#define STM32_WSPI_OCTOSPI1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
388+#define STM32_WSPI_OCTOSPI2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
389+#define STM32_WSPI_OCTOSPI1_DMA_PRIORITY 1
390+#define STM32_WSPI_OCTOSPI2_DMA_PRIORITY 1
391+#define STM32_WSPI_OCTOSPI1_DMA_IRQ_PRIORITY 10
392+#define STM32_WSPI_OCTOSPI2_DMA_IRQ_PRIORITY 10
393+#define STM32_WSPI_DMA_ERROR_HOOK(qspip) osalSysHalt("DMA failure")
394+
395+#endif /* MCUCONF_H */
--- trunk/demos/STM32/RT-STM32L4P5ZG-NUCLEO144/Makefile (nonexistent)
+++ trunk/demos/STM32/RT-STM32L4P5ZG-NUCLEO144/Makefile (revision 14606)
@@ -0,0 +1,189 @@
1+##############################################################################
2+# Build global options
3+# NOTE: Can be overridden externally.
4+#
5+
6+# Compiler options here.
7+ifeq ($(USE_OPT),)
8+ USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
9+endif
10+
11+# C specific options here (added to USE_OPT).
12+ifeq ($(USE_COPT),)
13+ USE_COPT =
14+endif
15+
16+# C++ specific options here (added to USE_OPT).
17+ifeq ($(USE_CPPOPT),)
18+ USE_CPPOPT = -fno-rtti
19+endif
20+
21+# Enable this if you want the linker to remove unused code and data.
22+ifeq ($(USE_LINK_GC),)
23+ USE_LINK_GC = yes
24+endif
25+
26+# Linker extra options here.
27+ifeq ($(USE_LDOPT),)
28+ USE_LDOPT =
29+endif
30+
31+# Enable this if you want link time optimizations (LTO).
32+ifeq ($(USE_LTO),)
33+ USE_LTO = yes
34+endif
35+
36+# Enable this if you want to see the full log while compiling.
37+ifeq ($(USE_VERBOSE_COMPILE),)
38+ USE_VERBOSE_COMPILE = no
39+endif
40+
41+# If enabled, this option makes the build process faster by not compiling
42+# modules not used in the current configuration.
43+ifeq ($(USE_SMART_BUILD),)
44+ USE_SMART_BUILD = yes
45+endif
46+
47+#
48+# Build global options
49+##############################################################################
50+
51+##############################################################################
52+# Architecture or project specific options
53+#
54+
55+# Stack size to be allocated to the Cortex-M process stack. This stack is
56+# the stack used by the main() thread.
57+ifeq ($(USE_PROCESS_STACKSIZE),)
58+ USE_PROCESS_STACKSIZE = 0x400
59+endif
60+
61+# Stack size to the allocated to the Cortex-M main/exceptions stack. This
62+# stack is used for processing interrupts and exceptions.
63+ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
64+ USE_EXCEPTIONS_STACKSIZE = 0x400
65+endif
66+
67+# Enables the use of FPU (no, softfp, hard).
68+ifeq ($(USE_FPU),)
69+ USE_FPU = no
70+endif
71+
72+# FPU-related options.
73+ifeq ($(USE_FPU_OPT),)
74+ USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16
75+endif
76+
77+#
78+# Architecture or project specific options
79+##############################################################################
80+
81+##############################################################################
82+# Project, target, sources and paths
83+#
84+
85+# Define project name here
86+PROJECT = ch
87+
88+# Target settings.
89+MCU = cortex-m4
90+
91+# Imported source files and paths.
92+CHIBIOS := ../../..
93+CONFDIR := ./cfg
94+BUILDDIR := ./build
95+DEPDIR := ./.dep
96+
97+# Licensing files.
98+include $(CHIBIOS)/os/license/license.mk
99+# Startup files.
100+include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l4xx.mk
101+# HAL-OSAL files (optional).
102+include $(CHIBIOS)/os/hal/hal.mk
103+include $(CHIBIOS)/os/hal/ports/STM32/STM32L4xx+/platform_l4p5_l4q5.mk
104+include $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_L4P5ZG/board.mk
105+include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk
106+# RTOS files (optional).
107+include $(CHIBIOS)/os/rt/rt.mk
108+include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk
109+# Auto-build files in ./source recursively.
110+include $(CHIBIOS)/tools/mk/autobuild.mk
111+# Other files (optional).
112+include $(CHIBIOS)/os/test/test.mk
113+include $(CHIBIOS)/test/rt/rt_test.mk
114+include $(CHIBIOS)/test/oslib/oslib_test.mk
115+
116+# Define linker script file here.
117+LDSCRIPT= $(STARTUPLD)/STM32L4P5xG.ld
118+
119+# C sources that can be compiled in ARM or THUMB mode depending on the global
120+# setting.
121+CSRC = $(ALLCSRC) \
122+ $(TESTSRC) \
123+ main.c
124+
125+# C++ sources that can be compiled in ARM or THUMB mode depending on the global
126+# setting.
127+CPPSRC = $(ALLCPPSRC)
128+
129+# List ASM source files here.
130+ASMSRC = $(ALLASMSRC)
131+
132+# List ASM with preprocessor source files here.
133+ASMXSRC = $(ALLXASMSRC)
134+
135+# Inclusion directories.
136+INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC)
137+
138+# Define C warning options here.
139+CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes
140+
141+# Define C++ warning options here.
142+CPPWARN = -Wall -Wextra -Wundef
143+
144+#
145+# Project, target, sources and paths
146+##############################################################################
147+
148+##############################################################################
149+# Start of user section
150+#
151+
152+# List all user C define here, like -D_DEBUG=1
153+UDEFS =
154+
155+# Define ASM defines here
156+UADEFS =
157+
158+# List all user directories here
159+UINCDIR =
160+
161+# List the user directory to look for the libraries here
162+ULIBDIR =
163+
164+# List all user libraries here
165+ULIBS =
166+
167+#
168+# End of user section
169+##############################################################################
170+
171+##############################################################################
172+# Common rules
173+#
174+
175+RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk
176+include $(RULESPATH)/arm-none-eabi.mk
177+include $(RULESPATH)/rules.mk
178+
179+#
180+# Common rules
181+##############################################################################
182+
183+##############################################################################
184+# Custom rules
185+#
186+
187+#
188+# Custom rules
189+##############################################################################
--- trunk/demos/STM32/RT-STM32L4P5ZG-NUCLEO144/main.c (nonexistent)
+++ trunk/demos/STM32/RT-STM32L4P5ZG-NUCLEO144/main.c (revision 14606)
@@ -0,0 +1,83 @@
1+/*
2+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3+
4+ Licensed under the Apache License, Version 2.0 (the "License");
5+ you may not use this file except in compliance with the License.
6+ You may obtain a copy of the License at
7+
8+ http://www.apache.org/licenses/LICENSE-2.0
9+
10+ Unless required by applicable law or agreed to in writing, software
11+ distributed under the License is distributed on an "AS IS" BASIS,
12+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13+ See the License for the specific language governing permissions and
14+ limitations under the License.
15+*/
16+
17+#include "ch.h"
18+#include "hal.h"
19+#include "rt_test_root.h"
20+#include "oslib_test_root.h"
21+
22+/*
23+ * This is a periodic thread that does absolutely nothing except flashing
24+ * a LED.
25+ */
26+static THD_WORKING_AREA(waThread1, 128);
27+static THD_FUNCTION(Thread1, arg) {
28+
29+ (void)arg;
30+ chRegSetThreadName("blinker");
31+ while (true) {
32+ palSetLine(LINE_LED1);
33+ chThdSleepMilliseconds(50);
34+ palSetLine(LINE_LED2);
35+ chThdSleepMilliseconds(50);
36+ palSetLine(LINE_LED3);
37+ chThdSleepMilliseconds(200);
38+ palClearLine(LINE_LED1);
39+ chThdSleepMilliseconds(50);
40+ palClearLine(LINE_LED2);
41+ chThdSleepMilliseconds(50);
42+ palClearLine(LINE_LED3);
43+ chThdSleepMilliseconds(200);
44+ }
45+}
46+
47+/*
48+ * Application entry point.
49+ */
50+int main(void) {
51+
52+ /*
53+ * System initializations.
54+ * - HAL initialization, this also initializes the configured device drivers
55+ * and performs the board-specific initializations.
56+ * - Kernel initialization, the main() function becomes a thread and the
57+ * RTOS is active.
58+ */
59+ halInit();
60+ chSysInit();
61+
62+ /*
63+ * Activates the serial driver 3 using the driver default configuration.
64+ */
65+ sdStart(&LPSD1, NULL);
66+
67+ /*
68+ * Creates the example thread.
69+ */
70+ chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO + 1, Thread1, NULL);
71+
72+ /*
73+ * Normal main() thread activity, in this demo it does nothing except
74+ * sleeping in a loop and check the button state.
75+ */
76+ while (true) {
77+ if (palReadLine(LINE_BUTTON)) {
78+ test_execute((BaseSequentialStream *)&LPSD1, &rt_test_suite);
79+ test_execute((BaseSequentialStream *)&LPSD1, &oslib_test_suite);
80+ }
81+ chThdSleepMilliseconds(500);
82+ }
83+}
--- trunk/demos/STM32/RT-STM32L4P5ZG-NUCLEO144/readme.txt (nonexistent)
+++ trunk/demos/STM32/RT-STM32L4P5ZG-NUCLEO144/readme.txt (revision 14606)
@@ -0,0 +1,28 @@
1+*****************************************************************************
2+** ChibiOS/RT port for ARM-Cortex-M4 STM32L4P5. **
3+*****************************************************************************
4+
5+** TARGET **
6+
7+The demo runs on an STM32 Nucleo144-L4P5ZG board.
8+
9+** The Demo **
10+
11+The demo flashes the board LEDs using a thread, by pressing the button located
12+on the board the test procedure is activated with output on the serial port
13+SD3 (USART3, mapped on STLink v2-1 Virtual COM Port).
14+
15+** Build Procedure **
16+
17+The demo has been tested by using the free Codesourcery GCC-based toolchain
18+and YAGARTO. just modify the TRGT line in the makefile in order to use
19+different GCC toolchains.
20+
21+** Notes **
22+
23+Some files used by the demo are not part of ChibiOS/RT but are copyright of
24+ST Microelectronics and are licensed under a different license.
25+Also note that not all the files present in the ST library are distributed
26+with ChibiOS/RT, you can find the whole library on the ST web site:
27+
28+ http://www.st.com
--- trunk/os/common/ext/ST/STM32L4xx/stm32l4p5xx.h (revision 14605)
+++ trunk/os/common/ext/ST/STM32L4xx/stm32l4p5xx.h (revision 14606)
@@ -1185,7 +1185,7 @@
11851185 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
11861186 } WWDG_TypeDef;
11871187
1188-#if STM32L4P5xx
1188+#ifdef STM32L4P5xx
11891189 /**
11901190 * @brief HASH
11911191 */
@@ -1587,7 +1587,7 @@
15871587 #define RTC ((RTC_TypeDef *) RTC_BASE)
15881588 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
15891589 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1590-#if STM32L4P5xx
1590+#ifdef STM32L4P5xx
15911591 #define TAMP ((TAMP_TypeDef *) TAMP_BASE)
15921592 #endif /* STM32L412xx || STM32L422xx || STM32L4P5xx || STM32L4Q5xx */
15931593 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
--- trunk/os/hal/boards/ST_NUCLEO144_L4P5ZG/board.c (nonexistent)
+++ trunk/os/hal/boards/ST_NUCLEO144_L4P5ZG/board.c (revision 14606)
@@ -0,0 +1,281 @@
1+/*
2+ ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
3+
4+ Licensed under the Apache License, Version 2.0 (the "License");
5+ you may not use this file except in compliance with the License.
6+ You may obtain a copy of the License at
7+
8+ http://www.apache.org/licenses/LICENSE-2.0
9+
10+ Unless required by applicable law or agreed to in writing, software
11+ distributed under the License is distributed on an "AS IS" BASIS,
12+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13+ See the License for the specific language governing permissions and
14+ limitations under the License.
15+*/
16+
17+/*
18+ * This file has been automatically generated using ChibiStudio board
19+ * generator plugin. Do not edit manually.
20+ */
21+
22+#include "hal.h"
23+#include "stm32_gpio.h"
24+
25+/*===========================================================================*/
26+/* Driver local definitions. */
27+/*===========================================================================*/
28+
29+/*===========================================================================*/
30+/* Driver exported variables. */
31+/*===========================================================================*/
32+
33+/*===========================================================================*/
34+/* Driver local variables and types. */
35+/*===========================================================================*/
36+
37+/**
38+ * @brief Type of STM32 GPIO port setup.
39+ */
40+typedef struct {
41+ uint32_t moder;
42+ uint32_t otyper;
43+ uint32_t ospeedr;
44+ uint32_t pupdr;
45+ uint32_t odr;
46+ uint32_t afrl;
47+ uint32_t afrh;
48+ uint32_t ascr;
49+ uint32_t lockr;
50+} gpio_setup_t;
51+
52+/**
53+ * @brief Type of STM32 GPIO initialization data.
54+ */
55+typedef struct {
56+#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
57+ gpio_setup_t PAData;
58+#endif
59+#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
60+ gpio_setup_t PBData;
61+#endif
62+#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
63+ gpio_setup_t PCData;
64+#endif
65+#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
66+ gpio_setup_t PDData;
67+#endif
68+#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
69+ gpio_setup_t PEData;
70+#endif
71+#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
72+ gpio_setup_t PFData;
73+#endif
74+#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
75+ gpio_setup_t PGData;
76+#endif
77+#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
78+ gpio_setup_t PHData;
79+#endif
80+#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
81+ gpio_setup_t PIData;
82+#endif
83+#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
84+ gpio_setup_t PJData;
85+#endif
86+#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
87+ gpio_setup_t PKData;
88+#endif
89+} gpio_config_t;
90+
91+/**
92+ * @brief STM32 GPIO static initialization data.
93+ */
94+static const gpio_config_t gpio_default_config = {
95+#if STM32_HAS_GPIOA
96+ {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
97+ VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH, VAL_GPIOA_ASCR,
98+ VAL_GPIOA_LOCKR},
99+#endif
100+#if STM32_HAS_GPIOB
101+ {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
102+ VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH, VAL_GPIOB_ASCR,
103+ VAL_GPIOB_LOCKR},
104+#endif
105+#if STM32_HAS_GPIOC
106+ {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
107+ VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH, VAL_GPIOC_ASCR,
108+ VAL_GPIOC_LOCKR},
109+#endif
110+#if STM32_HAS_GPIOD
111+ {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
112+ VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH, VAL_GPIOD_ASCR,
113+ VAL_GPIOD_LOCKR},
114+#endif
115+#if STM32_HAS_GPIOE
116+ {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
117+ VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH, VAL_GPIOE_ASCR,
118+ VAL_GPIOE_LOCKR},
119+#endif
120+#if STM32_HAS_GPIOF
121+ {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
122+ VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH, VAL_GPIOF_ASCR,
123+ VAL_GPIOF_LOCKR},
124+#endif
125+#if STM32_HAS_GPIOG
126+ {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
127+ VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH, VAL_GPIOG_ASCR,
128+ VAL_GPIOG_LOCKR},
129+#endif
130+#if STM32_HAS_GPIOH
131+ {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
132+ VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH, VAL_GPIOH_ASCR,
133+ VAL_GPIOH_LOCKR},
134+#endif
135+#if STM32_HAS_GPIOI
136+ {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
137+ VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH, VAL_GPIOI_ASCR,
138+ VAL_GPIOI_LOCKR},
139+#endif
140+#if STM32_HAS_GPIOJ
141+ {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
142+ VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH, VAL_GPIOJ_ASCR,
143+ VAL_GPIOJ_LOCKR},
144+#endif
145+#if STM32_HAS_GPIOK
146+ {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
147+ VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH, VAL_GPIOK_ASCR,
148+ VAL_GPIOK_LOCKR}
149+#endif
150+};
151+
152+/*===========================================================================*/
153+/* Driver local functions. */
154+/*===========================================================================*/
155+
156+static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
157+
158+ gpiop->OTYPER = config->otyper;
159+ gpiop->ASCR = config->ascr;
160+ gpiop->OSPEEDR = config->ospeedr;
161+ gpiop->PUPDR = config->pupdr;
162+ gpiop->ODR = config->odr;
163+ gpiop->AFRL = config->afrl;
164+ gpiop->AFRH = config->afrh;
165+ gpiop->MODER = config->moder;
166+ gpiop->LOCKR = config->lockr;
167+}
168+
169+static void stm32_gpio_init(void) {
170+
171+ /* Enabling GPIO-related clocks, the mask comes from the
172+ registry header file.*/
173+ rccResetAHB2(STM32_GPIO_EN_MASK);
174+ rccEnableAHB2(STM32_GPIO_EN_MASK, true);
175+
176+ /* Initializing all the defined GPIO ports.*/
177+#if STM32_HAS_GPIOA
178+ gpio_init(GPIOA, &gpio_default_config.PAData);
179+#endif
180+#if STM32_HAS_GPIOB
181+ gpio_init(GPIOB, &gpio_default_config.PBData);
182+#endif
183+#if STM32_HAS_GPIOC
184+ gpio_init(GPIOC, &gpio_default_config.PCData);
185+#endif
186+#if STM32_HAS_GPIOD
187+ gpio_init(GPIOD, &gpio_default_config.PDData);
188+#endif
189+#if STM32_HAS_GPIOE
190+ gpio_init(GPIOE, &gpio_default_config.PEData);
191+#endif
192+#if STM32_HAS_GPIOF
193+ gpio_init(GPIOF, &gpio_default_config.PFData);
194+#endif
195+#if STM32_HAS_GPIOG
196+ gpio_init(GPIOG, &gpio_default_config.PGData);
197+#endif
198+#if STM32_HAS_GPIOH
199+ gpio_init(GPIOH, &gpio_default_config.PHData);
200+#endif
201+#if STM32_HAS_GPIOI
202+ gpio_init(GPIOI, &gpio_default_config.PIData);
203+#endif
204+#if STM32_HAS_GPIOJ
205+ gpio_init(GPIOJ, &gpio_default_config.PJData);
206+#endif
207+#if STM32_HAS_GPIOK
208+ gpio_init(GPIOK, &gpio_default_config.PKData);
209+#endif
210+}
211+
212+/*===========================================================================*/
213+/* Driver interrupt handlers. */
214+/*===========================================================================*/
215+
216+/*===========================================================================*/
217+/* Driver exported functions. */
218+/*===========================================================================*/
219+
220+/**
221+ * @brief Early initialization code.
222+ * @details GPIO ports and system clocks are initialized before everything
223+ * else.
224+ */
225+void __early_init(void) {
226+
227+ stm32_gpio_init();
228+ stm32_clock_init();
229+}
230+
231+#if HAL_USE_SDC || defined(__DOXYGEN__)
232+/**
233+ * @brief SDC card detection.
234+ */
235+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
236+
237+ (void)sdcp;
238+ /* CHTODO: Fill the implementation.*/
239+ return true;
240+}
241+
242+/**
243+ * @brief SDC card write protection detection.
244+ */
245+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
246+
247+ (void)sdcp;
248+ /* CHTODO: Fill the implementation.*/
249+ return false;
250+}
251+#endif /* HAL_USE_SDC */
252+
253+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
254+/**
255+ * @brief MMC_SPI card detection.
256+ */
257+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
258+
259+ (void)mmcp;
260+ /* CHTODO: Fill the implementation.*/
261+ return true;
262+}
263+
264+/**
265+ * @brief MMC_SPI card write protection detection.
266+ */
267+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
268+
269+ (void)mmcp;
270+ /* CHTODO: Fill the implementation.*/
271+ return false;
272+}
273+#endif
274+
275+/**
276+ * @brief Board-specific initialization code.
277+ * @note You can add your board-specific code here.
278+ */
279+void boardInit(void) {
280+
281+}
--- trunk/os/hal/boards/ST_NUCLEO144_L4P5ZG/board.h (nonexistent)
+++ trunk/os/hal/boards/ST_NUCLEO144_L4P5ZG/board.h (revision 14606)
@@ -0,0 +1,1643 @@
1+/*
2+ ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
3+
4+ Licensed under the Apache License, Version 2.0 (the "License");
5+ you may not use this file except in compliance with the License.
6+ You may obtain a copy of the License at
7+
8+ http://www.apache.org/licenses/LICENSE-2.0
9+
10+ Unless required by applicable law or agreed to in writing, software
11+ distributed under the License is distributed on an "AS IS" BASIS,
12+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13+ See the License for the specific language governing permissions and
14+ limitations under the License.
15+*/
16+
17+/*
18+ * This file has been automatically generated using ChibiStudio board
19+ * generator plugin. Do not edit manually.
20+ */
21+
22+#ifndef BOARD_H
23+#define BOARD_H
24+
25+/*===========================================================================*/
26+/* Driver constants. */
27+/*===========================================================================*/
28+
29+/*
30+ * Setup for STMicroelectronics STM32 Nucleo144-L4R5ZI board.
31+ */
32+
33+/*
34+ * Board identifier.
35+ */
36+#define BOARD_ST_NUCLEO144_L4P5ZG
37+#define BOARD_NAME "STMicroelectronics STM32 Nucleo144-L4P5ZG"
38+
39+/*
40+ * Board oscillators-related settings.
41+ * NOTE: HSE not fitted.
42+ */
43+#if !defined(STM32_LSECLK)
44+#define STM32_LSECLK 32768U
45+#endif
46+
47+#define STM32_LSEDRV (3U << 3U)
48+
49+#if !defined(STM32_HSECLK)
50+#define STM32_HSECLK 0U
51+#endif
52+
53+/*
54+ * Board voltages.
55+ * Required for performance limits calculation.
56+ */
57+#define STM32_VDD 300U
58+
59+/*
60+ * MCU type as defined in the ST header.
61+ */
62+#define STM32L4P5xx
63+
64+/*
65+ * IO pins assignments.
66+ */
67+#define GPIOA_PIN0 0U
68+#define GPIOA_PIN1 1U
69+#define GPIOA_PIN2 2U
70+#define GPIOA_PIN3 3U
71+#define GPIOA_PIN4 4U
72+#define GPIOA_PIN5 5U
73+#define GPIOA_PIN6 6U
74+#define GPIOA_PIN7 7U
75+#define GPIOA_USB_SOF 8U
76+#define GPIOA_USB_VBUS 9U
77+#define GPIOA_USB_ID 10U
78+#define GPIOA_USB_DM 11U
79+#define GPIOA_USB_DP 12U
80+#define GPIOA_SWDIO 13U
81+#define GPIOA_SWCLK 14U
82+#define GPIOA_PIN15 15U
83+
84+#define GPIOB_PIN0 0U
85+#define GPIOB_PIN1 1U
86+#define GPIOB_PIN2 2U
87+#define GPIOB_SWO 3U
88+#define GPIOB_PIN4 4U
89+#define GPIOB_PIN5 5U
90+#define GPIOB_PIN6 6U
91+#define GPIOB_LED2 7U
92+#define GPIOB_LED_BLUE 7U
93+#define GPIOB_PIN8 8U
94+#define GPIOB_PIN9 9U
95+#define GPIOB_PIN10 10U
96+#define GPIOB_PIN11 11U
97+#define GPIOB_PIN12 12U
98+#define GPIOB_PIN13 13U
99+#define GPIOB_LED3 14U
100+#define GPIOB_LED_RED 14U
101+#define GPIOB_PIN15 15U
102+
103+#define GPIOC_PIN0 0U
104+#define GPIOC_PIN1 1U
105+#define GPIOC_PIN2 2U
106+#define GPIOC_PIN3 3U
107+#define GPIOC_PIN4 4U
108+#define GPIOC_PIN5 5U
109+#define GPIOC_PIN6 6U
110+#define GPIOC_LED1 7U
111+#define GPIOC_LED_GREEN 7U
112+#define GPIOC_PIN8 8U
113+#define GPIOC_PIN9 9U
114+#define GPIOC_PIN10 10U
115+#define GPIOC_PIN11 11U
116+#define GPIOC_PIN12 12U
117+#define GPIOC_BUTTON 13U
118+#define GPIOC_PIN14 14U
119+#define GPIOC_PIN15 15U
120+
121+#define GPIOD_PIN0 0U
122+#define GPIOD_PIN1 1U
123+#define GPIOD_PIN2 2U
124+#define GPIOD_PIN3 3U
125+#define GPIOD_PIN4 4U
126+#define GPIOD_PIN5 5U
127+#define GPIOD_PIN6 6U
128+#define GPIOD_PIN7 7U
129+#define GPIOD_PIN8 8U
130+#define GPIOD_PIN9 9U
131+#define GPIOD_PIN10 10U
132+#define GPIOD_PIN11 11U
133+#define GPIOD_PIN12 12U
134+#define GPIOD_PIN13 13U
135+#define GPIOD_PIN14 14U
136+#define GPIOD_PIN15 15U
137+
138+#define GPIOE_PIN0 0U
139+#define GPIOE_PIN1 1U
140+#define GPIOE_PIN2 2U
141+#define GPIOE_PIN3 3U
142+#define GPIOE_PIN4 4U
143+#define GPIOE_PIN5 5U
144+#define GPIOE_PIN6 6U
145+#define GPIOE_PIN7 7U
146+#define GPIOE_PIN8 8U
147+#define GPIOE_PIN9 9U
148+#define GPIOE_PIN10 10U
149+#define GPIOE_PIN11 11U
150+#define GPIOE_PIN12 12U
151+#define GPIOE_PIN13 13U
152+#define GPIOE_PIN14 14U
153+#define GPIOE_PIN15 15U
154+
155+#define GPIOF_PIN0 0U
156+#define GPIOF_PIN1 1U
157+#define GPIOF_PIN2 2U
158+#define GPIOF_PIN3 3U
159+#define GPIOF_PIN4 4U
160+#define GPIOF_PIN5 5U
161+#define GPIOF_PIN6 6U
162+#define GPIOF_PIN7 7U
163+#define GPIOF_PIN8 8U
164+#define GPIOF_PIN9 9U
165+#define GPIOF_PIN10 10U
166+#define GPIOF_PIN11 11U
167+#define GPIOF_PIN12 12U
168+#define GPIOF_PIN13 13U
169+#define GPIOF_PIN14 14U
170+#define GPIOF_PIN15 15U
171+
172+#define GPIOG_PIN0 0U
173+#define GPIOG_PIN1 1U
174+#define GPIOG_PIN2 2U
175+#define GPIOG_PIN3 3U
176+#define GPIOG_PIN4 4U
177+#define GPIOG_USB_OVER_CURRENT 5U
178+#define GPIOG_USB_POWER_SWITCH_ON 6U
179+#define GPIOG_LPUART1_TX 7U
180+#define GPIOG_LPUART1_RX 8U
181+#define GPIOG_PIN9 9U
182+#define GPIOG_PIN10 10U
183+#define GPIOG_PIN11 11U
184+#define GPIOG_PIN12 12U
185+#define GPIOG_PIN13 13U
186+#define GPIOG_PIN14 14U
187+#define GPIOG_PIN15 15U
188+
189+#define GPIOH_PIN0 0U
190+#define GPIOH_PIN1 1U
191+#define GPIOH_PIN2 2U
192+#define GPIOH_PIN3 3U
193+#define GPIOH_PIN4 4U
194+#define GPIOH_PIN5 5U
195+#define GPIOH_PIN6 6U
196+#define GPIOH_PIN7 7U
197+#define GPIOH_PIN8 8U
198+#define GPIOH_PIN9 9U
199+#define GPIOH_PIN10 10U
200+#define GPIOH_PIN11 11U
201+#define GPIOH_PIN12 12U
202+#define GPIOH_PIN13 13U
203+#define GPIOH_PIN14 14U
204+#define GPIOH_PIN15 15U
205+
206+#define GPIOI_PIN0 0U
207+#define GPIOI_PIN1 1U
208+#define GPIOI_PIN2 2U
209+#define GPIOI_PIN3 3U
210+#define GPIOI_PIN4 4U
211+#define GPIOI_PIN5 5U
212+#define GPIOI_PIN6 6U
213+#define GPIOI_PIN7 7U
214+#define GPIOI_PIN8 8U
215+#define GPIOI_PIN9 9U
216+#define GPIOI_PIN10 10U
217+#define GPIOI_PIN11 11U
218+#define GPIOI_PIN12 12U
219+#define GPIOI_PIN13 13U
220+#define GPIOI_PIN14 14U
221+#define GPIOI_PIN15 15U
222+
223+/*
224+ * IO lines assignments.
225+ */
226+#define LINE_USB_SOF PAL_LINE(GPIOA, 8U)
227+#define LINE_USB_VBUS PAL_LINE(GPIOA, 9U)
228+#define LINE_USB_ID PAL_LINE(GPIOA, 10U)
229+#define LINE_USB_DM PAL_LINE(GPIOA, 11U)
230+#define LINE_USB_DP PAL_LINE(GPIOA, 12U)
231+#define LINE_SWDIO PAL_LINE(GPIOA, 13U)
232+#define LINE_SWCLK PAL_LINE(GPIOA, 14U)
233+#define LINE_SWO PAL_LINE(GPIOB, 3U)
234+#define LINE_LED2 PAL_LINE(GPIOB, 7U)
235+#define LINE_LED_BLUE PAL_LINE(GPIOB, 7U)
236+#define LINE_LED3 PAL_LINE(GPIOB, 14U)
237+#define LINE_LED_RED PAL_LINE(GPIOB, 14U)
238+#define LINE_LED1 PAL_LINE(GPIOC, 7U)
239+#define LINE_LED_GREEN PAL_LINE(GPIOC, 7U)
240+#define LINE_BUTTON PAL_LINE(GPIOC, 13U)
241+#define LINE_USB_OVER_CURRENT PAL_LINE(GPIOG, 5U)
242+#define LINE_USB_POWER_SWITCH_ON PAL_LINE(GPIOG, 6U)
243+#define LINE_LPUART1_TX PAL_LINE(GPIOG, 7U)
244+#define LINE_LPUART1_RX PAL_LINE(GPIOG, 8U)
245+
246+/*===========================================================================*/
247+/* Driver pre-compile time settings. */
248+/*===========================================================================*/
249+
250+/*===========================================================================*/
251+/* Derived constants and error checks. */
252+/*===========================================================================*/
253+
254+/*===========================================================================*/
255+/* Driver data structures and types. */
256+/*===========================================================================*/
257+
258+/*===========================================================================*/
259+/* Driver macros. */
260+/*===========================================================================*/
261+
262+/*
263+ * I/O ports initial setup, this configuration is established soon after reset
264+ * in the initialization code.
265+ * Please refer to the STM32 Reference Manual for details.
266+ */
267+#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))
268+#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))
269+#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))
270+#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))
271+#define PIN_ODR_LOW(n) (0U << (n))
272+#define PIN_ODR_HIGH(n) (1U << (n))
273+#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
274+#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
275+#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U))
276+#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U))
277+#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U))
278+#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U))
279+#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))
280+#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
281+#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
282+#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
283+#define PIN_ASCR_DISABLED(n) (0U << (n))
284+#define PIN_ASCR_ENABLED(n) (1U << (n))
285+#define PIN_LOCKR_DISABLED(n) (0U << (n))
286+#define PIN_LOCKR_ENABLED(n) (1U << (n))
287+
288+/*
289+ * GPIOA setup:
290+ *
291+ * PA0 - PIN0 (analog).
292+ * PA1 - PIN1 (analog).
293+ * PA2 - PIN2 (analog).
294+ * PA3 - PIN3 (analog).
295+ * PA4 - PIN4 (analog).
296+ * PA5 - PIN5 (analog).
297+ * PA6 - PIN6 (analog).
298+ * PA7 - PIN7 (analog).
299+ * PA8 - USB_SOF (alternate 10).
300+ * PA9 - USB_VBUS (analog).
301+ * PA10 - USB_ID (alternate 10).
302+ * PA11 - USB_DM (alternate 10).
303+ * PA12 - USB_DP (alternate 10).
304+ * PA13 - SWDIO (alternate 0).
305+ * PA14 - SWCLK (alternate 0).
306+ * PA15 - PIN15 (analog).
307+ */
308+#define VAL_GPIOA_MODER (PIN_MODE_ANALOG(GPIOA_PIN0) | \
309+ PIN_MODE_ANALOG(GPIOA_PIN1) | \
310+ PIN_MODE_ANALOG(GPIOA_PIN2) | \
311+ PIN_MODE_ANALOG(GPIOA_PIN3) | \
312+ PIN_MODE_ANALOG(GPIOA_PIN4) | \
313+ PIN_MODE_ANALOG(GPIOA_PIN5) | \
314+ PIN_MODE_ANALOG(GPIOA_PIN6) | \
315+ PIN_MODE_ANALOG(GPIOA_PIN7) | \
316+ PIN_MODE_ALTERNATE(GPIOA_USB_SOF) | \
317+ PIN_MODE_ANALOG(GPIOA_USB_VBUS) | \
318+ PIN_MODE_ALTERNATE(GPIOA_USB_ID) | \
319+ PIN_MODE_ALTERNATE(GPIOA_USB_DM) | \
320+ PIN_MODE_ALTERNATE(GPIOA_USB_DP) | \
321+ PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \
322+ PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \
323+ PIN_MODE_ANALOG(GPIOA_PIN15))
324+#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) | \
325+ PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \
326+ PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \
327+ PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \
328+ PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \
329+ PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \
330+ PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \
331+ PIN_OTYPE_PUSHPULL(GPIOA_PIN7) | \
332+ PIN_OTYPE_PUSHPULL(GPIOA_USB_SOF) | \
333+ PIN_OTYPE_PUSHPULL(GPIOA_USB_VBUS) | \
334+ PIN_OTYPE_PUSHPULL(GPIOA_USB_ID) | \
335+ PIN_OTYPE_PUSHPULL(GPIOA_USB_DM) | \
336+ PIN_OTYPE_PUSHPULL(GPIOA_USB_DP) | \
337+ PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \
338+ PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \
339+ PIN_OTYPE_PUSHPULL(GPIOA_PIN15))
340+#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOA_PIN0) | \
341+ PIN_OSPEED_VERYLOW(GPIOA_PIN1) | \
342+ PIN_OSPEED_VERYLOW(GPIOA_PIN2) | \
343+ PIN_OSPEED_VERYLOW(GPIOA_PIN3) | \
344+ PIN_OSPEED_VERYLOW(GPIOA_PIN4) | \
345+ PIN_OSPEED_VERYLOW(GPIOA_PIN5) | \
346+ PIN_OSPEED_VERYLOW(GPIOA_PIN6) | \
347+ PIN_OSPEED_VERYLOW(GPIOA_PIN7) | \
348+ PIN_OSPEED_HIGH(GPIOA_USB_SOF) | \
349+ PIN_OSPEED_VERYLOW(GPIOA_USB_VBUS) | \
350+ PIN_OSPEED_HIGH(GPIOA_USB_ID) | \
351+ PIN_OSPEED_HIGH(GPIOA_USB_DM) | \
352+ PIN_OSPEED_HIGH(GPIOA_USB_DP) | \
353+ PIN_OSPEED_HIGH(GPIOA_SWDIO) | \
354+ PIN_OSPEED_HIGH(GPIOA_SWCLK) | \
355+ PIN_OSPEED_VERYLOW(GPIOA_PIN15))
356+#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_PIN0) | \
357+ PIN_PUPDR_FLOATING(GPIOA_PIN1) | \
358+ PIN_PUPDR_FLOATING(GPIOA_PIN2) | \
359+ PIN_PUPDR_FLOATING(GPIOA_PIN3) | \
360+ PIN_PUPDR_FLOATING(GPIOA_PIN4) | \
361+ PIN_PUPDR_FLOATING(GPIOA_PIN5) | \
362+ PIN_PUPDR_FLOATING(GPIOA_PIN6) | \
363+ PIN_PUPDR_FLOATING(GPIOA_PIN7) | \
364+ PIN_PUPDR_FLOATING(GPIOA_USB_SOF) | \
365+ PIN_PUPDR_FLOATING(GPIOA_USB_VBUS) | \
366+ PIN_PUPDR_FLOATING(GPIOA_USB_ID) | \
367+ PIN_PUPDR_FLOATING(GPIOA_USB_DM) | \
368+ PIN_PUPDR_FLOATING(GPIOA_USB_DP) | \
369+ PIN_PUPDR_PULLDOWN(GPIOA_SWDIO) | \
370+ PIN_PUPDR_PULLUP(GPIOA_SWCLK) | \
371+ PIN_PUPDR_FLOATING(GPIOA_PIN15))
372+#define VAL_GPIOA_ODR (PIN_ODR_LOW(GPIOA_PIN0) | \
373+ PIN_ODR_LOW(GPIOA_PIN1) | \
374+ PIN_ODR_LOW(GPIOA_PIN2) | \
375+ PIN_ODR_LOW(GPIOA_PIN3) | \
376+ PIN_ODR_LOW(GPIOA_PIN4) | \
377+ PIN_ODR_LOW(GPIOA_PIN5) | \
378+ PIN_ODR_LOW(GPIOA_PIN6) | \
379+ PIN_ODR_LOW(GPIOA_PIN7) | \
380+ PIN_ODR_LOW(GPIOA_USB_SOF) | \
381+ PIN_ODR_LOW(GPIOA_USB_VBUS) | \
382+ PIN_ODR_LOW(GPIOA_USB_ID) | \
383+ PIN_ODR_LOW(GPIOA_USB_DM) | \
384+ PIN_ODR_LOW(GPIOA_USB_DP) | \
385+ PIN_ODR_LOW(GPIOA_SWDIO) | \
386+ PIN_ODR_LOW(GPIOA_SWCLK) | \
387+ PIN_ODR_LOW(GPIOA_PIN15))
388+#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_PIN0, 0U) | \
389+ PIN_AFIO_AF(GPIOA_PIN1, 0U) | \
390+ PIN_AFIO_AF(GPIOA_PIN2, 0U) | \
391+ PIN_AFIO_AF(GPIOA_PIN3, 0U) | \
392+ PIN_AFIO_AF(GPIOA_PIN4, 0U) | \
393+ PIN_AFIO_AF(GPIOA_PIN5, 0U) | \
394+ PIN_AFIO_AF(GPIOA_PIN6, 0U) | \
395+ PIN_AFIO_AF(GPIOA_PIN7, 0U))
396+#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_USB_SOF, 10U) | \
397+ PIN_AFIO_AF(GPIOA_USB_VBUS, 0U) | \
398+ PIN_AFIO_AF(GPIOA_USB_ID, 10U) | \
399+ PIN_AFIO_AF(GPIOA_USB_DM, 10U) | \
400+ PIN_AFIO_AF(GPIOA_USB_DP, 10U) | \
401+ PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \
402+ PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \
403+ PIN_AFIO_AF(GPIOA_PIN15, 0U))
404+#define VAL_GPIOA_ASCR (PIN_ASCR_DISABLED(GPIOA_PIN0) | \
405+ PIN_ASCR_DISABLED(GPIOA_PIN1) | \
406+ PIN_ASCR_DISABLED(GPIOA_PIN2) | \
407+ PIN_ASCR_DISABLED(GPIOA_PIN3) | \
408+ PIN_ASCR_DISABLED(GPIOA_PIN4) | \
409+ PIN_ASCR_DISABLED(GPIOA_PIN5) | \
410+ PIN_ASCR_DISABLED(GPIOA_PIN6) | \
411+ PIN_ASCR_DISABLED(GPIOA_PIN7) | \
412+ PIN_ASCR_DISABLED(GPIOA_USB_SOF) | \
413+ PIN_ASCR_DISABLED(GPIOA_USB_VBUS) | \
414+ PIN_ASCR_DISABLED(GPIOA_USB_ID) | \
415+ PIN_ASCR_DISABLED(GPIOA_USB_DM) | \
416+ PIN_ASCR_DISABLED(GPIOA_USB_DP) | \
417+ PIN_ASCR_DISABLED(GPIOA_SWDIO) | \
418+ PIN_ASCR_DISABLED(GPIOA_SWCLK) | \
419+ PIN_ASCR_DISABLED(GPIOA_PIN15))
420+#define VAL_GPIOA_LOCKR (PIN_LOCKR_DISABLED(GPIOA_PIN0) | \
421+ PIN_LOCKR_DISABLED(GPIOA_PIN1) | \
422+ PIN_LOCKR_DISABLED(GPIOA_PIN2) | \
423+ PIN_LOCKR_DISABLED(GPIOA_PIN3) | \
424+ PIN_LOCKR_DISABLED(GPIOA_PIN4) | \
425+ PIN_LOCKR_DISABLED(GPIOA_PIN5) | \
426+ PIN_LOCKR_DISABLED(GPIOA_PIN6) | \
427+ PIN_LOCKR_DISABLED(GPIOA_PIN7) | \
428+ PIN_LOCKR_DISABLED(GPIOA_USB_SOF) | \
429+ PIN_LOCKR_DISABLED(GPIOA_USB_VBUS) | \
430+ PIN_LOCKR_DISABLED(GPIOA_USB_ID) | \
431+ PIN_LOCKR_DISABLED(GPIOA_USB_DM) | \
432+ PIN_LOCKR_DISABLED(GPIOA_USB_DP) | \
433+ PIN_LOCKR_DISABLED(GPIOA_SWDIO) | \
434+ PIN_LOCKR_DISABLED(GPIOA_SWCLK) | \
435+ PIN_LOCKR_DISABLED(GPIOA_PIN15))
436+
437+/*
438+ * GPIOB setup:
439+ *
440+ * PB0 - PIN0 (analog).
441+ * PB1 - PIN1 (analog).
442+ * PB2 - PIN2 (analog).
443+ * PB3 - SWO (alternate 0).
444+ * PB4 - PIN4 (analog).
445+ * PB5 - PIN5 (analog).
446+ * PB6 - PIN6 (analog).
447+ * PB7 - LED2 LED_BLUE (output pushpull maximum).
448+ * PB8 - PIN8 (analog).
449+ * PB9 - PIN9 (analog).
450+ * PB10 - PIN10 (analog).
451+ * PB11 - PIN11 (analog).
452+ * PB12 - PIN12 (analog).
453+ * PB13 - PIN13 (analog).
454+ * PB14 - LED3 LED_RED (output pushpull maximum).
455+ * PB15 - PIN15 (analog).
456+ */
457+#define VAL_GPIOB_MODER (PIN_MODE_ANALOG(GPIOB_PIN0) | \
458+ PIN_MODE_ANALOG(GPIOB_PIN1) | \
459+ PIN_MODE_ANALOG(GPIOB_PIN2) | \
460+ PIN_MODE_ALTERNATE(GPIOB_SWO) | \
461+ PIN_MODE_ANALOG(GPIOB_PIN4) | \
462+ PIN_MODE_ANALOG(GPIOB_PIN5) | \
463+ PIN_MODE_ANALOG(GPIOB_PIN6) | \
464+ PIN_MODE_OUTPUT(GPIOB_LED2) | \
465+ PIN_MODE_ANALOG(GPIOB_PIN8) | \
466+ PIN_MODE_ANALOG(GPIOB_PIN9) | \
467+ PIN_MODE_ANALOG(GPIOB_PIN10) | \
468+ PIN_MODE_ANALOG(GPIOB_PIN11) | \
469+ PIN_MODE_ANALOG(GPIOB_PIN12) | \
470+ PIN_MODE_ANALOG(GPIOB_PIN13) | \
471+ PIN_MODE_OUTPUT(GPIOB_LED3) | \
472+ PIN_MODE_ANALOG(GPIOB_PIN15))
473+#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \
474+ PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \
475+ PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \
476+ PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \
477+ PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \
478+ PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \
479+ PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \
480+ PIN_OTYPE_PUSHPULL(GPIOB_LED2) | \
481+ PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \
482+ PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \
483+ PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \
484+ PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \
485+ PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \
486+ PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \
487+ PIN_OTYPE_PUSHPULL(GPIOB_LED3) | \
488+ PIN_OTYPE_PUSHPULL(GPIOB_PIN15))
489+#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOB_PIN0) | \
490+ PIN_OSPEED_VERYLOW(GPIOB_PIN1) | \
491+ PIN_OSPEED_VERYLOW(GPIOB_PIN2) | \
492+ PIN_OSPEED_HIGH(GPIOB_SWO) | \
493+ PIN_OSPEED_VERYLOW(GPIOB_PIN4) | \
494+ PIN_OSPEED_VERYLOW(GPIOB_PIN5) | \
495+ PIN_OSPEED_VERYLOW(GPIOB_PIN6) | \
496+ PIN_OSPEED_HIGH(GPIOB_LED2) | \
497+ PIN_OSPEED_VERYLOW(GPIOB_PIN8) | \
498+ PIN_OSPEED_VERYLOW(GPIOB_PIN9) | \
499+ PIN_OSPEED_VERYLOW(GPIOB_PIN10) | \
500+ PIN_OSPEED_VERYLOW(GPIOB_PIN11) | \
501+ PIN_OSPEED_VERYLOW(GPIOB_PIN12) | \
502+ PIN_OSPEED_VERYLOW(GPIOB_PIN13) | \
503+ PIN_OSPEED_HIGH(GPIOB_LED3) | \
504+ PIN_OSPEED_VERYLOW(GPIOB_PIN15))
505+#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_PIN0) | \
506+ PIN_PUPDR_FLOATING(GPIOB_PIN1) | \
507+ PIN_PUPDR_FLOATING(GPIOB_PIN2) | \
508+ PIN_PUPDR_FLOATING(GPIOB_SWO) | \
509+ PIN_PUPDR_FLOATING(GPIOB_PIN4) | \
510+ PIN_PUPDR_FLOATING(GPIOB_PIN5) | \
511+ PIN_PUPDR_FLOATING(GPIOB_PIN6) | \
512+ PIN_PUPDR_FLOATING(GPIOB_LED2) | \
513+ PIN_PUPDR_FLOATING(GPIOB_PIN8) | \
514+ PIN_PUPDR_FLOATING(GPIOB_PIN9) | \
515+ PIN_PUPDR_FLOATING(GPIOB_PIN10) | \
516+ PIN_PUPDR_FLOATING(GPIOB_PIN11) | \
517+ PIN_PUPDR_FLOATING(GPIOB_PIN12) | \
518+ PIN_PUPDR_FLOATING(GPIOB_PIN13) | \
519+ PIN_PUPDR_FLOATING(GPIOB_LED3) | \
520+ PIN_PUPDR_FLOATING(GPIOB_PIN15))
521+#define VAL_GPIOB_ODR (PIN_ODR_LOW(GPIOB_PIN0) | \
522+ PIN_ODR_LOW(GPIOB_PIN1) | \
523+ PIN_ODR_LOW(GPIOB_PIN2) | \
524+ PIN_ODR_LOW(GPIOB_SWO) | \
525+ PIN_ODR_LOW(GPIOB_PIN4) | \
526+ PIN_ODR_LOW(GPIOB_PIN5) | \
527+ PIN_ODR_LOW(GPIOB_PIN6) | \
528+ PIN_ODR_LOW(GPIOB_LED2) | \
529+ PIN_ODR_LOW(GPIOB_PIN8) | \
530+ PIN_ODR_LOW(GPIOB_PIN9) | \
531+ PIN_ODR_LOW(GPIOB_PIN10) | \
532+ PIN_ODR_LOW(GPIOB_PIN11) | \
533+ PIN_ODR_LOW(GPIOB_PIN12) | \
534+ PIN_ODR_LOW(GPIOB_PIN13) | \
535+ PIN_ODR_LOW(GPIOB_LED3) | \
536+ PIN_ODR_LOW(GPIOB_PIN15))
537+#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0U) | \
538+ PIN_AFIO_AF(GPIOB_PIN1, 0U) | \
539+ PIN_AFIO_AF(GPIOB_PIN2, 0U) | \
540+ PIN_AFIO_AF(GPIOB_SWO, 0U) | \
541+ PIN_AFIO_AF(GPIOB_PIN4, 0U) | \
542+ PIN_AFIO_AF(GPIOB_PIN5, 0U) | \
543+ PIN_AFIO_AF(GPIOB_PIN6, 0U) | \
544+ PIN_AFIO_AF(GPIOB_LED2, 0U))
545+#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \
546+ PIN_AFIO_AF(GPIOB_PIN9, 0U) | \
547+ PIN_AFIO_AF(GPIOB_PIN10, 0U) | \
548+ PIN_AFIO_AF(GPIOB_PIN11, 0U) | \
549+ PIN_AFIO_AF(GPIOB_PIN12, 0U) | \
550+ PIN_AFIO_AF(GPIOB_PIN13, 0U) | \
551+ PIN_AFIO_AF(GPIOB_LED3, 0U) | \
552+ PIN_AFIO_AF(GPIOB_PIN15, 0U))
553+#define VAL_GPIOB_ASCR (PIN_ASCR_DISABLED(GPIOB_PIN0) | \
554+ PIN_ASCR_DISABLED(GPIOB_PIN1) | \
555+ PIN_ASCR_DISABLED(GPIOB_PIN2) | \
556+ PIN_ASCR_DISABLED(GPIOB_SWO) | \
557+ PIN_ASCR_DISABLED(GPIOB_PIN4) | \
558+ PIN_ASCR_DISABLED(GPIOB_PIN5) | \
559+ PIN_ASCR_DISABLED(GPIOB_PIN6) | \
560+ PIN_ASCR_DISABLED(GPIOB_LED2) | \
561+ PIN_ASCR_DISABLED(GPIOB_PIN8) | \
562+ PIN_ASCR_DISABLED(GPIOB_PIN9) | \
563+ PIN_ASCR_DISABLED(GPIOB_PIN10) | \
564+ PIN_ASCR_DISABLED(GPIOB_PIN11) | \
565+ PIN_ASCR_DISABLED(GPIOB_PIN12) | \
566+ PIN_ASCR_DISABLED(GPIOB_PIN13) | \
567+ PIN_ASCR_DISABLED(GPIOB_LED3) | \
568+ PIN_ASCR_DISABLED(GPIOB_PIN15))
569+#define VAL_GPIOB_LOCKR (PIN_LOCKR_DISABLED(GPIOB_PIN0) | \
570+ PIN_LOCKR_DISABLED(GPIOB_PIN1) | \
571+ PIN_LOCKR_DISABLED(GPIOB_PIN2) | \
572+ PIN_LOCKR_DISABLED(GPIOB_SWO) | \
573+ PIN_LOCKR_DISABLED(GPIOB_PIN4) | \
574+ PIN_LOCKR_DISABLED(GPIOB_PIN5) | \
575+ PIN_LOCKR_DISABLED(GPIOB_PIN6) | \
576+ PIN_LOCKR_DISABLED(GPIOB_LED2) | \
577+ PIN_LOCKR_DISABLED(GPIOB_PIN8) | \
578+ PIN_LOCKR_DISABLED(GPIOB_PIN9) | \
579+ PIN_LOCKR_DISABLED(GPIOB_PIN10) | \
580+ PIN_LOCKR_DISABLED(GPIOB_PIN11) | \
581+ PIN_LOCKR_DISABLED(GPIOB_PIN12) | \
582+ PIN_LOCKR_DISABLED(GPIOB_PIN13) | \
583+ PIN_LOCKR_DISABLED(GPIOB_LED3) | \
584+ PIN_LOCKR_DISABLED(GPIOB_PIN15))
585+
586+/*
587+ * GPIOC setup:
588+ *
589+ * PC0 - PIN0 (analog).
590+ * PC1 - PIN1 (analog).
591+ * PC2 - PIN2 (analog).
592+ * PC3 - PIN3 (analog).
593+ * PC4 - PIN4 (analog).
594+ * PC5 - PIN5 (analog).
595+ * PC6 - PIN6 (analog).
596+ * PC7 - LED1 LED_GREEN (output pushpull maximum).
597+ * PC8 - PIN8 (analog).
598+ * PC9 - PIN9 (analog).
599+ * PC10 - PIN10 (analog).
600+ * PC11 - PIN11 (analog).
601+ * PC12 - PIN12 (analog).
602+ * PC13 - BUTTON (input floating).
603+ * PC14 - PIN14 (analog).
604+ * PC15 - PIN15 (analog).
605+ */
606+#define VAL_GPIOC_MODER (PIN_MODE_ANALOG(GPIOC_PIN0) | \
607+ PIN_MODE_ANALOG(GPIOC_PIN1) | \
608+ PIN_MODE_ANALOG(GPIOC_PIN2) | \
609+ PIN_MODE_ANALOG(GPIOC_PIN3) | \
610+ PIN_MODE_ANALOG(GPIOC_PIN4) | \
611+ PIN_MODE_ANALOG(GPIOC_PIN5) | \
612+ PIN_MODE_ANALOG(GPIOC_PIN6) | \
613+ PIN_MODE_OUTPUT(GPIOC_LED1) | \
614+ PIN_MODE_ANALOG(GPIOC_PIN8) | \
615+ PIN_MODE_ANALOG(GPIOC_PIN9) | \
616+ PIN_MODE_ANALOG(GPIOC_PIN10) | \
617+ PIN_MODE_ANALOG(GPIOC_PIN11) | \
618+ PIN_MODE_ANALOG(GPIOC_PIN12) | \
619+ PIN_MODE_INPUT(GPIOC_BUTTON) | \
620+ PIN_MODE_ANALOG(GPIOC_PIN14) | \
621+ PIN_MODE_ANALOG(GPIOC_PIN15))
622+#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \
623+ PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \
624+ PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \
625+ PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \
626+ PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \
627+ PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \
628+ PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \
629+ PIN_OTYPE_PUSHPULL(GPIOC_LED1) | \
630+ PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \
631+ PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \
632+ PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \
633+ PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \
634+ PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \
635+ PIN_OTYPE_PUSHPULL(GPIOC_BUTTON) | \
636+ PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \
637+ PIN_OTYPE_PUSHPULL(GPIOC_PIN15))
638+#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOC_PIN0) | \
639+ PIN_OSPEED_VERYLOW(GPIOC_PIN1) | \
640+ PIN_OSPEED_VERYLOW(GPIOC_PIN2) | \
641+ PIN_OSPEED_VERYLOW(GPIOC_PIN3) | \
642+ PIN_OSPEED_VERYLOW(GPIOC_PIN4) | \
643+ PIN_OSPEED_VERYLOW(GPIOC_PIN5) | \
644+ PIN_OSPEED_VERYLOW(GPIOC_PIN6) | \
645+ PIN_OSPEED_HIGH(GPIOC_LED1) | \
646+ PIN_OSPEED_VERYLOW(GPIOC_PIN8) | \
647+ PIN_OSPEED_VERYLOW(GPIOC_PIN9) | \
648+ PIN_OSPEED_VERYLOW(GPIOC_PIN10) | \
649+ PIN_OSPEED_VERYLOW(GPIOC_PIN11) | \
650+ PIN_OSPEED_VERYLOW(GPIOC_PIN12) | \
651+ PIN_OSPEED_VERYLOW(GPIOC_BUTTON) | \
652+ PIN_OSPEED_VERYLOW(GPIOC_PIN14) | \
653+ PIN_OSPEED_VERYLOW(GPIOC_PIN15))
654+#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_PIN0) | \
655+ PIN_PUPDR_FLOATING(GPIOC_PIN1) | \
656+ PIN_PUPDR_FLOATING(GPIOC_PIN2) | \
657+ PIN_PUPDR_FLOATING(GPIOC_PIN3) | \
658+ PIN_PUPDR_FLOATING(GPIOC_PIN4) | \
659+ PIN_PUPDR_FLOATING(GPIOC_PIN5) | \
660+ PIN_PUPDR_FLOATING(GPIOC_PIN6) | \
661+ PIN_PUPDR_FLOATING(GPIOC_LED1) | \
662+ PIN_PUPDR_FLOATING(GPIOC_PIN8) | \
663+ PIN_PUPDR_FLOATING(GPIOC_PIN9) | \
664+ PIN_PUPDR_FLOATING(GPIOC_PIN10) | \
665+ PIN_PUPDR_FLOATING(GPIOC_PIN11) | \
666+ PIN_PUPDR_FLOATING(GPIOC_PIN12) | \
667+ PIN_PUPDR_FLOATING(GPIOC_BUTTON) | \
668+ PIN_PUPDR_FLOATING(GPIOC_PIN14) | \
669+ PIN_PUPDR_FLOATING(GPIOC_PIN15))
670+#define VAL_GPIOC_ODR (PIN_ODR_LOW(GPIOC_PIN0) | \
671+ PIN_ODR_LOW(GPIOC_PIN1) | \
672+ PIN_ODR_LOW(GPIOC_PIN2) | \
673+ PIN_ODR_LOW(GPIOC_PIN3) | \
674+ PIN_ODR_LOW(GPIOC_PIN4) | \
675+ PIN_ODR_LOW(GPIOC_PIN5) | \
676+ PIN_ODR_LOW(GPIOC_PIN6) | \
677+ PIN_ODR_LOW(GPIOC_LED1) | \
678+ PIN_ODR_LOW(GPIOC_PIN8) | \
679+ PIN_ODR_LOW(GPIOC_PIN9) | \
680+ PIN_ODR_LOW(GPIOC_PIN10) | \
681+ PIN_ODR_LOW(GPIOC_PIN11) | \
682+ PIN_ODR_LOW(GPIOC_PIN12) | \
683+ PIN_ODR_LOW(GPIOC_BUTTON) | \
684+ PIN_ODR_LOW(GPIOC_PIN14) | \
685+ PIN_ODR_LOW(GPIOC_PIN15))
686+#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \
687+ PIN_AFIO_AF(GPIOC_PIN1, 0U) | \
688+ PIN_AFIO_AF(GPIOC_PIN2, 0U) | \
689+ PIN_AFIO_AF(GPIOC_PIN3, 0U) | \
690+ PIN_AFIO_AF(GPIOC_PIN4, 0U) | \
691+ PIN_AFIO_AF(GPIOC_PIN5, 0U) | \
692+ PIN_AFIO_AF(GPIOC_PIN6, 0U) | \
693+ PIN_AFIO_AF(GPIOC_LED1, 0U))
694+#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \
695+ PIN_AFIO_AF(GPIOC_PIN9, 0U) | \
696+ PIN_AFIO_AF(GPIOC_PIN10, 0U) | \
697+ PIN_AFIO_AF(GPIOC_PIN11, 0U) | \
698+ PIN_AFIO_AF(GPIOC_PIN12, 0U) | \
699+ PIN_AFIO_AF(GPIOC_BUTTON, 0U) | \
700+ PIN_AFIO_AF(GPIOC_PIN14, 0U) | \
701+ PIN_AFIO_AF(GPIOC_PIN15, 0U))
702+#define VAL_GPIOC_ASCR (PIN_ASCR_DISABLED(GPIOC_PIN0) | \
703+ PIN_ASCR_DISABLED(GPIOC_PIN1) | \
704+ PIN_ASCR_DISABLED(GPIOC_PIN2) | \
705+ PIN_ASCR_DISABLED(GPIOC_PIN3) | \
706+ PIN_ASCR_DISABLED(GPIOC_PIN4) | \
707+ PIN_ASCR_DISABLED(GPIOC_PIN5) | \
708+ PIN_ASCR_DISABLED(GPIOC_PIN6) | \
709+ PIN_ASCR_DISABLED(GPIOC_LED1) | \
710+ PIN_ASCR_DISABLED(GPIOC_PIN8) | \
711+ PIN_ASCR_DISABLED(GPIOC_PIN9) | \
712+ PIN_ASCR_DISABLED(GPIOC_PIN10) | \
713+ PIN_ASCR_DISABLED(GPIOC_PIN11) | \
714+ PIN_ASCR_DISABLED(GPIOC_PIN12) | \
715+ PIN_ASCR_DISABLED(GPIOC_BUTTON) | \
716+ PIN_ASCR_DISABLED(GPIOC_PIN14) | \
717+ PIN_ASCR_DISABLED(GPIOC_PIN15))
718+#define VAL_GPIOC_LOCKR (PIN_LOCKR_DISABLED(GPIOC_PIN0) | \
719+ PIN_LOCKR_DISABLED(GPIOC_PIN1) | \
720+ PIN_LOCKR_DISABLED(GPIOC_PIN2) | \
721+ PIN_LOCKR_DISABLED(GPIOC_PIN3) | \
722+ PIN_LOCKR_DISABLED(GPIOC_PIN4) | \
723+ PIN_LOCKR_DISABLED(GPIOC_PIN5) | \
724+ PIN_LOCKR_DISABLED(GPIOC_PIN6) | \
725+ PIN_LOCKR_DISABLED(GPIOC_LED1) | \
726+ PIN_LOCKR_DISABLED(GPIOC_PIN8) | \
727+ PIN_LOCKR_DISABLED(GPIOC_PIN9) | \
728+ PIN_LOCKR_DISABLED(GPIOC_PIN10) | \
729+ PIN_LOCKR_DISABLED(GPIOC_PIN11) | \
730+ PIN_LOCKR_DISABLED(GPIOC_PIN12) | \
731+ PIN_LOCKR_DISABLED(GPIOC_BUTTON) | \
732+ PIN_LOCKR_DISABLED(GPIOC_PIN14) | \
733+ PIN_LOCKR_DISABLED(GPIOC_PIN15))
734+
735+/*
736+ * GPIOD setup:
737+ *
738+ * PD0 - PIN0 (analog).
739+ * PD1 - PIN1 (analog).
740+ * PD2 - PIN2 (analog).
741+ * PD3 - PIN3 (analog).
742+ * PD4 - PIN4 (analog).
743+ * PD5 - PIN5 (analog).
744+ * PD6 - PIN6 (analog).
745+ * PD7 - PIN7 (analog).
746+ * PD8 - PIN8 (analog).
747+ * PD9 - PIN9 (analog).
748+ * PD10 - PIN10 (analog).
749+ * PD11 - PIN11 (analog).
750+ * PD12 - PIN12 (analog).
751+ * PD13 - PIN13 (analog).
752+ * PD14 - PIN14 (analog).
753+ * PD15 - PIN15 (analog).
754+ */
755+#define VAL_GPIOD_MODER (PIN_MODE_ANALOG(GPIOD_PIN0) | \
756+ PIN_MODE_ANALOG(GPIOD_PIN1) | \
757+ PIN_MODE_ANALOG(GPIOD_PIN2) | \
758+ PIN_MODE_ANALOG(GPIOD_PIN3) | \
759+ PIN_MODE_ANALOG(GPIOD_PIN4) | \
760+ PIN_MODE_ANALOG(GPIOD_PIN5) | \
761+ PIN_MODE_ANALOG(GPIOD_PIN6) | \
762+ PIN_MODE_ANALOG(GPIOD_PIN7) | \
763+ PIN_MODE_ANALOG(GPIOD_PIN8) | \
764+ PIN_MODE_ANALOG(GPIOD_PIN9) | \
765+ PIN_MODE_ANALOG(GPIOD_PIN10) | \
766+ PIN_MODE_ANALOG(GPIOD_PIN11) | \
767+ PIN_MODE_ANALOG(GPIOD_PIN12) | \
768+ PIN_MODE_ANALOG(GPIOD_PIN13) | \
769+ PIN_MODE_ANALOG(GPIOD_PIN14) | \
770+ PIN_MODE_ANALOG(GPIOD_PIN15))
771+#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \
772+ PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \
773+ PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \
774+ PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \
775+ PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \
776+ PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \
777+ PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \
778+ PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \
779+ PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \
780+ PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \
781+ PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \
782+ PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \
783+ PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \
784+ PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \
785+ PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \
786+ PIN_OTYPE_PUSHPULL(GPIOD_PIN15))
787+#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOD_PIN0) | \
788+ PIN_OSPEED_VERYLOW(GPIOD_PIN1) | \
789+ PIN_OSPEED_VERYLOW(GPIOD_PIN2) | \
790+ PIN_OSPEED_VERYLOW(GPIOD_PIN3) | \
791+ PIN_OSPEED_VERYLOW(GPIOD_PIN4) | \
792+ PIN_OSPEED_VERYLOW(GPIOD_PIN5) | \
793+ PIN_OSPEED_VERYLOW(GPIOD_PIN6) | \
794+ PIN_OSPEED_VERYLOW(GPIOD_PIN7) | \
795+ PIN_OSPEED_VERYLOW(GPIOD_PIN8) | \
796+ PIN_OSPEED_VERYLOW(GPIOD_PIN9) | \
797+ PIN_OSPEED_VERYLOW(GPIOD_PIN10) | \
798+ PIN_OSPEED_VERYLOW(GPIOD_PIN11) | \
799+ PIN_OSPEED_VERYLOW(GPIOD_PIN12) | \
800+ PIN_OSPEED_VERYLOW(GPIOD_PIN13) | \
801+ PIN_OSPEED_VERYLOW(GPIOD_PIN14) | \
802+ PIN_OSPEED_VERYLOW(GPIOD_PIN15))
803+#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_PIN0) | \
804+ PIN_PUPDR_FLOATING(GPIOD_PIN1) | \
805+ PIN_PUPDR_FLOATING(GPIOD_PIN2) | \
806+ PIN_PUPDR_FLOATING(GPIOD_PIN3) | \
807+ PIN_PUPDR_FLOATING(GPIOD_PIN4) | \
808+ PIN_PUPDR_FLOATING(GPIOD_PIN5) | \
809+ PIN_PUPDR_FLOATING(GPIOD_PIN6) | \
810+ PIN_PUPDR_FLOATING(GPIOD_PIN7) | \
811+ PIN_PUPDR_FLOATING(GPIOD_PIN8) | \
812+ PIN_PUPDR_FLOATING(GPIOD_PIN9) | \
813+ PIN_PUPDR_FLOATING(GPIOD_PIN10) | \
814+ PIN_PUPDR_FLOATING(GPIOD_PIN11) | \
815+ PIN_PUPDR_FLOATING(GPIOD_PIN12) | \
816+ PIN_PUPDR_FLOATING(GPIOD_PIN13) | \
817+ PIN_PUPDR_FLOATING(GPIOD_PIN14) | \
818+ PIN_PUPDR_FLOATING(GPIOD_PIN15))
819+#define VAL_GPIOD_ODR (PIN_ODR_LOW(GPIOD_PIN0) | \
820+ PIN_ODR_LOW(GPIOD_PIN1) | \
821+ PIN_ODR_LOW(GPIOD_PIN2) | \
822+ PIN_ODR_LOW(GPIOD_PIN3) | \
823+ PIN_ODR_LOW(GPIOD_PIN4) | \
824+ PIN_ODR_LOW(GPIOD_PIN5) | \
825+ PIN_ODR_LOW(GPIOD_PIN6) | \
826+ PIN_ODR_LOW(GPIOD_PIN7) | \
827+ PIN_ODR_LOW(GPIOD_PIN8) | \
828+ PIN_ODR_LOW(GPIOD_PIN9) | \
829+ PIN_ODR_LOW(GPIOD_PIN10) | \
830+ PIN_ODR_LOW(GPIOD_PIN11) | \
831+ PIN_ODR_LOW(GPIOD_PIN12) | \
832+ PIN_ODR_LOW(GPIOD_PIN13) | \
833+ PIN_ODR_LOW(GPIOD_PIN14) | \
834+ PIN_ODR_LOW(GPIOD_PIN15))
835+#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \
836+ PIN_AFIO_AF(GPIOD_PIN1, 0U) | \
837+ PIN_AFIO_AF(GPIOD_PIN2, 0U) | \
838+ PIN_AFIO_AF(GPIOD_PIN3, 0U) | \
839+ PIN_AFIO_AF(GPIOD_PIN4, 0U) | \
840+ PIN_AFIO_AF(GPIOD_PIN5, 0U) | \
841+ PIN_AFIO_AF(GPIOD_PIN6, 0U) | \
842+ PIN_AFIO_AF(GPIOD_PIN7, 0U))
843+#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \
844+ PIN_AFIO_AF(GPIOD_PIN9, 0U) | \
845+ PIN_AFIO_AF(GPIOD_PIN10, 0U) | \
846+ PIN_AFIO_AF(GPIOD_PIN11, 0U) | \
847+ PIN_AFIO_AF(GPIOD_PIN12, 0U) | \
848+ PIN_AFIO_AF(GPIOD_PIN13, 0U) | \
849+ PIN_AFIO_AF(GPIOD_PIN14, 0U) | \
850+ PIN_AFIO_AF(GPIOD_PIN15, 0U))
851+#define VAL_GPIOD_ASCR (PIN_ASCR_DISABLED(GPIOD_PIN0) | \
852+ PIN_ASCR_DISABLED(GPIOD_PIN1) | \
853+ PIN_ASCR_DISABLED(GPIOD_PIN2) | \
854+ PIN_ASCR_DISABLED(GPIOD_PIN3) | \
855+ PIN_ASCR_DISABLED(GPIOD_PIN4) | \
856+ PIN_ASCR_DISABLED(GPIOD_PIN5) | \
857+ PIN_ASCR_DISABLED(GPIOD_PIN6) | \
858+ PIN_ASCR_DISABLED(GPIOD_PIN7) | \
859+ PIN_ASCR_DISABLED(GPIOD_PIN8) | \
860+ PIN_ASCR_DISABLED(GPIOD_PIN9) | \
861+ PIN_ASCR_DISABLED(GPIOD_PIN10) | \
862+ PIN_ASCR_DISABLED(GPIOD_PIN11) | \
863+ PIN_ASCR_DISABLED(GPIOD_PIN12) | \
864+ PIN_ASCR_DISABLED(GPIOD_PIN13) | \
865+ PIN_ASCR_DISABLED(GPIOD_PIN14) | \
866+ PIN_ASCR_DISABLED(GPIOD_PIN15))
867+#define VAL_GPIOD_LOCKR (PIN_LOCKR_DISABLED(GPIOD_PIN0) | \
868+ PIN_LOCKR_DISABLED(GPIOD_PIN1) | \
869+ PIN_LOCKR_DISABLED(GPIOD_PIN2) | \
870+ PIN_LOCKR_DISABLED(GPIOD_PIN3) | \
871+ PIN_LOCKR_DISABLED(GPIOD_PIN4) | \
872+ PIN_LOCKR_DISABLED(GPIOD_PIN5) | \
873+ PIN_LOCKR_DISABLED(GPIOD_PIN6) | \
874+ PIN_LOCKR_DISABLED(GPIOD_PIN7) | \
875+ PIN_LOCKR_DISABLED(GPIOD_PIN8) | \
876+ PIN_LOCKR_DISABLED(GPIOD_PIN9) | \
877+ PIN_LOCKR_DISABLED(GPIOD_PIN10) | \
878+ PIN_LOCKR_DISABLED(GPIOD_PIN11) | \
879+ PIN_LOCKR_DISABLED(GPIOD_PIN12) | \
880+ PIN_LOCKR_DISABLED(GPIOD_PIN13) | \
881+ PIN_LOCKR_DISABLED(GPIOD_PIN14) | \
882+ PIN_LOCKR_DISABLED(GPIOD_PIN15))
883+
884+/*
885+ * GPIOE setup:
886+ *
887+ * PE0 - PIN0 (analog).
888+ * PE1 - PIN1 (analog).
889+ * PE2 - PIN2 (analog).
890+ * PE3 - PIN3 (analog).
891+ * PE4 - PIN4 (analog).
892+ * PE5 - PIN5 (analog).
893+ * PE6 - PIN6 (analog).
894+ * PE7 - PIN7 (analog).
895+ * PE8 - PIN8 (analog).
896+ * PE9 - PIN9 (analog).
897+ * PE10 - PIN10 (analog).
898+ * PE11 - PIN11 (analog).
899+ * PE12 - PIN12 (analog).
900+ * PE13 - PIN13 (analog).
901+ * PE14 - PIN14 (analog).
902+ * PE15 - PIN15 (analog).
903+ */
904+#define VAL_GPIOE_MODER (PIN_MODE_ANALOG(GPIOE_PIN0) | \
905+ PIN_MODE_ANALOG(GPIOE_PIN1) | \
906+ PIN_MODE_ANALOG(GPIOE_PIN2) | \
907+ PIN_MODE_ANALOG(GPIOE_PIN3) | \
908+ PIN_MODE_ANALOG(GPIOE_PIN4) | \
909+ PIN_MODE_ANALOG(GPIOE_PIN5) | \
910+ PIN_MODE_ANALOG(GPIOE_PIN6) | \
911+ PIN_MODE_ANALOG(GPIOE_PIN7) | \
912+ PIN_MODE_ANALOG(GPIOE_PIN8) | \
913+ PIN_MODE_ANALOG(GPIOE_PIN9) | \
914+ PIN_MODE_ANALOG(GPIOE_PIN10) | \
915+ PIN_MODE_ANALOG(GPIOE_PIN11) | \
916+ PIN_MODE_ANALOG(GPIOE_PIN12) | \
917+ PIN_MODE_ANALOG(GPIOE_PIN13) | \
918+ PIN_MODE_ANALOG(GPIOE_PIN14) | \
919+ PIN_MODE_ANALOG(GPIOE_PIN15))
920+#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \
921+ PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \
922+ PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \
923+ PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \
924+ PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \
925+ PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \
926+ PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \
927+ PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \
928+ PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \
929+ PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \
930+ PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \
931+ PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \
932+ PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \
933+ PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \
934+ PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \
935+ PIN_OTYPE_PUSHPULL(GPIOE_PIN15))
936+#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOE_PIN0) | \
937+ PIN_OSPEED_VERYLOW(GPIOE_PIN1) | \
938+ PIN_OSPEED_VERYLOW(GPIOE_PIN2) | \
939+ PIN_OSPEED_VERYLOW(GPIOE_PIN3) | \
940+ PIN_OSPEED_VERYLOW(GPIOE_PIN4) | \
941+ PIN_OSPEED_VERYLOW(GPIOE_PIN5) | \
942+ PIN_OSPEED_VERYLOW(GPIOE_PIN6) | \
943+ PIN_OSPEED_VERYLOW(GPIOE_PIN7) | \
944+ PIN_OSPEED_VERYLOW(GPIOE_PIN8) | \
945+ PIN_OSPEED_VERYLOW(GPIOE_PIN9) | \
946+ PIN_OSPEED_VERYLOW(GPIOE_PIN10) | \
947+ PIN_OSPEED_VERYLOW(GPIOE_PIN11) | \
948+ PIN_OSPEED_VERYLOW(GPIOE_PIN12) | \
949+ PIN_OSPEED_VERYLOW(GPIOE_PIN13) | \
950+ PIN_OSPEED_VERYLOW(GPIOE_PIN14) | \
951+ PIN_OSPEED_VERYLOW(GPIOE_PIN15))
952+#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_PIN0) | \
953+ PIN_PUPDR_FLOATING(GPIOE_PIN1) | \
954+ PIN_PUPDR_FLOATING(GPIOE_PIN2) | \
955+ PIN_PUPDR_FLOATING(GPIOE_PIN3) | \
956+ PIN_PUPDR_FLOATING(GPIOE_PIN4) | \
957+ PIN_PUPDR_FLOATING(GPIOE_PIN5) | \
958+ PIN_PUPDR_FLOATING(GPIOE_PIN6) | \
959+ PIN_PUPDR_FLOATING(GPIOE_PIN7) | \
960+ PIN_PUPDR_FLOATING(GPIOE_PIN8) | \
961+ PIN_PUPDR_FLOATING(GPIOE_PIN9) | \
962+ PIN_PUPDR_FLOATING(GPIOE_PIN10) | \
963+ PIN_PUPDR_FLOATING(GPIOE_PIN11) | \
964+ PIN_PUPDR_FLOATING(GPIOE_PIN12) | \
965+ PIN_PUPDR_FLOATING(GPIOE_PIN13) | \
966+ PIN_PUPDR_FLOATING(GPIOE_PIN14) | \
967+ PIN_PUPDR_FLOATING(GPIOE_PIN15))
968+#define VAL_GPIOE_ODR (PIN_ODR_LOW(GPIOE_PIN0) | \
969+ PIN_ODR_LOW(GPIOE_PIN1) | \
970+ PIN_ODR_LOW(GPIOE_PIN2) | \
971+ PIN_ODR_LOW(GPIOE_PIN3) | \
972+ PIN_ODR_LOW(GPIOE_PIN4) | \
973+ PIN_ODR_LOW(GPIOE_PIN5) | \
974+ PIN_ODR_LOW(GPIOE_PIN6) | \
975+ PIN_ODR_LOW(GPIOE_PIN7) | \
976+ PIN_ODR_LOW(GPIOE_PIN8) | \
977+ PIN_ODR_LOW(GPIOE_PIN9) | \
978+ PIN_ODR_LOW(GPIOE_PIN10) | \
979+ PIN_ODR_LOW(GPIOE_PIN11) | \
980+ PIN_ODR_LOW(GPIOE_PIN12) | \
981+ PIN_ODR_LOW(GPIOE_PIN13) | \
982+ PIN_ODR_LOW(GPIOE_PIN14) | \
983+ PIN_ODR_LOW(GPIOE_PIN15))
984+#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \
985+ PIN_AFIO_AF(GPIOE_PIN1, 0U) | \
986+ PIN_AFIO_AF(GPIOE_PIN2, 0U) | \
987+ PIN_AFIO_AF(GPIOE_PIN3, 0U) | \
988+ PIN_AFIO_AF(GPIOE_PIN4, 0U) | \
989+ PIN_AFIO_AF(GPIOE_PIN5, 0U) | \
990+ PIN_AFIO_AF(GPIOE_PIN6, 0U) | \
991+ PIN_AFIO_AF(GPIOE_PIN7, 0U))
992+#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \
993+ PIN_AFIO_AF(GPIOE_PIN9, 0U) | \
994+ PIN_AFIO_AF(GPIOE_PIN10, 0U) | \
995+ PIN_AFIO_AF(GPIOE_PIN11, 0U) | \
996+ PIN_AFIO_AF(GPIOE_PIN12, 0U) | \
997+ PIN_AFIO_AF(GPIOE_PIN13, 0U) | \
998+ PIN_AFIO_AF(GPIOE_PIN14, 0U) | \
999+ PIN_AFIO_AF(GPIOE_PIN15, 0U))
1000+#define VAL_GPIOE_ASCR (PIN_ASCR_DISABLED(GPIOE_PIN0) | \
1001+ PIN_ASCR_DISABLED(GPIOE_PIN1) | \
1002+ PIN_ASCR_DISABLED(GPIOE_PIN2) | \
1003+ PIN_ASCR_DISABLED(GPIOE_PIN3) | \
1004+ PIN_ASCR_DISABLED(GPIOE_PIN4) | \
1005+ PIN_ASCR_DISABLED(GPIOE_PIN5) | \
1006+ PIN_ASCR_DISABLED(GPIOE_PIN6) | \
1007+ PIN_ASCR_DISABLED(GPIOE_PIN7) | \
1008+ PIN_ASCR_DISABLED(GPIOE_PIN8) | \
1009+ PIN_ASCR_DISABLED(GPIOE_PIN9) | \
1010+ PIN_ASCR_DISABLED(GPIOE_PIN10) | \
1011+ PIN_ASCR_DISABLED(GPIOE_PIN11) | \
1012+ PIN_ASCR_DISABLED(GPIOE_PIN12) | \
1013+ PIN_ASCR_DISABLED(GPIOE_PIN13) | \
1014+ PIN_ASCR_DISABLED(GPIOE_PIN14) | \
1015+ PIN_ASCR_DISABLED(GPIOE_PIN15))
1016+#define VAL_GPIOE_LOCKR (PIN_LOCKR_DISABLED(GPIOE_PIN0) | \
1017+ PIN_LOCKR_DISABLED(GPIOE_PIN1) | \
1018+ PIN_LOCKR_DISABLED(GPIOE_PIN2) | \
1019+ PIN_LOCKR_DISABLED(GPIOE_PIN3) | \
1020+ PIN_LOCKR_DISABLED(GPIOE_PIN4) | \
1021+ PIN_LOCKR_DISABLED(GPIOE_PIN5) | \
1022+ PIN_LOCKR_DISABLED(GPIOE_PIN6) | \
1023+ PIN_LOCKR_DISABLED(GPIOE_PIN7) | \
1024+ PIN_LOCKR_DISABLED(GPIOE_PIN8) | \
1025+ PIN_LOCKR_DISABLED(GPIOE_PIN9) | \
1026+ PIN_LOCKR_DISABLED(GPIOE_PIN10) | \
1027+ PIN_LOCKR_DISABLED(GPIOE_PIN11) | \
1028+ PIN_LOCKR_DISABLED(GPIOE_PIN12) | \
1029+ PIN_LOCKR_DISABLED(GPIOE_PIN13) | \
1030+ PIN_LOCKR_DISABLED(GPIOE_PIN14) | \
1031+ PIN_LOCKR_DISABLED(GPIOE_PIN15))
1032+
1033+/*
1034+ * GPIOF setup:
1035+ *
1036+ * PF0 - PIN0 (analog).
1037+ * PF1 - PIN1 (analog).
1038+ * PF2 - PIN2 (analog).
1039+ * PF3 - PIN3 (analog).
1040+ * PF4 - PIN4 (analog).
1041+ * PF5 - PIN5 (analog).
1042+ * PF6 - PIN6 (analog).
1043+ * PF7 - PIN7 (analog).
1044+ * PF8 - PIN8 (analog).
1045+ * PF9 - PIN9 (analog).
1046+ * PF10 - PIN10 (analog).
1047+ * PF11 - PIN11 (analog).
1048+ * PF12 - PIN12 (analog).
1049+ * PF13 - PIN13 (analog).
1050+ * PF14 - PIN14 (analog).
1051+ * PF15 - PIN15 (analog).
1052+ */
1053+#define VAL_GPIOF_MODER (PIN_MODE_ANALOG(GPIOF_PIN0) | \
1054+ PIN_MODE_ANALOG(GPIOF_PIN1) | \
1055+ PIN_MODE_ANALOG(GPIOF_PIN2) | \
1056+ PIN_MODE_ANALOG(GPIOF_PIN3) | \
1057+ PIN_MODE_ANALOG(GPIOF_PIN4) | \
1058+ PIN_MODE_ANALOG(GPIOF_PIN5) | \
1059+ PIN_MODE_ANALOG(GPIOF_PIN6) | \
1060+ PIN_MODE_ANALOG(GPIOF_PIN7) | \
1061+ PIN_MODE_ANALOG(GPIOF_PIN8) | \
1062+ PIN_MODE_ANALOG(GPIOF_PIN9) | \
1063+ PIN_MODE_ANALOG(GPIOF_PIN10) | \
1064+ PIN_MODE_ANALOG(GPIOF_PIN11) | \
1065+ PIN_MODE_ANALOG(GPIOF_PIN12) | \
1066+ PIN_MODE_ANALOG(GPIOF_PIN13) | \
1067+ PIN_MODE_ANALOG(GPIOF_PIN14) | \
1068+ PIN_MODE_ANALOG(GPIOF_PIN15))
1069+#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \
1070+ PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \
1071+ PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \
1072+ PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \
1073+ PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \
1074+ PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \
1075+ PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \
1076+ PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \
1077+ PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \
1078+ PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \
1079+ PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \
1080+ PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \
1081+ PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \
1082+ PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \
1083+ PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \
1084+ PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
1085+#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOF_PIN0) | \
1086+ PIN_OSPEED_VERYLOW(GPIOF_PIN1) | \
1087+ PIN_OSPEED_VERYLOW(GPIOF_PIN2) | \
1088+ PIN_OSPEED_VERYLOW(GPIOF_PIN3) | \
1089+ PIN_OSPEED_VERYLOW(GPIOF_PIN4) | \
1090+ PIN_OSPEED_VERYLOW(GPIOF_PIN5) | \
1091+ PIN_OSPEED_VERYLOW(GPIOF_PIN6) | \
1092+ PIN_OSPEED_VERYLOW(GPIOF_PIN7) | \
1093+ PIN_OSPEED_VERYLOW(GPIOF_PIN8) | \
1094+ PIN_OSPEED_VERYLOW(GPIOF_PIN9) | \
1095+ PIN_OSPEED_VERYLOW(GPIOF_PIN10) | \
1096+ PIN_OSPEED_VERYLOW(GPIOF_PIN11) | \
1097+ PIN_OSPEED_VERYLOW(GPIOF_PIN12) | \
1098+ PIN_OSPEED_VERYLOW(GPIOF_PIN13) | \
1099+ PIN_OSPEED_VERYLOW(GPIOF_PIN14) | \
1100+ PIN_OSPEED_VERYLOW(GPIOF_PIN15))
1101+#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_PIN0) | \
1102+ PIN_PUPDR_FLOATING(GPIOF_PIN1) | \
1103+ PIN_PUPDR_FLOATING(GPIOF_PIN2) | \
1104+ PIN_PUPDR_FLOATING(GPIOF_PIN3) | \
1105+ PIN_PUPDR_FLOATING(GPIOF_PIN4) | \
1106+ PIN_PUPDR_FLOATING(GPIOF_PIN5) | \
1107+ PIN_PUPDR_FLOATING(GPIOF_PIN6) | \
1108+ PIN_PUPDR_FLOATING(GPIOF_PIN7) | \
1109+ PIN_PUPDR_FLOATING(GPIOF_PIN8) | \
1110+ PIN_PUPDR_FLOATING(GPIOF_PIN9) | \
1111+ PIN_PUPDR_FLOATING(GPIOF_PIN10) | \
1112+ PIN_PUPDR_FLOATING(GPIOF_PIN11) | \
1113+ PIN_PUPDR_FLOATING(GPIOF_PIN12) | \
1114+ PIN_PUPDR_FLOATING(GPIOF_PIN13) | \
1115+ PIN_PUPDR_FLOATING(GPIOF_PIN14) | \
1116+ PIN_PUPDR_FLOATING(GPIOF_PIN15))
1117+#define VAL_GPIOF_ODR (PIN_ODR_LOW(GPIOF_PIN0) | \
1118+ PIN_ODR_LOW(GPIOF_PIN1) | \
1119+ PIN_ODR_LOW(GPIOF_PIN2) | \
1120+ PIN_ODR_LOW(GPIOF_PIN3) | \
1121+ PIN_ODR_LOW(GPIOF_PIN4) | \
1122+ PIN_ODR_LOW(GPIOF_PIN5) | \
1123+ PIN_ODR_LOW(GPIOF_PIN6) | \
1124+ PIN_ODR_LOW(GPIOF_PIN7) | \
1125+ PIN_ODR_LOW(GPIOF_PIN8) | \
1126+ PIN_ODR_LOW(GPIOF_PIN9) | \
1127+ PIN_ODR_LOW(GPIOF_PIN10) | \
1128+ PIN_ODR_LOW(GPIOF_PIN11) | \
1129+ PIN_ODR_LOW(GPIOF_PIN12) | \
1130+ PIN_ODR_LOW(GPIOF_PIN13) | \
1131+ PIN_ODR_LOW(GPIOF_PIN14) | \
1132+ PIN_ODR_LOW(GPIOF_PIN15))
1133+#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \
1134+ PIN_AFIO_AF(GPIOF_PIN1, 0U) | \
1135+ PIN_AFIO_AF(GPIOF_PIN2, 0U) | \
1136+ PIN_AFIO_AF(GPIOF_PIN3, 0U) | \
1137+ PIN_AFIO_AF(GPIOF_PIN4, 0U) | \
1138+ PIN_AFIO_AF(GPIOF_PIN5, 0U) | \
1139+ PIN_AFIO_AF(GPIOF_PIN6, 0U) | \
1140+ PIN_AFIO_AF(GPIOF_PIN7, 0U))
1141+#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \
1142+ PIN_AFIO_AF(GPIOF_PIN9, 0U) | \
1143+ PIN_AFIO_AF(GPIOF_PIN10, 0U) | \
1144+ PIN_AFIO_AF(GPIOF_PIN11, 0U) | \
1145+ PIN_AFIO_AF(GPIOF_PIN12, 0U) | \
1146+ PIN_AFIO_AF(GPIOF_PIN13, 0U) | \
1147+ PIN_AFIO_AF(GPIOF_PIN14, 0U) | \
1148+ PIN_AFIO_AF(GPIOF_PIN15, 0U))
1149+#define VAL_GPIOF_ASCR (PIN_ASCR_DISABLED(GPIOF_PIN0) | \
1150+ PIN_ASCR_DISABLED(GPIOF_PIN1) | \
1151+ PIN_ASCR_DISABLED(GPIOF_PIN2) | \
1152+ PIN_ASCR_DISABLED(GPIOF_PIN3) | \
1153+ PIN_ASCR_DISABLED(GPIOF_PIN4) | \
1154+ PIN_ASCR_DISABLED(GPIOF_PIN5) | \
1155+ PIN_ASCR_DISABLED(GPIOF_PIN6) | \
1156+ PIN_ASCR_DISABLED(GPIOF_PIN7) | \
1157+ PIN_ASCR_DISABLED(GPIOF_PIN8) | \
1158+ PIN_ASCR_DISABLED(GPIOF_PIN9) | \
1159+ PIN_ASCR_DISABLED(GPIOF_PIN10) | \
1160+ PIN_ASCR_DISABLED(GPIOF_PIN11) | \
1161+ PIN_ASCR_DISABLED(GPIOF_PIN12) | \
1162+ PIN_ASCR_DISABLED(GPIOF_PIN13) | \
1163+ PIN_ASCR_DISABLED(GPIOF_PIN14) | \
1164+ PIN_ASCR_DISABLED(GPIOF_PIN15))
1165+#define VAL_GPIOF_LOCKR (PIN_LOCKR_DISABLED(GPIOF_PIN0) | \
1166+ PIN_LOCKR_DISABLED(GPIOF_PIN1) | \
1167+ PIN_LOCKR_DISABLED(GPIOF_PIN2) | \
1168+ PIN_LOCKR_DISABLED(GPIOF_PIN3) | \
1169+ PIN_LOCKR_DISABLED(GPIOF_PIN4) | \
1170+ PIN_LOCKR_DISABLED(GPIOF_PIN5) | \
1171+ PIN_LOCKR_DISABLED(GPIOF_PIN6) | \
1172+ PIN_LOCKR_DISABLED(GPIOF_PIN7) | \
1173+ PIN_LOCKR_DISABLED(GPIOF_PIN8) | \
1174+ PIN_LOCKR_DISABLED(GPIOF_PIN9) | \
1175+ PIN_LOCKR_DISABLED(GPIOF_PIN10) | \
1176+ PIN_LOCKR_DISABLED(GPIOF_PIN11) | \
1177+ PIN_LOCKR_DISABLED(GPIOF_PIN12) | \
1178+ PIN_LOCKR_DISABLED(GPIOF_PIN13) | \
1179+ PIN_LOCKR_DISABLED(GPIOF_PIN14) | \
1180+ PIN_LOCKR_DISABLED(GPIOF_PIN15))
1181+
1182+/*
1183+ * GPIOG setup:
1184+ *
1185+ * PG0 - PIN0 (analog).
1186+ * PG1 - PIN1 (analog).
1187+ * PG2 - PIN2 (analog).
1188+ * PG3 - PIN3 (analog).
1189+ * PG4 - PIN4 (analog).
1190+ * PG5 - USB_OVER_CURRENT (input floating).
1191+ * PG6 - USB_POWER_SWITCH_ON (output pushpull maximum).
1192+ * PG7 - LPUART1_TX (alternate 8).
1193+ * PG8 - LPUART1_RX (alternate 8).
1194+ * PG9 - PIN9 (analog).
1195+ * PG10 - PIN10 (analog).
1196+ * PG11 - PIN11 (analog).
1197+ * PG12 - PIN12 (analog).
1198+ * PG13 - PIN13 (analog).
1199+ * PG14 - PIN14 (analog).
1200+ * PG15 - PIN15 (analog).
1201+ */
1202+#define VAL_GPIOG_MODER (PIN_MODE_ANALOG(GPIOG_PIN0) | \
1203+ PIN_MODE_ANALOG(GPIOG_PIN1) | \
1204+ PIN_MODE_ANALOG(GPIOG_PIN2) | \
1205+ PIN_MODE_ANALOG(GPIOG_PIN3) | \
1206+ PIN_MODE_ANALOG(GPIOG_PIN4) | \
1207+ PIN_MODE_INPUT(GPIOG_USB_OVER_CURRENT) |\
1208+ PIN_MODE_OUTPUT(GPIOG_USB_POWER_SWITCH_ON) |\
1209+ PIN_MODE_ALTERNATE(GPIOG_LPUART1_TX) | \
1210+ PIN_MODE_ALTERNATE(GPIOG_LPUART1_RX) | \
1211+ PIN_MODE_ANALOG(GPIOG_PIN9) | \
1212+ PIN_MODE_ANALOG(GPIOG_PIN10) | \
1213+ PIN_MODE_ANALOG(GPIOG_PIN11) | \
1214+ PIN_MODE_ANALOG(GPIOG_PIN12) | \
1215+ PIN_MODE_ANALOG(GPIOG_PIN13) | \
1216+ PIN_MODE_ANALOG(GPIOG_PIN14) | \
1217+ PIN_MODE_ANALOG(GPIOG_PIN15))
1218+#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \
1219+ PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \
1220+ PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \
1221+ PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \
1222+ PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \
1223+ PIN_OTYPE_PUSHPULL(GPIOG_USB_OVER_CURRENT) |\
1224+ PIN_OTYPE_PUSHPULL(GPIOG_USB_POWER_SWITCH_ON) |\
1225+ PIN_OTYPE_PUSHPULL(GPIOG_LPUART1_TX) | \
1226+ PIN_OTYPE_PUSHPULL(GPIOG_LPUART1_RX) | \
1227+ PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \
1228+ PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \
1229+ PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \
1230+ PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \
1231+ PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \
1232+ PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \
1233+ PIN_OTYPE_PUSHPULL(GPIOG_PIN15))
1234+#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOG_PIN0) | \
1235+ PIN_OSPEED_VERYLOW(GPIOG_PIN1) | \
1236+ PIN_OSPEED_VERYLOW(GPIOG_PIN2) | \
1237+ PIN_OSPEED_VERYLOW(GPIOG_PIN3) | \
1238+ PIN_OSPEED_VERYLOW(GPIOG_PIN4) | \
1239+ PIN_OSPEED_VERYLOW(GPIOG_USB_OVER_CURRENT) |\
1240+ PIN_OSPEED_HIGH(GPIOG_USB_POWER_SWITCH_ON) |\
1241+ PIN_OSPEED_VERYLOW(GPIOG_LPUART1_TX) | \
1242+ PIN_OSPEED_VERYLOW(GPIOG_LPUART1_RX) | \
1243+ PIN_OSPEED_VERYLOW(GPIOG_PIN9) | \
1244+ PIN_OSPEED_VERYLOW(GPIOG_PIN10) | \
1245+ PIN_OSPEED_VERYLOW(GPIOG_PIN11) | \
1246+ PIN_OSPEED_VERYLOW(GPIOG_PIN12) | \
1247+ PIN_OSPEED_VERYLOW(GPIOG_PIN13) | \
1248+ PIN_OSPEED_VERYLOW(GPIOG_PIN14) | \
1249+ PIN_OSPEED_VERYLOW(GPIOG_PIN15))
1250+#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_PIN0) | \
1251+ PIN_PUPDR_FLOATING(GPIOG_PIN1) | \
1252+ PIN_PUPDR_FLOATING(GPIOG_PIN2) | \
1253+ PIN_PUPDR_FLOATING(GPIOG_PIN3) | \
1254+ PIN_PUPDR_FLOATING(GPIOG_PIN4) | \
1255+ PIN_PUPDR_FLOATING(GPIOG_USB_OVER_CURRENT) |\
1256+ PIN_PUPDR_FLOATING(GPIOG_USB_POWER_SWITCH_ON) |\
1257+ PIN_PUPDR_FLOATING(GPIOG_LPUART1_TX) | \
1258+ PIN_PUPDR_FLOATING(GPIOG_LPUART1_RX) | \
1259+ PIN_PUPDR_FLOATING(GPIOG_PIN9) | \
1260+ PIN_PUPDR_FLOATING(GPIOG_PIN10) | \
1261+ PIN_PUPDR_FLOATING(GPIOG_PIN11) | \
1262+ PIN_PUPDR_FLOATING(GPIOG_PIN12) | \
1263+ PIN_PUPDR_FLOATING(GPIOG_PIN13) | \
1264+ PIN_PUPDR_FLOATING(GPIOG_PIN14) | \
1265+ PIN_PUPDR_FLOATING(GPIOG_PIN15))
1266+#define VAL_GPIOG_ODR (PIN_ODR_LOW(GPIOG_PIN0) | \
1267+ PIN_ODR_LOW(GPIOG_PIN1) | \
1268+ PIN_ODR_LOW(GPIOG_PIN2) | \
1269+ PIN_ODR_LOW(GPIOG_PIN3) | \
1270+ PIN_ODR_LOW(GPIOG_PIN4) | \
1271+ PIN_ODR_LOW(GPIOG_USB_OVER_CURRENT) | \
1272+ PIN_ODR_LOW(GPIOG_USB_POWER_SWITCH_ON) |\
1273+ PIN_ODR_LOW(GPIOG_LPUART1_TX) | \
1274+ PIN_ODR_LOW(GPIOG_LPUART1_RX) | \
1275+ PIN_ODR_LOW(GPIOG_PIN9) | \
1276+ PIN_ODR_LOW(GPIOG_PIN10) | \
1277+ PIN_ODR_LOW(GPIOG_PIN11) | \
1278+ PIN_ODR_LOW(GPIOG_PIN12) | \
1279+ PIN_ODR_LOW(GPIOG_PIN13) | \
1280+ PIN_ODR_LOW(GPIOG_PIN14) | \
1281+ PIN_ODR_LOW(GPIOG_PIN15))
1282+#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \
1283+ PIN_AFIO_AF(GPIOG_PIN1, 0U) | \
1284+ PIN_AFIO_AF(GPIOG_PIN2, 0U) | \
1285+ PIN_AFIO_AF(GPIOG_PIN3, 0U) | \
1286+ PIN_AFIO_AF(GPIOG_PIN4, 0U) | \
1287+ PIN_AFIO_AF(GPIOG_USB_OVER_CURRENT, 0U) |\
1288+ PIN_AFIO_AF(GPIOG_USB_POWER_SWITCH_ON, 0U) |\
1289+ PIN_AFIO_AF(GPIOG_LPUART1_TX, 8U))
1290+#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_LPUART1_RX, 8U) | \
1291+ PIN_AFIO_AF(GPIOG_PIN9, 0U) | \
1292+ PIN_AFIO_AF(GPIOG_PIN10, 0U) | \
1293+ PIN_AFIO_AF(GPIOG_PIN11, 0U) | \
1294+ PIN_AFIO_AF(GPIOG_PIN12, 0U) | \
1295+ PIN_AFIO_AF(GPIOG_PIN13, 0U) | \
1296+ PIN_AFIO_AF(GPIOG_PIN14, 0U) | \
1297+ PIN_AFIO_AF(GPIOG_PIN15, 0U))
1298+#define VAL_GPIOG_ASCR (PIN_ASCR_DISABLED(GPIOG_PIN0) | \
1299+ PIN_ASCR_DISABLED(GPIOG_PIN1) | \
1300+ PIN_ASCR_DISABLED(GPIOG_PIN2) | \
1301+ PIN_ASCR_DISABLED(GPIOG_PIN3) | \
1302+ PIN_ASCR_DISABLED(GPIOG_PIN4) | \
1303+ PIN_ASCR_DISABLED(GPIOG_USB_OVER_CURRENT) |\
1304+ PIN_ASCR_DISABLED(GPIOG_USB_POWER_SWITCH_ON) |\
1305+ PIN_ASCR_DISABLED(GPIOG_LPUART1_TX) | \
1306+ PIN_ASCR_DISABLED(GPIOG_LPUART1_RX) | \
1307+ PIN_ASCR_DISABLED(GPIOG_PIN9) | \
1308+ PIN_ASCR_DISABLED(GPIOG_PIN10) | \
1309+ PIN_ASCR_DISABLED(GPIOG_PIN11) | \
1310+ PIN_ASCR_DISABLED(GPIOG_PIN12) | \
1311+ PIN_ASCR_DISABLED(GPIOG_PIN13) | \
1312+ PIN_ASCR_DISABLED(GPIOG_PIN14) | \
1313+ PIN_ASCR_DISABLED(GPIOG_PIN15))
1314+#define VAL_GPIOG_LOCKR (PIN_LOCKR_DISABLED(GPIOG_PIN0) | \
1315+ PIN_LOCKR_DISABLED(GPIOG_PIN1) | \
1316+ PIN_LOCKR_DISABLED(GPIOG_PIN2) | \
1317+ PIN_LOCKR_DISABLED(GPIOG_PIN3) | \
1318+ PIN_LOCKR_DISABLED(GPIOG_PIN4) | \
1319+ PIN_LOCKR_DISABLED(GPIOG_USB_OVER_CURRENT) |\
1320+ PIN_LOCKR_DISABLED(GPIOG_USB_POWER_SWITCH_ON) |\
1321+ PIN_LOCKR_DISABLED(GPIOG_LPUART1_TX) | \
1322+ PIN_LOCKR_DISABLED(GPIOG_LPUART1_RX) | \
1323+ PIN_LOCKR_DISABLED(GPIOG_PIN9) | \
1324+ PIN_LOCKR_DISABLED(GPIOG_PIN10) | \
1325+ PIN_LOCKR_DISABLED(GPIOG_PIN11) | \
1326+ PIN_LOCKR_DISABLED(GPIOG_PIN12) | \
1327+ PIN_LOCKR_DISABLED(GPIOG_PIN13) | \
1328+ PIN_LOCKR_DISABLED(GPIOG_PIN14) | \
1329+ PIN_LOCKR_DISABLED(GPIOG_PIN15))
1330+
1331+/*
1332+ * GPIOH setup:
1333+ *
1334+ * PH0 - PIN0 (analog).
1335+ * PH1 - PIN1 (analog).
1336+ * PH2 - PIN2 (analog).
1337+ * PH3 - PIN3 (input floating).
1338+ * PH4 - PIN4 (analog).
1339+ * PH5 - PIN5 (analog).
1340+ * PH6 - PIN6 (analog).
1341+ * PH7 - PIN7 (analog).
1342+ * PH8 - PIN8 (analog).
1343+ * PH9 - PIN9 (analog).
1344+ * PH10 - PIN10 (analog).
1345+ * PH11 - PIN11 (analog).
1346+ * PH12 - PIN12 (analog).
1347+ * PH13 - PIN13 (analog).
1348+ * PH14 - PIN14 (analog).
1349+ * PH15 - PIN15 (analog).
1350+ */
1351+#define VAL_GPIOH_MODER (PIN_MODE_ANALOG(GPIOH_PIN0) | \
1352+ PIN_MODE_ANALOG(GPIOH_PIN1) | \
1353+ PIN_MODE_ANALOG(GPIOH_PIN2) | \
1354+ PIN_MODE_INPUT(GPIOH_PIN3) | \
1355+ PIN_MODE_ANALOG(GPIOH_PIN4) | \
1356+ PIN_MODE_ANALOG(GPIOH_PIN5) | \
1357+ PIN_MODE_ANALOG(GPIOH_PIN6) | \
1358+ PIN_MODE_ANALOG(GPIOH_PIN7) | \
1359+ PIN_MODE_ANALOG(GPIOH_PIN8) | \
1360+ PIN_MODE_ANALOG(GPIOH_PIN9) | \
1361+ PIN_MODE_ANALOG(GPIOH_PIN10) | \
1362+ PIN_MODE_ANALOG(GPIOH_PIN11) | \
1363+ PIN_MODE_ANALOG(GPIOH_PIN12) | \
1364+ PIN_MODE_ANALOG(GPIOH_PIN13) | \
1365+ PIN_MODE_ANALOG(GPIOH_PIN14) | \
1366+ PIN_MODE_ANALOG(GPIOH_PIN15))
1367+#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_PIN0) | \
1368+ PIN_OTYPE_PUSHPULL(GPIOH_PIN1) | \
1369+ PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \
1370+ PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \
1371+ PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \
1372+ PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \
1373+ PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \
1374+ PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \
1375+ PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \
1376+ PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \
1377+ PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \
1378+ PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \
1379+ PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \
1380+ PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \
1381+ PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \
1382+ PIN_OTYPE_PUSHPULL(GPIOH_PIN15))
1383+#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOH_PIN0) | \
1384+ PIN_OSPEED_VERYLOW(GPIOH_PIN1) | \
1385+ PIN_OSPEED_VERYLOW(GPIOH_PIN2) | \
1386+ PIN_OSPEED_VERYLOW(GPIOH_PIN3) | \
1387+ PIN_OSPEED_VERYLOW(GPIOH_PIN4) | \
1388+ PIN_OSPEED_VERYLOW(GPIOH_PIN5) | \
1389+ PIN_OSPEED_VERYLOW(GPIOH_PIN6) | \
1390+ PIN_OSPEED_VERYLOW(GPIOH_PIN7) | \
1391+ PIN_OSPEED_VERYLOW(GPIOH_PIN8) | \
1392+ PIN_OSPEED_VERYLOW(GPIOH_PIN9) | \
1393+ PIN_OSPEED_VERYLOW(GPIOH_PIN10) | \
1394+ PIN_OSPEED_VERYLOW(GPIOH_PIN11) | \
1395+ PIN_OSPEED_VERYLOW(GPIOH_PIN12) | \
1396+ PIN_OSPEED_VERYLOW(GPIOH_PIN13) | \
1397+ PIN_OSPEED_VERYLOW(GPIOH_PIN14) | \
1398+ PIN_OSPEED_VERYLOW(GPIOH_PIN15))
1399+#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_PIN0) | \
1400+ PIN_PUPDR_FLOATING(GPIOH_PIN1) | \
1401+ PIN_PUPDR_FLOATING(GPIOH_PIN2) | \
1402+ PIN_PUPDR_FLOATING(GPIOH_PIN3) | \
1403+ PIN_PUPDR_FLOATING(GPIOH_PIN4) | \
1404+ PIN_PUPDR_FLOATING(GPIOH_PIN5) | \
1405+ PIN_PUPDR_FLOATING(GPIOH_PIN6) | \
1406+ PIN_PUPDR_FLOATING(GPIOH_PIN7) | \
1407+ PIN_PUPDR_FLOATING(GPIOH_PIN8) | \
1408+ PIN_PUPDR_FLOATING(GPIOH_PIN9) | \
1409+ PIN_PUPDR_FLOATING(GPIOH_PIN10) | \
1410+ PIN_PUPDR_FLOATING(GPIOH_PIN11) | \
1411+ PIN_PUPDR_FLOATING(GPIOH_PIN12) | \
1412+ PIN_PUPDR_FLOATING(GPIOH_PIN13) | \
1413+ PIN_PUPDR_FLOATING(GPIOH_PIN14) | \
1414+ PIN_PUPDR_FLOATING(GPIOH_PIN15))
1415+#define VAL_GPIOH_ODR (PIN_ODR_LOW(GPIOH_PIN0) | \
1416+ PIN_ODR_LOW(GPIOH_PIN1) | \
1417+ PIN_ODR_LOW(GPIOH_PIN2) | \
1418+ PIN_ODR_LOW(GPIOH_PIN3) | \
1419+ PIN_ODR_LOW(GPIOH_PIN4) | \
1420+ PIN_ODR_LOW(GPIOH_PIN5) | \
1421+ PIN_ODR_LOW(GPIOH_PIN6) | \
1422+ PIN_ODR_LOW(GPIOH_PIN7) | \
1423+ PIN_ODR_LOW(GPIOH_PIN8) | \
1424+ PIN_ODR_LOW(GPIOH_PIN9) | \
1425+ PIN_ODR_LOW(GPIOH_PIN10) | \
1426+ PIN_ODR_LOW(GPIOH_PIN11) | \
1427+ PIN_ODR_LOW(GPIOH_PIN12) | \
1428+ PIN_ODR_LOW(GPIOH_PIN13) | \
1429+ PIN_ODR_LOW(GPIOH_PIN14) | \
1430+ PIN_ODR_LOW(GPIOH_PIN15))
1431+#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_PIN0, 0U) | \
1432+ PIN_AFIO_AF(GPIOH_PIN1, 0U) | \
1433+ PIN_AFIO_AF(GPIOH_PIN2, 0U) | \
1434+ PIN_AFIO_AF(GPIOH_PIN3, 0U) | \
1435+ PIN_AFIO_AF(GPIOH_PIN4, 0U) | \
1436+ PIN_AFIO_AF(GPIOH_PIN5, 0U) | \
1437+ PIN_AFIO_AF(GPIOH_PIN6, 0U) | \
1438+ PIN_AFIO_AF(GPIOH_PIN7, 0U))
1439+#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \
1440+ PIN_AFIO_AF(GPIOH_PIN9, 0U) | \
1441+ PIN_AFIO_AF(GPIOH_PIN10, 0U) | \
1442+ PIN_AFIO_AF(GPIOH_PIN11, 0U) | \
1443+ PIN_AFIO_AF(GPIOH_PIN12, 0U) | \
1444+ PIN_AFIO_AF(GPIOH_PIN13, 0U) | \
1445+ PIN_AFIO_AF(GPIOH_PIN14, 0U) | \
1446+ PIN_AFIO_AF(GPIOH_PIN15, 0U))
1447+#define VAL_GPIOH_ASCR (PIN_ASCR_DISABLED(GPIOH_PIN0) | \
1448+ PIN_ASCR_DISABLED(GPIOH_PIN1) | \
1449+ PIN_ASCR_DISABLED(GPIOH_PIN2) | \
1450+ PIN_ASCR_DISABLED(GPIOH_PIN3) | \
1451+ PIN_ASCR_DISABLED(GPIOH_PIN4) | \
1452+ PIN_ASCR_DISABLED(GPIOH_PIN5) | \
1453+ PIN_ASCR_DISABLED(GPIOH_PIN6) | \
1454+ PIN_ASCR_DISABLED(GPIOH_PIN7) | \
1455+ PIN_ASCR_DISABLED(GPIOH_PIN8) | \
1456+ PIN_ASCR_DISABLED(GPIOH_PIN9) | \
1457+ PIN_ASCR_DISABLED(GPIOH_PIN10) | \
1458+ PIN_ASCR_DISABLED(GPIOH_PIN11) | \
1459+ PIN_ASCR_DISABLED(GPIOH_PIN12) | \
1460+ PIN_ASCR_DISABLED(GPIOH_PIN13) | \
1461+ PIN_ASCR_DISABLED(GPIOH_PIN14) | \
1462+ PIN_ASCR_DISABLED(GPIOH_PIN15))
1463+#define VAL_GPIOH_LOCKR (PIN_LOCKR_DISABLED(GPIOH_PIN0) | \
1464+ PIN_LOCKR_DISABLED(GPIOH_PIN1) | \
1465+ PIN_LOCKR_DISABLED(GPIOH_PIN2) | \
1466+ PIN_LOCKR_DISABLED(GPIOH_PIN3) | \
1467+ PIN_LOCKR_DISABLED(GPIOH_PIN4) | \
1468+ PIN_LOCKR_DISABLED(GPIOH_PIN5) | \
1469+ PIN_LOCKR_DISABLED(GPIOH_PIN6) | \
1470+ PIN_LOCKR_DISABLED(GPIOH_PIN7) | \
1471+ PIN_LOCKR_DISABLED(GPIOH_PIN8) | \
1472+ PIN_LOCKR_DISABLED(GPIOH_PIN9) | \
1473+ PIN_LOCKR_DISABLED(GPIOH_PIN10) | \
1474+ PIN_LOCKR_DISABLED(GPIOH_PIN11) | \
1475+ PIN_LOCKR_DISABLED(GPIOH_PIN12) | \
1476+ PIN_LOCKR_DISABLED(GPIOH_PIN13) | \
1477+ PIN_LOCKR_DISABLED(GPIOH_PIN14) | \
1478+ PIN_LOCKR_DISABLED(GPIOH_PIN15))
1479+
1480+/*
1481+ * GPIOI setup:
1482+ *
1483+ * PI0 - PIN0 (analog).
1484+ * PI1 - PIN1 (analog).
1485+ * PI2 - PIN2 (analog).
1486+ * PI3 - PIN3 (analog).
1487+ * PI4 - PIN4 (analog).
1488+ * PI5 - PIN5 (analog).
1489+ * PI6 - PIN6 (analog).
1490+ * PI7 - PIN7 (analog).
1491+ * PI8 - PIN8 (analog).
1492+ * PI9 - PIN9 (analog).
1493+ * PI10 - PIN10 (analog).
1494+ * PI11 - PIN11 (analog).
1495+ * PI12 - PIN12 (analog).
1496+ * PI13 - PIN13 (analog).
1497+ * PI14 - PIN14 (analog).
1498+ * PI15 - PIN15 (analog).
1499+ */
1500+#define VAL_GPIOI_MODER (PIN_MODE_ANALOG(GPIOI_PIN0) | \
1501+ PIN_MODE_ANALOG(GPIOI_PIN1) | \
1502+ PIN_MODE_ANALOG(GPIOI_PIN2) | \
1503+ PIN_MODE_ANALOG(GPIOI_PIN3) | \
1504+ PIN_MODE_ANALOG(GPIOI_PIN4) | \
1505+ PIN_MODE_ANALOG(GPIOI_PIN5) | \
1506+ PIN_MODE_ANALOG(GPIOI_PIN6) | \
1507+ PIN_MODE_ANALOG(GPIOI_PIN7) | \
1508+ PIN_MODE_ANALOG(GPIOI_PIN8) | \
1509+ PIN_MODE_ANALOG(GPIOI_PIN9) | \
1510+ PIN_MODE_ANALOG(GPIOI_PIN10) | \
1511+ PIN_MODE_ANALOG(GPIOI_PIN11) | \
1512+ PIN_MODE_ANALOG(GPIOI_PIN12) | \
1513+ PIN_MODE_ANALOG(GPIOI_PIN13) | \
1514+ PIN_MODE_ANALOG(GPIOI_PIN14) | \
1515+ PIN_MODE_ANALOG(GPIOI_PIN15))
1516+#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \
1517+ PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \
1518+ PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \
1519+ PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \
1520+ PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \
1521+ PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \
1522+ PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \
1523+ PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \
1524+ PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \
1525+ PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \
1526+ PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \
1527+ PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \
1528+ PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \
1529+ PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \
1530+ PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \
1531+ PIN_OTYPE_PUSHPULL(GPIOI_PIN15))
1532+#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOI_PIN0) | \
1533+ PIN_OSPEED_VERYLOW(GPIOI_PIN1) | \
1534+ PIN_OSPEED_VERYLOW(GPIOI_PIN2) | \
1535+ PIN_OSPEED_VERYLOW(GPIOI_PIN3) | \
1536+ PIN_OSPEED_VERYLOW(GPIOI_PIN4) | \
1537+ PIN_OSPEED_VERYLOW(GPIOI_PIN5) | \
1538+ PIN_OSPEED_VERYLOW(GPIOI_PIN6) | \
1539+ PIN_OSPEED_VERYLOW(GPIOI_PIN7) | \
1540+ PIN_OSPEED_VERYLOW(GPIOI_PIN8) | \
1541+ PIN_OSPEED_VERYLOW(GPIOI_PIN9) | \
1542+ PIN_OSPEED_VERYLOW(GPIOI_PIN10) | \
1543+ PIN_OSPEED_VERYLOW(GPIOI_PIN11) | \
1544+ PIN_OSPEED_VERYLOW(GPIOI_PIN12) | \
1545+ PIN_OSPEED_VERYLOW(GPIOI_PIN13) | \
1546+ PIN_OSPEED_VERYLOW(GPIOI_PIN14) | \
1547+ PIN_OSPEED_VERYLOW(GPIOI_PIN15))
1548+#define VAL_GPIOI_PUPDR (PIN_PUPDR_FLOATING(GPIOI_PIN0) | \
1549+ PIN_PUPDR_FLOATING(GPIOI_PIN1) | \
1550+ PIN_PUPDR_FLOATING(GPIOI_PIN2) | \
1551+ PIN_PUPDR_FLOATING(GPIOI_PIN3) | \
1552+ PIN_PUPDR_FLOATING(GPIOI_PIN4) | \
1553+ PIN_PUPDR_FLOATING(GPIOI_PIN5) | \
1554+ PIN_PUPDR_FLOATING(GPIOI_PIN6) | \
1555+ PIN_PUPDR_FLOATING(GPIOI_PIN7) | \
1556+ PIN_PUPDR_FLOATING(GPIOI_PIN8) | \
1557+ PIN_PUPDR_FLOATING(GPIOI_PIN9) | \
1558+ PIN_PUPDR_FLOATING(GPIOI_PIN10) | \
1559+ PIN_PUPDR_FLOATING(GPIOI_PIN11) | \
1560+ PIN_PUPDR_FLOATING(GPIOI_PIN12) | \
1561+ PIN_PUPDR_FLOATING(GPIOI_PIN13) | \
1562+ PIN_PUPDR_FLOATING(GPIOI_PIN14) | \
1563+ PIN_PUPDR_FLOATING(GPIOI_PIN15))
1564+#define VAL_GPIOI_ODR (PIN_ODR_LOW(GPIOI_PIN0) | \
1565+ PIN_ODR_LOW(GPIOI_PIN1) | \
1566+ PIN_ODR_LOW(GPIOI_PIN2) | \
1567+ PIN_ODR_LOW(GPIOI_PIN3) | \
1568+ PIN_ODR_LOW(GPIOI_PIN4) | \
1569+ PIN_ODR_LOW(GPIOI_PIN5) | \
1570+ PIN_ODR_LOW(GPIOI_PIN6) | \
1571+ PIN_ODR_LOW(GPIOI_PIN7) | \
1572+ PIN_ODR_LOW(GPIOI_PIN8) | \
1573+ PIN_ODR_LOW(GPIOI_PIN9) | \
1574+ PIN_ODR_LOW(GPIOI_PIN10) | \
1575+ PIN_ODR_LOW(GPIOI_PIN11) | \
1576+ PIN_ODR_LOW(GPIOI_PIN12) | \
1577+ PIN_ODR_LOW(GPIOI_PIN13) | \
1578+ PIN_ODR_LOW(GPIOI_PIN14) | \
1579+ PIN_ODR_LOW(GPIOI_PIN15))
1580+#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0U) | \
1581+ PIN_AFIO_AF(GPIOI_PIN1, 0U) | \
1582+ PIN_AFIO_AF(GPIOI_PIN2, 0U) | \
1583+ PIN_AFIO_AF(GPIOI_PIN3, 0U) | \
1584+ PIN_AFIO_AF(GPIOI_PIN4, 0U) | \
1585+ PIN_AFIO_AF(GPIOI_PIN5, 0U) | \
1586+ PIN_AFIO_AF(GPIOI_PIN6, 0U) | \
1587+ PIN_AFIO_AF(GPIOI_PIN7, 0U))
1588+#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0U) | \
1589+ PIN_AFIO_AF(GPIOI_PIN9, 0U) | \
1590+ PIN_AFIO_AF(GPIOI_PIN10, 0U) | \
1591+ PIN_AFIO_AF(GPIOI_PIN11, 0U) | \
1592+ PIN_AFIO_AF(GPIOI_PIN12, 0U) | \
1593+ PIN_AFIO_AF(GPIOI_PIN13, 0U) | \
1594+ PIN_AFIO_AF(GPIOI_PIN14, 0U) | \
1595+ PIN_AFIO_AF(GPIOI_PIN15, 0U))
1596+#define VAL_GPIOI_ASCR (PIN_ASCR_DISABLED(GPIOI_PIN0) | \
1597+ PIN_ASCR_DISABLED(GPIOI_PIN1) | \
1598+ PIN_ASCR_DISABLED(GPIOI_PIN2) | \
1599+ PIN_ASCR_DISABLED(GPIOI_PIN3) | \
1600+ PIN_ASCR_DISABLED(GPIOI_PIN4) | \
1601+ PIN_ASCR_DISABLED(GPIOI_PIN5) | \
1602+ PIN_ASCR_DISABLED(GPIOI_PIN6) | \
1603+ PIN_ASCR_DISABLED(GPIOI_PIN7) | \
1604+ PIN_ASCR_DISABLED(GPIOI_PIN8) | \
1605+ PIN_ASCR_DISABLED(GPIOI_PIN9) | \
1606+ PIN_ASCR_DISABLED(GPIOI_PIN10) | \
1607+ PIN_ASCR_DISABLED(GPIOI_PIN11) | \
1608+ PIN_ASCR_DISABLED(GPIOI_PIN12) | \
1609+ PIN_ASCR_DISABLED(GPIOI_PIN13) | \
1610+ PIN_ASCR_DISABLED(GPIOI_PIN14) | \
1611+ PIN_ASCR_DISABLED(GPIOI_PIN15))
1612+#define VAL_GPIOI_LOCKR (PIN_LOCKR_DISABLED(GPIOI_PIN0) | \
1613+ PIN_LOCKR_DISABLED(GPIOI_PIN1) | \
1614+ PIN_LOCKR_DISABLED(GPIOI_PIN2) | \
1615+ PIN_LOCKR_DISABLED(GPIOI_PIN3) | \
1616+ PIN_LOCKR_DISABLED(GPIOI_PIN4) | \
1617+ PIN_LOCKR_DISABLED(GPIOI_PIN5) | \
1618+ PIN_LOCKR_DISABLED(GPIOI_PIN6) | \
1619+ PIN_LOCKR_DISABLED(GPIOI_PIN7) | \
1620+ PIN_LOCKR_DISABLED(GPIOI_PIN8) | \
1621+ PIN_LOCKR_DISABLED(GPIOI_PIN9) | \
1622+ PIN_LOCKR_DISABLED(GPIOI_PIN10) | \
1623+ PIN_LOCKR_DISABLED(GPIOI_PIN11) | \
1624+ PIN_LOCKR_DISABLED(GPIOI_PIN12) | \
1625+ PIN_LOCKR_DISABLED(GPIOI_PIN13) | \
1626+ PIN_LOCKR_DISABLED(GPIOI_PIN14) | \
1627+ PIN_LOCKR_DISABLED(GPIOI_PIN15))
1628+
1629+/*===========================================================================*/
1630+/* External declarations. */
1631+/*===========================================================================*/
1632+
1633+#if !defined(_FROM_ASM_)
1634+#ifdef __cplusplus
1635+extern "C" {
1636+#endif
1637+ void boardInit(void);
1638+#ifdef __cplusplus
1639+}
1640+#endif
1641+#endif /* _FROM_ASM_ */
1642+
1643+#endif /* BOARD_H */
--- trunk/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c (revision 14605)
+++ trunk/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c (revision 14606)
@@ -578,12 +578,13 @@
578578 rccResetADC123();
579579 #if defined(ADC1_2_COMMON)
580580 ADC1_2_COMMON->CCR = STM32_ADC_ADC123_PRESC | STM32_ADC_ADC123_CLOCK_MODE | ADC_DMA_MDMA;
581+#elif defined(ADC12_COMMON)
582+ ADC12_COMMON->CCR = STM32_ADC_ADC123_PRESC | STM32_ADC_ADC123_CLOCK_MODE | ADC_DMA_MDMA;
581583 #elif defined(ADC123_COMMON)
582584 ADC123_COMMON->CCR = STM32_ADC_ADC123_PRESC | STM32_ADC_ADC123_CLOCK_MODE | ADC_DMA_MDMA;
583585 #else
584586 ADC1_COMMON->CCR = STM32_ADC_ADC123_PRESC | STM32_ADC_ADC123_CLOCK_MODE | ADC_DMA_MDMA;
585587 #endif
586-
587588 rccDisableADC123();
588589 #endif
589590
--- trunk/os/hal/ports/STM32/STM32L4xx+/hal_efl_lld.h (revision 14605)
+++ trunk/os/hal/ports/STM32/STM32L4xx+/hal_efl_lld.h (revision 14606)
@@ -16,7 +16,7 @@
1616
1717 /**
1818 * @file hal_efl_lld.h
19- * @brief STM32L4R/Snxx Embedded Flash subsystem low level driver header.
19+ * @brief STM32L4+ Embedded Flash subsystem low level driver header.
2020 *
2121 * @addtogroup HAL_EFL
2222 * @{
@@ -51,9 +51,9 @@
5151 /* Derived constants and error checks. */
5252 /*===========================================================================*/
5353
54-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || \
55- defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) || \
56- defined(__DOXYGEN__)
54+#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || \
55+ defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \
56+ defined(STM32L4S7xx) || defined(STM32L4S9xx) || defined(__DOXYGEN__)
5757
5858 /* Flash size register. */
5959 #define STM32_FLASH_SIZE_REGISTER 0x1FFF75E0
--- trunk/os/hal/ports/STM32/STM32L4xx+/hal_lld.h (revision 14605)
+++ trunk/os/hal/ports/STM32/STM32L4xx+/hal_lld.h (revision 14606)
@@ -26,6 +26,7 @@
2626 * - STM32_HSE_BYPASS (optionally).
2727 * .
2828 * One of the following macros must also be defined:
29+ * - STM32L4P5xx, STM32L4Q5xx.
2930 * - STM32L4R5xx, STM32L4R7xx, STM32L4R9xx.
3031 * - STM32L4S5xx, STM32L4S7xx, STM32L4S9xx.
3132 * .
@@ -47,11 +48,12 @@
4748 * @name Platform identification
4849 * @{
4950 */
50-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || \
51- defined(__DOXYGEN__)
51+#if defined(STM32L4P5xx) || defined(STM32L4R5xx) || defined(STM32L4R7xx) || \
52+ defined(STM32L4R9xx) || defined(__DOXYGEN__)
5253 #define PLATFORM_NAME "STM32L4+ Ultra Low Power"
5354
54-#elif defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
55+#elif defined(STM32L4Q5xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || \
56+ defined(STM32L4S9xx)
5557 #define PLATFORM_NAME "STM32L4+ Ultra Low Power with Crypto"
5658
5759 #else
@@ -948,7 +950,13 @@
948950 #error "Using a wrong mcuconf.h file, STM32L4xx_MCUCONF not defined"
949951 #endif
950952
951-#if defined(STM32L4R5xx) && !defined(STM32L4R5_MCUCONF)
953+#if defined(STM32L4P5xx) && !defined(STM32L4P5_MCUCONF)
954+#error "Using a wrong mcuconf.h file, STM32L4P5_MCUCONF not defined"
955+
956+#elif defined(STM32L4Q5xx) && !defined(STM32L4Q5_MCUCONF)
957+#error "Using a wrong mcuconf.h file, STM32L4Q5_MCUCONF not defined"
958+
959+#elif defined(STM32L4R5xx) && !defined(STM32L4R5_MCUCONF)
952960 #error "Using a wrong mcuconf.h file, STM32L4R5_MCUCONF not defined"
953961
954962 #elif defined(STM32L4S5xx) && !defined(STM32L4S5_MCUCONF)
--- trunk/os/hal/ports/STM32/STM32L4xx+/stm32_dmamux.h (revision 14605)
+++ trunk/os/hal/ports/STM32/STM32L4xx+/stm32_dmamux.h (revision 14606)
@@ -33,11 +33,107 @@
3333 * @name DMAMUX1 request sources
3434 * @{
3535 */
36+#if defined(STM32L4P5xx) || defined(STM32L4Q5xx)
3637 #define STM32_DMAMUX1_REQ_GEN0 1
3738 #define STM32_DMAMUX1_REQ_GEN1 2
3839 #define STM32_DMAMUX1_REQ_GEN2 3
3940 #define STM32_DMAMUX1_REQ_GEN3 4
4041 #define STM32_DMAMUX1_ADC1 5
42+#define STM32_DMAMUX1_ADC2 6
43+#define STM32_DMAMUX1_DAC1_CH1 7
44+#define STM32_DMAMUX1_DAC1_CH2 8
45+#define STM32_DMAMUX1_TIM6_UP 9
46+#define STM32_DMAMUX1_TIM7_UP 10
47+#define STM32_DMAMUX1_SPI1_RX 11
48+#define STM32_DMAMUX1_SPI1_TX 12
49+#define STM32_DMAMUX1_SPI2_RX 13
50+#define STM32_DMAMUX1_SPI2_TX 14
51+#define STM32_DMAMUX1_SPI3_RX 15
52+#define STM32_DMAMUX1_SPI3_TX 16
53+#define STM32_DMAMUX1_I2C1_RX 17
54+#define STM32_DMAMUX1_I2C1_TX 18
55+#define STM32_DMAMUX1_I2C2_RX 19
56+#define STM32_DMAMUX1_I2C2_TX 20
57+#define STM32_DMAMUX1_I2C3_RX 21
58+#define STM32_DMAMUX1_I2C3_TX 22
59+#define STM32_DMAMUX1_I2C4_RX 23
60+#define STM32_DMAMUX1_I2C4_TX 24
61+#define STM32_DMAMUX1_USART1_RX 25
62+#define STM32_DMAMUX1_USART1_TX 26
63+#define STM32_DMAMUX1_USART2_RX 27
64+#define STM32_DMAMUX1_USART2_TX 28
65+#define STM32_DMAMUX1_USART3_RX 29
66+#define STM32_DMAMUX1_USART3_TX 30
67+#define STM32_DMAMUX1_UART4_RX 31
68+#define STM32_DMAMUX1_UART4_TX 32
69+#define STM32_DMAMUX1_UART5_RX 33
70+#define STM32_DMAMUX1_UART5_TX 34
71+#define STM32_DMAMUX1_LPUART1_RX 35
72+#define STM32_DMAMUX1_LPUART1_TX 36
73+#define STM32_DMAMUX1_SAI1_A 37
74+#define STM32_DMAMUX1_SAI1_B 38
75+#define STM32_DMAMUX1_SAI2_A 39
76+#define STM32_DMAMUX1_SAI2_B 40
77+#define STM32_DMAMUX1_OCTOSPI1 41
78+#define STM32_DMAMUX1_OCTOSPI2 42
79+#define STM32_DMAMUX1_TIM1_CH1 43
80+#define STM32_DMAMUX1_TIM1_CH2 44
81+#define STM32_DMAMUX1_TIM1_CH3 45
82+#define STM32_DMAMUX1_TIM1_CH4 46
83+#define STM32_DMAMUX1_TIM1_UP 47
84+#define STM32_DMAMUX1_TIM1_TRIG 48
85+#define STM32_DMAMUX1_TIM1_COM 49
86+#define STM32_DMAMUX1_TIM8_CH1 50
87+#define STM32_DMAMUX1_TIM8_CH2 51
88+#define STM32_DMAMUX1_TIM8_CH3 52
89+#define STM32_DMAMUX1_TIM8_CH4 53
90+#define STM32_DMAMUX1_TIM8_UP 54
91+#define STM32_DMAMUX1_TIM8_TRIG 55
92+#define STM32_DMAMUX1_TIM8_COM 56
93+#define STM32_DMAMUX1_TIM2_CH1 57
94+#define STM32_DMAMUX1_TIM2_CH2 58
95+#define STM32_DMAMUX1_TIM2_CH3 59
96+#define STM32_DMAMUX1_TIM2_CH4 60
97+#define STM32_DMAMUX1_TIM2_UP 61
98+#define STM32_DMAMUX1_TIM3_CH1 62
99+#define STM32_DMAMUX1_TIM3_CH2 63
100+#define STM32_DMAMUX1_TIM3_CH3 64
101+#define STM32_DMAMUX1_TIM3_CH4 65
102+#define STM32_DMAMUX1_TIM3_UP 66
103+#define STM32_DMAMUX1_TIM3_TRIG 67
104+#define STM32_DMAMUX1_TIM4_CH1 68
105+#define STM32_DMAMUX1_TIM4_CH2 69
106+#define STM32_DMAMUX1_TIM4_CH3 70
107+#define STM32_DMAMUX1_TIM4_CH4 71
108+#define STM32_DMAMUX1_TIM4_UP 72
109+#define STM32_DMAMUX1_TIM5_CH1 73
110+#define STM32_DMAMUX1_TIM5_CH2 74
111+#define STM32_DMAMUX1_TIM5_CH3 75
112+#define STM32_DMAMUX1_TIM5_CH4 76
113+#define STM32_DMAMUX1_TIM5_UP 77
114+#define STM32_DMAMUX1_TIM5_TRIG 78
115+#define STM32_DMAMUX1_TIM15_CH1 79
116+#define STM32_DMAMUX1_TIM15_UP 80
117+#define STM32_DMAMUX1_TIM15_TRIG 81
118+#define STM32_DMAMUX1_TIM15_COM 82
119+#define STM32_DMAMUX1_TIM16_CH1 83
120+#define STM32_DMAMUX1_TIM16_UP 84
121+#define STM32_DMAMUX1_TIM17_CH1 85
122+#define STM32_DMAMUX1_TIM17_UP 86
123+#define STM32_DMAMUX1_DFSDM1_FLT0 87
124+#define STM32_DMAMUX1_DFSDM1_FLT1 88
125+#define STM32_DMAMUX1_DFSDM1_FLT2 89
126+#define STM32_DMAMUX1_DFSDM1_FLT3 90
127+#define STM32_DMAMUX1_DCMI 91
128+#define STM32_DMAMUX1_AES_IN 92
129+#define STM32_DMAMUX1_AES_OUT 93
130+#define STM32_DMAMUX1_HASH_IN 94
131+#else
132+#define STM32_DMAMUX1_REQ_GEN0 1
133+#define STM32_DMAMUX1_REQ_GEN1 2
134+#define STM32_DMAMUX1_REQ_GEN2 3
135+#define STM32_DMAMUX1_REQ_GEN3 4
136+#define STM32_DMAMUX1_ADC1 5
41137 #define STM32_DMAMUX1_DAC1_CH1 6
42138 #define STM32_DMAMUX1_DAC1_CH2 7
43139 #define STM32_DMAMUX1_TIM6_UP 8
@@ -126,6 +222,7 @@
126222 #define STM32_DMAMUX1_AES_IN 91
127223 #define STM32_DMAMUX1_AES_OUT 92
128224 #define STM32_DMAMUX1_HASH_IN 93
225+#endif /* defined(STM32L4P5xx) || defined(STM32L4Q5xx) */
129226 /** @} */
130227
131228 /*===========================================================================*/
--- trunk/os/hal/ports/STM32/STM32L4xx+/stm32_registry.h (revision 14605)
+++ trunk/os/hal/ports/STM32/STM32L4xx+/stm32_registry.h (revision 14606)
@@ -86,10 +86,40 @@
8686 nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI18_PRIORITY); \
8787 } while (false)
8888
89-#if defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) || \
90- defined(__DOXYGEN__)
89+#if defined(STM32L4P5xx) || defined(STM32L4Q5xx)
90+
91+ /* Enabling RTC-related EXTI lines.*/
92+#define STM32_RTC_ENABLE_ALL_EXTI() do { \
93+ extiEnableGroup1(EXTI_MASK1(STM32_RTC_ALARM_EXTI) | \
94+ EXTI_MASK1(STM32_RTC_TAMP_STAMP_EXTI) | \
95+ EXTI_MASK1(STM32_RTC_WKUP_EXTI), \
96+ EXTI_MODE_RISING_EDGE | EXTI_MODE_ACTION_INTERRUPT); \
97+} while (false)
98+
99+/* Clearing EXTI interrupts. */
100+#define STM32_RTC_CLEAR_ALL_EXTI() do { \
101+ extiClearGroup1(EXTI_MASK1(STM32_RTC_ALARM_EXTI) | \
102+ EXTI_MASK1(STM32_RTC_TAMP_STAMP_EXTI) | \
103+ EXTI_MASK1(STM32_RTC_WKUP_EXTI)); \
104+} while (false)
105+
106+/* Masks used to preserve state of RTC and TAMP register reserved bits. */
107+#define STM32_RTC_CR_MASK 0xE7FFFF7F
108+#define STM32_RTC_PRER_MASK 0x007F7FFF
109+#define STM32_TAMP_CR1_MASK 0x003C0007
110+#define STM32_TAMP_CR2_MASK 0x07070007
111+#define STM32_TAMP_FLTCR_MASK 0x000000FF
112+#define STM32_TAMP_IER_MASK 0x003C0007
113+#endif/* !(defined(STM32L4P5xx) || defined(STM32L4Q5xx)) */
114+
115+#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4S5xx) || \
116+ defined(STM32L4S7xx) || defined(STM32L4S9xx) || defined(__DOXYGEN__)
91117 #define STM32_HAS_HASH1 TRUE
118+#if defined(STM32L4P5xx)
119+#define STM32_HAS_CRYP1 FALSE
120+#else
92121 #define STM32_HAS_CRYP1 TRUE
122+#endif
93123 #else
94124 #define STM32_HAS_HASH1 FALSE
95125 #define STM32_HAS_CRYP1 FALSE
@@ -102,9 +132,9 @@
102132 /* STM32L4yyxx+. */
103133 /*===========================================================================*/
104134
105-#if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || \
106- defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) || \
107- defined(__DOXYGEN__)
135+#if defined(STM32L4P5xx) || defined(STM32L4Q5xx) || defined(STM32L4R5xx) || \
136+ defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \
137+ defined(STM32L4S7xx) || defined(STM32L4S9xx) || defined(__DOXYGEN__)
108138
109139 /* ADC attributes.*/
110140 #define STM32_HAS_ADC1 TRUE
@@ -180,7 +210,12 @@
180210
181211 /* SDMMC attributes.*/
182212 #define STM32_HAS_SDMMC1 TRUE
213+
214+#if defined(STM32L4P5xx) || defined(STM32L4Q5xx)
215+#define STM32_HAS_SDMMC2 TRUE
216+#else
183217 #define STM32_HAS_SDMMC2 FALSE
218+#endif
184219
185220 /* SPI attributes.*/
186221 #define STM32_HAS_SPI1 TRUE
@@ -295,7 +330,8 @@
295330 /* DCMI attributes.*/
296331 #define STM32_HAS_DCMI TRUE
297332
298-#endif /* defined(STM32L4R5xx) || defined(STM32L4R7xx) ||
333+#endif /* defined(STM32L4P5xx) || defined(STM32L4Q5xx) ||
334+ defined(STM32L4R5xx) || defined(STM32L4R7xx) ||
299335 defined(STM32L4R9xx) || defined(STM32L4S5xx) ||
300336 defined(STM32L4S7xx) || defined(STM32L4S9xx) */
301337
--- trunk/tools/ftl/schema/boards/stm32l4xx_board.xsd (revision 14605)
+++ trunk/tools/ftl/schema/boards/stm32l4xx_board.xsd (revision 14606)
@@ -24,6 +24,8 @@
2424 <xs:enumeration value="STM32L486xx"></xs:enumeration>
2525 <xs:enumeration value="STM32L496xx"></xs:enumeration>
2626 <xs:enumeration value="STM32L4A6xx"></xs:enumeration>
27+ <xs:enumeration value="STM32L4P5xx"></xs:enumeration>
28+ <xs:enumeration value="STM32L4Q5xx"></xs:enumeration>
2729 <xs:enumeration value="STM32L4R5xx"></xs:enumeration>
2830 <xs:enumeration value="STM32L4R7xx"></xs:enumeration>
2931 <xs:enumeration value="STM32L4R9xx"></xs:enumeration>
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