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chibios: Commit


Commit MetaInfo

Revision14627 (tree)
Time2021-07-28 23:24:03
Authorvrepetenko

Log Message

Fixed STM32_ADCSEL name, added STM32_RNGSEL default value.

Change Summary

Incremental Difference

--- trunk/demos/STM32/RT-STM32WL55JC-NUCLEO64/cfg/mcuconf.h (revision 14626)
+++ trunk/demos/STM32/RT-STM32WL55JC-NUCLEO64/cfg/mcuconf.h (revision 14627)
@@ -79,7 +79,7 @@
7979 /*
8080 * Peripherals clock sources.
8181 */
82-#define STM32_ADC1SEL STM32_ADCSEL_NOCLK
82+#define STM32_ADCSEL STM32_ADCSEL_NOCLK
8383 #define STM32_USART1SEL STM32_USART1SEL_SYSCLK
8484 #define STM32_USART2SEL STM32_USART2SEL_SYSCLK
8585 #define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
--- trunk/os/hal/ports/STM32/STM32WLxx/hal_lld.h (revision 14626)
+++ trunk/os/hal/ports/STM32/STM32WLxx/hal_lld.h (revision 14627)
@@ -708,6 +708,13 @@
708708 #if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
709709 #define STM32_RTCSEL STM32_RTCSEL_LSI
710710 #endif
711+
712+/**
713+ * @brief RNG clock source.
714+ */
715+#if !defined(STM32_RNGSEL) || defined(__DOXYGEN__)
716+#define STM32_RNGSEL STM32_RNGSEL_PLLQCLK
717+#endif
711718 /** @} */
712719
713720 /*===========================================================================*/
@@ -1244,7 +1251,7 @@
12441251 * PLL enable check.
12451252 */
12461253 #if (STM32_SW == STM32_SW_PLL) || \
1247- (STM32_ADC1SEL == STM32_ADCSEL_PLLPCLK) || \
1254+ (STM32_ADCSEL == STM32_ADCSEL_PLLPCLK) || \
12481255 (STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) || \
12491256 (STM32_MCOSEL == STM32_MCOSEL_PLLPCLK) || \
12501257 (STM32_MCOSEL == STM32_MCOSEL_PLLQCLK) || \
@@ -1263,7 +1270,7 @@
12631270 /**
12641271 * @brief STM32_PLLPEN field.
12651272 */
1266-#if (STM32_ADC1SEL == STM32_ADCSEL_PLLPCLK) || \
1273+#if (STM32_ADCSEL == STM32_ADCSEL_PLLPCLK) || \
12671274 (STM32_MCOSEL == STM32_MCOSEL_PLLPCLK) || \
12681275 defined(__DOXYGEN__)
12691276 #define STM32_PLLPEN (1U << 16)
--- trunk/testrt/IRQ_STORM/cfg/stm32wl55jc_nucleo64/mcuconf.h (revision 14626)
+++ trunk/testrt/IRQ_STORM/cfg/stm32wl55jc_nucleo64/mcuconf.h (revision 14627)
@@ -79,7 +79,7 @@
7979 /*
8080 * Peripherals clock sources.
8181 */
82-#define STM32_ADC1SEL STM32_ADCSEL_NOCLK
82+#define STM32_ADCSEL STM32_ADCSEL_NOCLK
8383 #define STM32_USART1SEL STM32_USART1SEL_SYSCLK
8484 #define STM32_USART2SEL STM32_USART2SEL_SYSCLK
8585 #define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
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