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chibios: Commit


Commit MetaInfo

Revision14772 (tree)
Time2021-09-15 15:18:48
Authortridge

Log Message

added support for STM32G491

Change Summary

Incremental Difference

--- trunk/os/common/ext/ST/STM32G4xx/stm32g491xx.h (nonexistent)
+++ trunk/os/common/ext/ST/STM32G4xx/stm32g491xx.h (revision 14772)
@@ -0,0 +1,13702 @@
1+/**
2+ ******************************************************************************
3+ * @file stm32g491xx.h
4+ * @author MCD Application Team
5+ * @brief CMSIS STM32G491xx Device Peripheral Access Layer Header File.
6+ *
7+ * This file contains:
8+ * - Data structures and the address mapping for all peripherals
9+ * - Peripheral's registers declarations and bits definition
10+ * - Macros to access peripheral’s registers hardware
11+ *
12+ ******************************************************************************
13+ * @attention
14+ *
15+ * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
16+ * All rights reserved.</center></h2>
17+ *
18+ * This software component is licensed by ST under BSD 3-Clause license,
19+ * the "License"; You may not use this file except in compliance with the
20+ * License. You may obtain a copy of the License at:
21+ * opensource.org/licenses/BSD-3-Clause
22+ *
23+ ******************************************************************************
24+ */
25+
26+/** @addtogroup CMSIS_Device
27+ * @{
28+ */
29+
30+/** @addtogroup stm32g491xx
31+ * @{
32+ */
33+
34+#ifndef __STM32G491xx_H
35+#define __STM32G491xx_H
36+
37+#ifdef __cplusplus
38+ extern "C" {
39+#endif /* __cplusplus */
40+
41+/** @addtogroup Configuration_section_for_CMSIS
42+ * @{
43+ */
44+
45+/**
46+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
47+ */
48+#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
49+#define __MPU_PRESENT 1 /*!< STM32G4XX provides an MPU */
50+#define __NVIC_PRIO_BITS 4 /*!< STM32G4XX uses 4 Bits for the Priority Levels */
51+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
52+#define __FPU_PRESENT 1 /*!< FPU present */
53+
54+/**
55+ * @}
56+ */
57+
58+/** @addtogroup Peripheral_interrupt_number_definition
59+ * @{
60+ */
61+
62+/**
63+ * @brief STM32G4XX Interrupt Number Definition, according to the selected device
64+ * in @ref Library_configuration_section
65+ */
66+typedef enum
67+{
68+/****** Cortex-M4 Processor Exceptions Numbers *********************************************************************************/
69+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
70+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
71+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
72+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
73+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
74+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
75+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
76+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
77+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
78+/****** STM32 specific Interrupt Numbers ***************************************************************************************/
79+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
80+ PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */
81+ RTC_TAMP_LSECSS_IRQn = 2, /*!< RTC Tamper and TimeStamp and RCC LSE CSS interrupts through the EXTI */
82+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
83+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
84+ RCC_IRQn = 5, /*!< RCC global Interrupt */
85+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
86+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
87+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
88+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
89+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
90+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
91+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
92+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
93+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
94+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
95+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
96+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
97+ ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
98+ USB_HP_IRQn = 19, /*!< USB HP Interrupt */
99+ USB_LP_IRQn = 20, /*!< USB LP Interrupt */
100+ FDCAN1_IT0_IRQn = 21, /*!< FDCAN1 IT0 Interrupt */
101+ FDCAN1_IT1_IRQn = 22, /*!< FDCAN1 IT1 Interrupt */
102+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
103+ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break, Transition error, Index error and TIM15 global interrupt */
104+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */
105+ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 TIM1 Trigger, Commutation, Direction change, Index and TIM17 global interrupt */
106+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
107+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
108+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
109+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
110+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
111+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
112+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
113+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
114+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
115+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
116+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
117+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
118+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
119+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
120+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
121+ USBWakeUp_IRQn = 42, /*!< USB Wakeup through EXTI line Interrupt */
122+ TIM8_BRK_IRQn = 43, /*!< TIM8 Break, Transition error and Index error Interrupt */
123+ TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
124+ TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger, Commutation, Direction change and Index Interrupt */
125+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
126+ ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
127+ LPTIM1_IRQn = 49, /*!< LP TIM1 Interrupt */
128+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
129+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
130+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
131+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&3 underrun error interrupts */
132+ TIM7_IRQn = 55, /*!< TIM7 global interrupts */
133+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
134+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
135+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
136+ DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
137+ DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
138+ UCPD1_IRQn = 63, /*!< UCPD global Interrupt */
139+ COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 Interrupts */
140+ COMP4_IRQn = 65, /*!< COMP4 */
141+ CRS_IRQn = 75, /*!< CRS global interrupt */
142+ SAI1_IRQn = 76, /*!< Serial Audio Interface global interrupt */
143+ TIM20_BRK_IRQn = 77, /*!< TIM20 Break, Transition error and Index error Interrupt */
144+ TIM20_UP_IRQn = 78, /*!< TIM20 Update interrupt */
145+ TIM20_TRG_COM_IRQn = 79, /*!< TIM20 Trigger, Commutation, Direction change and Index Interrupt */
146+ TIM20_CC_IRQn = 80, /*!< TIM20 Capture Compare interrupt */
147+ FPU_IRQn = 81, /*!< FPU global interrupt */
148+ FDCAN2_IT0_IRQn = 86, /*!< FDCAN2 interrupt line 0 interrupt */
149+ FDCAN2_IT1_IRQn = 87, /*!< FDCAN2 interrupt line 1 interrupt */
150+ RNG_IRQn = 90, /*!< RNG global interrupt */
151+ LPUART1_IRQn = 91, /*!< LP UART 1 Interrupt */
152+ I2C3_EV_IRQn = 92, /*!< I2C3 Event Interrupt */
153+ I2C3_ER_IRQn = 93, /*!< I2C3 Error interrupt */
154+ DMAMUX_OVR_IRQn = 94, /*!< DMAMUX overrun global interrupt */
155+ QUADSPI_IRQn = 95, /*!< QUADSPI interrupt */
156+ DMA1_Channel8_IRQn = 96, /*!< DMA1 Channel 8 interrupt */
157+ DMA2_Channel6_IRQn = 97, /*!< DMA2 Channel 6 interrupt */
158+ DMA2_Channel7_IRQn = 98, /*!< DMA2 Channel 7 interrupt */
159+ DMA2_Channel8_IRQn = 99, /*!< DMA2 Channel 8 interrupt */
160+ CORDIC_IRQn = 100, /*!< CORDIC global Interrupt */
161+ FMAC_IRQn = 101 /*!< FMAC global Interrupt */
162+} IRQn_Type;
163+
164+/**
165+ * @}
166+ */
167+
168+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
169+#include "system_stm32g4xx.h"
170+#include <stdint.h>
171+
172+/** @addtogroup Peripheral_registers_structures
173+ * @{
174+ */
175+
176+/**
177+ * @brief Analog to Digital Converter
178+ */
179+
180+typedef struct
181+{
182+ __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
183+ __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
184+ __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
185+ __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */
186+ __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
187+ __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */
188+ __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */
189+ uint32_t RESERVED1; /*!< Reserved, 0x1C */
190+ __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
191+ __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
192+ __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */
193+ uint32_t RESERVED2; /*!< Reserved, 0x2C */
194+ __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */
195+ __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */
196+ __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */
197+ __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */
198+ __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
199+ uint32_t RESERVED3; /*!< Reserved, 0x44 */
200+ uint32_t RESERVED4; /*!< Reserved, 0x48 */
201+ __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */
202+ uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */
203+ __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
204+ __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
205+ __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
206+ __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
207+ uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */
208+ __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */
209+ __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */
210+ __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */
211+ __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */
212+ uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
213+ __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */
214+ __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */
215+ uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
216+ uint32_t RESERVED9; /*!< Reserved, 0x0AC */
217+ __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */
218+ __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */
219+ uint32_t RESERVED10[2];/*!< Reserved, 0x0B8 - 0x0BC */
220+ __IO uint32_t GCOMP; /*!< ADC calibration factors, Address offset: 0xC0 */
221+} ADC_TypeDef;
222+
223+typedef struct
224+{
225+ __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 + 0x00 */
226+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x300 + 0x04 */
227+ __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x300 + 0x08 */
228+ __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */
229+} ADC_Common_TypeDef;
230+
231+/**
232+ * @brief FD Controller Area Network
233+ */
234+
235+typedef struct
236+{
237+ __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */
238+ __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */
239+ uint32_t RESERVED1; /*!< Reserved, 0x008 */
240+ __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */
241+ __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */
242+ __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */
243+ __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */
244+ __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */
245+ __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */
246+ __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */
247+ __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */
248+ __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */
249+ uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */
250+ __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */
251+ __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */
252+ __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */
253+ uint32_t RESERVED3; /*!< Reserved, 0x04C */
254+ __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */
255+ __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */
256+ __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */
257+ __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */
258+ uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */
259+ __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */
260+ __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */
261+ __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */
262+ uint32_t RESERVED5; /*!< Reserved, 0x08C */
263+ __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */
264+ __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */
265+ __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */
266+ __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */
267+ uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */
268+ __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */
269+ __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */
270+ __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */
271+ __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */
272+ __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */
273+ __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */
274+ __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */
275+ __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */
276+ __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */
277+ __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */
278+ __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */
279+} FDCAN_GlobalTypeDef;
280+
281+/**
282+ * @brief FD Controller Area Network Configuration
283+ */
284+
285+typedef struct
286+{
287+ __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */
288+} FDCAN_Config_TypeDef;
289+
290+/**
291+ * @brief Comparator
292+ */
293+
294+typedef struct
295+{
296+ __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
297+} COMP_TypeDef;
298+
299+/**
300+ * @brief CRC calculation unit
301+ */
302+
303+typedef struct
304+{
305+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
306+ __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
307+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
308+ uint32_t RESERVED0; /*!< Reserved, 0x0C */
309+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
310+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
311+} CRC_TypeDef;
312+
313+/**
314+ * @brief Clock Recovery System
315+ */
316+typedef struct
317+{
318+ __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
319+ __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
320+ __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
321+ __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
322+} CRS_TypeDef;
323+
324+/**
325+ * @brief Digital to Analog Converter
326+ */
327+
328+typedef struct
329+{
330+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
331+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
332+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
333+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
334+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
335+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
336+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
337+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
338+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
339+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
340+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
341+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
342+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
343+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
344+ __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
345+ __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
346+ __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
347+ __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
348+ __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
349+ __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
350+ __IO uint32_t RESERVED[2];
351+ __IO uint32_t STR1; /*!< DAC Sawtooth register, Address offset: 0x58 */
352+ __IO uint32_t STR2; /*!< DAC Sawtooth register, Address offset: 0x5C */
353+ __IO uint32_t STMODR; /*!< DAC Sawtooth Mode register, Address offset: 0x60 */
354+} DAC_TypeDef;
355+
356+/**
357+ * @brief Debug MCU
358+ */
359+
360+typedef struct
361+{
362+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
363+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
364+ __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
365+ __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
366+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
367+} DBGMCU_TypeDef;
368+
369+/**
370+ * @brief DMA Controller
371+ */
372+
373+typedef struct
374+{
375+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
376+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
377+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
378+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
379+} DMA_Channel_TypeDef;
380+
381+typedef struct
382+{
383+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
384+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
385+} DMA_TypeDef;
386+
387+/**
388+ * @brief DMA Multiplexer
389+ */
390+
391+typedef struct
392+{
393+ __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */
394+}DMAMUX_Channel_TypeDef;
395+
396+typedef struct
397+{
398+ __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */
399+ __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */
400+}DMAMUX_ChannelStatus_TypeDef;
401+
402+typedef struct
403+{
404+ __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */
405+}DMAMUX_RequestGen_TypeDef;
406+
407+typedef struct
408+{
409+ __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */
410+ __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */
411+}DMAMUX_RequestGenStatus_TypeDef;
412+
413+/**
414+ * @brief External Interrupt/Event Controller
415+ */
416+
417+typedef struct
418+{
419+ __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */
420+ __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */
421+ __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */
422+ __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */
423+ __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */
424+ __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */
425+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
426+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
427+ __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */
428+ __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */
429+ __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */
430+ __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */
431+ __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */
432+ __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */
433+} EXTI_TypeDef;
434+
435+/**
436+ * @brief FLASH Registers
437+ */
438+
439+typedef struct
440+{
441+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
442+ __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */
443+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */
444+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */
445+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */
446+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */
447+ __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */
448+ uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */
449+ __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */
450+ __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
451+ __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */
452+ __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */
453+ __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */
454+ uint32_t RESERVED2[15]; /*!< Reserved2, Address offset: 0x34 */
455+ __IO uint32_t SEC1R; /*!< FLASH Securable memory register bank1, Address offset: 0x70 */
456+} FLASH_TypeDef;
457+
458+/**
459+ * @brief FMAC
460+ */
461+typedef struct
462+{
463+ __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */
464+ __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */
465+ __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */
466+ __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */
467+ __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */
468+ __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */
469+ __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */
470+ __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */
471+} FMAC_TypeDef;
472+
473+
474+/**
475+ * @brief General Purpose I/O
476+ */
477+
478+typedef struct
479+{
480+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
481+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
482+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
483+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
484+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
485+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
486+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
487+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
488+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
489+ __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
490+} GPIO_TypeDef;
491+
492+/**
493+ * @brief Inter-integrated Circuit Interface
494+ */
495+
496+typedef struct
497+{
498+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
499+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
500+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
501+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
502+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
503+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
504+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
505+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
506+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
507+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
508+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
509+} I2C_TypeDef;
510+
511+/**
512+ * @brief Independent WATCHDOG
513+ */
514+
515+typedef struct
516+{
517+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
518+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
519+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
520+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
521+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
522+} IWDG_TypeDef;
523+
524+/**
525+ * @brief LPTIMER
526+ */
527+
528+typedef struct
529+{
530+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
531+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
532+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
533+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
534+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
535+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
536+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
537+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
538+ __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
539+} LPTIM_TypeDef;
540+
541+/**
542+ * @brief Operational Amplifier (OPAMP)
543+ */
544+
545+typedef struct
546+{
547+ __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
548+ __IO uint32_t RESERVED[5]; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
549+ __IO uint32_t TCMR; /*!< OPAMP timer controlled mux mode register, Address offset: 0x18 */
550+} OPAMP_TypeDef;
551+
552+/**
553+ * @brief Power Control
554+ */
555+
556+typedef struct
557+{
558+ __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
559+ __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */
560+ __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */
561+ __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */
562+ __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */
563+ __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */
564+ __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */
565+ uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */
566+ __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */
567+ __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
568+ __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */
569+ __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
570+ __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */
571+ __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
572+ __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */
573+ __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
574+ __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */
575+ __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
576+ __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */
577+ __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */
578+ __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */
579+ __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */
580+ uint32_t RESERVED1[10]; /*!< Reserved Address offset: 0x58 - 0x7C */
581+ __IO uint32_t CR5; /*!< PWR power control register 5, Address offset: 0x80 */
582+} PWR_TypeDef;
583+
584+/**
585+ * @brief QUAD Serial Peripheral Interface
586+ */
587+
588+typedef struct
589+{
590+ __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
591+ __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
592+ __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
593+ __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
594+ __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
595+ __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
596+ __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
597+ __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
598+ __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
599+ __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
600+ __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
601+ __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
602+ __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
603+} QUADSPI_TypeDef;
604+
605+/**
606+ * @brief Reset and Clock Control
607+ */
608+
609+typedef struct
610+{
611+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
612+ __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */
613+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
614+ __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */
615+ uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */
616+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
617+ __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */
618+ __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */
619+ __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */
620+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */
621+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */
622+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */
623+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */
624+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x34 */
625+ __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */
626+ __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */
627+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */
628+ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x44 */
629+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */
630+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */
631+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */
632+ uint32_t RESERVED5; /*!< Reserved, Address offset: 0x54 */
633+ __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */
634+ __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */
635+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */
636+ uint32_t RESERVED6; /*!< Reserved, Address offset: 0x64 */
637+ __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */
638+ __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */
639+ __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */
640+ uint32_t RESERVED7; /*!< Reserved, Address offset: 0x74 */
641+ __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
642+ __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
643+ __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
644+ uint32_t RESERVED8; /*!< Reserved, Address offset: 0x84 */
645+ __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */
646+ uint32_t RESERVED9; /*!< Reserved, Address offset: 0x8C */
647+ __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */
648+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */
649+ __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */
650+ __IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */
651+} RCC_TypeDef;
652+
653+/**
654+ * @brief Real-Time Clock
655+ */
656+/*
657+* @brief Specific device feature definitions
658+*/
659+#define RTC_TAMP_INT_6_SUPPORT
660+#define RTC_TAMP_INT_NB 4u
661+
662+#define RTC_TAMP_NB 3u
663+#define RTC_BACKUP_NB 32u
664+
665+
666+typedef struct
667+{
668+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
669+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
670+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */
671+ __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */
672+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
673+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
674+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */
675+ uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */
676+ uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */
677+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
678+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */
679+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
680+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
681+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
682+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
683+ uint32_t RESERVED2; /*!< Reserved Address offset: 0x3C */
684+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */
685+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
686+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */
687+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */
688+ __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */
689+ __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */
690+ uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */
691+ __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */
692+} RTC_TypeDef;
693+
694+/**
695+ * @brief Tamper and backup registers
696+ */
697+
698+typedef struct
699+{
700+ __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */
701+ __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */
702+ uint32_t RESERVED0; /*!< no configuration register 3, Address offset: 0x08 */
703+ __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */
704+ uint32_t RESERVED1[6]; /*!< Reserved Address offset: 0x10 - 0x24 */
705+ uint32_t RESERVED2; /*!< Reserved Address offset: 0x28 */
706+ __IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */
707+ __IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */
708+ __IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register Address offset: 0x34 */
709+ uint32_t RESERVED3; /*!< Reserved Address offset: 0x38 */
710+ __IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */
711+ uint32_t RESERVED4[48]; /*!< Reserved Address offset: 0x040 - 0xFC */
712+ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */
713+ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */
714+ __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */
715+ __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */
716+ __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */
717+ __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */
718+ __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */
719+ __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */
720+ __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */
721+ __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */
722+ __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */
723+ __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */
724+ __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */
725+ __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */
726+ __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */
727+ __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */
728+ __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */
729+ __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */
730+ __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */
731+ __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */
732+ __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */
733+ __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */
734+ __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */
735+ __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */
736+ __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */
737+ __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */
738+ __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */
739+ __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */
740+ __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */
741+ __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */
742+ __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */
743+ __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */
744+} TAMP_TypeDef;
745+
746+/**
747+ * @brief Serial Audio Interface
748+ */
749+
750+typedef struct
751+{
752+ __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
753+ uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */
754+ __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
755+ __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
756+} SAI_TypeDef;
757+
758+typedef struct
759+{
760+ __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
761+ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
762+ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
763+ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
764+ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
765+ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
766+ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
767+ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
768+} SAI_Block_TypeDef;
769+
770+/**
771+ * @brief Serial Peripheral Interface
772+ */
773+
774+typedef struct
775+{
776+ __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
777+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
778+ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
779+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
780+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
781+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
782+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
783+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
784+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
785+} SPI_TypeDef;
786+
787+/**
788+ * @brief System configuration controller
789+ */
790+
791+typedef struct
792+{
793+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
794+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
795+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
796+ __IO uint32_t SCSR; /*!< SYSCFG CCMSRAM control and status register, Address offset: 0x18 */
797+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */
798+ __IO uint32_t SWPR; /*!< SYSCFG CCMSRAM write protection register, Address offset: 0x20 */
799+ __IO uint32_t SKR; /*!< SYSCFG CCMSRAM Key Register, Address offset: 0x24 */
800+} SYSCFG_TypeDef;
801+
802+/**
803+ * @brief TIM
804+ */
805+
806+typedef struct
807+{
808+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
809+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
810+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
811+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
812+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
813+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
814+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
815+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
816+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
817+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
818+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
819+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
820+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
821+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
822+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
823+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
824+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
825+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
826+ __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */
827+ __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */
828+ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */
829+ __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */
830+ __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */
831+ __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */
832+ __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */
833+ __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */
834+ __IO uint32_t OR ; /*!< TIM option register, Address offset: 0x68 */
835+ uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */
836+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */
837+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */
838+} TIM_TypeDef;
839+
840+/**
841+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
842+ */
843+typedef struct
844+{
845+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
846+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
847+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
848+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
849+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
850+ __IO uint32_t RTOR; /*!< USART Receiver Timeout register, Address offset: 0x14 */
851+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
852+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
853+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
854+ __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
855+ __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
856+ __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */
857+} USART_TypeDef;
858+
859+/**
860+ * @brief Universal Serial Bus Full Speed Device
861+ */
862+
863+typedef struct
864+{
865+ __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
866+ __IO uint16_t RESERVED0; /*!< Reserved */
867+ __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
868+ __IO uint16_t RESERVED1; /*!< Reserved */
869+ __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
870+ __IO uint16_t RESERVED2; /*!< Reserved */
871+ __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
872+ __IO uint16_t RESERVED3; /*!< Reserved */
873+ __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
874+ __IO uint16_t RESERVED4; /*!< Reserved */
875+ __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
876+ __IO uint16_t RESERVED5; /*!< Reserved */
877+ __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
878+ __IO uint16_t RESERVED6; /*!< Reserved */
879+ __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
880+ __IO uint16_t RESERVED7[17]; /*!< Reserved */
881+ __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
882+ __IO uint16_t RESERVED8; /*!< Reserved */
883+ __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
884+ __IO uint16_t RESERVED9; /*!< Reserved */
885+ __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
886+ __IO uint16_t RESERVEDA; /*!< Reserved */
887+ __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
888+ __IO uint16_t RESERVEDB; /*!< Reserved */
889+ __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
890+ __IO uint16_t RESERVEDC; /*!< Reserved */
891+ __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
892+ __IO uint16_t RESERVEDD; /*!< Reserved */
893+ __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
894+ __IO uint16_t RESERVEDE; /*!< Reserved */
895+} USB_TypeDef;
896+
897+/**
898+ * @brief VREFBUF
899+ */
900+
901+typedef struct
902+{
903+ __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
904+ __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
905+} VREFBUF_TypeDef;
906+
907+/**
908+ * @brief Window WATCHDOG
909+ */
910+
911+typedef struct
912+{
913+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
914+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
915+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
916+} WWDG_TypeDef;
917+
918+
919+/**
920+ * @brief RNG
921+ */
922+typedef struct
923+{
924+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
925+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
926+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
927+} RNG_TypeDef;
928+
929+/**
930+ * @brief CORDIC
931+ */
932+
933+typedef struct
934+{
935+ __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */
936+ __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */
937+ __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */
938+} CORDIC_TypeDef;
939+
940+/**
941+ * @brief UCPD
942+ */
943+
944+typedef struct
945+{
946+ __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */
947+ __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */
948+ __IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */
949+ __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */
950+ __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */
951+ __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */
952+ __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */
953+ __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */
954+ __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */
955+ __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */
956+ __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */
957+ __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */
958+ __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */
959+ __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */
960+ __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */
961+} UCPD_TypeDef;
962+
963+
964+/** @addtogroup Peripheral_memory_map
965+ * @{
966+ */
967+
968+#define FLASH_BASE (0x08000000UL) /*!< FLASH (up to 512 kB) base address */
969+#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 80 KB) base address */
970+#define SRAM2_BASE (0x20014000UL) /*!< SRAM2(16 KB) base address */
971+#define CCMSRAM_BASE (0x10000000UL) /*!< CCMSRAM(16 KB) base address */
972+#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
973+#define QSPI_BASE (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */
974+
975+#define QSPI_R_BASE (0xA0001000UL) /*!< QUADSPI control registers base address */
976+#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(80 KB) base address in the bit-band region */
977+#define SRAM2_BB_BASE (0x22280000UL) /*!< SRAM2(16 KB) base address in the bit-band region */
978+#define CCMSRAM_BB_BASE (0x22300000UL) /*!< CCMSRAM(16 KB) base address in the bit-band region */
979+#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */
980+/* Legacy defines */
981+#define SRAM_BASE SRAM1_BASE
982+#define SRAM_BB_BASE SRAM1_BB_BASE
983+
984+#define SRAM1_SIZE_MAX (0x00014000UL) /*!< maximum SRAM1 size (up to 80 KBytes) */
985+#define SRAM2_SIZE (0x00004000UL) /*!< SRAM2 size (16 KBytes) */
986+#define CCMSRAM_SIZE (0x00004000UL) /*!< CCMSRAM size (16 KBytes) */
987+
988+/*!< Peripheral memory map */
989+#define APB1PERIPH_BASE PERIPH_BASE
990+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
991+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
992+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)
993+
994+
995+/*!< APB1 peripherals */
996+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
997+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
998+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
999+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
1000+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
1001+#define CRS_BASE (APB1PERIPH_BASE + 0x2000UL)
1002+#define TAMP_BASE (APB1PERIPH_BASE + 0x2400UL)
1003+#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
1004+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
1005+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
1006+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
1007+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
1008+#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
1009+#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
1010+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)
1011+#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL)
1012+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
1013+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
1014+#define USB_BASE (APB1PERIPH_BASE + 0x5C00UL) /*!< USB_IP Peripheral Registers base address */
1015+#define USB_PMAADDR (APB1PERIPH_BASE + 0x6000UL) /*!< USB_IP Packet Memory Area base address */
1016+#define FDCAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
1017+#define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0x6500UL) /*!< FDCAN configuration registers base address */
1018+#define FDCAN2_BASE (APB1PERIPH_BASE + 0x6800UL)
1019+#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
1020+#define I2C3_BASE (APB1PERIPH_BASE + 0x7800UL)
1021+#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL)
1022+#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL)
1023+#define UCPD1_BASE (APB1PERIPH_BASE + 0xA000UL)
1024+#define SRAMCAN_BASE (APB1PERIPH_BASE + 0xA400UL)
1025+
1026+/*!< APB2 peripherals */
1027+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL)
1028+#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL)
1029+#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL)
1030+#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL)
1031+#define COMP3_BASE (APB2PERIPH_BASE + 0x0208UL)
1032+#define COMP4_BASE (APB2PERIPH_BASE + 0x020CUL)
1033+#define OPAMP_BASE (APB2PERIPH_BASE + 0x0300UL)
1034+#define OPAMP1_BASE (APB2PERIPH_BASE + 0x0300UL)
1035+#define OPAMP2_BASE (APB2PERIPH_BASE + 0x0304UL)
1036+#define OPAMP3_BASE (APB2PERIPH_BASE + 0x0308UL)
1037+#define OPAMP6_BASE (APB2PERIPH_BASE + 0x0314UL)
1038+
1039+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL)
1040+#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL)
1041+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
1042+#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL)
1043+#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL)
1044+#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL)
1045+#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL)
1046+#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL)
1047+#define TIM20_BASE (APB2PERIPH_BASE + 0x5000UL)
1048+#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL)
1049+#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL)
1050+#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL)
1051+
1052+/*!< AHB1 peripherals */
1053+#define DMA1_BASE (AHB1PERIPH_BASE)
1054+#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL)
1055+#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x0800UL)
1056+#define CORDIC_BASE (AHB1PERIPH_BASE + 0x0C00UL)
1057+#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL)
1058+#define FMAC_BASE (AHB1PERIPH_BASE + 0x1400UL)
1059+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL)
1060+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
1061+
1062+#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL)
1063+#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL)
1064+#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL)
1065+#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL)
1066+#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL)
1067+#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL)
1068+#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL)
1069+#define DMA1_Channel8_BASE (DMA1_BASE + 0x0094UL)
1070+
1071+#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL)
1072+#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL)
1073+#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL)
1074+#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL)
1075+#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL)
1076+#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL)
1077+#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL)
1078+#define DMA2_Channel8_BASE (DMA2_BASE + 0x0094UL)
1079+
1080+#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
1081+#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL)
1082+#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL)
1083+#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL)
1084+#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL)
1085+#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL)
1086+#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL)
1087+#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL)
1088+#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL)
1089+#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL)
1090+#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL)
1091+#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL)
1092+#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL)
1093+#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL)
1094+#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL)
1095+#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL)
1096+#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL)
1097+#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL)
1098+#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL)
1099+#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL)
1100+
1101+#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL)
1102+#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL)
1103+
1104+/*!< AHB2 peripherals */
1105+#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL)
1106+#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL)
1107+#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL)
1108+#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL)
1109+#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL)
1110+#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL)
1111+#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL)
1112+
1113+#define ADC1_BASE (AHB2PERIPH_BASE + 0x08000000UL)
1114+#define ADC2_BASE (AHB2PERIPH_BASE + 0x08000100UL)
1115+#define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08000300UL)
1116+#define ADC3_BASE (AHB2PERIPH_BASE + 0x08000400UL)
1117+#define ADC345_COMMON_BASE (AHB2PERIPH_BASE + 0x08000700UL)
1118+
1119+#define DAC_BASE (AHB2PERIPH_BASE + 0x08000800UL)
1120+#define DAC1_BASE (AHB2PERIPH_BASE + 0x08000800UL)
1121+#define DAC3_BASE (AHB2PERIPH_BASE + 0x08001000UL)
1122+
1123+#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL)
1124+/* Debug MCU registers base address */
1125+#define DBGMCU_BASE (0xE0042000UL)
1126+
1127+#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */
1128+#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */
1129+#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */
1130+/**
1131+ * @}
1132+ */
1133+
1134+/** @addtogroup Peripheral_declaration
1135+ * @{
1136+ */
1137+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1138+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1139+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1140+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1141+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1142+#define CRS ((CRS_TypeDef *) CRS_BASE)
1143+#define TAMP ((TAMP_TypeDef *) TAMP_BASE)
1144+#define RTC ((RTC_TypeDef *) RTC_BASE)
1145+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1146+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1147+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1148+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1149+#define USART2 ((USART_TypeDef *) USART2_BASE)
1150+#define USART3 ((USART_TypeDef *) USART3_BASE)
1151+#define UART4 ((USART_TypeDef *) UART4_BASE)
1152+#define UART5 ((USART_TypeDef *) UART5_BASE)
1153+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1154+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1155+#define USB ((USB_TypeDef *) USB_BASE)
1156+#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
1157+#define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE)
1158+#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
1159+#define PWR ((PWR_TypeDef *) PWR_BASE)
1160+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1161+#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
1162+#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
1163+#define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE)
1164+
1165+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1166+#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
1167+#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
1168+#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
1169+#define COMP3 ((COMP_TypeDef *) COMP3_BASE)
1170+#define COMP4 ((COMP_TypeDef *) COMP4_BASE)
1171+
1172+#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
1173+#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
1174+#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
1175+#define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE)
1176+#define OPAMP6 ((OPAMP_TypeDef *) OPAMP6_BASE)
1177+
1178+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1179+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1180+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1181+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1182+#define USART1 ((USART_TypeDef *) USART1_BASE)
1183+#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
1184+#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
1185+#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
1186+#define TIM20 ((TIM_TypeDef *) TIM20_BASE)
1187+#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1188+#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1189+#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1190+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1191+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1192+#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
1193+#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE)
1194+#define RCC ((RCC_TypeDef *) RCC_BASE)
1195+#define FMAC ((FMAC_TypeDef *) FMAC_BASE)
1196+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1197+#define CRC ((CRC_TypeDef *) CRC_BASE)
1198+
1199+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1200+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1201+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1202+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1203+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1204+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1205+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1206+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1207+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1208+#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
1209+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1210+#define ADC345_COMMON ((ADC_Common_TypeDef *) ADC345_COMMON_BASE)
1211+#define DAC ((DAC_TypeDef *) DAC_BASE)
1212+#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
1213+#define DAC3 ((DAC_TypeDef *) DAC3_BASE)
1214+#define RNG ((RNG_TypeDef *) RNG_BASE)
1215+
1216+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
1217+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
1218+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
1219+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
1220+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
1221+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
1222+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
1223+#define DMA1_Channel8 ((DMA_Channel_TypeDef *) DMA1_Channel8_BASE)
1224+
1225+#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
1226+#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
1227+#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
1228+#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
1229+#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
1230+#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
1231+#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
1232+#define DMA2_Channel8 ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE)
1233+
1234+#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
1235+#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
1236+#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
1237+#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
1238+#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
1239+#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
1240+#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
1241+#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
1242+#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
1243+#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
1244+#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
1245+#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
1246+#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
1247+#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
1248+#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
1249+#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
1250+
1251+#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
1252+#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
1253+#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
1254+#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
1255+
1256+#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
1257+#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
1258+
1259+
1260+#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1261+
1262+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1263+
1264+/**
1265+ * @}
1266+ */
1267+
1268+/** @addtogroup Exported_constants
1269+ * @{
1270+ */
1271+
1272+/** @addtogroup Peripheral_Registers_Bits_Definition
1273+ * @{
1274+ */
1275+
1276+/******************************************************************************/
1277+/* Peripheral Registers_Bits_Definition */
1278+/******************************************************************************/
1279+
1280+/******************************************************************************/
1281+/* */
1282+/* Analog to Digital Converter */
1283+/* */
1284+/******************************************************************************/
1285+
1286+/*
1287+ * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
1288+ */
1289+#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
1290+
1291+/******************** Bit definition for ADC_ISR register *******************/
1292+#define ADC_ISR_ADRDY_Pos (0U)
1293+#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
1294+#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
1295+#define ADC_ISR_EOSMP_Pos (1U)
1296+#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
1297+#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
1298+#define ADC_ISR_EOC_Pos (2U)
1299+#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
1300+#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
1301+#define ADC_ISR_EOS_Pos (3U)
1302+#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
1303+#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
1304+#define ADC_ISR_OVR_Pos (4U)
1305+#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
1306+#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
1307+#define ADC_ISR_JEOC_Pos (5U)
1308+#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
1309+#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */
1310+#define ADC_ISR_JEOS_Pos (6U)
1311+#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
1312+#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
1313+#define ADC_ISR_AWD1_Pos (7U)
1314+#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
1315+#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
1316+#define ADC_ISR_AWD2_Pos (8U)
1317+#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
1318+#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */
1319+#define ADC_ISR_AWD3_Pos (9U)
1320+#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
1321+#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */
1322+#define ADC_ISR_JQOVF_Pos (10U)
1323+#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
1324+#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */
1325+
1326+/******************** Bit definition for ADC_IER register *******************/
1327+#define ADC_IER_ADRDYIE_Pos (0U)
1328+#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
1329+#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
1330+#define ADC_IER_EOSMPIE_Pos (1U)
1331+#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
1332+#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
1333+#define ADC_IER_EOCIE_Pos (2U)
1334+#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
1335+#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
1336+#define ADC_IER_EOSIE_Pos (3U)
1337+#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
1338+#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
1339+#define ADC_IER_OVRIE_Pos (4U)
1340+#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
1341+#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
1342+#define ADC_IER_JEOCIE_Pos (5U)
1343+#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
1344+#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */
1345+#define ADC_IER_JEOSIE_Pos (6U)
1346+#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
1347+#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
1348+#define ADC_IER_AWD1IE_Pos (7U)
1349+#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
1350+#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
1351+#define ADC_IER_AWD2IE_Pos (8U)
1352+#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
1353+#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */
1354+#define ADC_IER_AWD3IE_Pos (9U)
1355+#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
1356+#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */
1357+#define ADC_IER_JQOVFIE_Pos (10U)
1358+#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
1359+#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */
1360+
1361+/******************** Bit definition for ADC_CR register ********************/
1362+#define ADC_CR_ADEN_Pos (0U)
1363+#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
1364+#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
1365+#define ADC_CR_ADDIS_Pos (1U)
1366+#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
1367+#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
1368+#define ADC_CR_ADSTART_Pos (2U)
1369+#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
1370+#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
1371+#define ADC_CR_JADSTART_Pos (3U)
1372+#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
1373+#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */
1374+#define ADC_CR_ADSTP_Pos (4U)
1375+#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
1376+#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
1377+#define ADC_CR_JADSTP_Pos (5U)
1378+#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
1379+#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */
1380+#define ADC_CR_ADVREGEN_Pos (28U)
1381+#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
1382+#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */
1383+#define ADC_CR_DEEPPWD_Pos (29U)
1384+#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
1385+#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */
1386+#define ADC_CR_ADCALDIF_Pos (30U)
1387+#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
1388+#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */
1389+#define ADC_CR_ADCAL_Pos (31U)
1390+#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
1391+#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
1392+
1393+/******************** Bit definition for ADC_CFGR register ******************/
1394+#define ADC_CFGR_DMAEN_Pos (0U)
1395+#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */
1396+#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */
1397+#define ADC_CFGR_DMACFG_Pos (1U)
1398+#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */
1399+#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */
1400+
1401+#define ADC_CFGR_RES_Pos (3U)
1402+#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */
1403+#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */
1404+#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
1405+#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
1406+
1407+#define ADC_CFGR_EXTSEL_Pos (5U)
1408+#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */
1409+#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */
1410+#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */
1411+#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
1412+#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
1413+#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
1414+#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
1415+
1416+#define ADC_CFGR_EXTEN_Pos (10U)
1417+#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
1418+#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */
1419+#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
1420+#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
1421+
1422+#define ADC_CFGR_OVRMOD_Pos (12U)
1423+#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
1424+#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */
1425+#define ADC_CFGR_CONT_Pos (13U)
1426+#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
1427+#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */
1428+#define ADC_CFGR_AUTDLY_Pos (14U)
1429+#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
1430+#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */
1431+#define ADC_CFGR_ALIGN_Pos (15U)
1432+#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */
1433+#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
1434+#define ADC_CFGR_DISCEN_Pos (16U)
1435+#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
1436+#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
1437+
1438+#define ADC_CFGR_DISCNUM_Pos (17U)
1439+#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
1440+#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
1441+#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
1442+#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
1443+#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
1444+
1445+#define ADC_CFGR_JDISCEN_Pos (20U)
1446+#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
1447+#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
1448+#define ADC_CFGR_JQM_Pos (21U)
1449+#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
1450+#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */
1451+#define ADC_CFGR_AWD1SGL_Pos (22U)
1452+#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
1453+#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
1454+#define ADC_CFGR_AWD1EN_Pos (23U)
1455+#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
1456+#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
1457+#define ADC_CFGR_JAWD1EN_Pos (24U)
1458+#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
1459+#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
1460+#define ADC_CFGR_JAUTO_Pos (25U)
1461+#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
1462+#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
1463+
1464+#define ADC_CFGR_AWD1CH_Pos (26U)
1465+#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
1466+#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
1467+#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
1468+#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
1469+#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
1470+#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
1471+#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
1472+
1473+#define ADC_CFGR_JQDIS_Pos (31U)
1474+#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
1475+#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */
1476+
1477+/******************** Bit definition for ADC_CFGR2 register *****************/
1478+#define ADC_CFGR2_ROVSE_Pos (0U)
1479+#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
1480+#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */
1481+#define ADC_CFGR2_JOVSE_Pos (1U)
1482+#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
1483+#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */
1484+
1485+#define ADC_CFGR2_OVSR_Pos (2U)
1486+#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
1487+#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */
1488+#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
1489+#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
1490+#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
1491+
1492+#define ADC_CFGR2_OVSS_Pos (5U)
1493+#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
1494+#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */
1495+#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
1496+#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
1497+#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
1498+#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
1499+
1500+#define ADC_CFGR2_TROVS_Pos (9U)
1501+#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
1502+#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
1503+#define ADC_CFGR2_ROVSM_Pos (10U)
1504+#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
1505+#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
1506+
1507+#define ADC_CFGR2_GCOMP_Pos (16U)
1508+#define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */
1509+#define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */
1510+
1511+#define ADC_CFGR2_SWTRIG_Pos (25U)
1512+#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */
1513+#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */
1514+#define ADC_CFGR2_BULB_Pos (26U)
1515+#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */
1516+#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */
1517+#define ADC_CFGR2_SMPTRIG_Pos (27U)
1518+#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */
1519+#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */
1520+
1521+/******************** Bit definition for ADC_SMPR1 register *****************/
1522+#define ADC_SMPR1_SMP0_Pos (0U)
1523+#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
1524+#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */
1525+#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
1526+#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
1527+#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
1528+
1529+#define ADC_SMPR1_SMP1_Pos (3U)
1530+#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
1531+#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */
1532+#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
1533+#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
1534+#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
1535+
1536+#define ADC_SMPR1_SMP2_Pos (6U)
1537+#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
1538+#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */
1539+#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
1540+#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
1541+#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
1542+
1543+#define ADC_SMPR1_SMP3_Pos (9U)
1544+#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
1545+#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */
1546+#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
1547+#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
1548+#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
1549+
1550+#define ADC_SMPR1_SMP4_Pos (12U)
1551+#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
1552+#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */
1553+#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
1554+#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
1555+#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
1556+
1557+#define ADC_SMPR1_SMP5_Pos (15U)
1558+#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
1559+#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */
1560+#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
1561+#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
1562+#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
1563+
1564+#define ADC_SMPR1_SMP6_Pos (18U)
1565+#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
1566+#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */
1567+#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
1568+#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
1569+#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
1570+
1571+#define ADC_SMPR1_SMP7_Pos (21U)
1572+#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
1573+#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */
1574+#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
1575+#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
1576+#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
1577+
1578+#define ADC_SMPR1_SMP8_Pos (24U)
1579+#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
1580+#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */
1581+#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
1582+#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
1583+#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
1584+
1585+#define ADC_SMPR1_SMP9_Pos (27U)
1586+#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
1587+#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */
1588+#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
1589+#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
1590+#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
1591+
1592+#define ADC_SMPR1_SMPPLUS_Pos (31U)
1593+#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */
1594+#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */
1595+
1596+/******************** Bit definition for ADC_SMPR2 register *****************/
1597+#define ADC_SMPR2_SMP10_Pos (0U)
1598+#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
1599+#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */
1600+#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
1601+#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
1602+#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
1603+
1604+#define ADC_SMPR2_SMP11_Pos (3U)
1605+#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
1606+#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */
1607+#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
1608+#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
1609+#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
1610+
1611+#define ADC_SMPR2_SMP12_Pos (6U)
1612+#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
1613+#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */
1614+#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
1615+#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
1616+#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
1617+
1618+#define ADC_SMPR2_SMP13_Pos (9U)
1619+#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
1620+#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */
1621+#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
1622+#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
1623+#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
1624+
1625+#define ADC_SMPR2_SMP14_Pos (12U)
1626+#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
1627+#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */
1628+#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
1629+#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
1630+#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
1631+
1632+#define ADC_SMPR2_SMP15_Pos (15U)
1633+#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
1634+#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */
1635+#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
1636+#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
1637+#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
1638+
1639+#define ADC_SMPR2_SMP16_Pos (18U)
1640+#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
1641+#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */
1642+#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
1643+#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
1644+#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
1645+
1646+#define ADC_SMPR2_SMP17_Pos (21U)
1647+#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
1648+#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */
1649+#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
1650+#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
1651+#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
1652+
1653+#define ADC_SMPR2_SMP18_Pos (24U)
1654+#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
1655+#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */
1656+#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
1657+#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
1658+#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
1659+
1660+/******************** Bit definition for ADC_TR1 register *******************/
1661+#define ADC_TR1_LT1_Pos (0U)
1662+#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
1663+#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
1664+
1665+#define ADC_TR1_AWDFILT_Pos (12U)
1666+#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */
1667+#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */
1668+#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */
1669+#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */
1670+#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */
1671+
1672+#define ADC_TR1_HT1_Pos (16U)
1673+#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
1674+#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */
1675+
1676+/******************** Bit definition for ADC_TR2 register *******************/
1677+#define ADC_TR2_LT2_Pos (0U)
1678+#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */
1679+#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
1680+
1681+#define ADC_TR2_HT2_Pos (16U)
1682+#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */
1683+#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
1684+
1685+/******************** Bit definition for ADC_TR3 register *******************/
1686+#define ADC_TR3_LT3_Pos (0U)
1687+#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */
1688+#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
1689+
1690+#define ADC_TR3_HT3_Pos (16U)
1691+#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */
1692+#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
1693+
1694+/******************** Bit definition for ADC_SQR1 register ******************/
1695+#define ADC_SQR1_L_Pos (0U)
1696+#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
1697+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
1698+#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
1699+#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
1700+#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
1701+#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */
1702+
1703+#define ADC_SQR1_SQ1_Pos (6U)
1704+#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
1705+#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
1706+#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
1707+#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
1708+#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
1709+#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
1710+#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
1711+
1712+#define ADC_SQR1_SQ2_Pos (12U)
1713+#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
1714+#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
1715+#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
1716+#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
1717+#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
1718+#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
1719+#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
1720+
1721+#define ADC_SQR1_SQ3_Pos (18U)
1722+#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
1723+#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
1724+#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
1725+#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
1726+#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
1727+#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
1728+#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
1729+
1730+#define ADC_SQR1_SQ4_Pos (24U)
1731+#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
1732+#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
1733+#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
1734+#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
1735+#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
1736+#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
1737+#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
1738+
1739+/******************** Bit definition for ADC_SQR2 register ******************/
1740+#define ADC_SQR2_SQ5_Pos (0U)
1741+#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
1742+#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
1743+#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
1744+#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
1745+#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
1746+#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
1747+#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
1748+
1749+#define ADC_SQR2_SQ6_Pos (6U)
1750+#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
1751+#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
1752+#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
1753+#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
1754+#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
1755+#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
1756+#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
1757+
1758+#define ADC_SQR2_SQ7_Pos (12U)
1759+#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
1760+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
1761+#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
1762+#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
1763+#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
1764+#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
1765+#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
1766+
1767+#define ADC_SQR2_SQ8_Pos (18U)
1768+#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
1769+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
1770+#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
1771+#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
1772+#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
1773+#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
1774+#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
1775+
1776+#define ADC_SQR2_SQ9_Pos (24U)
1777+#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
1778+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
1779+#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
1780+#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
1781+#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
1782+#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
1783+#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
1784+
1785+/******************** Bit definition for ADC_SQR3 register ******************/
1786+#define ADC_SQR3_SQ10_Pos (0U)
1787+#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
1788+#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
1789+#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
1790+#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
1791+#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
1792+#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
1793+#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
1794+
1795+#define ADC_SQR3_SQ11_Pos (6U)
1796+#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
1797+#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */
1798+#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
1799+#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
1800+#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
1801+#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
1802+#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
1803+
1804+#define ADC_SQR3_SQ12_Pos (12U)
1805+#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
1806+#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
1807+#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
1808+#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
1809+#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
1810+#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
1811+#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
1812+
1813+#define ADC_SQR3_SQ13_Pos (18U)
1814+#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
1815+#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
1816+#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
1817+#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
1818+#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
1819+#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
1820+#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
1821+
1822+#define ADC_SQR3_SQ14_Pos (24U)
1823+#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
1824+#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
1825+#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
1826+#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
1827+#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
1828+#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
1829+#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
1830+
1831+/******************** Bit definition for ADC_SQR4 register ******************/
1832+#define ADC_SQR4_SQ15_Pos (0U)
1833+#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
1834+#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
1835+#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
1836+#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
1837+#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
1838+#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
1839+#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
1840+
1841+#define ADC_SQR4_SQ16_Pos (6U)
1842+#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
1843+#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
1844+#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
1845+#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
1846+#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
1847+#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
1848+#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
1849+
1850+/******************** Bit definition for ADC_DR register ********************/
1851+#define ADC_DR_RDATA_Pos (0U)
1852+#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */
1853+#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */
1854+
1855+/******************** Bit definition for ADC_JSQR register ******************/
1856+#define ADC_JSQR_JL_Pos (0U)
1857+#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
1858+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
1859+#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
1860+#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
1861+
1862+#define ADC_JSQR_JEXTSEL_Pos (2U)
1863+#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */
1864+#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */
1865+#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
1866+#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
1867+#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
1868+#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
1869+#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */
1870+
1871+#define ADC_JSQR_JEXTEN_Pos (7U)
1872+#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */
1873+#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */
1874+#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
1875+#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */
1876+
1877+#define ADC_JSQR_JSQ1_Pos (9U)
1878+#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */
1879+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
1880+#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
1881+#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
1882+#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
1883+#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
1884+#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */
1885+
1886+#define ADC_JSQR_JSQ2_Pos (15U)
1887+#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */
1888+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
1889+#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */
1890+#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
1891+#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
1892+#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
1893+#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
1894+
1895+#define ADC_JSQR_JSQ3_Pos (21U)
1896+#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */
1897+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
1898+#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
1899+#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
1900+#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
1901+#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
1902+#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */
1903+
1904+#define ADC_JSQR_JSQ4_Pos (27U)
1905+#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */
1906+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
1907+#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
1908+#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
1909+#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
1910+#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
1911+#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */
1912+
1913+/******************** Bit definition for ADC_OFR1 register ******************/
1914+#define ADC_OFR1_OFFSET1_Pos (0U)
1915+#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */
1916+#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */
1917+
1918+#define ADC_OFR1_OFFSETPOS_Pos (24U)
1919+#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */
1920+#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */
1921+#define ADC_OFR1_SATEN_Pos (25U)
1922+#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */
1923+#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */
1924+
1925+#define ADC_OFR1_OFFSET1_CH_Pos (26U)
1926+#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
1927+#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */
1928+#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
1929+#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
1930+#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
1931+#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
1932+#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
1933+
1934+#define ADC_OFR1_OFFSET1_EN_Pos (31U)
1935+#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */
1936+#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */
1937+
1938+/******************** Bit definition for ADC_OFR2 register ******************/
1939+#define ADC_OFR2_OFFSET2_Pos (0U)
1940+#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */
1941+#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */
1942+
1943+#define ADC_OFR2_OFFSETPOS_Pos (24U)
1944+#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */
1945+#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */
1946+#define ADC_OFR2_SATEN_Pos (25U)
1947+#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */
1948+#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */
1949+
1950+#define ADC_OFR2_OFFSET2_CH_Pos (26U)
1951+#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
1952+#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */
1953+#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
1954+#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
1955+#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
1956+#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
1957+#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
1958+
1959+#define ADC_OFR2_OFFSET2_EN_Pos (31U)
1960+#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */
1961+#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */
1962+
1963+/******************** Bit definition for ADC_OFR3 register ******************/
1964+#define ADC_OFR3_OFFSET3_Pos (0U)
1965+#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */
1966+#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */
1967+
1968+#define ADC_OFR3_OFFSETPOS_Pos (24U)
1969+#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */
1970+#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */
1971+#define ADC_OFR3_SATEN_Pos (25U)
1972+#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */
1973+#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */
1974+
1975+#define ADC_OFR3_OFFSET3_CH_Pos (26U)
1976+#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
1977+#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */
1978+#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
1979+#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
1980+#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
1981+#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
1982+#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
1983+
1984+#define ADC_OFR3_OFFSET3_EN_Pos (31U)
1985+#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */
1986+#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */
1987+
1988+/******************** Bit definition for ADC_OFR4 register ******************/
1989+#define ADC_OFR4_OFFSET4_Pos (0U)
1990+#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */
1991+#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */
1992+
1993+#define ADC_OFR4_OFFSETPOS_Pos (24U)
1994+#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */
1995+#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */
1996+#define ADC_OFR4_SATEN_Pos (25U)
1997+#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */
1998+#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */
1999+
2000+#define ADC_OFR4_OFFSET4_CH_Pos (26U)
2001+#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
2002+#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */
2003+#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
2004+#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
2005+#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
2006+#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
2007+#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
2008+
2009+#define ADC_OFR4_OFFSET4_EN_Pos (31U)
2010+#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */
2011+#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */
2012+
2013+/******************** Bit definition for ADC_JDR1 register ******************/
2014+#define ADC_JDR1_JDATA_Pos (0U)
2015+#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
2016+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
2017+
2018+/******************** Bit definition for ADC_JDR2 register ******************/
2019+#define ADC_JDR2_JDATA_Pos (0U)
2020+#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
2021+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
2022+
2023+/******************** Bit definition for ADC_JDR3 register ******************/
2024+#define ADC_JDR3_JDATA_Pos (0U)
2025+#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
2026+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
2027+
2028+/******************** Bit definition for ADC_JDR4 register ******************/
2029+#define ADC_JDR4_JDATA_Pos (0U)
2030+#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
2031+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
2032+
2033+/******************** Bit definition for ADC_AWD2CR register ****************/
2034+#define ADC_AWD2CR_AWD2CH_Pos (0U)
2035+#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
2036+#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */
2037+#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
2038+#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
2039+#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
2040+#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
2041+#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
2042+#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
2043+#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
2044+#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
2045+#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
2046+#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
2047+#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
2048+#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
2049+#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
2050+#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
2051+#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
2052+#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
2053+#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
2054+#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
2055+#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
2056+
2057+/******************** Bit definition for ADC_AWD3CR register ****************/
2058+#define ADC_AWD3CR_AWD3CH_Pos (0U)
2059+#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
2060+#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */
2061+#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
2062+#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
2063+#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
2064+#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
2065+#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
2066+#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
2067+#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
2068+#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
2069+#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
2070+#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
2071+#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
2072+#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
2073+#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
2074+#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
2075+#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
2076+#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
2077+#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
2078+#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
2079+#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
2080+
2081+/******************** Bit definition for ADC_DIFSEL register ****************/
2082+#define ADC_DIFSEL_DIFSEL_Pos (0U)
2083+#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */
2084+#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */
2085+#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
2086+#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
2087+#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
2088+#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
2089+#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
2090+#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
2091+#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
2092+#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
2093+#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
2094+#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
2095+#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
2096+#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
2097+#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
2098+#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
2099+#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
2100+#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
2101+#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
2102+#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
2103+#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
2104+
2105+/******************** Bit definition for ADC_CALFACT register ***************/
2106+#define ADC_CALFACT_CALFACT_S_Pos (0U)
2107+#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */
2108+#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */
2109+#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
2110+#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
2111+#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
2112+#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
2113+#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
2114+#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
2115+#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */
2116+
2117+#define ADC_CALFACT_CALFACT_D_Pos (16U)
2118+#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */
2119+#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */
2120+#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
2121+#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
2122+#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
2123+#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
2124+#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
2125+#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
2126+#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */
2127+
2128+/******************** Bit definition for ADC_GCOMP register *****************/
2129+#define ADC_GCOMP_GCOMPCOEFF_Pos (0U)
2130+#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */
2131+#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Gain Compensation Coefficient */
2132+
2133+/************************* ADC Common registers *****************************/
2134+/******************** Bit definition for ADC_CSR register *******************/
2135+#define ADC_CSR_ADRDY_MST_Pos (0U)
2136+#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
2137+#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */
2138+#define ADC_CSR_EOSMP_MST_Pos (1U)
2139+#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
2140+#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */
2141+#define ADC_CSR_EOC_MST_Pos (2U)
2142+#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */
2143+#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */
2144+#define ADC_CSR_EOS_MST_Pos (3U)
2145+#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */
2146+#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */
2147+#define ADC_CSR_OVR_MST_Pos (4U)
2148+#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */
2149+#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */
2150+#define ADC_CSR_JEOC_MST_Pos (5U)
2151+#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
2152+#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */
2153+#define ADC_CSR_JEOS_MST_Pos (6U)
2154+#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
2155+#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */
2156+#define ADC_CSR_AWD1_MST_Pos (7U)
2157+#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
2158+#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */
2159+#define ADC_CSR_AWD2_MST_Pos (8U)
2160+#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
2161+#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */
2162+#define ADC_CSR_AWD3_MST_Pos (9U)
2163+#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
2164+#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */
2165+#define ADC_CSR_JQOVF_MST_Pos (10U)
2166+#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
2167+#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */
2168+
2169+#define ADC_CSR_ADRDY_SLV_Pos (16U)
2170+#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
2171+#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */
2172+#define ADC_CSR_EOSMP_SLV_Pos (17U)
2173+#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
2174+#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */
2175+#define ADC_CSR_EOC_SLV_Pos (18U)
2176+#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
2177+#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */
2178+#define ADC_CSR_EOS_SLV_Pos (19U)
2179+#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
2180+#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */
2181+#define ADC_CSR_OVR_SLV_Pos (20U)
2182+#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
2183+#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */
2184+#define ADC_CSR_JEOC_SLV_Pos (21U)
2185+#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
2186+#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */
2187+#define ADC_CSR_JEOS_SLV_Pos (22U)
2188+#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */
2189+#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */
2190+#define ADC_CSR_AWD1_SLV_Pos (23U)
2191+#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
2192+#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */
2193+#define ADC_CSR_AWD2_SLV_Pos (24U)
2194+#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
2195+#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */
2196+#define ADC_CSR_AWD3_SLV_Pos (25U)
2197+#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
2198+#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */
2199+#define ADC_CSR_JQOVF_SLV_Pos (26U)
2200+#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
2201+#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */
2202+
2203+/******************** Bit definition for ADC_CCR register *******************/
2204+#define ADC_CCR_DUAL_Pos (0U)
2205+#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */
2206+#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */
2207+#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */
2208+#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */
2209+#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */
2210+#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */
2211+#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */
2212+
2213+#define ADC_CCR_DELAY_Pos (8U)
2214+#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
2215+#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */
2216+#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
2217+#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
2218+#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
2219+#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
2220+
2221+#define ADC_CCR_DMACFG_Pos (13U)
2222+#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */
2223+#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */
2224+
2225+#define ADC_CCR_MDMA_Pos (14U)
2226+#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */
2227+#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */
2228+#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */
2229+#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */
2230+
2231+#define ADC_CCR_CKMODE_Pos (16U)
2232+#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
2233+#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
2234+#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
2235+#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
2236+
2237+#define ADC_CCR_PRESC_Pos (18U)
2238+#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
2239+#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */
2240+#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
2241+#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
2242+#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
2243+#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
2244+
2245+#define ADC_CCR_VREFEN_Pos (22U)
2246+#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
2247+#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
2248+#define ADC_CCR_VSENSESEL_Pos (23U)
2249+#define ADC_CCR_VSENSESEL_Msk (0x1UL << ADC_CCR_VSENSESEL_Pos) /*!< 0x00800000 */
2250+#define ADC_CCR_VSENSESEL ADC_CCR_VSENSESEL_Msk /*!< ADC internal path to temperature sensor enable */
2251+#define ADC_CCR_VBATSEL_Pos (24U)
2252+#define ADC_CCR_VBATSEL_Msk (0x1UL << ADC_CCR_VBATSEL_Pos) /*!< 0x01000000 */
2253+#define ADC_CCR_VBATSEL ADC_CCR_VBATSEL_Msk /*!< ADC internal path to battery voltage enable */
2254+
2255+/******************** Bit definition for ADC_CDR register *******************/
2256+#define ADC_CDR_RDATA_MST_Pos (0U)
2257+#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
2258+#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */
2259+
2260+#define ADC_CDR_RDATA_SLV_Pos (16U)
2261+#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
2262+#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */
2263+
2264+
2265+/******************************************************************************/
2266+/* */
2267+/* Analog Comparators (COMP) */
2268+/* */
2269+/******************************************************************************/
2270+/********************** Bit definition for COMP_CSR register ****************/
2271+#define COMP_CSR_EN_Pos (0U)
2272+#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */
2273+#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */
2274+
2275+#define COMP_CSR_INMSEL_Pos (4U)
2276+#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */
2277+#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */
2278+#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */
2279+#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */
2280+#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */
2281+#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */
2282+
2283+#define COMP_CSR_INPSEL_Pos (8U)
2284+#define COMP_CSR_INPSEL_Msk (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */
2285+#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */
2286+
2287+#define COMP_CSR_POLARITY_Pos (15U)
2288+#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */
2289+#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */
2290+
2291+#define COMP_CSR_HYST_Pos (16U)
2292+#define COMP_CSR_HYST_Msk (0x7UL << COMP_CSR_HYST_Pos) /*!< 0x00070000 */
2293+#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */
2294+#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */
2295+#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */
2296+#define COMP_CSR_HYST_2 (0x4UL << COMP_CSR_HYST_Pos) /*!< 0x00040000 */
2297+
2298+#define COMP_CSR_BLANKING_Pos (19U)
2299+#define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x00380000 */
2300+#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */
2301+#define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
2302+#define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
2303+#define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */
2304+
2305+#define COMP_CSR_BRGEN_Pos (22U)
2306+#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */
2307+#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator scaler bridge enable */
2308+
2309+#define COMP_CSR_SCALEN_Pos (23U)
2310+#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */
2311+#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator voltage scaler enable */
2312+
2313+#define COMP_CSR_VALUE_Pos (30U)
2314+#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */
2315+#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */
2316+
2317+#define COMP_CSR_LOCK_Pos (31U)
2318+#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */
2319+#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */
2320+
2321+/******************************************************************************/
2322+/* */
2323+/* CORDIC calculation unit */
2324+/* */
2325+/******************************************************************************/
2326+/******************* Bit definition for CORDIC_CSR register *****************/
2327+#define CORDIC_CSR_FUNC_Pos (0U)
2328+#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */
2329+#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */
2330+#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */
2331+#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */
2332+#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */
2333+#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */
2334+#define CORDIC_CSR_PRECISION_Pos (4U)
2335+#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */
2336+#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */
2337+#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */
2338+#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */
2339+#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */
2340+#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */
2341+#define CORDIC_CSR_SCALE_Pos (8U)
2342+#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */
2343+#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */
2344+#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */
2345+#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */
2346+#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */
2347+#define CORDIC_CSR_IEN_Pos (16U)
2348+#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */
2349+#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */
2350+#define CORDIC_CSR_DMAREN_Pos (17U)
2351+#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */
2352+#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */
2353+#define CORDIC_CSR_DMAWEN_Pos (18U)
2354+#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */
2355+#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */
2356+#define CORDIC_CSR_NRES_Pos (19U)
2357+#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */
2358+#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */
2359+#define CORDIC_CSR_NARGS_Pos (20U)
2360+#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */
2361+#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */
2362+#define CORDIC_CSR_RESSIZE_Pos (21U)
2363+#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */
2364+#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */
2365+#define CORDIC_CSR_ARGSIZE_Pos (22U)
2366+#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */
2367+#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */
2368+#define CORDIC_CSR_RRDY_Pos (31U)
2369+#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */
2370+#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */
2371+
2372+/******************* Bit definition for CORDIC_WDATA register ***************/
2373+#define CORDIC_WDATA_ARG_Pos (0U)
2374+#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */
2375+#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */
2376+
2377+/******************* Bit definition for CORDIC_RDATA register ***************/
2378+#define CORDIC_RDATA_RES_Pos (0U)
2379+#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */
2380+#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */
2381+
2382+/******************************************************************************/
2383+/* */
2384+/* CRC calculation unit */
2385+/* */
2386+/******************************************************************************/
2387+/******************* Bit definition for CRC_DR register *********************/
2388+#define CRC_DR_DR_Pos (0U)
2389+#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
2390+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
2391+
2392+/******************* Bit definition for CRC_IDR register ********************/
2393+#define CRC_IDR_IDR_Pos (0U)
2394+#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
2395+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */
2396+
2397+/******************** Bit definition for CRC_CR register ********************/
2398+#define CRC_CR_RESET_Pos (0U)
2399+#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
2400+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
2401+#define CRC_CR_POLYSIZE_Pos (3U)
2402+#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
2403+#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
2404+#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
2405+#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
2406+#define CRC_CR_REV_IN_Pos (5U)
2407+#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
2408+#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
2409+#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
2410+#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
2411+#define CRC_CR_REV_OUT_Pos (7U)
2412+#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
2413+#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
2414+
2415+/******************* Bit definition for CRC_INIT register *******************/
2416+#define CRC_INIT_INIT_Pos (0U)
2417+#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
2418+#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
2419+
2420+/******************* Bit definition for CRC_POL register ********************/
2421+#define CRC_POL_POL_Pos (0U)
2422+#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
2423+#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
2424+
2425+/******************************************************************************/
2426+/* */
2427+/* CRS Clock Recovery System */
2428+/******************************************************************************/
2429+
2430+/******************* Bit definition for CRS_CR register *********************/
2431+#define CRS_CR_SYNCOKIE_Pos (0U)
2432+#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
2433+#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */
2434+#define CRS_CR_SYNCWARNIE_Pos (1U)
2435+#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
2436+#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */
2437+#define CRS_CR_ERRIE_Pos (2U)
2438+#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
2439+#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */
2440+#define CRS_CR_ESYNCIE_Pos (3U)
2441+#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
2442+#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */
2443+#define CRS_CR_CEN_Pos (5U)
2444+#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */
2445+#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */
2446+#define CRS_CR_AUTOTRIMEN_Pos (6U)
2447+#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
2448+#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */
2449+#define CRS_CR_SWSYNC_Pos (7U)
2450+#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
2451+#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
2452+#define CRS_CR_TRIM_Pos (8U)
2453+#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */
2454+#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
2455+
2456+/******************* Bit definition for CRS_CFGR register *********************/
2457+#define CRS_CFGR_RELOAD_Pos (0U)
2458+#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
2459+#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */
2460+#define CRS_CFGR_FELIM_Pos (16U)
2461+#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
2462+#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */
2463+
2464+#define CRS_CFGR_SYNCDIV_Pos (24U)
2465+#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
2466+#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */
2467+#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
2468+#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
2469+#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
2470+
2471+#define CRS_CFGR_SYNCSRC_Pos (28U)
2472+#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
2473+#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */
2474+#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
2475+#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
2476+
2477+#define CRS_CFGR_SYNCPOL_Pos (31U)
2478+#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
2479+#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */
2480+
2481+/******************* Bit definition for CRS_ISR register *********************/
2482+#define CRS_ISR_SYNCOKF_Pos (0U)
2483+#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
2484+#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */
2485+#define CRS_ISR_SYNCWARNF_Pos (1U)
2486+#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
2487+#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */
2488+#define CRS_ISR_ERRF_Pos (2U)
2489+#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
2490+#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */
2491+#define CRS_ISR_ESYNCF_Pos (3U)
2492+#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
2493+#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */
2494+#define CRS_ISR_SYNCERR_Pos (8U)
2495+#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
2496+#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */
2497+#define CRS_ISR_SYNCMISS_Pos (9U)
2498+#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
2499+#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */
2500+#define CRS_ISR_TRIMOVF_Pos (10U)
2501+#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
2502+#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */
2503+#define CRS_ISR_FEDIR_Pos (15U)
2504+#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
2505+#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */
2506+#define CRS_ISR_FECAP_Pos (16U)
2507+#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
2508+#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */
2509+
2510+/******************* Bit definition for CRS_ICR register *********************/
2511+#define CRS_ICR_SYNCOKC_Pos (0U)
2512+#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
2513+#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */
2514+#define CRS_ICR_SYNCWARNC_Pos (1U)
2515+#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
2516+#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */
2517+#define CRS_ICR_ERRC_Pos (2U)
2518+#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
2519+#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */
2520+#define CRS_ICR_ESYNCC_Pos (3U)
2521+#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
2522+#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */
2523+
2524+/******************************************************************************/
2525+/* */
2526+/* Digital to Analog Converter */
2527+/* */
2528+/******************************************************************************/
2529+/*
2530+ * @brief Specific device feature definitions (not present on all devices in the STM32G4 series)
2531+ */
2532+#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */
2533+
2534+/******************** Bit definition for DAC_CR register ********************/
2535+#define DAC_CR_EN1_Pos (0U)
2536+#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */
2537+#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
2538+#define DAC_CR_TEN1_Pos (1U)
2539+#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000002 */
2540+#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
2541+
2542+#define DAC_CR_TSEL1_Pos (2U)
2543+#define DAC_CR_TSEL1_Msk (0xFUL << DAC_CR_TSEL1_Pos) /*!< 0x0000003C */
2544+#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[3:0] (DAC channel1 Trigger selection) */
2545+#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */
2546+#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
2547+#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
2548+#define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
2549+
2550+#define DAC_CR_WAVE1_Pos (6U)
2551+#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
2552+#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
2553+#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
2554+#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
2555+
2556+#define DAC_CR_MAMP1_Pos (8U)
2557+#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
2558+#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
2559+#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
2560+#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
2561+#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
2562+#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
2563+
2564+#define DAC_CR_DMAEN1_Pos (12U)
2565+#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
2566+#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
2567+#define DAC_CR_DMAUDRIE1_Pos (13U)
2568+#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
2569+#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/
2570+#define DAC_CR_CEN1_Pos (14U)
2571+#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
2572+#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/
2573+
2574+#define DAC_CR_HFSEL_Pos (15U)
2575+#define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */
2576+#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!<DAC channel 1 and 2 high frequency mode enable >*/
2577+
2578+#define DAC_CR_EN2_Pos (16U)
2579+#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */
2580+#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
2581+#define DAC_CR_TEN2_Pos (17U)
2582+#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00020000 */
2583+#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
2584+
2585+#define DAC_CR_TSEL2_Pos (18U)
2586+#define DAC_CR_TSEL2_Msk (0xFUL << DAC_CR_TSEL2_Pos) /*!< 0x003C0000 */
2587+#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[3:0] (DAC channel2 Trigger selection) */
2588+#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00040000 */
2589+#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
2590+#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
2591+#define DAC_CR_TSEL2_3 (0x8UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
2592+
2593+#define DAC_CR_WAVE2_Pos (22U)
2594+#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
2595+#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
2596+#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
2597+#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
2598+
2599+#define DAC_CR_MAMP2_Pos (24U)
2600+#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
2601+#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
2602+#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
2603+#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
2604+#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
2605+#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
2606+
2607+#define DAC_CR_DMAEN2_Pos (28U)
2608+#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
2609+#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
2610+#define DAC_CR_DMAUDRIE2_Pos (29U)
2611+#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
2612+#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/
2613+#define DAC_CR_CEN2_Pos (30U)
2614+#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
2615+#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/
2616+
2617+/***************** Bit definition for DAC_SWTRIGR register ******************/
2618+#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
2619+#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
2620+#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
2621+#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
2622+#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
2623+#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
2624+#define DAC_SWTRIGR_SWTRIGB1_Pos (16U)
2625+#define DAC_SWTRIGR_SWTRIGB1_Msk (0x1UL << DAC_SWTRIGR_SWTRIGB1_Pos) /*!< 0x00010000 */
2626+#define DAC_SWTRIGR_SWTRIGB1 DAC_SWTRIGR_SWTRIGB1_Msk /*!<DAC channel1 software trigger B */
2627+#define DAC_SWTRIGR_SWTRIGB2_Pos (17U)
2628+#define DAC_SWTRIGR_SWTRIGB2_Msk (0x1UL << DAC_SWTRIGR_SWTRIGB2_Pos) /*!< 0x00020000 */
2629+#define DAC_SWTRIGR_SWTRIGB2 DAC_SWTRIGR_SWTRIGB2_Msk /*!<DAC channel2 software trigger B */
2630+
2631+/***************** Bit definition for DAC_DHR12R1 register ******************/
2632+#define DAC_DHR12R1_DACC1DHR_Pos (0U)
2633+#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
2634+#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
2635+#define DAC_DHR12R1_DACC1DHRB_Pos (16U)
2636+#define DAC_DHR12R1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x0FFF0000 */
2637+#define DAC_DHR12R1_DACC1DHRB DAC_DHR12R1_DACC1DHRB_Msk /*!<DAC channel1 12-bit Right-aligned data B */
2638+
2639+/***************** Bit definition for DAC_DHR12L1 register ******************/
2640+#define DAC_DHR12L1_DACC1DHR_Pos (4U)
2641+#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
2642+#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
2643+#define DAC_DHR12L1_DACC1DHRB_Pos (20U)
2644+#define DAC_DHR12L1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0xFFF00000 */
2645+#define DAC_DHR12L1_DACC1DHRB DAC_DHR12L1_DACC1DHRB_Msk /*!<DAC channel1 12-bit Left aligned data B */
2646+
2647+/****************** Bit definition for DAC_DHR8R1 register ******************/
2648+#define DAC_DHR8R1_DACC1DHR_Pos (0U)
2649+#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
2650+#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
2651+#define DAC_DHR8R1_DACC1DHRB_Pos (8U)
2652+#define DAC_DHR8R1_DACC1DHRB_Msk (0xFFUL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x0000FF00 */
2653+#define DAC_DHR8R1_DACC1DHRB DAC_DHR8R1_DACC1DHRB_Msk /*!<DAC channel1 8-bit Right aligned data B */
2654+
2655+/***************** Bit definition for DAC_DHR12R2 register ******************/
2656+#define DAC_DHR12R2_DACC2DHR_Pos (0U)
2657+#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
2658+#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
2659+#define DAC_DHR12R2_DACC2DHRB_Pos (16U)
2660+#define DAC_DHR12R2_DACC2DHRB_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHRB_Pos) /*!< 0x0FFF0000 */
2661+#define DAC_DHR12R2_DACC2DHRB DAC_DHR12R2_DACC2DHRB_Msk /*!<DAC channel2 12-bit Right-aligned data B */
2662+
2663+/***************** Bit definition for DAC_DHR12L2 register ******************/
2664+#define DAC_DHR12L2_DACC2DHR_Pos (4U)
2665+#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
2666+#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
2667+#define DAC_DHR12L2_DACC2DHRB_Pos (20U)
2668+#define DAC_DHR12L2_DACC2DHRB_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHRB_Pos) /*!< 0xFFF00000 */
2669+#define DAC_DHR12L2_DACC2DHRB DAC_DHR12L2_DACC2DHRB_Msk /*!<DAC channel2 12-bit Left aligned data B */
2670+
2671+/****************** Bit definition for DAC_DHR8R2 register ******************/
2672+#define DAC_DHR8R2_DACC2DHR_Pos (0U)
2673+#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
2674+#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
2675+#define DAC_DHR8R2_DACC2DHRB_Pos (8U)
2676+#define DAC_DHR8R2_DACC2DHRB_Msk (0xFFUL << DAC_DHR8R2_DACC2DHRB_Pos) /*!< 0x0000FF00 */
2677+#define DAC_DHR8R2_DACC2DHRB DAC_DHR8R2_DACC2DHRB_Msk /*!<DAC channel2 8-bit Right aligned data B */
2678+
2679+/***************** Bit definition for DAC_DHR12RD register ******************/
2680+#define DAC_DHR12RD_DACC1DHR_Pos (0U)
2681+#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
2682+#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
2683+#define DAC_DHR12RD_DACC2DHR_Pos (16U)
2684+#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
2685+#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
2686+
2687+/***************** Bit definition for DAC_DHR12LD register ******************/
2688+#define DAC_DHR12LD_DACC1DHR_Pos (4U)
2689+#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
2690+#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
2691+#define DAC_DHR12LD_DACC2DHR_Pos (20U)
2692+#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
2693+#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
2694+
2695+/****************** Bit definition for DAC_DHR8RD register ******************/
2696+#define DAC_DHR8RD_DACC1DHR_Pos (0U)
2697+#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
2698+#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
2699+#define DAC_DHR8RD_DACC2DHR_Pos (8U)
2700+#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
2701+#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
2702+
2703+/******************* Bit definition for DAC_DOR1 register *******************/
2704+#define DAC_DOR1_DACC1DOR_Pos (0U)
2705+#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
2706+#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
2707+#define DAC_DOR1_DACC1DORB_Pos (16U)
2708+#define DAC_DOR1_DACC1DORB_Msk (0xFFFUL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x0FFF0000 */
2709+#define DAC_DOR1_DACC1DORB DAC_DOR1_DACC1DORB_Msk /*!<DAC channel1 data output B */
2710+
2711+/******************* Bit definition for DAC_DOR2 register *******************/
2712+#define DAC_DOR2_DACC2DOR_Pos (0U)
2713+#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
2714+#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
2715+#define DAC_DOR2_DACC2DORB_Pos (16U)
2716+#define DAC_DOR2_DACC2DORB_Msk (0xFFFUL << DAC_DOR2_DACC2DORB_Pos) /*!< 0x0FFF0000 */
2717+#define DAC_DOR2_DACC2DORB DAC_DOR2_DACC2DORB_Msk /*!<DAC channel2 data output B */
2718+
2719+/******************** Bit definition for DAC_SR register ********************/
2720+#define DAC_SR_DAC1RDY_Pos (11U)
2721+#define DAC_SR_DAC1RDY_Msk (0x1UL << DAC_SR_DAC1RDY_Pos) /*!< 0x00000800 */
2722+#define DAC_SR_DAC1RDY DAC_SR_DAC1RDY_Msk /*!<DAC channel 1 ready status bit */
2723+#define DAC_SR_DORSTAT1_Pos (12U)
2724+#define DAC_SR_DORSTAT1_Msk (0x1UL << DAC_SR_DORSTAT1_Pos) /*!< 0x00001000 */
2725+#define DAC_SR_DORSTAT1 DAC_SR_DORSTAT1_Msk /*!<DAC channel 1 output register status bit */
2726+#define DAC_SR_DMAUDR1_Pos (13U)
2727+#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
2728+#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
2729+#define DAC_SR_CAL_FLAG1_Pos (14U)
2730+#define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */
2731+#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */
2732+#define DAC_SR_BWST1_Pos (15U)
2733+#define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos) /*!< 0x00008000 */
2734+#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
2735+
2736+#define DAC_SR_DAC2RDY_Pos (27U)
2737+#define DAC_SR_DAC2RDY_Msk (0x1UL << DAC_SR_DAC2RDY_Pos) /*!< 0x08000000 */
2738+#define DAC_SR_DAC2RDY DAC_SR_DAC2RDY_Msk /*!<DAC channel 2 ready status bit */
2739+#define DAC_SR_DORSTAT2_Pos (28U)
2740+#define DAC_SR_DORSTAT2_Msk (0x1UL << DAC_SR_DORSTAT2_Pos) /*!< 0x10000000 */
2741+#define DAC_SR_DORSTAT2 DAC_SR_DORSTAT2_Msk /*!<DAC channel 2 output register status bit */
2742+#define DAC_SR_DMAUDR2_Pos (29U)
2743+#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
2744+#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
2745+#define DAC_SR_CAL_FLAG2_Pos (30U)
2746+#define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */
2747+#define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */
2748+#define DAC_SR_BWST2_Pos (31U)
2749+#define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos) /*!< 0x80000000 */
2750+#define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */
2751+
2752+/******************* Bit definition for DAC_CCR register ********************/
2753+#define DAC_CCR_OTRIM1_Pos (0U)
2754+#define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */
2755+#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */
2756+#define DAC_CCR_OTRIM2_Pos (16U)
2757+#define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */
2758+#define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */
2759+
2760+/******************* Bit definition for DAC_MCR register *******************/
2761+#define DAC_MCR_MODE1_Pos (0U)
2762+#define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */
2763+#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */
2764+#define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */
2765+#define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */
2766+#define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */
2767+
2768+#define DAC_MCR_DMADOUBLE1_Pos (8U)
2769+#define DAC_MCR_DMADOUBLE1_Msk (0x1UL << DAC_MCR_DMADOUBLE1_Pos) /*!< 0x00000100 */
2770+#define DAC_MCR_DMADOUBLE1 DAC_MCR_DMADOUBLE1_Msk /*!<DAC Channel 1 DMA double data mode */
2771+
2772+#define DAC_MCR_SINFORMAT1_Pos (9U)
2773+#define DAC_MCR_SINFORMAT1_Msk (0x1UL << DAC_MCR_SINFORMAT1_Pos) /*!< 0x00000200 */
2774+#define DAC_MCR_SINFORMAT1 DAC_MCR_SINFORMAT1_Msk /*!<DAC Channel 1 enable signed format */
2775+
2776+#define DAC_MCR_HFSEL_Pos (14U)
2777+#define DAC_MCR_HFSEL_Msk (0x3UL << DAC_MCR_HFSEL_Pos) /*!< 0x0000C000 */
2778+#define DAC_MCR_HFSEL DAC_MCR_HFSEL_Msk /*!<HFSEL[1:0] (High Frequency interface mode selection) */
2779+#define DAC_MCR_HFSEL_0 (0x1UL << DAC_MCR_HFSEL_Pos) /*!< 0x00004000 */
2780+#define DAC_MCR_HFSEL_1 (0x2UL << DAC_MCR_HFSEL_Pos) /*!< 0x00008000 */
2781+
2782+#define DAC_MCR_MODE2_Pos (16U)
2783+#define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */
2784+#define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */
2785+#define DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */
2786+#define DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */
2787+#define DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */
2788+
2789+#define DAC_MCR_DMADOUBLE2_Pos (24U)
2790+#define DAC_MCR_DMADOUBLE2_Msk (0x1UL << DAC_MCR_DMADOUBLE2_Pos) /*!< 0x01000000 */
2791+#define DAC_MCR_DMADOUBLE2 DAC_MCR_DMADOUBLE2_Msk /*!<DAC Channel 2 DMA double data mode */
2792+
2793+#define DAC_MCR_SINFORMAT2_Pos (25U)
2794+#define DAC_MCR_SINFORMAT2_Msk (0x1UL << DAC_MCR_SINFORMAT2_Pos) /*!< 0x02000000 */
2795+#define DAC_MCR_SINFORMAT2 DAC_MCR_SINFORMAT2_Msk /*!<DAC Channel 2 enable signed format */
2796+
2797+/****************** Bit definition for DAC_SHSR1 register ******************/
2798+#define DAC_SHSR1_TSAMPLE1_Pos (0U)
2799+#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */
2800+#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */
2801+
2802+/****************** Bit definition for DAC_SHSR2 register ******************/
2803+#define DAC_SHSR2_TSAMPLE2_Pos (0U)
2804+#define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */
2805+#define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!<DAC channel2 sample time */
2806+
2807+/****************** Bit definition for DAC_SHHR register ******************/
2808+#define DAC_SHHR_THOLD1_Pos (0U)
2809+#define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */
2810+#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */
2811+#define DAC_SHHR_THOLD2_Pos (16U)
2812+#define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */
2813+#define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */
2814+
2815+/****************** Bit definition for DAC_SHRR register ******************/
2816+#define DAC_SHRR_TREFRESH1_Pos (0U)
2817+#define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */
2818+#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */
2819+#define DAC_SHRR_TREFRESH2_Pos (16U)
2820+#define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
2821+#define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */
2822+
2823+/****************** Bit definition for DAC_STR1 register ******************/
2824+#define DAC_STR1_STRSTDATA1_Pos (0U)
2825+#define DAC_STR1_STRSTDATA1_Msk (0xFFFUL << DAC_STR1_STRSTDATA1_Pos) /*!< 0x00000FFF */
2826+#define DAC_STR1_STRSTDATA1 DAC_STR1_STRSTDATA1_Msk /*!<DAC Channel 1 Sawtooth starting value */
2827+#define DAC_STR1_STDIR1_Pos (12U)
2828+#define DAC_STR1_STDIR1_Msk (0x1UL << DAC_STR1_STDIR1_Pos) /*!< 0x00001000 */
2829+#define DAC_STR1_STDIR1 DAC_STR1_STDIR1_Msk /*!<DAC Channel 1 Sawtooth direction setting */
2830+
2831+#define DAC_STR1_STINCDATA1_Pos (16U)
2832+#define DAC_STR1_STINCDATA1_Msk (0xFFFFUL << DAC_STR1_STINCDATA1_Pos) /*!< 0xFFFF0000 */
2833+#define DAC_STR1_STINCDATA1 DAC_STR1_STINCDATA1_Msk /*!<DAC Channel 1 Sawtooth increment value (12.4 bit format) */
2834+
2835+/****************** Bit definition for DAC_STR2 register ******************/
2836+#define DAC_STR2_STRSTDATA2_Pos (0U)
2837+#define DAC_STR2_STRSTDATA2_Msk (0xFFFUL << DAC_STR2_STRSTDATA2_Pos) /*!< 0x00000FFF */
2838+#define DAC_STR2_STRSTDATA2 DAC_STR2_STRSTDATA2_Msk /*!<DAC Channel 2 Sawtooth starting value */
2839+#define DAC_STR2_STDIR2_Pos (12U)
2840+#define DAC_STR2_STDIR2_Msk (0x1UL << DAC_STR2_STDIR2_Pos) /*!< 0x00001000 */
2841+#define DAC_STR2_STDIR2 DAC_STR2_STDIR2_Msk /*!<DAC Channel 2 Sawtooth direction setting */
2842+
2843+#define DAC_STR2_STINCDATA2_Pos (16U)
2844+#define DAC_STR2_STINCDATA2_Msk (0xFFFFUL << DAC_STR2_STINCDATA2_Pos) /*!< 0xFFFF0000 */
2845+#define DAC_STR2_STINCDATA2 DAC_STR2_STINCDATA2_Msk /*!<DAC Channel 2 Sawtooth increment value (12.4 bit format) */
2846+
2847+/****************** Bit definition for DAC_STMODR register ****************/
2848+#define DAC_STMODR_STRSTTRIGSEL1_Pos (0U)
2849+#define DAC_STMODR_STRSTTRIGSEL1_Msk (0xFUL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x0000000F */
2850+#define DAC_STMODR_STRSTTRIGSEL1 DAC_STMODR_STRSTTRIGSEL1_Msk /*!<STRSTTRIGSEL1[3:0] (DAC Channel 1 Sawtooth Increment trigger selection) */
2851+#define DAC_STMODR_STRSTTRIGSEL1_0 (0x1UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000001 */
2852+#define DAC_STMODR_STRSTTRIGSEL1_1 (0x2UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000002 */
2853+#define DAC_STMODR_STRSTTRIGSEL1_2 (0x4UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000004 */
2854+#define DAC_STMODR_STRSTTRIGSEL1_3 (0x8UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000008 */
2855+
2856+#define DAC_STMODR_STINCTRIGSEL1_Pos (8U)
2857+#define DAC_STMODR_STINCTRIGSEL1_Msk (0xFUL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x0000000F */
2858+#define DAC_STMODR_STINCTRIGSEL1 DAC_STMODR_STINCTRIGSEL1_Msk /*!<STINCTRIGSEL1[3:0] (DAC Channel 1 Sawtooth Increment trigger selection) */
2859+#define DAC_STMODR_STINCTRIGSEL1_0 (0x1UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000001 */
2860+#define DAC_STMODR_STINCTRIGSEL1_1 (0x2UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000002 */
2861+#define DAC_STMODR_STINCTRIGSEL1_2 (0x4UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000004 */
2862+#define DAC_STMODR_STINCTRIGSEL1_3 (0x8UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000008 */
2863+
2864+#define DAC_STMODR_STRSTTRIGSEL2_Pos (16U)
2865+#define DAC_STMODR_STRSTTRIGSEL2_Msk (0xFUL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x0000000F */
2866+#define DAC_STMODR_STRSTTRIGSEL2 DAC_STMODR_STRSTTRIGSEL2_Msk /*!<STRSTTRIGSEL2[3:0] (DAC Channel 2 Sawtooth Increment trigger selection) */
2867+#define DAC_STMODR_STRSTTRIGSEL2_0 (0x1UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000001 */
2868+#define DAC_STMODR_STRSTTRIGSEL2_1 (0x2UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000002 */
2869+#define DAC_STMODR_STRSTTRIGSEL2_2 (0x4UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000004 */
2870+#define DAC_STMODR_STRSTTRIGSEL2_3 (0x8UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000008 */
2871+
2872+#define DAC_STMODR_STINCTRIGSEL2_Pos (24U)
2873+#define DAC_STMODR_STINCTRIGSEL2_Msk (0xFUL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x0000000F */
2874+#define DAC_STMODR_STINCTRIGSEL2 DAC_STMODR_STINCTRIGSEL2_Msk /*!<STINCTRIGSEL2[3:0] (DAC Channel 2 Sawtooth Increment trigger selection) */
2875+#define DAC_STMODR_STINCTRIGSEL2_0 (0x1UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000001 */
2876+#define DAC_STMODR_STINCTRIGSEL2_1 (0x2UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000002 */
2877+#define DAC_STMODR_STINCTRIGSEL2_2 (0x4UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000004 */
2878+#define DAC_STMODR_STINCTRIGSEL2_3 (0x8UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000008 */
2879+
2880+/******************************************************************************/
2881+/* */
2882+/* Debug MCU */
2883+/* */
2884+/******************************************************************************/
2885+/******************** Bit definition for DBGMCU_IDCODE register *************/
2886+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
2887+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)/*!< 0x00000FFF */
2888+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
2889+#define DBGMCU_IDCODE_REV_ID_Pos (16U)
2890+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)/*!< 0xFFFF0000 */
2891+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
2892+
2893+/******************** Bit definition for DBGMCU_CR register *****************/
2894+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
2895+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)/*!< 0x00000001 */
2896+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
2897+#define DBGMCU_CR_DBG_STOP_Pos (1U)
2898+#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)/*!< 0x00000002 */
2899+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
2900+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
2901+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)/*!< 0x00000004 */
2902+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
2903+#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
2904+#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)/*!< 0x00000020 */
2905+#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
2906+
2907+#define DBGMCU_CR_TRACE_MODE_Pos (6U)
2908+#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x000000C0 */
2909+#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
2910+#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x00000040 */
2911+#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x00000080 */
2912+
2913+/******************** Bit definition for DBGMCU_APB1FZR1 register ***********/
2914+#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U)
2915+#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)/*!< 0x00000001 */
2916+#define DBGMCU_APB1FZR1_DBG_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
2917+#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos (1U)
2918+#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos)/*!< 0x00000002 */
2919+#define DBGMCU_APB1FZR1_DBG_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk
2920+#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos (2U)
2921+#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos)/*!< 0x00000004 */
2922+#define DBGMCU_APB1FZR1_DBG_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk
2923+#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos (4U)
2924+#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos)/*!< 0x00000010 */
2925+#define DBGMCU_APB1FZR1_DBG_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
2926+#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos (5U)
2927+#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos)/*!< 0x00000020 */
2928+#define DBGMCU_APB1FZR1_DBG_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk
2929+#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos (10U)
2930+#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos)/*!< 0x00000400 */
2931+#define DBGMCU_APB1FZR1_DBG_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
2932+#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos (11U)
2933+#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos)/*!< 0x00000800 */
2934+#define DBGMCU_APB1FZR1_DBG_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
2935+#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos (12U)
2936+#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos)/*!< 0x00001000 */
2937+#define DBGMCU_APB1FZR1_DBG_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
2938+#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos (21U)
2939+#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos)/*!< 0x00200000 */
2940+#define DBGMCU_APB1FZR1_DBG_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
2941+#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos (22U)
2942+#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos)/*!< 0x00400000 */
2943+#define DBGMCU_APB1FZR1_DBG_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
2944+#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos (30U)
2945+#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos)/*!< 0x40000000 */
2946+#define DBGMCU_APB1FZR1_DBG_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk
2947+#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos (31U)
2948+#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos)/*!< 0x80000000 */
2949+#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
2950+
2951+
2952+/******************** Bit definition for DBGMCU_APB2FZ register ************/
2953+#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U)
2954+#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos)/*!< 0x00000800 */
2955+#define DBGMCU_APB2FZ_DBG_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk
2956+#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos (13U)
2957+#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos)/*!< 0x00002000 */
2958+#define DBGMCU_APB2FZ_DBG_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk
2959+#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos (16U)
2960+#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos)/*!< 0x00010000 */
2961+#define DBGMCU_APB2FZ_DBG_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk
2962+#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos (17U)
2963+#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos)/*!< 0x00020000 */
2964+#define DBGMCU_APB2FZ_DBG_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk
2965+#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos (18U)
2966+#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */
2967+#define DBGMCU_APB2FZ_DBG_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk
2968+#define DBGMCU_APB2FZ_DBG_TIM20_STOP_Pos (20U)
2969+#define DBGMCU_APB2FZ_DBG_TIM20_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM20_STOP_Pos)/*!< 0x00100000 */
2970+#define DBGMCU_APB2FZ_DBG_TIM20_STOP DBGMCU_APB2FZ_DBG_TIM20_STOP_Msk
2971+
2972+/******************************************************************************/
2973+/* */
2974+/* DMA Controller (DMA) */
2975+/* */
2976+/******************************************************************************/
2977+
2978+/******************* Bit definition for DMA_ISR register ********************/
2979+#define DMA_ISR_GIF1_Pos (0U)
2980+#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
2981+#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
2982+#define DMA_ISR_TCIF1_Pos (1U)
2983+#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
2984+#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
2985+#define DMA_ISR_HTIF1_Pos (2U)
2986+#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
2987+#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
2988+#define DMA_ISR_TEIF1_Pos (3U)
2989+#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
2990+#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
2991+#define DMA_ISR_GIF2_Pos (4U)
2992+#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
2993+#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
2994+#define DMA_ISR_TCIF2_Pos (5U)
2995+#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
2996+#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
2997+#define DMA_ISR_HTIF2_Pos (6U)
2998+#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
2999+#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
3000+#define DMA_ISR_TEIF2_Pos (7U)
3001+#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
3002+#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
3003+#define DMA_ISR_GIF3_Pos (8U)
3004+#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
3005+#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
3006+#define DMA_ISR_TCIF3_Pos (9U)
3007+#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
3008+#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
3009+#define DMA_ISR_HTIF3_Pos (10U)
3010+#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
3011+#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
3012+#define DMA_ISR_TEIF3_Pos (11U)
3013+#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
3014+#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
3015+#define DMA_ISR_GIF4_Pos (12U)
3016+#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
3017+#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
3018+#define DMA_ISR_TCIF4_Pos (13U)
3019+#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
3020+#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
3021+#define DMA_ISR_HTIF4_Pos (14U)
3022+#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
3023+#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
3024+#define DMA_ISR_TEIF4_Pos (15U)
3025+#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
3026+#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
3027+#define DMA_ISR_GIF5_Pos (16U)
3028+#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
3029+#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
3030+#define DMA_ISR_TCIF5_Pos (17U)
3031+#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
3032+#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
3033+#define DMA_ISR_HTIF5_Pos (18U)
3034+#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
3035+#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
3036+#define DMA_ISR_TEIF5_Pos (19U)
3037+#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
3038+#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
3039+#define DMA_ISR_GIF6_Pos (20U)
3040+#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
3041+#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
3042+#define DMA_ISR_TCIF6_Pos (21U)
3043+#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
3044+#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
3045+#define DMA_ISR_HTIF6_Pos (22U)
3046+#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
3047+#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
3048+#define DMA_ISR_TEIF6_Pos (23U)
3049+#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
3050+#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
3051+#define DMA_ISR_GIF7_Pos (24U)
3052+#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
3053+#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
3054+#define DMA_ISR_TCIF7_Pos (25U)
3055+#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
3056+#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
3057+#define DMA_ISR_HTIF7_Pos (26U)
3058+#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
3059+#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
3060+#define DMA_ISR_TEIF7_Pos (27U)
3061+#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
3062+#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
3063+#define DMA_ISR_GIF8_Pos (28U)
3064+#define DMA_ISR_GIF8_Msk (0x1UL << DMA_ISR_GIF8_Pos) /*!< 0x10000000 */
3065+#define DMA_ISR_GIF8 DMA_ISR_GIF8_Msk /*!< Channel 8 Global interrupt flag */
3066+#define DMA_ISR_TCIF8_Pos (29U)
3067+#define DMA_ISR_TCIF8_Msk (0x1UL << DMA_ISR_TCIF8_Pos) /*!< 0x20000000 */
3068+#define DMA_ISR_TCIF8 DMA_ISR_TCIF8_Msk /*!< Channel 8 Transfer Complete flag */
3069+#define DMA_ISR_HTIF8_Pos (30U)
3070+#define DMA_ISR_HTIF8_Msk (0x1UL << DMA_ISR_HTIF8_Pos) /*!< 0x40000000 */
3071+#define DMA_ISR_HTIF8 DMA_ISR_HTIF8_Msk /*!< Channel 8 Half Transfer flag */
3072+#define DMA_ISR_TEIF8_Pos (31U)
3073+#define DMA_ISR_TEIF8_Msk (0x1UL << DMA_ISR_TEIF8_Pos) /*!< 0x80000000 */
3074+#define DMA_ISR_TEIF8 DMA_ISR_TEIF8_Msk /*!< Channel 8 Transfer Error flag */
3075+
3076+/******************* Bit definition for DMA_IFCR register *******************/
3077+#define DMA_IFCR_CGIF1_Pos (0U)
3078+#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
3079+#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */
3080+#define DMA_IFCR_CTCIF1_Pos (1U)
3081+#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
3082+#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
3083+#define DMA_IFCR_CHTIF1_Pos (2U)
3084+#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
3085+#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
3086+#define DMA_IFCR_CTEIF1_Pos (3U)
3087+#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
3088+#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
3089+#define DMA_IFCR_CGIF2_Pos (4U)
3090+#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
3091+#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
3092+#define DMA_IFCR_CTCIF2_Pos (5U)
3093+#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
3094+#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
3095+#define DMA_IFCR_CHTIF2_Pos (6U)
3096+#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
3097+#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
3098+#define DMA_IFCR_CTEIF2_Pos (7U)
3099+#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
3100+#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
3101+#define DMA_IFCR_CGIF3_Pos (8U)
3102+#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
3103+#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
3104+#define DMA_IFCR_CTCIF3_Pos (9U)
3105+#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
3106+#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
3107+#define DMA_IFCR_CHTIF3_Pos (10U)
3108+#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
3109+#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
3110+#define DMA_IFCR_CTEIF3_Pos (11U)
3111+#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
3112+#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
3113+#define DMA_IFCR_CGIF4_Pos (12U)
3114+#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
3115+#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
3116+#define DMA_IFCR_CTCIF4_Pos (13U)
3117+#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
3118+#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
3119+#define DMA_IFCR_CHTIF4_Pos (14U)
3120+#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
3121+#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
3122+#define DMA_IFCR_CTEIF4_Pos (15U)
3123+#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
3124+#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
3125+#define DMA_IFCR_CGIF5_Pos (16U)
3126+#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
3127+#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
3128+#define DMA_IFCR_CTCIF5_Pos (17U)
3129+#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
3130+#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
3131+#define DMA_IFCR_CHTIF5_Pos (18U)
3132+#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
3133+#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
3134+#define DMA_IFCR_CTEIF5_Pos (19U)
3135+#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
3136+#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
3137+#define DMA_IFCR_CGIF6_Pos (20U)
3138+#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
3139+#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
3140+#define DMA_IFCR_CTCIF6_Pos (21U)
3141+#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
3142+#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
3143+#define DMA_IFCR_CHTIF6_Pos (22U)
3144+#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
3145+#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
3146+#define DMA_IFCR_CTEIF6_Pos (23U)
3147+#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
3148+#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
3149+#define DMA_IFCR_CGIF7_Pos (24U)
3150+#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
3151+#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
3152+#define DMA_IFCR_CTCIF7_Pos (25U)
3153+#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
3154+#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
3155+#define DMA_IFCR_CHTIF7_Pos (26U)
3156+#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
3157+#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
3158+#define DMA_IFCR_CTEIF7_Pos (27U)
3159+#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
3160+#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
3161+#define DMA_IFCR_CGIF8_Pos (28U)
3162+#define DMA_IFCR_CGIF8_Msk (0x1UL << DMA_IFCR_CGIF8_Pos) /*!< 0x10000000 */
3163+#define DMA_IFCR_CGIF8 DMA_IFCR_CGIF8_Msk /*!< Channel 8 Global interrupt clear */
3164+#define DMA_IFCR_CTCIF8_Pos (29U)
3165+#define DMA_IFCR_CTCIF8_Msk (0x1UL << DMA_IFCR_CTCIF8_Pos) /*!< 0x20000000 */
3166+#define DMA_IFCR_CTCIF8 DMA_IFCR_CTCIF8_Msk /*!< Channel 8 Transfer Complete clear */
3167+#define DMA_IFCR_CHTIF8_Pos (30U)
3168+#define DMA_IFCR_CHTIF8_Msk (0x1UL << DMA_IFCR_CHTIF8_Pos) /*!< 0x40000000 */
3169+#define DMA_IFCR_CHTIF8 DMA_IFCR_CHTIF8_Msk /*!< Channel 8 Half Transfer clear */
3170+#define DMA_IFCR_CTEIF8_Pos (31U)
3171+#define DMA_IFCR_CTEIF8_Msk (0x1UL << DMA_IFCR_CTEIF8_Pos) /*!< 0x80000000 */
3172+#define DMA_IFCR_CTEIF8 DMA_IFCR_CTEIF8_Msk /*!< Channel 8 Transfer Error clear */
3173+
3174+/******************* Bit definition for DMA_CCR register ********************/
3175+#define DMA_CCR_EN_Pos (0U)
3176+#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
3177+#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
3178+#define DMA_CCR_TCIE_Pos (1U)
3179+#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
3180+#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
3181+#define DMA_CCR_HTIE_Pos (2U)
3182+#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
3183+#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
3184+#define DMA_CCR_TEIE_Pos (3U)
3185+#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
3186+#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
3187+#define DMA_CCR_DIR_Pos (4U)
3188+#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
3189+#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
3190+#define DMA_CCR_CIRC_Pos (5U)
3191+#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
3192+#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
3193+#define DMA_CCR_PINC_Pos (6U)
3194+#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
3195+#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
3196+#define DMA_CCR_MINC_Pos (7U)
3197+#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
3198+#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
3199+
3200+#define DMA_CCR_PSIZE_Pos (8U)
3201+#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
3202+#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
3203+#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
3204+#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
3205+
3206+#define DMA_CCR_MSIZE_Pos (10U)
3207+#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
3208+#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
3209+#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
3210+#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
3211+
3212+#define DMA_CCR_PL_Pos (12U)
3213+#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
3214+#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
3215+#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */
3216+#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */
3217+
3218+#define DMA_CCR_MEM2MEM_Pos (14U)
3219+#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
3220+#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
3221+
3222+/****************** Bit definition for DMA_CNDTR register *******************/
3223+#define DMA_CNDTR_NDT_Pos (0U)
3224+#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
3225+#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
3226+
3227+/****************** Bit definition for DMA_CPAR register ********************/
3228+#define DMA_CPAR_PA_Pos (0U)
3229+#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
3230+#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
3231+
3232+/****************** Bit definition for DMA_CMAR register ********************/
3233+#define DMA_CMAR_MA_Pos (0U)
3234+#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
3235+#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
3236+
3237+/******************************************************************************/
3238+/* */
3239+/* DMAMUX Controller */
3240+/* */
3241+/******************************************************************************/
3242+
3243+/******************** Bits definition for DMAMUX_CxCR register **************/
3244+#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
3245+#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x000000FF */
3246+#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk
3247+#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000001 */
3248+#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000002 */
3249+#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000004 */
3250+#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000008 */
3251+#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000010 */
3252+#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000020 */
3253+#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000040 */
3254+#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000080 */
3255+
3256+#define DMAMUX_CxCR_SOIE_Pos (8U)
3257+#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos)/*!< 0x00000100 */
3258+#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk
3259+
3260+#define DMAMUX_CxCR_EGE_Pos (9U)
3261+#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos)/*!< 0x00000200 */
3262+#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk
3263+
3264+#define DMAMUX_CxCR_SE_Pos (16U)
3265+#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos)/*!< 0x00010000 */
3266+#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk
3267+
3268+#define DMAMUX_CxCR_SPOL_Pos (17U)
3269+#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00060000 */
3270+#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk
3271+#define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00020000 */
3272+#define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00040000 */
3273+
3274+#define DMAMUX_CxCR_NBREQ_Pos (19U)
3275+#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00F80000 */
3276+#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk
3277+#define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00080000 */
3278+#define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00100000 */
3279+#define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00200000 */
3280+#define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00400000 */
3281+#define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00800000 */
3282+
3283+#define DMAMUX_CxCR_SYNC_ID_Pos (24U)
3284+#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x1F000000 */
3285+#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk
3286+#define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x01000000 */
3287+#define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x02000000 */
3288+#define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x04000000 */
3289+#define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x08000000 */
3290+#define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x10000000 */
3291+
3292+/******************** Bits definition for DMAMUX_CSR register ****************/
3293+#define DMAMUX_CSR_SOF0_Pos (0U)
3294+#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos)/*!< 0x00000001 */
3295+#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk
3296+#define DMAMUX_CSR_SOF1_Pos (1U)
3297+#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos)/*!< 0x00000002 */
3298+#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk
3299+#define DMAMUX_CSR_SOF2_Pos (2U)
3300+#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos)/*!< 0x00000004 */
3301+#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk
3302+#define DMAMUX_CSR_SOF3_Pos (3U)
3303+#define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos)/*!< 0x00000008 */
3304+#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk
3305+#define DMAMUX_CSR_SOF4_Pos (4U)
3306+#define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos)/*!< 0x00000010 */
3307+#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk
3308+#define DMAMUX_CSR_SOF5_Pos (5U)
3309+#define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos)/*!< 0x00000020 */
3310+#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk
3311+#define DMAMUX_CSR_SOF6_Pos (6U)
3312+#define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos)/*!< 0x00000040 */
3313+#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk
3314+#define DMAMUX_CSR_SOF7_Pos (7U)
3315+#define DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos)/*!< 0x00000080 */
3316+#define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk
3317+#define DMAMUX_CSR_SOF8_Pos (8U)
3318+#define DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos)/*!< 0x00000100 */
3319+#define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk
3320+#define DMAMUX_CSR_SOF9_Pos (9U)
3321+#define DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos)/*!< 0x00000200 */
3322+#define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk
3323+#define DMAMUX_CSR_SOF10_Pos (10U)
3324+#define DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos)/*!< 0x00000400 */
3325+#define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk
3326+#define DMAMUX_CSR_SOF11_Pos (11U)
3327+#define DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos)/*!< 0x00000800 */
3328+#define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk
3329+#define DMAMUX_CSR_SOF12_Pos (12U)
3330+#define DMAMUX_CSR_SOF12_Msk (0x1UL << DMAMUX_CSR_SOF12_Pos)/*!< 0x00001000 */
3331+#define DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk
3332+#define DMAMUX_CSR_SOF13_Pos (13U)
3333+#define DMAMUX_CSR_SOF13_Msk (0x1UL << DMAMUX_CSR_SOF13_Pos)/*!< 0x00002000 */
3334+#define DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk
3335+#define DMAMUX_CSR_SOF14_Pos (14U)
3336+#define DMAMUX_CSR_SOF14_Msk (0x1UL << DMAMUX_CSR_SOF14_Pos)/*!< 0x00004000 */
3337+#define DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14_Msk
3338+#define DMAMUX_CSR_SOF15_Pos (15U)
3339+#define DMAMUX_CSR_SOF15_Msk (0x1UL << DMAMUX_CSR_SOF15_Pos)/*!< 0x00008000 */
3340+#define DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15_Msk
3341+
3342+/******************** Bits definition for DMAMUX_CFR register ****************/
3343+#define DMAMUX_CFR_CSOF0_Pos (0U)
3344+#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos)/*!< 0x00000001 */
3345+#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk
3346+#define DMAMUX_CFR_CSOF1_Pos (1U)
3347+#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos)/*!< 0x00000002 */
3348+#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk
3349+#define DMAMUX_CFR_CSOF2_Pos (2U)
3350+#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos)/*!< 0x00000004 */
3351+#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk
3352+#define DMAMUX_CFR_CSOF3_Pos (3U)
3353+#define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos)/*!< 0x00000008 */
3354+#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk
3355+#define DMAMUX_CFR_CSOF4_Pos (4U)
3356+#define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos)/*!< 0x00000010 */
3357+#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk
3358+#define DMAMUX_CFR_CSOF5_Pos (5U)
3359+#define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos)/*!< 0x00000020 */
3360+#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk
3361+#define DMAMUX_CFR_CSOF6_Pos (6U)
3362+#define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos)/*!< 0x00000040 */
3363+#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk
3364+#define DMAMUX_CFR_CSOF7_Pos (7U)
3365+#define DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos)/*!< 0x00000080 */
3366+#define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk
3367+#define DMAMUX_CFR_CSOF8_Pos (8U)
3368+#define DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos)/*!< 0x00000100 */
3369+#define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk
3370+#define DMAMUX_CFR_CSOF9_Pos (9U)
3371+#define DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos)/*!< 0x00000200 */
3372+#define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk
3373+#define DMAMUX_CFR_CSOF10_Pos (10U)
3374+#define DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos)/*!< 0x00000400 */
3375+#define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk
3376+#define DMAMUX_CFR_CSOF11_Pos (11U)
3377+#define DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos)/*!< 0x00000800 */
3378+#define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk
3379+#define DMAMUX_CFR_CSOF12_Pos (12U)
3380+#define DMAMUX_CFR_CSOF12_Msk (0x1UL << DMAMUX_CFR_CSOF12_Pos)/*!< 0x00001000 */
3381+#define DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk
3382+#define DMAMUX_CFR_CSOF13_Pos (13U)
3383+#define DMAMUX_CFR_CSOF13_Msk (0x1UL << DMAMUX_CFR_CSOF13_Pos)/*!< 0x00002000 */
3384+#define DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk
3385+#define DMAMUX_CFR_CSOF14_Pos (14U)
3386+#define DMAMUX_CFR_CSOF14_Msk (0x1UL << DMAMUX_CFR_CSOF14_Pos)/*!< 0x00004000 */
3387+#define DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14_Msk
3388+#define DMAMUX_CFR_CSOF15_Pos (15U)
3389+#define DMAMUX_CFR_CSOF15_Msk (0x1UL << DMAMUX_CFR_CSOF15_Pos)/*!< 0x00008000 */
3390+#define DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15_Msk
3391+
3392+/******************** Bits definition for DMAMUX_RGxCR register ************/
3393+#define DMAMUX_RGxCR_SIG_ID_Pos (0U)
3394+#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x0000001F */
3395+#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk
3396+#define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000001 */
3397+#define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000002 */
3398+#define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000004 */
3399+#define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000008 */
3400+#define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000010 */
3401+
3402+#define DMAMUX_RGxCR_OIE_Pos (8U)
3403+#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos)/*!< 0x00000100 */
3404+#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk
3405+
3406+#define DMAMUX_RGxCR_GE_Pos (16U)
3407+#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos)/*!< 0x00010000 */
3408+#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk
3409+
3410+#define DMAMUX_RGxCR_GPOL_Pos (17U)
3411+#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00060000 */
3412+#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk
3413+#define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00020000 */
3414+#define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00040000 */
3415+
3416+#define DMAMUX_RGxCR_GNBREQ_Pos (19U)
3417+#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00F80000 */
3418+#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk
3419+#define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00080000 */
3420+#define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00100000 */
3421+#define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00200000 */
3422+#define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00400000 */
3423+#define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00800000 */
3424+
3425+/******************** Bits definition for DMAMUX_RGSR register **************/
3426+#define DMAMUX_RGSR_OF0_Pos (0U)
3427+#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos)/*!< 0x00000001 */
3428+#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk
3429+#define DMAMUX_RGSR_OF1_Pos (1U)
3430+#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos)/*!< 0x00000002 */
3431+#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk
3432+#define DMAMUX_RGSR_OF2_Pos (2U)
3433+#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos)/*!< 0x00000004 */
3434+#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk
3435+#define DMAMUX_RGSR_OF3_Pos (3U)
3436+#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos)/*!< 0x00000008 */
3437+#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk
3438+
3439+/******************** Bits definition for DMAMUX_RGCFR register ************/
3440+#define DMAMUX_RGCFR_COF0_Pos (0U)
3441+#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos)/*!< 0x00000001 */
3442+#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk
3443+#define DMAMUX_RGCFR_COF1_Pos (1U)
3444+#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos)/*!< 0x00000002 */
3445+#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk
3446+#define DMAMUX_RGCFR_COF2_Pos (2U)
3447+#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos)/*!< 0x00000004 */
3448+#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk
3449+#define DMAMUX_RGCFR_COF3_Pos (3U)
3450+#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos)/*!< 0x00000008 */
3451+#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk
3452+
3453+/******************** Bits definition for DMAMUX_IPHW_CFGR2 ******************/
3454+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos (0U)
3455+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos)/*!< 0x00000001 */
3456+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk
3457+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos (1U)
3458+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos)/*!< 0x00000002 */
3459+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk
3460+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos (2U)
3461+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos)/*!< 0x00000004 */
3462+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk
3463+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos (3U)
3464+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos)/*!< 0x00000008 */
3465+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk
3466+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos (4U)
3467+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos)/*!< 0x00000010 */
3468+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk
3469+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos (5U)
3470+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos)/*!< 0x00000020 */
3471+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk
3472+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos (6U)
3473+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos)/*!< 0x00000040 */
3474+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk
3475+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos (7U)
3476+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos)/*!< 0x00000080 */
3477+#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk
3478+
3479+/******************** Bits definition for DMAMUX_IPHW_CFGR1 ******************/
3480+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos (0U)
3481+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos)/*!< 0x00000001 */
3482+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk
3483+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos (1U)
3484+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos)/*!< 0x00000002 */
3485+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk
3486+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos (2U)
3487+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos)/*!< 0x00000004 */
3488+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk
3489+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos (3U)
3490+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos)/*!< 0x00000008 */
3491+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk
3492+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos (4U)
3493+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos)/*!< 0x00000010 */
3494+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk
3495+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos (5U)
3496+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos)/*!< 0x00000020 */
3497+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk
3498+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos (6U)
3499+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos)/*!< 0x00000040 */
3500+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk
3501+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos (7U)
3502+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos)/*!< 0x00000080 */
3503+#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk
3504+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos (8U)
3505+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos)/*!< 0x00000100 */
3506+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk
3507+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos (9U)
3508+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos)/*!< 0x00000200 */
3509+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk
3510+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos (10U)
3511+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos)/*!< 0x00000400 */
3512+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk
3513+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos (11U)
3514+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos)/*!< 0x00000800 */
3515+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk
3516+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos (12U)
3517+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos)/*!< 0x00001000 */
3518+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk
3519+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos (13U)
3520+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos)/*!< 0x00002000 */
3521+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk
3522+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos (14U)
3523+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos)/*!< 0x00004000 */
3524+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk
3525+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos (15U)
3526+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos)/*!< 0x00008000 */
3527+#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk
3528+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos (16U)
3529+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos)/*!< 0x00010000 */
3530+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk
3531+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos (17U)
3532+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos)/*!< 0x00020000 */
3533+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk
3534+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos (18U)
3535+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos)/*!< 0x00040000 */
3536+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk
3537+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos (19U)
3538+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos)/*!< 0x00080000 */
3539+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk
3540+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos (20U)
3541+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos)/*!< 0x00100000 */
3542+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk
3543+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos (21U)
3544+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos)/*!< 0x00200000 */
3545+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk
3546+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos (22U)
3547+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos)/*!< 0x00400000 */
3548+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk
3549+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos (23U)
3550+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos)/*!< 0x00800000 */
3551+#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk
3552+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos (24U)
3553+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos)/*!< 0x01000000 */
3554+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk
3555+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos (25U)
3556+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos)/*!< 0x02000000 */
3557+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk
3558+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos (26U)
3559+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos)/*!< 0x04000000 */
3560+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk
3561+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos (27U)
3562+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos)/*!< 0x08000000 */
3563+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk
3564+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos (28U)
3565+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos)/*!< 0x10000000 */
3566+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk
3567+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos (29U)
3568+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos)/*!< 0x20000000 */
3569+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk
3570+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos (30U)
3571+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos)/*!< 0x40000000 */
3572+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk
3573+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos (31U)
3574+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos)/*!< 0x80000000 */
3575+#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk
3576+
3577+
3578+/******************************************************************************/
3579+/* */
3580+/* External Interrupt/Event Controller */
3581+/* */
3582+/******************************************************************************/
3583+/******************* Bit definition for EXTI_IMR1 register ******************/
3584+#define EXTI_IMR1_IM0_Pos (0U)
3585+#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
3586+#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
3587+#define EXTI_IMR1_IM1_Pos (1U)
3588+#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
3589+#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
3590+#define EXTI_IMR1_IM2_Pos (2U)
3591+#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
3592+#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
3593+#define EXTI_IMR1_IM3_Pos (3U)
3594+#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
3595+#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
3596+#define EXTI_IMR1_IM4_Pos (4U)
3597+#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
3598+#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
3599+#define EXTI_IMR1_IM5_Pos (5U)
3600+#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
3601+#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
3602+#define EXTI_IMR1_IM6_Pos (6U)
3603+#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
3604+#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
3605+#define EXTI_IMR1_IM7_Pos (7U)
3606+#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
3607+#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
3608+#define EXTI_IMR1_IM8_Pos (8U)
3609+#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
3610+#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
3611+#define EXTI_IMR1_IM9_Pos (9U)
3612+#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
3613+#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
3614+#define EXTI_IMR1_IM10_Pos (10U)
3615+#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
3616+#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
3617+#define EXTI_IMR1_IM11_Pos (11U)
3618+#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
3619+#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
3620+#define EXTI_IMR1_IM12_Pos (12U)
3621+#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
3622+#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
3623+#define EXTI_IMR1_IM13_Pos (13U)
3624+#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
3625+#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
3626+#define EXTI_IMR1_IM14_Pos (14U)
3627+#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
3628+#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
3629+#define EXTI_IMR1_IM15_Pos (15U)
3630+#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
3631+#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
3632+#define EXTI_IMR1_IM16_Pos (16U)
3633+#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */
3634+#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */
3635+#define EXTI_IMR1_IM17_Pos (17U)
3636+#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */
3637+#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */
3638+#define EXTI_IMR1_IM18_Pos (18U)
3639+#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */
3640+#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */
3641+#define EXTI_IMR1_IM19_Pos (19U)
3642+#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
3643+#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
3644+#define EXTI_IMR1_IM20_Pos (20U)
3645+#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
3646+#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */
3647+#define EXTI_IMR1_IM21_Pos (21U)
3648+#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
3649+#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
3650+#define EXTI_IMR1_IM22_Pos (22U)
3651+#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
3652+#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */
3653+#define EXTI_IMR1_IM23_Pos (23U)
3654+#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
3655+#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
3656+#define EXTI_IMR1_IM24_Pos (24U)
3657+#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
3658+#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
3659+#define EXTI_IMR1_IM25_Pos (25U)
3660+#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
3661+#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
3662+#define EXTI_IMR1_IM26_Pos (26U)
3663+#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
3664+#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */
3665+#define EXTI_IMR1_IM27_Pos (27U)
3666+#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
3667+#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */
3668+#define EXTI_IMR1_IM28_Pos (28U)
3669+#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
3670+#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */
3671+#define EXTI_IMR1_IM29_Pos (29U)
3672+#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */
3673+#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */
3674+#define EXTI_IMR1_IM30_Pos (30U)
3675+#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */
3676+#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */
3677+#define EXTI_IMR1_IM_Pos (0U)
3678+#define EXTI_IMR1_IM_Msk (0x7FFFFFFFUL << EXTI_IMR1_IM_Pos) /*!< 0x7FFFFFFF */
3679+#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */
3680+
3681+/******************* Bit definition for EXTI_EMR1 register ******************/
3682+#define EXTI_EMR1_EM0_Pos (0U)
3683+#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
3684+#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
3685+#define EXTI_EMR1_EM1_Pos (1U)
3686+#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
3687+#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
3688+#define EXTI_EMR1_EM2_Pos (2U)
3689+#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
3690+#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
3691+#define EXTI_EMR1_EM3_Pos (3U)
3692+#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
3693+#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
3694+#define EXTI_EMR1_EM4_Pos (4U)
3695+#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
3696+#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
3697+#define EXTI_EMR1_EM5_Pos (5U)
3698+#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
3699+#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
3700+#define EXTI_EMR1_EM6_Pos (6U)
3701+#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
3702+#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
3703+#define EXTI_EMR1_EM7_Pos (7U)
3704+#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
3705+#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
3706+#define EXTI_EMR1_EM8_Pos (8U)
3707+#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
3708+#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
3709+#define EXTI_EMR1_EM9_Pos (9U)
3710+#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
3711+#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
3712+#define EXTI_EMR1_EM10_Pos (10U)
3713+#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
3714+#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
3715+#define EXTI_EMR1_EM11_Pos (11U)
3716+#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
3717+#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
3718+#define EXTI_EMR1_EM12_Pos (12U)
3719+#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
3720+#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
3721+#define EXTI_EMR1_EM13_Pos (13U)
3722+#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
3723+#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
3724+#define EXTI_EMR1_EM14_Pos (14U)
3725+#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
3726+#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
3727+#define EXTI_EMR1_EM15_Pos (15U)
3728+#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
3729+#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
3730+#define EXTI_EMR1_EM16_Pos (16U)
3731+#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */
3732+#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */
3733+#define EXTI_EMR1_EM17_Pos (17U)
3734+#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */
3735+#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */
3736+#define EXTI_EMR1_EM18_Pos (18U)
3737+#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */
3738+#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */
3739+#define EXTI_EMR1_EM19_Pos (19U)
3740+#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */
3741+#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */
3742+#define EXTI_EMR1_EM20_Pos (20U)
3743+#define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */
3744+#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */
3745+#define EXTI_EMR1_EM21_Pos (21U)
3746+#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
3747+#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
3748+#define EXTI_EMR1_EM22_Pos (22U)
3749+#define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */
3750+#define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< Event Mask on line 22 */
3751+#define EXTI_EMR1_EM23_Pos (23U)
3752+#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
3753+#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
3754+#define EXTI_EMR1_EM24_Pos (24U)
3755+#define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */
3756+#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */
3757+#define EXTI_EMR1_EM25_Pos (25U)
3758+#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
3759+#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
3760+#define EXTI_EMR1_EM26_Pos (26U)
3761+#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */
3762+#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */
3763+#define EXTI_EMR1_EM27_Pos (27U)
3764+#define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */
3765+#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */
3766+#define EXTI_EMR1_EM28_Pos (28U)
3767+#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */
3768+#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */
3769+#define EXTI_EMR1_EM29_Pos (29U)
3770+#define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */
3771+#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */
3772+#define EXTI_EMR1_EM30_Pos (30U)
3773+#define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */
3774+#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */
3775+
3776+/****************** Bit definition for EXTI_RTSR1 register ******************/
3777+#define EXTI_RTSR1_RT0_Pos (0U)
3778+#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */
3779+#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
3780+#define EXTI_RTSR1_RT1_Pos (1U)
3781+#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */
3782+#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
3783+#define EXTI_RTSR1_RT2_Pos (2U)
3784+#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */
3785+#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
3786+#define EXTI_RTSR1_RT3_Pos (3U)
3787+#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */
3788+#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
3789+#define EXTI_RTSR1_RT4_Pos (4U)
3790+#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */
3791+#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
3792+#define EXTI_RTSR1_RT5_Pos (5U)
3793+#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */
3794+#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
3795+#define EXTI_RTSR1_RT6_Pos (6U)
3796+#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */
3797+#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
3798+#define EXTI_RTSR1_RT7_Pos (7U)
3799+#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */
3800+#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
3801+#define EXTI_RTSR1_RT8_Pos (8U)
3802+#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */
3803+#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
3804+#define EXTI_RTSR1_RT9_Pos (9U)
3805+#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */
3806+#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
3807+#define EXTI_RTSR1_RT10_Pos (10U)
3808+#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */
3809+#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
3810+#define EXTI_RTSR1_RT11_Pos (11U)
3811+#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */
3812+#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
3813+#define EXTI_RTSR1_RT12_Pos (12U)
3814+#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */
3815+#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
3816+#define EXTI_RTSR1_RT13_Pos (13U)
3817+#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */
3818+#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
3819+#define EXTI_RTSR1_RT14_Pos (14U)
3820+#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */
3821+#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
3822+#define EXTI_RTSR1_RT15_Pos (15U)
3823+#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */
3824+#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
3825+#define EXTI_RTSR1_RT16_Pos (16U)
3826+#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */
3827+#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
3828+#define EXTI_RTSR1_RT17_Pos (17U)
3829+#define EXTI_RTSR1_RT17_Msk (0x1UL << EXTI_RTSR1_RT17_Pos) /*!< 0x00020000 */
3830+#define EXTI_RTSR1_RT17 EXTI_RTSR1_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */
3831+#define EXTI_RTSR1_RT19_Pos (19U)
3832+#define EXTI_RTSR1_RT19_Msk (0x1UL << EXTI_RTSR1_RT19_Pos) /*!< 0x00080000 */
3833+#define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
3834+#define EXTI_RTSR1_RT20_Pos (20U)
3835+#define EXTI_RTSR1_RT20_Msk (0x1UL << EXTI_RTSR1_RT20_Pos) /*!< 0x00100000 */
3836+#define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
3837+#define EXTI_RTSR1_RT21_Pos (21U)
3838+#define EXTI_RTSR1_RT21_Msk (0x1UL << EXTI_RTSR1_RT21_Pos) /*!< 0x00200000 */
3839+#define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
3840+#define EXTI_RTSR1_RT22_Pos (22U)
3841+#define EXTI_RTSR1_RT22_Msk (0x1UL << EXTI_RTSR1_RT22_Pos) /*!< 0x00400000 */
3842+#define EXTI_RTSR1_RT22 EXTI_RTSR1_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
3843+#define EXTI_RTSR1_RT29_Pos (29U)
3844+#define EXTI_RTSR1_RT29_Msk (0x1UL << EXTI_RTSR1_RT29_Pos) /*!< 0x20000000 */
3845+#define EXTI_RTSR1_RT29 EXTI_RTSR1_RT29_Msk /*!< Rising trigger event configuration bit of line 29 */
3846+#define EXTI_RTSR1_RT30_Pos (30U)
3847+#define EXTI_RTSR1_RT30_Msk (0x1UL << EXTI_RTSR1_RT30_Pos) /*!< 0x40000000 */
3848+#define EXTI_RTSR1_RT30 EXTI_RTSR1_RT30_Msk /*!< Rising trigger event configuration bit of line 30 */
3849+
3850+/****************** Bit definition for EXTI_FTSR1 register ******************/
3851+#define EXTI_FTSR1_FT0_Pos (0U)
3852+#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */
3853+#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
3854+#define EXTI_FTSR1_FT1_Pos (1U)
3855+#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */
3856+#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
3857+#define EXTI_FTSR1_FT2_Pos (2U)
3858+#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */
3859+#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
3860+#define EXTI_FTSR1_FT3_Pos (3U)
3861+#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */
3862+#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
3863+#define EXTI_FTSR1_FT4_Pos (4U)
3864+#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */
3865+#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
3866+#define EXTI_FTSR1_FT5_Pos (5U)
3867+#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */
3868+#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
3869+#define EXTI_FTSR1_FT6_Pos (6U)
3870+#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */
3871+#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
3872+#define EXTI_FTSR1_FT7_Pos (7U)
3873+#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */
3874+#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
3875+#define EXTI_FTSR1_FT8_Pos (8U)
3876+#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */
3877+#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
3878+#define EXTI_FTSR1_FT9_Pos (9U)
3879+#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */
3880+#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
3881+#define EXTI_FTSR1_FT10_Pos (10U)
3882+#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */
3883+#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
3884+#define EXTI_FTSR1_FT11_Pos (11U)
3885+#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */
3886+#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
3887+#define EXTI_FTSR1_FT12_Pos (12U)
3888+#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */
3889+#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
3890+#define EXTI_FTSR1_FT13_Pos (13U)
3891+#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */
3892+#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
3893+#define EXTI_FTSR1_FT14_Pos (14U)
3894+#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */
3895+#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
3896+#define EXTI_FTSR1_FT15_Pos (15U)
3897+#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */
3898+#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
3899+#define EXTI_FTSR1_FT16_Pos (16U)
3900+#define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */
3901+#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
3902+#define EXTI_FTSR1_FT17_Pos (17U)
3903+#define EXTI_FTSR1_FT17_Msk (0x1UL << EXTI_FTSR1_FT17_Pos) /*!< 0x00020000 */
3904+#define EXTI_FTSR1_FT17 EXTI_FTSR1_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */
3905+#define EXTI_FTSR1_FT19_Pos (19U)
3906+#define EXTI_FTSR1_FT19_Msk (0x1UL << EXTI_FTSR1_FT19_Pos) /*!< 0x00080000 */
3907+#define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
3908+#define EXTI_FTSR1_FT20_Pos (20U)
3909+#define EXTI_FTSR1_FT20_Msk (0x1UL << EXTI_FTSR1_FT20_Pos) /*!< 0x00100000 */
3910+#define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
3911+#define EXTI_FTSR1_FT21_Pos (21U)
3912+#define EXTI_FTSR1_FT21_Msk (0x1UL << EXTI_FTSR1_FT21_Pos) /*!< 0x00200000 */
3913+#define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
3914+#define EXTI_FTSR1_FT22_Pos (22U)
3915+#define EXTI_FTSR1_FT22_Msk (0x1UL << EXTI_FTSR1_FT22_Pos) /*!< 0x00400000 */
3916+#define EXTI_FTSR1_FT22 EXTI_FTSR1_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
3917+#define EXTI_FTSR1_FT29_Pos (29U)
3918+#define EXTI_FTSR1_FT29_Msk (0x1UL << EXTI_FTSR1_FT29_Pos) /*!< 0x20000000 */
3919+#define EXTI_FTSR1_FT29 EXTI_FTSR1_FT29_Msk /*!< Falling trigger event configuration bit of line 29 */
3920+#define EXTI_FTSR1_FT30_Pos (30U)
3921+#define EXTI_FTSR1_FT30_Msk (0x1UL << EXTI_FTSR1_FT30_Pos) /*!< 0x40000000 */
3922+#define EXTI_FTSR1_FT30 EXTI_FTSR1_FT30_Msk /*!< Falling trigger event configuration bit of line 30 */
3923+
3924+/****************** Bit definition for EXTI_SWIER1 register *****************/
3925+#define EXTI_SWIER1_SWI0_Pos (0U)
3926+#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */
3927+#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */
3928+#define EXTI_SWIER1_SWI1_Pos (1U)
3929+#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */
3930+#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */
3931+#define EXTI_SWIER1_SWI2_Pos (2U)
3932+#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */
3933+#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */
3934+#define EXTI_SWIER1_SWI3_Pos (3U)
3935+#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */
3936+#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */
3937+#define EXTI_SWIER1_SWI4_Pos (4U)
3938+#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */
3939+#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */
3940+#define EXTI_SWIER1_SWI5_Pos (5U)
3941+#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */
3942+#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */
3943+#define EXTI_SWIER1_SWI6_Pos (6U)
3944+#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */
3945+#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */
3946+#define EXTI_SWIER1_SWI7_Pos (7U)
3947+#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */
3948+#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */
3949+#define EXTI_SWIER1_SWI8_Pos (8U)
3950+#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */
3951+#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */
3952+#define EXTI_SWIER1_SWI9_Pos (9U)
3953+#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */
3954+#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */
3955+#define EXTI_SWIER1_SWI10_Pos (10U)
3956+#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */
3957+#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */
3958+#define EXTI_SWIER1_SWI11_Pos (11U)
3959+#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */
3960+#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */
3961+#define EXTI_SWIER1_SWI12_Pos (12U)
3962+#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */
3963+#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */
3964+#define EXTI_SWIER1_SWI13_Pos (13U)
3965+#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */
3966+#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */
3967+#define EXTI_SWIER1_SWI14_Pos (14U)
3968+#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */
3969+#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */
3970+#define EXTI_SWIER1_SWI15_Pos (15U)
3971+#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */
3972+#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */
3973+#define EXTI_SWIER1_SWI16_Pos (16U)
3974+#define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */
3975+#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */
3976+#define EXTI_SWIER1_SWI17_Pos (17U)
3977+#define EXTI_SWIER1_SWI17_Msk (0x1UL << EXTI_SWIER1_SWI17_Pos) /*!< 0x00020000 */
3978+#define EXTI_SWIER1_SWI17 EXTI_SWIER1_SWI17_Msk /*!< Software Interrupt on line 17 */
3979+#define EXTI_SWIER1_SWI19_Pos (19U)
3980+#define EXTI_SWIER1_SWI19_Msk (0x1UL << EXTI_SWIER1_SWI19_Pos) /*!< 0x00080000 */
3981+#define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk /*!< Software Interrupt on line 19 */
3982+#define EXTI_SWIER1_SWI20_Pos (20U)
3983+#define EXTI_SWIER1_SWI20_Msk (0x1UL << EXTI_SWIER1_SWI20_Pos) /*!< 0x00100000 */
3984+#define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk /*!< Software Interrupt on line 20 */
3985+#define EXTI_SWIER1_SWI21_Pos (21U)
3986+#define EXTI_SWIER1_SWI21_Msk (0x1UL << EXTI_SWIER1_SWI21_Pos) /*!< 0x00200000 */
3987+#define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk /*!< Software Interrupt on line 21 */
3988+#define EXTI_SWIER1_SWI22_Pos (22U)
3989+#define EXTI_SWIER1_SWI22_Msk (0x1UL << EXTI_SWIER1_SWI22_Pos) /*!< 0x00400000 */
3990+#define EXTI_SWIER1_SWI22 EXTI_SWIER1_SWI22_Msk /*!< Software Interrupt on line 22 */
3991+#define EXTI_SWIER1_SWI29_Pos (29U)
3992+#define EXTI_SWIER1_SWI29_Msk (0x1UL << EXTI_SWIER1_SWI29_Pos) /*!< 0x20000000 */
3993+#define EXTI_SWIER1_SWI29 EXTI_SWIER1_SWI29_Msk /*!< Software Interrupt on line 29 */
3994+#define EXTI_SWIER1_SWI30_Pos (30U)
3995+#define EXTI_SWIER1_SWI30_Msk (0x1UL << EXTI_SWIER1_SWI30_Pos) /*!< 0x40000000 */
3996+#define EXTI_SWIER1_SWI30 EXTI_SWIER1_SWI30_Msk /*!< Software Interrupt on line 30 */
3997+
3998+/******************* Bit definition for EXTI_PR1 register *******************/
3999+#define EXTI_PR1_PIF0_Pos (0U)
4000+#define EXTI_PR1_PIF0_Msk (0x1UL << EXTI_PR1_PIF0_Pos) /*!< 0x00000001 */
4001+#define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk /*!< Pending bit for line 0 */
4002+#define EXTI_PR1_PIF1_Pos (1U)
4003+#define EXTI_PR1_PIF1_Msk (0x1UL << EXTI_PR1_PIF1_Pos) /*!< 0x00000002 */
4004+#define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk /*!< Pending bit for line 1 */
4005+#define EXTI_PR1_PIF2_Pos (2U)
4006+#define EXTI_PR1_PIF2_Msk (0x1UL << EXTI_PR1_PIF2_Pos) /*!< 0x00000004 */
4007+#define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk /*!< Pending bit for line 2 */
4008+#define EXTI_PR1_PIF3_Pos (3U)
4009+#define EXTI_PR1_PIF3_Msk (0x1UL << EXTI_PR1_PIF3_Pos) /*!< 0x00000008 */
4010+#define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk /*!< Pending bit for line 3 */
4011+#define EXTI_PR1_PIF4_Pos (4U)
4012+#define EXTI_PR1_PIF4_Msk (0x1UL << EXTI_PR1_PIF4_Pos) /*!< 0x00000010 */
4013+#define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk /*!< Pending bit for line 4 */
4014+#define EXTI_PR1_PIF5_Pos (5U)
4015+#define EXTI_PR1_PIF5_Msk (0x1UL << EXTI_PR1_PIF5_Pos) /*!< 0x00000020 */
4016+#define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk /*!< Pending bit for line 5 */
4017+#define EXTI_PR1_PIF6_Pos (6U)
4018+#define EXTI_PR1_PIF6_Msk (0x1UL << EXTI_PR1_PIF6_Pos) /*!< 0x00000040 */
4019+#define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk /*!< Pending bit for line 6 */
4020+#define EXTI_PR1_PIF7_Pos (7U)
4021+#define EXTI_PR1_PIF7_Msk (0x1UL << EXTI_PR1_PIF7_Pos) /*!< 0x00000080 */
4022+#define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk /*!< Pending bit for line 7 */
4023+#define EXTI_PR1_PIF8_Pos (8U)
4024+#define EXTI_PR1_PIF8_Msk (0x1UL << EXTI_PR1_PIF8_Pos) /*!< 0x00000100 */
4025+#define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk /*!< Pending bit for line 8 */
4026+#define EXTI_PR1_PIF9_Pos (9U)
4027+#define EXTI_PR1_PIF9_Msk (0x1UL << EXTI_PR1_PIF9_Pos) /*!< 0x00000200 */
4028+#define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk /*!< Pending bit for line 9 */
4029+#define EXTI_PR1_PIF10_Pos (10U)
4030+#define EXTI_PR1_PIF10_Msk (0x1UL << EXTI_PR1_PIF10_Pos) /*!< 0x00000400 */
4031+#define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk /*!< Pending bit for line 10 */
4032+#define EXTI_PR1_PIF11_Pos (11U)
4033+#define EXTI_PR1_PIF11_Msk (0x1UL << EXTI_PR1_PIF11_Pos) /*!< 0x00000800 */
4034+#define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk /*!< Pending bit for line 11 */
4035+#define EXTI_PR1_PIF12_Pos (12U)
4036+#define EXTI_PR1_PIF12_Msk (0x1UL << EXTI_PR1_PIF12_Pos) /*!< 0x00001000 */
4037+#define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk /*!< Pending bit for line 12 */
4038+#define EXTI_PR1_PIF13_Pos (13U)
4039+#define EXTI_PR1_PIF13_Msk (0x1UL << EXTI_PR1_PIF13_Pos) /*!< 0x00002000 */
4040+#define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk /*!< Pending bit for line 13 */
4041+#define EXTI_PR1_PIF14_Pos (14U)
4042+#define EXTI_PR1_PIF14_Msk (0x1UL << EXTI_PR1_PIF14_Pos) /*!< 0x00004000 */
4043+#define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk /*!< Pending bit for line 14 */
4044+#define EXTI_PR1_PIF15_Pos (15U)
4045+#define EXTI_PR1_PIF15_Msk (0x1UL << EXTI_PR1_PIF15_Pos) /*!< 0x00008000 */
4046+#define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk /*!< Pending bit for line 15 */
4047+#define EXTI_PR1_PIF16_Pos (16U)
4048+#define EXTI_PR1_PIF16_Msk (0x1UL << EXTI_PR1_PIF16_Pos) /*!< 0x00010000 */
4049+#define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk /*!< Pending bit for line 16 */
4050+#define EXTI_PR1_PIF17_Pos (17U)
4051+#define EXTI_PR1_PIF17_Msk (0x1UL << EXTI_PR1_PIF17_Pos) /*!< 0x00020000 */
4052+#define EXTI_PR1_PIF17 EXTI_PR1_PIF17_Msk /*!< Pending bit for line 17 */
4053+#define EXTI_PR1_PIF19_Pos (19U)
4054+#define EXTI_PR1_PIF19_Msk (0x1UL << EXTI_PR1_PIF19_Pos) /*!< 0x00080000 */
4055+#define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk /*!< Pending bit for line 19 */
4056+#define EXTI_PR1_PIF20_Pos (20U)
4057+#define EXTI_PR1_PIF20_Msk (0x1UL << EXTI_PR1_PIF20_Pos) /*!< 0x00100000 */
4058+#define EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk /*!< Pending bit for line 20 */
4059+#define EXTI_PR1_PIF21_Pos (21U)
4060+#define EXTI_PR1_PIF21_Msk (0x1UL << EXTI_PR1_PIF21_Pos) /*!< 0x00200000 */
4061+#define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk /*!< Pending bit for line 21 */
4062+#define EXTI_PR1_PIF22_Pos (22U)
4063+#define EXTI_PR1_PIF22_Msk (0x1UL << EXTI_PR1_PIF22_Pos) /*!< 0x00400000 */
4064+#define EXTI_PR1_PIF22 EXTI_PR1_PIF22_Msk /*!< Pending bit for line 22 */
4065+#define EXTI_PR1_PIF29_Pos (29U)
4066+#define EXTI_PR1_PIF29_Msk (0x1UL << EXTI_PR1_PIF29_Pos) /*!< 0x20000000 */
4067+#define EXTI_PR1_PIF29 EXTI_PR1_PIF29_Msk /*!< Pending bit for line 29 */
4068+#define EXTI_PR1_PIF30_Pos (30U)
4069+#define EXTI_PR1_PIF30_Msk (0x1UL << EXTI_PR1_PIF30_Pos) /*!< 0x40000000 */
4070+#define EXTI_PR1_PIF30 EXTI_PR1_PIF30_Msk /*!< Pending bit for line 30 */
4071+
4072+/******************* Bit definition for EXTI_IMR2 register ******************/
4073+#define EXTI_IMR2_IM34_Pos (2U)
4074+#define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
4075+#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
4076+#define EXTI_IMR2_IM35_Pos (3U)
4077+#define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
4078+#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
4079+#define EXTI_IMR2_IM36_Pos (4U)
4080+#define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
4081+#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
4082+#define EXTI_IMR2_IM37_Pos (5U)
4083+#define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
4084+#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
4085+#define EXTI_IMR2_IM38_Pos (6U)
4086+#define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
4087+#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
4088+#define EXTI_IMR2_IM39_Pos (7U)
4089+#define EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
4090+#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
4091+#define EXTI_IMR2_IM40_Pos (8U)
4092+#define EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */
4093+#define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< Interrupt Mask on line 40 */
4094+#define EXTI_IMR2_IM41_Pos (9U)
4095+#define EXTI_IMR2_IM41_Msk (0x1UL << EXTI_IMR2_IM41_Pos) /*!< 0x00000200 */
4096+#define EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk /*!< Interrupt Mask on line 41 */
4097+#define EXTI_IMR2_IM_Pos (0U)
4098+#define EXTI_IMR2_IM_Msk (0x2FCUL << EXTI_IMR2_IM_Pos) /*!< 0x000002FC */
4099+#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
4100+
4101+/******************* Bit definition for EXTI_EMR2 register ******************/
4102+#define EXTI_EMR2_EM34_Pos (2U)
4103+#define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
4104+#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34 */
4105+#define EXTI_EMR2_EM36_Pos (4U)
4106+#define EXTI_EMR2_EM36_Msk (0x1UL << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
4107+#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36 */
4108+#define EXTI_EMR2_EM37_Pos (5U)
4109+#define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
4110+#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */
4111+#define EXTI_EMR2_EM38_Pos (6U)
4112+#define EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
4113+#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
4114+#define EXTI_EMR2_EM39_Pos (7U)
4115+#define EXTI_EMR2_EM39_Msk (0x1UL << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
4116+#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
4117+#define EXTI_EMR2_EM40_Pos (8U)
4118+#define EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */
4119+#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< Event Mask on line 40 */
4120+#define EXTI_EMR2_EM41_Pos (9U)
4121+#define EXTI_EMR2_EM41_Msk (0x1UL << EXTI_EMR2_EM41_Pos) /*!< 0x00000200 */
4122+#define EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk /*!< Event Mask on line 41 */
4123+#define EXTI_EMR2_EM_Pos (0U)
4124+#define EXTI_EMR2_EM_Msk (0x2FCUL << EXTI_EMR2_EM_Pos) /*!< 0x000002FC */
4125+#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
4126+
4127+/****************** Bit definition for EXTI_RTSR2 register ******************/
4128+#define EXTI_RTSR2_RT38_Pos (6U)
4129+#define EXTI_RTSR2_RT38_Msk (0x1UL << EXTI_RTSR2_RT38_Pos) /*!< 0x00000040 */
4130+#define EXTI_RTSR2_RT38 EXTI_RTSR2_RT38_Msk /*!< Rising trigger event configuration bit of line 38 */
4131+#define EXTI_RTSR2_RT39_Pos (7U)
4132+#define EXTI_RTSR2_RT39_Msk (0x1UL << EXTI_RTSR2_RT39_Pos) /*!< 0x00000080 */
4133+#define EXTI_RTSR2_RT39 EXTI_RTSR2_RT39_Msk /*!< Rising trigger event configuration bit of line 39 */
4134+#define EXTI_RTSR2_RT40_Pos (8U)
4135+#define EXTI_RTSR2_RT40_Msk (0x1UL << EXTI_RTSR2_RT40_Pos) /*!< 0x00000100 */
4136+#define EXTI_RTSR2_RT40 EXTI_RTSR2_RT40_Msk /*!< Rising trigger event configuration bit of line 40 */
4137+#define EXTI_RTSR2_RT41_Pos (9U)
4138+#define EXTI_RTSR2_RT41_Msk (0x1UL << EXTI_RTSR2_RT41_Pos) /*!< 0x00000200 */
4139+#define EXTI_RTSR2_RT41 EXTI_RTSR2_RT41_Msk /*!< Rising trigger event configuration bit of line 41 */
4140+
4141+/****************** Bit definition for EXTI_FTSR2 register ******************/
4142+#define EXTI_FTSR2_FT38_Pos (6U)
4143+#define EXTI_FTSR2_FT38_Msk (0x1UL << EXTI_FTSR2_FT38_Pos) /*!< 0x00000040 */
4144+#define EXTI_FTSR2_FT38 EXTI_FTSR2_FT38_Msk /*!< Falling trigger event configuration bit of line 37 */
4145+#define EXTI_FTSR2_FT39_Pos (7U)
4146+#define EXTI_FTSR2_FT39_Msk (0x1UL << EXTI_FTSR2_FT39_Pos) /*!< 0x00000080 */
4147+#define EXTI_FTSR2_FT39 EXTI_FTSR2_FT39_Msk /*!< Falling trigger event configuration bit of line 39 */
4148+#define EXTI_FTSR2_FT40_Pos (8U)
4149+#define EXTI_FTSR2_FT40_Msk (0x1UL << EXTI_FTSR2_FT40_Pos) /*!< 0x00000100 */
4150+#define EXTI_FTSR2_FT40 EXTI_FTSR2_FT40_Msk /*!< Falling trigger event configuration bit of line 40 */
4151+#define EXTI_FTSR2_FT41_Pos (9U)
4152+#define EXTI_FTSR2_FT41_Msk (0x1UL << EXTI_FTSR2_FT41_Pos) /*!< 0x00000200 */
4153+#define EXTI_FTSR2_FT41 EXTI_FTSR2_FT41_Msk /*!< Falling trigger event configuration bit of line 41 */
4154+
4155+/****************** Bit definition for EXTI_SWIER2 register *****************/
4156+#define EXTI_SWIER2_SWI38_Pos (6U)
4157+#define EXTI_SWIER2_SWI38_Msk (0x1UL << EXTI_SWIER2_SWI38_Pos) /*!< 0x00000040 */
4158+#define EXTI_SWIER2_SWI38 EXTI_SWIER2_SWI38_Msk /*!< Software Interrupt on line 38 */
4159+#define EXTI_SWIER2_SWI39_Pos (7U)
4160+#define EXTI_SWIER2_SWI39_Msk (0x1UL << EXTI_SWIER2_SWI39_Pos) /*!< 0x00000080 */
4161+#define EXTI_SWIER2_SWI39 EXTI_SWIER2_SWI39_Msk /*!< Software Interrupt on line 39 */
4162+#define EXTI_SWIER2_SWI40_Pos (8U)
4163+#define EXTI_SWIER2_SWI40_Msk (0x1UL << EXTI_SWIER2_SWI40_Pos) /*!< 0x00000100 */
4164+#define EXTI_SWIER2_SWI40 EXTI_SWIER2_SWI40_Msk /*!< Software Interrupt on line 40 */
4165+#define EXTI_SWIER2_SWI41_Pos (9U)
4166+#define EXTI_SWIER2_SWI41_Msk (0x1UL << EXTI_SWIER2_SWI41_Pos) /*!< 0x00000200 */
4167+#define EXTI_SWIER2_SWI41 EXTI_SWIER2_SWI41_Msk /*!< Software Interrupt on line 41 */
4168+
4169+/******************* Bit definition for EXTI_PR2 register *******************/
4170+#define EXTI_PR2_PIF38_Pos (6U)
4171+#define EXTI_PR2_PIF38_Msk (0x1UL << EXTI_PR2_PIF38_Pos) /*!< 0x00000040 */
4172+#define EXTI_PR2_PIF38 EXTI_PR2_PIF38_Msk /*!< Pending bit for line 38 */
4173+#define EXTI_PR2_PIF39_Pos (7U)
4174+#define EXTI_PR2_PIF39_Msk (0x1UL << EXTI_PR2_PIF39_Pos) /*!< 0x00000080 */
4175+#define EXTI_PR2_PIF39 EXTI_PR2_PIF39_Msk /*!< Pending bit for line 39 */
4176+#define EXTI_PR2_PIF40_Pos (8U)
4177+#define EXTI_PR2_PIF40_Msk (0x1UL << EXTI_PR2_PIF40_Pos) /*!< 0x00000100 */
4178+#define EXTI_PR2_PIF40 EXTI_PR2_PIF40_Msk /*!< Pending bit for line 40 */
4179+#define EXTI_PR2_PIF41_Pos (9U)
4180+#define EXTI_PR2_PIF41_Msk (0x1UL << EXTI_PR2_PIF41_Pos) /*!< 0x00000200 */
4181+#define EXTI_PR2_PIF41 EXTI_PR2_PIF41_Msk /*!< Pending bit for line 41 */
4182+
4183+/******************************************************************************/
4184+/* */
4185+/* Flexible Datarate Controller Area Network */
4186+/* */
4187+/******************************************************************************/
4188+/*!<FDCAN control and status registers */
4189+/***************** Bit definition for FDCAN_CREL register *******************/
4190+#define FDCAN_CREL_DAY_Pos (0U)
4191+#define FDCAN_CREL_DAY_Msk (0xFFUL << FDCAN_CREL_DAY_Pos) /*!< 0x000000FF */
4192+#define FDCAN_CREL_DAY FDCAN_CREL_DAY_Msk /*!<Timestamp Day */
4193+#define FDCAN_CREL_MON_Pos (8U)
4194+#define FDCAN_CREL_MON_Msk (0xFFUL << FDCAN_CREL_MON_Pos) /*!< 0x0000FF00 */
4195+#define FDCAN_CREL_MON FDCAN_CREL_MON_Msk /*!<Timestamp Month */
4196+#define FDCAN_CREL_YEAR_Pos (16U)
4197+#define FDCAN_CREL_YEAR_Msk (0xFUL << FDCAN_CREL_YEAR_Pos) /*!< 0x000F0000 */
4198+#define FDCAN_CREL_YEAR FDCAN_CREL_YEAR_Msk /*!<Timestamp Year */
4199+#define FDCAN_CREL_SUBSTEP_Pos (20U)
4200+#define FDCAN_CREL_SUBSTEP_Msk (0xFUL << FDCAN_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */
4201+#define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */
4202+#define FDCAN_CREL_STEP_Pos (24U)
4203+#define FDCAN_CREL_STEP_Msk (0xFUL << FDCAN_CREL_STEP_Pos) /*!< 0x0F000000 */
4204+#define FDCAN_CREL_STEP FDCAN_CREL_STEP_Msk /*!<Step of Core release */
4205+#define FDCAN_CREL_REL_Pos (28U)
4206+#define FDCAN_CREL_REL_Msk (0xFUL << FDCAN_CREL_REL_Pos) /*!< 0xF0000000 */
4207+#define FDCAN_CREL_REL FDCAN_CREL_REL_Msk /*!<Core release */
4208+
4209+/***************** Bit definition for FDCAN_ENDN register *******************/
4210+#define FDCAN_ENDN_ETV_Pos (0U)
4211+#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
4212+#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
4213+
4214+/***************** Bit definition for FDCAN_DBTP register *******************/
4215+#define FDCAN_DBTP_DSJW_Pos (0U)
4216+#define FDCAN_DBTP_DSJW_Msk (0xFUL << FDCAN_DBTP_DSJW_Pos) /*!< 0x0000000F */
4217+#define FDCAN_DBTP_DSJW FDCAN_DBTP_DSJW_Msk /*!<Synchronization Jump Width */
4218+#define FDCAN_DBTP_DTSEG2_Pos (4U)
4219+#define FDCAN_DBTP_DTSEG2_Msk (0xFUL << FDCAN_DBTP_DTSEG2_Pos) /*!< 0x000000F0 */
4220+#define FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_Msk /*!<Data time segment after sample point */
4221+#define FDCAN_DBTP_DTSEG1_Pos (8U)
4222+#define FDCAN_DBTP_DTSEG1_Msk (0x1FUL << FDCAN_DBTP_DTSEG1_Pos) /*!< 0x00001F00 */
4223+#define FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_Msk /*!<Data time segment before sample point */
4224+#define FDCAN_DBTP_DBRP_Pos (16U)
4225+#define FDCAN_DBTP_DBRP_Msk (0x1FUL << FDCAN_DBTP_DBRP_Pos) /*!< 0x001F0000 */
4226+#define FDCAN_DBTP_DBRP FDCAN_DBTP_DBRP_Msk /*!<Data BIt Rate Prescaler */
4227+#define FDCAN_DBTP_TDC_Pos (23U)
4228+#define FDCAN_DBTP_TDC_Msk (0x1UL << FDCAN_DBTP_TDC_Pos) /*!< 0x00800000 */
4229+#define FDCAN_DBTP_TDC FDCAN_DBTP_TDC_Msk /*!<Transceiver Delay Compensation */
4230+
4231+/***************** Bit definition for FDCAN_TEST register *******************/
4232+#define FDCAN_TEST_LBCK_Pos (4U)
4233+#define FDCAN_TEST_LBCK_Msk (0x1UL << FDCAN_TEST_LBCK_Pos) /*!< 0x00000010 */
4234+#define FDCAN_TEST_LBCK FDCAN_TEST_LBCK_Msk /*!<Loop Back mode */
4235+#define FDCAN_TEST_TX_Pos (5U)
4236+#define FDCAN_TEST_TX_Msk (0x3UL << FDCAN_TEST_TX_Pos) /*!< 0x00000060 */
4237+#define FDCAN_TEST_TX FDCAN_TEST_TX_Msk /*!<Control of Transmit Pin */
4238+#define FDCAN_TEST_RX_Pos (7U)
4239+#define FDCAN_TEST_RX_Msk (0x1UL << FDCAN_TEST_RX_Pos) /*!< 0x00000080 */
4240+#define FDCAN_TEST_RX FDCAN_TEST_RX_Msk /*!<Receive Pin */
4241+
4242+/***************** Bit definition for FDCAN_RWD register ********************/
4243+#define FDCAN_RWD_WDC_Pos (0U)
4244+#define FDCAN_RWD_WDC_Msk (0xFFUL << FDCAN_RWD_WDC_Pos) /*!< 0x000000FF */
4245+#define FDCAN_RWD_WDC FDCAN_RWD_WDC_Msk /*!<Watchdog configuration */
4246+#define FDCAN_RWD_WDV_Pos (8U)
4247+#define FDCAN_RWD_WDV_Msk (0xFFUL << FDCAN_RWD_WDV_Pos) /*!< 0x0000FF00 */
4248+#define FDCAN_RWD_WDV FDCAN_RWD_WDV_Msk /*!<Watchdog value */
4249+
4250+/***************** Bit definition for FDCAN_CCCR register ********************/
4251+#define FDCAN_CCCR_INIT_Pos (0U)
4252+#define FDCAN_CCCR_INIT_Msk (0x1UL << FDCAN_CCCR_INIT_Pos) /*!< 0x00000001 */
4253+#define FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk /*!<Initialization */
4254+#define FDCAN_CCCR_CCE_Pos (1U)
4255+#define FDCAN_CCCR_CCE_Msk (0x1UL << FDCAN_CCCR_CCE_Pos) /*!< 0x00000002 */
4256+#define FDCAN_CCCR_CCE FDCAN_CCCR_CCE_Msk /*!<Configuration Change Enable */
4257+#define FDCAN_CCCR_ASM_Pos (2U)
4258+#define FDCAN_CCCR_ASM_Msk (0x1UL << FDCAN_CCCR_ASM_Pos) /*!< 0x00000004 */
4259+#define FDCAN_CCCR_ASM FDCAN_CCCR_ASM_Msk /*!<ASM Restricted Operation Mode */
4260+#define FDCAN_CCCR_CSA_Pos (3U)
4261+#define FDCAN_CCCR_CSA_Msk (0x1UL << FDCAN_CCCR_CSA_Pos) /*!< 0x00000008 */
4262+#define FDCAN_CCCR_CSA FDCAN_CCCR_CSA_Msk /*!<Clock Stop Acknowledge */
4263+#define FDCAN_CCCR_CSR_Pos (4U)
4264+#define FDCAN_CCCR_CSR_Msk (0x1UL << FDCAN_CCCR_CSR_Pos) /*!< 0x00000010 */
4265+#define FDCAN_CCCR_CSR FDCAN_CCCR_CSR_Msk /*!<Clock Stop Request */
4266+#define FDCAN_CCCR_MON_Pos (5U)
4267+#define FDCAN_CCCR_MON_Msk (0x1UL << FDCAN_CCCR_MON_Pos) /*!< 0x00000020 */
4268+#define FDCAN_CCCR_MON FDCAN_CCCR_MON_Msk /*!<Bus Monitoring Mode */
4269+#define FDCAN_CCCR_DAR_Pos (6U)
4270+#define FDCAN_CCCR_DAR_Msk (0x1UL << FDCAN_CCCR_DAR_Pos) /*!< 0x00000040 */
4271+#define FDCAN_CCCR_DAR FDCAN_CCCR_DAR_Msk /*!<Disable Automatic Retransmission */
4272+#define FDCAN_CCCR_TEST_Pos (7U)
4273+#define FDCAN_CCCR_TEST_Msk (0x1UL << FDCAN_CCCR_TEST_Pos) /*!< 0x00000080 */
4274+#define FDCAN_CCCR_TEST FDCAN_CCCR_TEST_Msk /*!<Test Mode Enable */
4275+#define FDCAN_CCCR_FDOE_Pos (8U)
4276+#define FDCAN_CCCR_FDOE_Msk (0x1UL << FDCAN_CCCR_FDOE_Pos) /*!< 0x00000100 */
4277+#define FDCAN_CCCR_FDOE FDCAN_CCCR_FDOE_Msk /*!<FD Operation Enable */
4278+#define FDCAN_CCCR_BRSE_Pos (9U)
4279+#define FDCAN_CCCR_BRSE_Msk (0x1UL << FDCAN_CCCR_BRSE_Pos) /*!< 0x00000200 */
4280+#define FDCAN_CCCR_BRSE FDCAN_CCCR_BRSE_Msk /*!<FDCAN Bit Rate Switching */
4281+#define FDCAN_CCCR_PXHD_Pos (12U)
4282+#define FDCAN_CCCR_PXHD_Msk (0x1UL << FDCAN_CCCR_PXHD_Pos) /*!< 0x00001000 */
4283+#define FDCAN_CCCR_PXHD FDCAN_CCCR_PXHD_Msk /*!<Protocol Exception Handling Disable */
4284+#define FDCAN_CCCR_EFBI_Pos (13U)
4285+#define FDCAN_CCCR_EFBI_Msk (0x1UL << FDCAN_CCCR_EFBI_Pos) /*!< 0x00002000 */
4286+#define FDCAN_CCCR_EFBI FDCAN_CCCR_EFBI_Msk /*!<Edge Filtering during Bus Integration */
4287+#define FDCAN_CCCR_TXP_Pos (14U)
4288+#define FDCAN_CCCR_TXP_Msk (0x1UL << FDCAN_CCCR_TXP_Pos) /*!< 0x00004000 */
4289+#define FDCAN_CCCR_TXP FDCAN_CCCR_TXP_Msk /*!<Two CAN bit times Pause */
4290+#define FDCAN_CCCR_NISO_Pos (15U)
4291+#define FDCAN_CCCR_NISO_Msk (0x1UL << FDCAN_CCCR_NISO_Pos) /*!< 0x00008000 */
4292+#define FDCAN_CCCR_NISO FDCAN_CCCR_NISO_Msk /*!<Non ISO Operation */
4293+
4294+/***************** Bit definition for FDCAN_NBTP register ********************/
4295+#define FDCAN_NBTP_NTSEG2_Pos (0U)
4296+#define FDCAN_NBTP_NTSEG2_Msk (0x7FUL << FDCAN_NBTP_NTSEG2_Pos) /*!< 0x0000007F */
4297+#define FDCAN_NBTP_NTSEG2 FDCAN_NBTP_NTSEG2_Msk /*!<Nominal Time segment after sample point */
4298+#define FDCAN_NBTP_NTSEG1_Pos (8U)
4299+#define FDCAN_NBTP_NTSEG1_Msk (0xFFUL << FDCAN_NBTP_NTSEG1_Pos) /*!< 0x0000FF00 */
4300+#define FDCAN_NBTP_NTSEG1 FDCAN_NBTP_NTSEG1_Msk /*!<Nominal Time segment before sample point */
4301+#define FDCAN_NBTP_NBRP_Pos (16U)
4302+#define FDCAN_NBTP_NBRP_Msk (0x1FFUL << FDCAN_NBTP_NBRP_Pos) /*!< 0x01FF0000 */
4303+#define FDCAN_NBTP_NBRP FDCAN_NBTP_NBRP_Msk /*!<Bit Rate Prescaler */
4304+#define FDCAN_NBTP_NSJW_Pos (25U)
4305+#define FDCAN_NBTP_NSJW_Msk (0x7FUL << FDCAN_NBTP_NSJW_Pos) /*!< 0xFE000000 */
4306+#define FDCAN_NBTP_NSJW FDCAN_NBTP_NSJW_Msk /*!<Nominal (Re)Synchronization Jump Width */
4307+
4308+/***************** Bit definition for FDCAN_TSCC register ********************/
4309+#define FDCAN_TSCC_TSS_Pos (0U)
4310+#define FDCAN_TSCC_TSS_Msk (0x3UL << FDCAN_TSCC_TSS_Pos) /*!< 0x00000003 */
4311+#define FDCAN_TSCC_TSS FDCAN_TSCC_TSS_Msk /*!<Timestamp Select */
4312+#define FDCAN_TSCC_TCP_Pos (16U)
4313+#define FDCAN_TSCC_TCP_Msk (0xFUL << FDCAN_TSCC_TCP_Pos) /*!< 0x000F0000 */
4314+#define FDCAN_TSCC_TCP FDCAN_TSCC_TCP_Msk /*!<Timestamp Counter Prescaler */
4315+
4316+/***************** Bit definition for FDCAN_TSCV register ********************/
4317+#define FDCAN_TSCV_TSC_Pos (0U)
4318+#define FDCAN_TSCV_TSC_Msk (0xFFFFUL << FDCAN_TSCV_TSC_Pos) /*!< 0x0000FFFF */
4319+#define FDCAN_TSCV_TSC FDCAN_TSCV_TSC_Msk /*!<Timestamp Counter */
4320+
4321+/***************** Bit definition for FDCAN_TOCC register ********************/
4322+#define FDCAN_TOCC_ETOC_Pos (0U)
4323+#define FDCAN_TOCC_ETOC_Msk (0x1UL << FDCAN_TOCC_ETOC_Pos) /*!< 0x00000001 */
4324+#define FDCAN_TOCC_ETOC FDCAN_TOCC_ETOC_Msk /*!<Enable Timeout Counter */
4325+#define FDCAN_TOCC_TOS_Pos (1U)
4326+#define FDCAN_TOCC_TOS_Msk (0x3UL << FDCAN_TOCC_TOS_Pos) /*!< 0x00000006 */
4327+#define FDCAN_TOCC_TOS FDCAN_TOCC_TOS_Msk /*!<Timeout Select */
4328+#define FDCAN_TOCC_TOP_Pos (16U)
4329+#define FDCAN_TOCC_TOP_Msk (0xFFFFUL << FDCAN_TOCC_TOP_Pos) /*!< 0xFFFF0000 */
4330+#define FDCAN_TOCC_TOP FDCAN_TOCC_TOP_Msk /*!<Timeout Period */
4331+
4332+/***************** Bit definition for FDCAN_TOCV register ********************/
4333+#define FDCAN_TOCV_TOC_Pos (0U)
4334+#define FDCAN_TOCV_TOC_Msk (0xFFFFUL << FDCAN_TOCV_TOC_Pos) /*!< 0x0000FFFF */
4335+#define FDCAN_TOCV_TOC FDCAN_TOCV_TOC_Msk /*!<Timeout Counter */
4336+
4337+/***************** Bit definition for FDCAN_ECR register *********************/
4338+#define FDCAN_ECR_TEC_Pos (0U)
4339+#define FDCAN_ECR_TEC_Msk (0xFFUL << FDCAN_ECR_TEC_Pos) /*!< 0x000000FF */
4340+#define FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk /*!<Transmit Error Counter */
4341+#define FDCAN_ECR_REC_Pos (8U)
4342+#define FDCAN_ECR_REC_Msk (0x7FUL << FDCAN_ECR_REC_Pos) /*!< 0x00007F00 */
4343+#define FDCAN_ECR_REC FDCAN_ECR_REC_Msk /*!<Receive Error Counter */
4344+#define FDCAN_ECR_RP_Pos (15U)
4345+#define FDCAN_ECR_RP_Msk (0x1UL << FDCAN_ECR_RP_Pos) /*!< 0x00008000 */
4346+#define FDCAN_ECR_RP FDCAN_ECR_RP_Msk /*!<Receive Error Passive */
4347+#define FDCAN_ECR_CEL_Pos (16U)
4348+#define FDCAN_ECR_CEL_Msk (0xFFUL << FDCAN_ECR_CEL_Pos) /*!< 0x00FF0000 */
4349+#define FDCAN_ECR_CEL FDCAN_ECR_CEL_Msk /*!<CAN Error Logging */
4350+
4351+/***************** Bit definition for FDCAN_PSR register *********************/
4352+#define FDCAN_PSR_LEC_Pos (0U)
4353+#define FDCAN_PSR_LEC_Msk (0x7UL << FDCAN_PSR_LEC_Pos) /*!< 0x00000007 */
4354+#define FDCAN_PSR_LEC FDCAN_PSR_LEC_Msk /*!<Last Error Code */
4355+#define FDCAN_PSR_ACT_Pos (3U)
4356+#define FDCAN_PSR_ACT_Msk (0x3UL << FDCAN_PSR_ACT_Pos) /*!< 0x00000018 */
4357+#define FDCAN_PSR_ACT FDCAN_PSR_ACT_Msk /*!<Activity */
4358+#define FDCAN_PSR_EP_Pos (5U)
4359+#define FDCAN_PSR_EP_Msk (0x1UL << FDCAN_PSR_EP_Pos) /*!< 0x00000020 */
4360+#define FDCAN_PSR_EP FDCAN_PSR_EP_Msk /*!<Error Passive */
4361+#define FDCAN_PSR_EW_Pos (6U)
4362+#define FDCAN_PSR_EW_Msk (0x1UL << FDCAN_PSR_EW_Pos) /*!< 0x00000040 */
4363+#define FDCAN_PSR_EW FDCAN_PSR_EW_Msk /*!<Warning Status */
4364+#define FDCAN_PSR_BO_Pos (7U)
4365+#define FDCAN_PSR_BO_Msk (0x1UL << FDCAN_PSR_BO_Pos) /*!< 0x00000080 */
4366+#define FDCAN_PSR_BO FDCAN_PSR_BO_Msk /*!<Bus_Off Status */
4367+#define FDCAN_PSR_DLEC_Pos (8U)
4368+#define FDCAN_PSR_DLEC_Msk (0x7UL << FDCAN_PSR_DLEC_Pos) /*!< 0x00000700 */
4369+#define FDCAN_PSR_DLEC FDCAN_PSR_DLEC_Msk /*!<Data Last Error Code */
4370+#define FDCAN_PSR_RESI_Pos (11U)
4371+#define FDCAN_PSR_RESI_Msk (0x1UL << FDCAN_PSR_RESI_Pos) /*!< 0x00000800 */
4372+#define FDCAN_PSR_RESI FDCAN_PSR_RESI_Msk /*!<ESI flag of last received FDCAN Message */
4373+#define FDCAN_PSR_RBRS_Pos (12U)
4374+#define FDCAN_PSR_RBRS_Msk (0x1UL << FDCAN_PSR_RBRS_Pos) /*!< 0x00001000 */
4375+#define FDCAN_PSR_RBRS FDCAN_PSR_RBRS_Msk /*!<BRS flag of last received FDCAN Message */
4376+#define FDCAN_PSR_REDL_Pos (13U)
4377+#define FDCAN_PSR_REDL_Msk (0x1UL << FDCAN_PSR_REDL_Pos) /*!< 0x00002000 */
4378+#define FDCAN_PSR_REDL FDCAN_PSR_REDL_Msk /*!<Received FDCAN Message */
4379+#define FDCAN_PSR_PXE_Pos (14U)
4380+#define FDCAN_PSR_PXE_Msk (0x1UL << FDCAN_PSR_PXE_Pos) /*!< 0x00004000 */
4381+#define FDCAN_PSR_PXE FDCAN_PSR_PXE_Msk /*!<Protocol Exception Event */
4382+#define FDCAN_PSR_TDCV_Pos (16U)
4383+#define FDCAN_PSR_TDCV_Msk (0x7FUL << FDCAN_PSR_TDCV_Pos) /*!< 0x007F0000 */
4384+#define FDCAN_PSR_TDCV FDCAN_PSR_TDCV_Msk /*!<Transmitter Delay Compensation Value */
4385+
4386+/***************** Bit definition for FDCAN_TDCR register ********************/
4387+#define FDCAN_TDCR_TDCF_Pos (0U)
4388+#define FDCAN_TDCR_TDCF_Msk (0x7FUL << FDCAN_TDCR_TDCF_Pos) /*!< 0x0000007F */
4389+#define FDCAN_TDCR_TDCF FDCAN_TDCR_TDCF_Msk /*!<Transmitter Delay Compensation Filter */
4390+#define FDCAN_TDCR_TDCO_Pos (8U)
4391+#define FDCAN_TDCR_TDCO_Msk (0x7FUL << FDCAN_TDCR_TDCO_Pos) /*!< 0x00007F00 */
4392+#define FDCAN_TDCR_TDCO FDCAN_TDCR_TDCO_Msk /*!<Transmitter Delay Compensation Offset */
4393+
4394+/***************** Bit definition for FDCAN_IR register **********************/
4395+#define FDCAN_IR_RF0N_Pos (0U)
4396+#define FDCAN_IR_RF0N_Msk (0x1UL << FDCAN_IR_RF0N_Pos) /*!< 0x00000001 */
4397+#define FDCAN_IR_RF0N FDCAN_IR_RF0N_Msk /*!<Rx FIFO 0 New Message */
4398+#define FDCAN_IR_RF0F_Pos (1U)
4399+#define FDCAN_IR_RF0F_Msk (0x1UL << FDCAN_IR_RF0F_Pos) /*!< 0x00000002 */
4400+#define FDCAN_IR_RF0F FDCAN_IR_RF0F_Msk /*!<Rx FIFO 0 Full */
4401+#define FDCAN_IR_RF0L_Pos (2U)
4402+#define FDCAN_IR_RF0L_Msk (0x1UL << FDCAN_IR_RF0L_Pos) /*!< 0x00000004 */
4403+#define FDCAN_IR_RF0L FDCAN_IR_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
4404+#define FDCAN_IR_RF1N_Pos (3U)
4405+#define FDCAN_IR_RF1N_Msk (0x1UL << FDCAN_IR_RF1N_Pos) /*!< 0x00000008 */
4406+#define FDCAN_IR_RF1N FDCAN_IR_RF1N_Msk /*!<Rx FIFO 1 New Message */
4407+#define FDCAN_IR_RF1F_Pos (4U)
4408+#define FDCAN_IR_RF1F_Msk (0x1UL << FDCAN_IR_RF1F_Pos) /*!< 0x00000010 */
4409+#define FDCAN_IR_RF1F FDCAN_IR_RF1F_Msk /*!<Rx FIFO 1 Full */
4410+#define FDCAN_IR_RF1L_Pos (5U)
4411+#define FDCAN_IR_RF1L_Msk (0x1UL << FDCAN_IR_RF1L_Pos) /*!< 0x00000020 */
4412+#define FDCAN_IR_RF1L FDCAN_IR_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
4413+#define FDCAN_IR_HPM_Pos (6U)
4414+#define FDCAN_IR_HPM_Msk (0x1UL << FDCAN_IR_HPM_Pos) /*!< 0x00000040 */
4415+#define FDCAN_IR_HPM FDCAN_IR_HPM_Msk /*!<High Priority Message */
4416+#define FDCAN_IR_TC_Pos (7U)
4417+#define FDCAN_IR_TC_Msk (0x1UL << FDCAN_IR_TC_Pos) /*!< 0x00000080 */
4418+#define FDCAN_IR_TC FDCAN_IR_TC_Msk /*!<Transmission Completed */
4419+#define FDCAN_IR_TCF_Pos (8U)
4420+#define FDCAN_IR_TCF_Msk (0x1UL << FDCAN_IR_TCF_Pos) /*!< 0x00000100 */
4421+#define FDCAN_IR_TCF FDCAN_IR_TCF_Msk /*!<Transmission Cancellation Finished */
4422+#define FDCAN_IR_TFE_Pos (9U)
4423+#define FDCAN_IR_TFE_Msk (0x1UL << FDCAN_IR_TFE_Pos) /*!< 0x00000200 */
4424+#define FDCAN_IR_TFE FDCAN_IR_TFE_Msk /*!<Tx FIFO Empty */
4425+#define FDCAN_IR_TEFN_Pos (10U)
4426+#define FDCAN_IR_TEFN_Msk (0x1UL << FDCAN_IR_TEFN_Pos) /*!< 0x00000400 */
4427+#define FDCAN_IR_TEFN FDCAN_IR_TEFN_Msk /*!<Tx Event FIFO New Entry */
4428+#define FDCAN_IR_TEFF_Pos (11U)
4429+#define FDCAN_IR_TEFF_Msk (0x1UL << FDCAN_IR_TEFF_Pos) /*!< 0x00000800 */
4430+#define FDCAN_IR_TEFF FDCAN_IR_TEFF_Msk /*!<Tx Event FIFO Full */
4431+#define FDCAN_IR_TEFL_Pos (12U)
4432+#define FDCAN_IR_TEFL_Msk (0x1UL << FDCAN_IR_TEFL_Pos) /*!< 0x00001000 */
4433+#define FDCAN_IR_TEFL FDCAN_IR_TEFL_Msk /*!<Tx Event FIFO Element Lost */
4434+#define FDCAN_IR_TSW_Pos (13U)
4435+#define FDCAN_IR_TSW_Msk (0x1UL << FDCAN_IR_TSW_Pos) /*!< 0x00002000 */
4436+#define FDCAN_IR_TSW FDCAN_IR_TSW_Msk /*!<Timestamp Wraparound */
4437+#define FDCAN_IR_MRAF_Pos (14U)
4438+#define FDCAN_IR_MRAF_Msk (0x1UL << FDCAN_IR_MRAF_Pos) /*!< 0x00004000 */
4439+#define FDCAN_IR_MRAF FDCAN_IR_MRAF_Msk /*!<Message RAM Access Failure */
4440+#define FDCAN_IR_TOO_Pos (15U)
4441+#define FDCAN_IR_TOO_Msk (0x1UL << FDCAN_IR_TOO_Pos) /*!< 0x00008000 */
4442+#define FDCAN_IR_TOO FDCAN_IR_TOO_Msk /*!<Timeout Occurred */
4443+#define FDCAN_IR_ELO_Pos (16U)
4444+#define FDCAN_IR_ELO_Msk (0x1UL << FDCAN_IR_ELO_Pos) /*!< 0x00010000 */
4445+#define FDCAN_IR_ELO FDCAN_IR_ELO_Msk /*!<Error Logging Overflow */
4446+#define FDCAN_IR_EP_Pos (17U)
4447+#define FDCAN_IR_EP_Msk (0x1UL << FDCAN_IR_EP_Pos) /*!< 0x00020000 */
4448+#define FDCAN_IR_EP FDCAN_IR_EP_Msk /*!<Error Passive */
4449+#define FDCAN_IR_EW_Pos (18U)
4450+#define FDCAN_IR_EW_Msk (0x1UL << FDCAN_IR_EW_Pos) /*!< 0x00040000 */
4451+#define FDCAN_IR_EW FDCAN_IR_EW_Msk /*!<Warning Status */
4452+#define FDCAN_IR_BO_Pos (19U)
4453+#define FDCAN_IR_BO_Msk (0x1UL << FDCAN_IR_BO_Pos) /*!< 0x00080000 */
4454+#define FDCAN_IR_BO FDCAN_IR_BO_Msk /*!<Bus_Off Status */
4455+#define FDCAN_IR_WDI_Pos (20U)
4456+#define FDCAN_IR_WDI_Msk (0x1UL << FDCAN_IR_WDI_Pos) /*!< 0x00100000 */
4457+#define FDCAN_IR_WDI FDCAN_IR_WDI_Msk /*!<Watchdog Interrupt */
4458+#define FDCAN_IR_PEA_Pos (21U)
4459+#define FDCAN_IR_PEA_Msk (0x1UL << FDCAN_IR_PEA_Pos) /*!< 0x00200000 */
4460+#define FDCAN_IR_PEA FDCAN_IR_PEA_Msk /*!<Protocol Error in Arbitration Phase */
4461+#define FDCAN_IR_PED_Pos (22U)
4462+#define FDCAN_IR_PED_Msk (0x1UL << FDCAN_IR_PED_Pos) /*!< 0x00400000 */
4463+#define FDCAN_IR_PED FDCAN_IR_PED_Msk /*!<Protocol Error in Data Phase */
4464+#define FDCAN_IR_ARA_Pos (23U)
4465+#define FDCAN_IR_ARA_Msk (0x1UL << FDCAN_IR_ARA_Pos) /*!< 0x00800000 */
4466+#define FDCAN_IR_ARA FDCAN_IR_ARA_Msk /*!<Access to Reserved Address */
4467+
4468+/***************** Bit definition for FDCAN_IE register **********************/
4469+#define FDCAN_IE_RF0NE_Pos (0U)
4470+#define FDCAN_IE_RF0NE_Msk (0x1UL << FDCAN_IE_RF0NE_Pos) /*!< 0x00000001 */
4471+#define FDCAN_IE_RF0NE FDCAN_IE_RF0NE_Msk /*!<Rx FIFO 0 New Message Enable */
4472+#define FDCAN_IE_RF0FE_Pos (1U)
4473+#define FDCAN_IE_RF0FE_Msk (0x1UL << FDCAN_IE_RF0FE_Pos) /*!< 0x00000002 */
4474+#define FDCAN_IE_RF0FE FDCAN_IE_RF0FE_Msk /*!<Rx FIFO 0 Full Enable */
4475+#define FDCAN_IE_RF0LE_Pos (2U)
4476+#define FDCAN_IE_RF0LE_Msk (0x1UL << FDCAN_IE_RF0LE_Pos) /*!< 0x00000004 */
4477+#define FDCAN_IE_RF0LE FDCAN_IE_RF0LE_Msk /*!<Rx FIFO 0 Message Lost Enable */
4478+#define FDCAN_IE_RF1NE_Pos (3U)
4479+#define FDCAN_IE_RF1NE_Msk (0x1UL << FDCAN_IE_RF1NE_Pos) /*!< 0x00000008 */
4480+#define FDCAN_IE_RF1NE FDCAN_IE_RF1NE_Msk /*!<Rx FIFO 1 New Message Enable */
4481+#define FDCAN_IE_RF1FE_Pos (4U)
4482+#define FDCAN_IE_RF1FE_Msk (0x1UL << FDCAN_IE_RF1FE_Pos) /*!< 0x00000010 */
4483+#define FDCAN_IE_RF1FE FDCAN_IE_RF1FE_Msk /*!<Rx FIFO 1 Full Enable */
4484+#define FDCAN_IE_RF1LE_Pos (5U)
4485+#define FDCAN_IE_RF1LE_Msk (0x1UL << FDCAN_IE_RF1LE_Pos) /*!< 0x00000020 */
4486+#define FDCAN_IE_RF1LE FDCAN_IE_RF1LE_Msk /*!<Rx FIFO 1 Message Lost Enable */
4487+#define FDCAN_IE_HPME_Pos (6U)
4488+#define FDCAN_IE_HPME_Msk (0x1UL << FDCAN_IE_HPME_Pos) /*!< 0x00000040 */
4489+#define FDCAN_IE_HPME FDCAN_IE_HPME_Msk /*!<High Priority Message Enable */
4490+#define FDCAN_IE_TCE_Pos (7U)
4491+#define FDCAN_IE_TCE_Msk (0x1UL << FDCAN_IE_TCE_Pos) /*!< 0x00000080 */
4492+#define FDCAN_IE_TCE FDCAN_IE_TCE_Msk /*!<Transmission Completed Enable */
4493+#define FDCAN_IE_TCFE_Pos (8U)
4494+#define FDCAN_IE_TCFE_Msk (0x1UL << FDCAN_IE_TCFE_Pos) /*!< 0x00000100 */
4495+#define FDCAN_IE_TCFE FDCAN_IE_TCFE_Msk /*!<Transmission Cancellation Finished Enable*/
4496+#define FDCAN_IE_TFEE_Pos (9U)
4497+#define FDCAN_IE_TFEE_Msk (0x1UL << FDCAN_IE_TFEE_Pos) /*!< 0x00000200 */
4498+#define FDCAN_IE_TFEE FDCAN_IE_TFEE_Msk /*!<Tx FIFO Empty Enable */
4499+#define FDCAN_IE_TEFNE_Pos (10U)
4500+#define FDCAN_IE_TEFNE_Msk (0x1UL << FDCAN_IE_TEFNE_Pos) /*!< 0x00000400 */
4501+#define FDCAN_IE_TEFNE FDCAN_IE_TEFNE_Msk /*!<Tx Event FIFO New Entry Enable */
4502+#define FDCAN_IE_TEFFE_Pos (11U)
4503+#define FDCAN_IE_TEFFE_Msk (0x1UL << FDCAN_IE_TEFFE_Pos) /*!< 0x00000800 */
4504+#define FDCAN_IE_TEFFE FDCAN_IE_TEFFE_Msk /*!<Tx Event FIFO Full Enable */
4505+#define FDCAN_IE_TEFLE_Pos (12U)
4506+#define FDCAN_IE_TEFLE_Msk (0x1UL << FDCAN_IE_TEFLE_Pos) /*!< 0x00001000 */
4507+#define FDCAN_IE_TEFLE FDCAN_IE_TEFLE_Msk /*!<Tx Event FIFO Element Lost Enable */
4508+#define FDCAN_IE_TSWE_Pos (13U)
4509+#define FDCAN_IE_TSWE_Msk (0x1UL << FDCAN_IE_TSWE_Pos) /*!< 0x00002000 */
4510+#define FDCAN_IE_TSWE FDCAN_IE_TSWE_Msk /*!<Timestamp Wraparound Enable */
4511+#define FDCAN_IE_MRAFE_Pos (14U)
4512+#define FDCAN_IE_MRAFE_Msk (0x1UL << FDCAN_IE_MRAFE_Pos) /*!< 0x00004000 */
4513+#define FDCAN_IE_MRAFE FDCAN_IE_MRAFE_Msk /*!<Message RAM Access Failure Enable */
4514+#define FDCAN_IE_TOOE_Pos (15U)
4515+#define FDCAN_IE_TOOE_Msk (0x1UL << FDCAN_IE_TOOE_Pos) /*!< 0x00008000 */
4516+#define FDCAN_IE_TOOE FDCAN_IE_TOOE_Msk /*!<Timeout Occurred Enable */
4517+#define FDCAN_IE_ELOE_Pos (16U)
4518+#define FDCAN_IE_ELOE_Msk (0x1UL << FDCAN_IE_ELOE_Pos) /*!< 0x00010000 */
4519+#define FDCAN_IE_ELOE FDCAN_IE_ELOE_Msk /*!<Error Logging Overflow Enable */
4520+#define FDCAN_IE_EPE_Pos (17U)
4521+#define FDCAN_IE_EPE_Msk (0x1UL << FDCAN_IE_EPE_Pos) /*!< 0x00020000 */
4522+#define FDCAN_IE_EPE FDCAN_IE_EPE_Msk /*!<Error Passive Enable */
4523+#define FDCAN_IE_EWE_Pos (18U)
4524+#define FDCAN_IE_EWE_Msk (0x1UL << FDCAN_IE_EWE_Pos) /*!< 0x00040000 */
4525+#define FDCAN_IE_EWE FDCAN_IE_EWE_Msk /*!<Warning Status Enable */
4526+#define FDCAN_IE_BOE_Pos (19U)
4527+#define FDCAN_IE_BOE_Msk (0x1UL << FDCAN_IE_BOE_Pos) /*!< 0x00080000 */
4528+#define FDCAN_IE_BOE FDCAN_IE_BOE_Msk /*!<Bus_Off Status Enable */
4529+#define FDCAN_IE_WDIE_Pos (20U)
4530+#define FDCAN_IE_WDIE_Msk (0x1UL << FDCAN_IE_WDIE_Pos) /*!< 0x00100000 */
4531+#define FDCAN_IE_WDIE FDCAN_IE_WDIE_Msk /*!<Watchdog Interrupt Enable */
4532+#define FDCAN_IE_PEAE_Pos (21U)
4533+#define FDCAN_IE_PEAE_Msk (0x1UL << FDCAN_IE_PEAE_Pos) /*!< 0x00200000 */
4534+#define FDCAN_IE_PEAE FDCAN_IE_PEAE_Msk /*!<Protocol Error in Arbitration Phase Enable*/
4535+#define FDCAN_IE_PEDE_Pos (22U)
4536+#define FDCAN_IE_PEDE_Msk (0x1UL << FDCAN_IE_PEDE_Pos) /*!< 0x00400000 */
4537+#define FDCAN_IE_PEDE FDCAN_IE_PEDE_Msk /*!<Protocol Error in Data Phase Enable */
4538+#define FDCAN_IE_ARAE_Pos (23U)
4539+#define FDCAN_IE_ARAE_Msk (0x1UL << FDCAN_IE_ARAE_Pos) /*!< 0x00800000 */
4540+#define FDCAN_IE_ARAE FDCAN_IE_ARAE_Msk /*!<Access to Reserved Address Enable */
4541+
4542+/***************** Bit definition for FDCAN_ILS register **********************/
4543+#define FDCAN_ILS_RXFIFO0_Pos (0U)
4544+#define FDCAN_ILS_RXFIFO0_Msk (0x1UL << FDCAN_ILS_RXFIFO0_Pos) /*!< 0x00000001 */
4545+#define FDCAN_ILS_RXFIFO0 FDCAN_ILS_RXFIFO0_Msk /*!<Rx FIFO 0 Message Lost
4546+ Rx FIFO 0 is Full
4547+ Rx FIFO 0 Has New Message */
4548+#define FDCAN_ILS_RXFIFO1_Pos (1U)
4549+#define FDCAN_ILS_RXFIFO1_Msk (0x1UL << FDCAN_ILS_RXFIFO1_Pos) /*!< 0x00000002 */
4550+#define FDCAN_ILS_RXFIFO1 FDCAN_ILS_RXFIFO1_Msk /*!<Rx FIFO 1 Message Lost
4551+ Rx FIFO 1 is Full
4552+ Rx FIFO 1 Has New Message */
4553+#define FDCAN_ILS_SMSG_Pos (2U)
4554+#define FDCAN_ILS_SMSG_Msk (0x1UL << FDCAN_ILS_SMSG_Pos) /*!< 0x00000004 */
4555+#define FDCAN_ILS_SMSG FDCAN_ILS_SMSG_Msk /*!<Transmission Cancellation Finished
4556+ Transmission Completed
4557+ High Priority Message */
4558+#define FDCAN_ILS_TFERR_Pos (3U)
4559+#define FDCAN_ILS_TFERR_Msk (0x1UL << FDCAN_ILS_TFERR_Pos) /*!< 0x00000008 */
4560+#define FDCAN_ILS_TFERR FDCAN_ILS_TFERR_Msk /*!<Tx Event FIFO Element Lost
4561+ Tx Event FIFO Full
4562+ Tx Event FIFO New Entry
4563+ Tx FIFO Empty Interrupt Line */
4564+#define FDCAN_ILS_MISC_Pos (4U)
4565+#define FDCAN_ILS_MISC_Msk (0x1UL << FDCAN_ILS_MISC_Pos) /*!< 0x00000010 */
4566+#define FDCAN_ILS_MISC FDCAN_ILS_MISC_Msk /*!<Timeout Occurred
4567+ Message RAM Access Failure
4568+ Timestamp Wraparound */
4569+#define FDCAN_ILS_BERR_Pos (5U)
4570+#define FDCAN_ILS_BERR_Msk (0x1UL << FDCAN_ILS_BERR_Pos) /*!< 0x00000020 */
4571+#define FDCAN_ILS_BERR FDCAN_ILS_BERR_Msk /*!<Error Passive
4572+ Error Logging Overflow */
4573+#define FDCAN_ILS_PERR_Pos (6U)
4574+#define FDCAN_ILS_PERR_Msk (0x1UL << FDCAN_ILS_PERR_Pos) /*!< 0x00000040 */
4575+#define FDCAN_ILS_PERR FDCAN_ILS_PERR_Msk /*!<Access to Reserved Address Line
4576+ Protocol Error in Data Phase Line
4577+ Protocol Error in Arbitration Phase Line
4578+ Watchdog Interrupt Line
4579+ Bus_Off Status
4580+ Warning Status */
4581+
4582+/***************** Bit definition for FDCAN_ILE register **********************/
4583+#define FDCAN_ILE_EINT0_Pos (0U)
4584+#define FDCAN_ILE_EINT0_Msk (0x1UL << FDCAN_ILE_EINT0_Pos) /*!< 0x00000001 */
4585+#define FDCAN_ILE_EINT0 FDCAN_ILE_EINT0_Msk /*!<Enable Interrupt Line 0 */
4586+#define FDCAN_ILE_EINT1_Pos (1U)
4587+#define FDCAN_ILE_EINT1_Msk (0x1UL << FDCAN_ILE_EINT1_Pos) /*!< 0x00000002 */
4588+#define FDCAN_ILE_EINT1 FDCAN_ILE_EINT1_Msk /*!<Enable Interrupt Line 1 */
4589+
4590+/***************** Bit definition for FDCAN_RXGFC register ********************/
4591+#define FDCAN_RXGFC_RRFE_Pos (0U)
4592+#define FDCAN_RXGFC_RRFE_Msk (0x1UL << FDCAN_RXGFC_RRFE_Pos) /*!< 0x00000001 */
4593+#define FDCAN_RXGFC_RRFE FDCAN_RXGFC_RRFE_Msk /*!<Reject Remote Frames Extended */
4594+#define FDCAN_RXGFC_RRFS_Pos (1U)
4595+#define FDCAN_RXGFC_RRFS_Msk (0x1UL << FDCAN_RXGFC_RRFS_Pos) /*!< 0x00000002 */
4596+#define FDCAN_RXGFC_RRFS FDCAN_RXGFC_RRFS_Msk /*!<Reject Remote Frames Standard */
4597+#define FDCAN_RXGFC_ANFE_Pos (2U)
4598+#define FDCAN_RXGFC_ANFE_Msk (0x3UL << FDCAN_RXGFC_ANFE_Pos) /*!< 0x0000000C */
4599+#define FDCAN_RXGFC_ANFE FDCAN_RXGFC_ANFE_Msk /*!<Accept Non-matching Frames Extended */
4600+#define FDCAN_RXGFC_ANFS_Pos (4U)
4601+#define FDCAN_RXGFC_ANFS_Msk (0x3UL << FDCAN_RXGFC_ANFS_Pos) /*!< 0x00000030 */
4602+#define FDCAN_RXGFC_ANFS FDCAN_RXGFC_ANFS_Msk /*!<Accept Non-matching Frames Standard */
4603+#define FDCAN_RXGFC_F1OM_Pos (8U)
4604+#define FDCAN_RXGFC_F1OM_Msk (0x1UL << FDCAN_RXGFC_F1OM_Pos) /*!< 0x00000100 */
4605+#define FDCAN_RXGFC_F1OM FDCAN_RXGFC_F1OM_Msk /*!<FIFO 1 operation mode */
4606+#define FDCAN_RXGFC_F0OM_Pos (9U)
4607+#define FDCAN_RXGFC_F0OM_Msk (0x1UL << FDCAN_RXGFC_F0OM_Pos) /*!< 0x00000200 */
4608+#define FDCAN_RXGFC_F0OM FDCAN_RXGFC_F0OM_Msk /*!<FIFO 0 operation mode */
4609+#define FDCAN_RXGFC_LSS_Pos (16U)
4610+#define FDCAN_RXGFC_LSS_Msk (0x1FUL << FDCAN_RXGFC_LSS_Pos) /*!< 0x001F0000 */
4611+#define FDCAN_RXGFC_LSS FDCAN_RXGFC_LSS_Msk /*!<List Size Standard */
4612+#define FDCAN_RXGFC_LSE_Pos (24U)
4613+#define FDCAN_RXGFC_LSE_Msk (0xFUL << FDCAN_RXGFC_LSE_Pos) /*!< 0x0F000000 */
4614+#define FDCAN_RXGFC_LSE FDCAN_RXGFC_LSE_Msk /*!<List Size Extended */
4615+
4616+/***************** Bit definition for FDCAN_XIDAM register ********************/
4617+#define FDCAN_XIDAM_EIDM_Pos (0U)
4618+#define FDCAN_XIDAM_EIDM_Msk (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos) /*!< 0x1FFFFFFF */
4619+#define FDCAN_XIDAM_EIDM FDCAN_XIDAM_EIDM_Msk /*!<Extended ID Mask */
4620+
4621+/***************** Bit definition for FDCAN_HPMS register *********************/
4622+#define FDCAN_HPMS_BIDX_Pos (0U)
4623+#define FDCAN_HPMS_BIDX_Msk (0x7UL << FDCAN_HPMS_BIDX_Pos) /*!< 0x00000007 */
4624+#define FDCAN_HPMS_BIDX FDCAN_HPMS_BIDX_Msk /*!<Buffer Index */
4625+#define FDCAN_HPMS_MSI_Pos (6U)
4626+#define FDCAN_HPMS_MSI_Msk (0x3UL << FDCAN_HPMS_MSI_Pos) /*!< 0x000000C0 */
4627+#define FDCAN_HPMS_MSI FDCAN_HPMS_MSI_Msk /*!<Message Storage Indicator */
4628+#define FDCAN_HPMS_FIDX_Pos (8U)
4629+#define FDCAN_HPMS_FIDX_Msk (0x1FUL << FDCAN_HPMS_FIDX_Pos) /*!< 0x00001F00 */
4630+#define FDCAN_HPMS_FIDX FDCAN_HPMS_FIDX_Msk /*!<Filter Index */
4631+#define FDCAN_HPMS_FLST_Pos (15U)
4632+#define FDCAN_HPMS_FLST_Msk (0x1UL << FDCAN_HPMS_FLST_Pos) /*!< 0x00008000 */
4633+#define FDCAN_HPMS_FLST FDCAN_HPMS_FLST_Msk /*!<Filter List */
4634+
4635+/***************** Bit definition for FDCAN_RXF0S register ********************/
4636+#define FDCAN_RXF0S_F0FL_Pos (0U)
4637+#define FDCAN_RXF0S_F0FL_Msk (0xFUL << FDCAN_RXF0S_F0FL_Pos) /*!< 0x0000000F */
4638+#define FDCAN_RXF0S_F0FL FDCAN_RXF0S_F0FL_Msk /*!<Rx FIFO 0 Fill Level */
4639+#define FDCAN_RXF0S_F0GI_Pos (8U)
4640+#define FDCAN_RXF0S_F0GI_Msk (0x3UL << FDCAN_RXF0S_F0GI_Pos) /*!< 0x00000300 */
4641+#define FDCAN_RXF0S_F0GI FDCAN_RXF0S_F0GI_Msk /*!<Rx FIFO 0 Get Index */
4642+#define FDCAN_RXF0S_F0PI_Pos (16U)
4643+#define FDCAN_RXF0S_F0PI_Msk (0x3UL << FDCAN_RXF0S_F0PI_Pos) /*!< 0x00030000 */
4644+#define FDCAN_RXF0S_F0PI FDCAN_RXF0S_F0PI_Msk /*!<Rx FIFO 0 Put Index */
4645+#define FDCAN_RXF0S_F0F_Pos (24U)
4646+#define FDCAN_RXF0S_F0F_Msk (0x1UL << FDCAN_RXF0S_F0F_Pos) /*!< 0x01000000 */
4647+#define FDCAN_RXF0S_F0F FDCAN_RXF0S_F0F_Msk /*!<Rx FIFO 0 Full */
4648+#define FDCAN_RXF0S_RF0L_Pos (25U)
4649+#define FDCAN_RXF0S_RF0L_Msk (0x1UL << FDCAN_RXF0S_RF0L_Pos) /*!< 0x02000000 */
4650+#define FDCAN_RXF0S_RF0L FDCAN_RXF0S_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
4651+
4652+/***************** Bit definition for FDCAN_RXF0A register ********************/
4653+#define FDCAN_RXF0A_F0AI_Pos (0U)
4654+#define FDCAN_RXF0A_F0AI_Msk (0x7UL << FDCAN_RXF0A_F0AI_Pos) /*!< 0x00000007 */
4655+#define FDCAN_RXF0A_F0AI FDCAN_RXF0A_F0AI_Msk /*!<Rx FIFO 0 Acknowledge Index */
4656+
4657+/***************** Bit definition for FDCAN_RXF1S register ********************/
4658+#define FDCAN_RXF1S_F1FL_Pos (0U)
4659+#define FDCAN_RXF1S_F1FL_Msk (0xFUL << FDCAN_RXF1S_F1FL_Pos) /*!< 0x0000000F */
4660+#define FDCAN_RXF1S_F1FL FDCAN_RXF1S_F1FL_Msk /*!<Rx FIFO 1 Fill Level */
4661+#define FDCAN_RXF1S_F1GI_Pos (8U)
4662+#define FDCAN_RXF1S_F1GI_Msk (0x3UL << FDCAN_RXF1S_F1GI_Pos) /*!< 0x00000300 */
4663+#define FDCAN_RXF1S_F1GI FDCAN_RXF1S_F1GI_Msk /*!<Rx FIFO 1 Get Index */
4664+#define FDCAN_RXF1S_F1PI_Pos (16U)
4665+#define FDCAN_RXF1S_F1PI_Msk (0x3UL << FDCAN_RXF1S_F1PI_Pos) /*!< 0x00030000 */
4666+#define FDCAN_RXF1S_F1PI FDCAN_RXF1S_F1PI_Msk /*!<Rx FIFO 1 Put Index */
4667+#define FDCAN_RXF1S_F1F_Pos (24U)
4668+#define FDCAN_RXF1S_F1F_Msk (0x1UL << FDCAN_RXF1S_F1F_Pos) /*!< 0x01000000 */
4669+#define FDCAN_RXF1S_F1F FDCAN_RXF1S_F1F_Msk /*!<Rx FIFO 1 Full */
4670+#define FDCAN_RXF1S_RF1L_Pos (25U)
4671+#define FDCAN_RXF1S_RF1L_Msk (0x1UL << FDCAN_RXF1S_RF1L_Pos) /*!< 0x02000000 */
4672+#define FDCAN_RXF1S_RF1L FDCAN_RXF1S_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
4673+
4674+/***************** Bit definition for FDCAN_RXF1A register ********************/
4675+#define FDCAN_RXF1A_F1AI_Pos (0U)
4676+#define FDCAN_RXF1A_F1AI_Msk (0x7UL << FDCAN_RXF1A_F1AI_Pos) /*!< 0x00000007 */
4677+#define FDCAN_RXF1A_F1AI FDCAN_RXF1A_F1AI_Msk /*!<Rx FIFO 1 Acknowledge Index */
4678+
4679+/***************** Bit definition for FDCAN_TXBC register *********************/
4680+#define FDCAN_TXBC_TFQM_Pos (24U)
4681+#define FDCAN_TXBC_TFQM_Msk (0x1UL << FDCAN_TXBC_TFQM_Pos) /*!< 0x01000000 */
4682+#define FDCAN_TXBC_TFQM FDCAN_TXBC_TFQM_Msk /*!<Tx FIFO/Queue Mode */
4683+
4684+/***************** Bit definition for FDCAN_TXFQS register *********************/
4685+#define FDCAN_TXFQS_TFFL_Pos (0U)
4686+#define FDCAN_TXFQS_TFFL_Msk (0x7UL << FDCAN_TXFQS_TFFL_Pos) /*!< 0x00000007 */
4687+#define FDCAN_TXFQS_TFFL FDCAN_TXFQS_TFFL_Msk /*!<Tx FIFO Free Level */
4688+#define FDCAN_TXFQS_TFGI_Pos (8U)
4689+#define FDCAN_TXFQS_TFGI_Msk (0x3UL << FDCAN_TXFQS_TFGI_Pos) /*!< 0x00000300 */
4690+#define FDCAN_TXFQS_TFGI FDCAN_TXFQS_TFGI_Msk /*!<Tx FIFO Get Index */
4691+#define FDCAN_TXFQS_TFQPI_Pos (16U)
4692+#define FDCAN_TXFQS_TFQPI_Msk (0x3UL << FDCAN_TXFQS_TFQPI_Pos) /*!< 0x00030000 */
4693+#define FDCAN_TXFQS_TFQPI FDCAN_TXFQS_TFQPI_Msk /*!<Tx FIFO/Queue Put Index */
4694+#define FDCAN_TXFQS_TFQF_Pos (21U)
4695+#define FDCAN_TXFQS_TFQF_Msk (0x1UL << FDCAN_TXFQS_TFQF_Pos) /*!< 0x00200000 */
4696+#define FDCAN_TXFQS_TFQF FDCAN_TXFQS_TFQF_Msk /*!<Tx FIFO/Queue Full */
4697+
4698+/***************** Bit definition for FDCAN_TXBRP register *********************/
4699+#define FDCAN_TXBRP_TRP_Pos (0U)
4700+#define FDCAN_TXBRP_TRP_Msk (0x7UL << FDCAN_TXBRP_TRP_Pos) /*!< 0x00000007 */
4701+#define FDCAN_TXBRP_TRP FDCAN_TXBRP_TRP_Msk /*!<Transmission Request Pending */
4702+
4703+/***************** Bit definition for FDCAN_TXBAR register *********************/
4704+#define FDCAN_TXBAR_AR_Pos (0U)
4705+#define FDCAN_TXBAR_AR_Msk (0x7UL << FDCAN_TXBAR_AR_Pos) /*!< 0x00000007 */
4706+#define FDCAN_TXBAR_AR FDCAN_TXBAR_AR_Msk /*!<Add Request */
4707+
4708+/***************** Bit definition for FDCAN_TXBCR register *********************/
4709+#define FDCAN_TXBCR_CR_Pos (0U)
4710+#define FDCAN_TXBCR_CR_Msk (0x7UL << FDCAN_TXBCR_CR_Pos) /*!< 0x00000007 */
4711+#define FDCAN_TXBCR_CR FDCAN_TXBCR_CR_Msk /*!<Cancellation Request */
4712+
4713+/***************** Bit definition for FDCAN_TXBTO register *********************/
4714+#define FDCAN_TXBTO_TO_Pos (0U)
4715+#define FDCAN_TXBTO_TO_Msk (0x7UL << FDCAN_TXBTO_TO_Pos) /*!< 0x00000007 */
4716+#define FDCAN_TXBTO_TO FDCAN_TXBTO_TO_Msk /*!<Transmission Occurred */
4717+
4718+/***************** Bit definition for FDCAN_TXBCF register *********************/
4719+#define FDCAN_TXBCF_CF_Pos (0U)
4720+#define FDCAN_TXBCF_CF_Msk (0x7UL << FDCAN_TXBCF_CF_Pos) /*!< 0x00000007 */
4721+#define FDCAN_TXBCF_CF FDCAN_TXBCF_CF_Msk /*!<Cancellation Finished */
4722+
4723+/***************** Bit definition for FDCAN_TXBTIE register ********************/
4724+#define FDCAN_TXBTIE_TIE_Pos (0U)
4725+#define FDCAN_TXBTIE_TIE_Msk (0x7UL << FDCAN_TXBTIE_TIE_Pos) /*!< 0x00000007 */
4726+#define FDCAN_TXBTIE_TIE FDCAN_TXBTIE_TIE_Msk /*!<Transmission Interrupt Enable */
4727+
4728+/***************** Bit definition for FDCAN_ TXBCIE register *******************/
4729+#define FDCAN_TXBCIE_CFIE_Pos (0U)
4730+#define FDCAN_TXBCIE_CFIE_Msk (0x7UL << FDCAN_TXBCIE_CFIE_Pos) /*!< 0x00000007 */
4731+#define FDCAN_TXBCIE_CFIE FDCAN_TXBCIE_CFIE_Msk /*!<Cancellation Finished Interrupt Enable */
4732+
4733+/***************** Bit definition for FDCAN_TXEFS register *********************/
4734+#define FDCAN_TXEFS_EFFL_Pos (0U)
4735+#define FDCAN_TXEFS_EFFL_Msk (0x7UL << FDCAN_TXEFS_EFFL_Pos) /*!< 0x00000007 */
4736+#define FDCAN_TXEFS_EFFL FDCAN_TXEFS_EFFL_Msk /*!<Event FIFO Fill Level */
4737+#define FDCAN_TXEFS_EFGI_Pos (8U)
4738+#define FDCAN_TXEFS_EFGI_Msk (0x3UL << FDCAN_TXEFS_EFGI_Pos) /*!< 0x00000300 */
4739+#define FDCAN_TXEFS_EFGI FDCAN_TXEFS_EFGI_Msk /*!<Event FIFO Get Index */
4740+#define FDCAN_TXEFS_EFPI_Pos (16U)
4741+#define FDCAN_TXEFS_EFPI_Msk (0x3UL << FDCAN_TXEFS_EFPI_Pos) /*!< 0x00030000 */
4742+#define FDCAN_TXEFS_EFPI FDCAN_TXEFS_EFPI_Msk /*!<Event FIFO Put Index */
4743+#define FDCAN_TXEFS_EFF_Pos (24U)
4744+#define FDCAN_TXEFS_EFF_Msk (0x1UL << FDCAN_TXEFS_EFF_Pos) /*!< 0x01000000 */
4745+#define FDCAN_TXEFS_EFF FDCAN_TXEFS_EFF_Msk /*!<Event FIFO Full */
4746+#define FDCAN_TXEFS_TEFL_Pos (25U)
4747+#define FDCAN_TXEFS_TEFL_Msk (0x1UL << FDCAN_TXEFS_TEFL_Pos) /*!< 0x02000000 */
4748+#define FDCAN_TXEFS_TEFL FDCAN_TXEFS_TEFL_Msk /*!<Tx Event FIFO Element Lost */
4749+
4750+/***************** Bit definition for FDCAN_TXEFA register *********************/
4751+#define FDCAN_TXEFA_EFAI_Pos (0U)
4752+#define FDCAN_TXEFA_EFAI_Msk (0x3UL << FDCAN_TXEFA_EFAI_Pos) /*!< 0x00000003 */
4753+#define FDCAN_TXEFA_EFAI FDCAN_TXEFA_EFAI_Msk /*!<Event FIFO Acknowledge Index */
4754+
4755+
4756+/*!<FDCAN config registers */
4757+/***************** Bit definition for FDCAN_CKDIV register *********************/
4758+#define FDCAN_CKDIV_PDIV_Pos (0U)
4759+#define FDCAN_CKDIV_PDIV_Msk (0xFUL << FDCAN_CKDIV_PDIV_Pos) /*!< 0x0000000F */
4760+#define FDCAN_CKDIV_PDIV FDCAN_CKDIV_PDIV_Msk /*!<Input Clock Divider */
4761+
4762+/******************************************************************************/
4763+/* */
4764+/* FLASH */
4765+/* */
4766+/******************************************************************************/
4767+/******************* Bits definition for FLASH_ACR register *****************/
4768+#define FLASH_ACR_LATENCY_Pos (0U)
4769+#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
4770+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
4771+#define FLASH_ACR_LATENCY_0WS (0x00000000U)
4772+#define FLASH_ACR_LATENCY_1WS (0x00000001U)
4773+#define FLASH_ACR_LATENCY_2WS (0x00000002U)
4774+#define FLASH_ACR_LATENCY_3WS (0x00000003U)
4775+#define FLASH_ACR_LATENCY_4WS (0x00000004U)
4776+#define FLASH_ACR_LATENCY_5WS (0x00000005U)
4777+#define FLASH_ACR_LATENCY_6WS (0x00000006U)
4778+#define FLASH_ACR_LATENCY_7WS (0x00000007U)
4779+#define FLASH_ACR_LATENCY_8WS (0x00000008U)
4780+#define FLASH_ACR_LATENCY_9WS (0x00000009U)
4781+#define FLASH_ACR_LATENCY_10WS (0x0000000AU)
4782+#define FLASH_ACR_LATENCY_11WS (0x0000000BU)
4783+#define FLASH_ACR_LATENCY_12WS (0x0000000CU)
4784+#define FLASH_ACR_LATENCY_13WS (0x0000000DU)
4785+#define FLASH_ACR_LATENCY_14WS (0x0000000EU)
4786+#define FLASH_ACR_LATENCY_15WS (0x0000000FU)
4787+#define FLASH_ACR_PRFTEN_Pos (8U)
4788+#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
4789+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
4790+#define FLASH_ACR_ICEN_Pos (9U)
4791+#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
4792+#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
4793+#define FLASH_ACR_DCEN_Pos (10U)
4794+#define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
4795+#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
4796+#define FLASH_ACR_ICRST_Pos (11U)
4797+#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
4798+#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
4799+#define FLASH_ACR_DCRST_Pos (12U)
4800+#define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
4801+#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
4802+#define FLASH_ACR_RUN_PD_Pos (13U)
4803+#define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00002000 */
4804+#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash power down mode during run */
4805+#define FLASH_ACR_SLEEP_PD_Pos (14U)
4806+#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */
4807+#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power down mode during sleep */
4808+#define FLASH_ACR_DBG_SWEN_Pos (18U)
4809+#define FLASH_ACR_DBG_SWEN_Msk (0x1UL << FLASH_ACR_DBG_SWEN_Pos) /*!< 0x00040000 */
4810+#define FLASH_ACR_DBG_SWEN FLASH_ACR_DBG_SWEN_Msk /*!< Software disable for debugger */
4811+
4812+/******************* Bits definition for FLASH_SR register ******************/
4813+#define FLASH_SR_EOP_Pos (0U)
4814+#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
4815+#define FLASH_SR_EOP FLASH_SR_EOP_Msk
4816+#define FLASH_SR_OPERR_Pos (1U)
4817+#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */
4818+#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
4819+#define FLASH_SR_PROGERR_Pos (3U)
4820+#define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */
4821+#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk
4822+#define FLASH_SR_WRPERR_Pos (4U)
4823+#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
4824+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
4825+#define FLASH_SR_PGAERR_Pos (5U)
4826+#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
4827+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
4828+#define FLASH_SR_SIZERR_Pos (6U)
4829+#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */
4830+#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk
4831+#define FLASH_SR_PGSERR_Pos (7U)
4832+#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
4833+#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
4834+#define FLASH_SR_MISERR_Pos (8U)
4835+#define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */
4836+#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk
4837+#define FLASH_SR_FASTERR_Pos (9U)
4838+#define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */
4839+#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk
4840+#define FLASH_SR_RDERR_Pos (14U)
4841+#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */
4842+#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
4843+#define FLASH_SR_OPTVERR_Pos (15U)
4844+#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */
4845+#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk
4846+#define FLASH_SR_BSY_Pos (16U)
4847+#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
4848+#define FLASH_SR_BSY FLASH_SR_BSY_Msk
4849+
4850+/******************* Bits definition for FLASH_CR register ******************/
4851+#define FLASH_CR_PG_Pos (0U)
4852+#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */
4853+#define FLASH_CR_PG FLASH_CR_PG_Msk
4854+#define FLASH_CR_PER_Pos (1U)
4855+#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */
4856+#define FLASH_CR_PER FLASH_CR_PER_Msk
4857+#define FLASH_CR_MER1_Pos (2U)
4858+#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
4859+#define FLASH_CR_MER1 FLASH_CR_MER1_Msk
4860+#define FLASH_CR_PNB_Pos (3U)
4861+#define FLASH_CR_PNB_Msk (0xFFUL << FLASH_CR_PNB_Pos) /*!< 0x000007F8 */
4862+#define FLASH_CR_PNB FLASH_CR_PNB_Msk
4863+#define FLASH_CR_STRT_Pos (16U)
4864+#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
4865+#define FLASH_CR_STRT FLASH_CR_STRT_Msk
4866+#define FLASH_CR_OPTSTRT_Pos (17U)
4867+#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */
4868+#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk
4869+#define FLASH_CR_FSTPG_Pos (18U)
4870+#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */
4871+#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk
4872+#define FLASH_CR_EOPIE_Pos (24U)
4873+#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
4874+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
4875+#define FLASH_CR_ERRIE_Pos (25U)
4876+#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */
4877+#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
4878+#define FLASH_CR_RDERRIE_Pos (26U)
4879+#define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */
4880+#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk
4881+#define FLASH_CR_OBL_LAUNCH_Pos (27U)
4882+#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
4883+#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk
4884+#define FLASH_CR_SEC_PROT1_Pos (28U)
4885+#define FLASH_CR_SEC_PROT1_Msk (0x1UL << FLASH_CR_SEC_PROT1_Pos) /*!< 0x10000000 */
4886+#define FLASH_CR_SEC_PROT1 FLASH_CR_SEC_PROT1_Msk
4887+#define FLASH_CR_OPTLOCK_Pos (30U)
4888+#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */
4889+#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk
4890+#define FLASH_CR_LOCK_Pos (31U)
4891+#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
4892+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
4893+
4894+/******************* Bits definition for FLASH_ECCR register ***************/
4895+#define FLASH_ECCR_ADDR_ECC_Pos (0U)
4896+#define FLASH_ECCR_ADDR_ECC_Msk (0x7FFFFUL << FLASH_ECCR_ADDR_ECC_Pos)/*!< 0x0007FFFF */
4897+#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk
4898+#define FLASH_ECCR_BK_ECC_Pos (21U)
4899+#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00200000 */
4900+#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk
4901+#define FLASH_ECCR_SYSF_ECC_Pos (22U)
4902+#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */
4903+#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk
4904+#define FLASH_ECCR_ECCIE_Pos (24U)
4905+#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */
4906+#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk
4907+#define FLASH_ECCR_ECCC_Pos (30U)
4908+#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */
4909+#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk
4910+#define FLASH_ECCR_ECCD_Pos (31U)
4911+#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */
4912+#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk
4913+
4914+/******************* Bits definition for FLASH_OPTR register ***************/
4915+#define FLASH_OPTR_RDP_Pos (0U)
4916+#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */
4917+#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk
4918+#define FLASH_OPTR_BOR_LEV_Pos (8U)
4919+#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */
4920+#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk
4921+#define FLASH_OPTR_BOR_LEV_0 (0x0UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000000 */
4922+#define FLASH_OPTR_BOR_LEV_1 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */
4923+#define FLASH_OPTR_BOR_LEV_2 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */
4924+#define FLASH_OPTR_BOR_LEV_3 (0x3UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000300 */
4925+#define FLASH_OPTR_BOR_LEV_4 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */
4926+#define FLASH_OPTR_nRST_STOP_Pos (12U)
4927+#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */
4928+#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk
4929+#define FLASH_OPTR_nRST_STDBY_Pos (13U)
4930+#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */
4931+#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk
4932+#define FLASH_OPTR_nRST_SHDW_Pos (14U)
4933+#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */
4934+#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk
4935+#define FLASH_OPTR_IWDG_SW_Pos (16U)
4936+#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */
4937+#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk
4938+#define FLASH_OPTR_IWDG_STOP_Pos (17U)
4939+#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */
4940+#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk
4941+#define FLASH_OPTR_IWDG_STDBY_Pos (18U)
4942+#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
4943+#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk
4944+#define FLASH_OPTR_WWDG_SW_Pos (19U)
4945+#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */
4946+#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk
4947+#define FLASH_OPTR_PB4_PUPEN_Pos (22U)
4948+#define FLASH_OPTR_PB4_PUPEN_Msk (0x1UL << FLASH_OPTR_PB4_PUPEN_Pos) /*!< 0x00400000 */
4949+#define FLASH_OPTR_PB4_PUPEN FLASH_OPTR_PB4_PUPEN_Msk
4950+#define FLASH_OPTR_nBOOT1_Pos (23U)
4951+#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x00800000 */
4952+#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk
4953+#define FLASH_OPTR_SRAM_PE_Pos (24U)
4954+#define FLASH_OPTR_SRAM_PE_Msk (0x1UL << FLASH_OPTR_SRAM_PE_Pos) /*!< 0x01000000 */
4955+#define FLASH_OPTR_SRAM_PE FLASH_OPTR_SRAM_PE_Msk
4956+#define FLASH_OPTR_CCMSRAM_RST_Pos (25U)
4957+#define FLASH_OPTR_CCMSRAM_RST_Msk (0x1UL << FLASH_OPTR_CCMSRAM_RST_Pos)/*!< 0x02000000 */
4958+#define FLASH_OPTR_CCMSRAM_RST FLASH_OPTR_CCMSRAM_RST_Msk
4959+#define FLASH_OPTR_nSWBOOT0_Pos (26U)
4960+#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */
4961+#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk
4962+#define FLASH_OPTR_nBOOT0_Pos (27U)
4963+#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */
4964+#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk
4965+#define FLASH_OPTR_NRST_MODE_Pos (28U)
4966+#define FLASH_OPTR_NRST_MODE_Msk (0x3UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x30000000 */
4967+#define FLASH_OPTR_NRST_MODE FLASH_OPTR_NRST_MODE_Msk
4968+#define FLASH_OPTR_NRST_MODE_0 (0x1UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x10000000 */
4969+#define FLASH_OPTR_NRST_MODE_1 (0x2UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x20000000 */
4970+#define FLASH_OPTR_IRHEN_Pos (30U)
4971+#define FLASH_OPTR_IRHEN_Msk (0x1UL << FLASH_OPTR_IRHEN_Pos) /*!< 0x40000000 */
4972+#define FLASH_OPTR_IRHEN FLASH_OPTR_IRHEN_Msk
4973+
4974+/****************** Bits definition for FLASH_PCROP1SR register **********/
4975+#define FLASH_PCROP1SR_PCROP1_STRT_Pos (0U)
4976+#define FLASH_PCROP1SR_PCROP1_STRT_Msk (0x7FFFUL << FLASH_PCROP1SR_PCROP1_STRT_Pos)/*!< 0x00007FFF */
4977+#define FLASH_PCROP1SR_PCROP1_STRT FLASH_PCROP1SR_PCROP1_STRT_Msk
4978+
4979+/****************** Bits definition for FLASH_PCROP1ER register ***********/
4980+#define FLASH_PCROP1ER_PCROP1_END_Pos (0U)
4981+#define FLASH_PCROP1ER_PCROP1_END_Msk (0x7FFFUL << FLASH_PCROP1ER_PCROP1_END_Pos)/*!< 0x00007FFF */
4982+#define FLASH_PCROP1ER_PCROP1_END FLASH_PCROP1ER_PCROP1_END_Msk
4983+#define FLASH_PCROP1ER_PCROP_RDP_Pos (31U)
4984+#define FLASH_PCROP1ER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1ER_PCROP_RDP_Pos)/*!< 0x80000000 */
4985+#define FLASH_PCROP1ER_PCROP_RDP FLASH_PCROP1ER_PCROP_RDP_Msk
4986+
4987+/****************** Bits definition for FLASH_WRP1AR register ***************/
4988+#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U)
4989+#define FLASH_WRP1AR_WRP1A_STRT_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_STRT_Pos)/*!< 0x0000007F */
4990+#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
4991+#define FLASH_WRP1AR_WRP1A_END_Pos (16U)
4992+#define FLASH_WRP1AR_WRP1A_END_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_END_Pos)/*!< 0x007F0000 */
4993+#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
4994+
4995+/****************** Bits definition for FLASH_WRPB1R register ***************/
4996+#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
4997+#define FLASH_WRP1BR_WRP1B_STRT_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_STRT_Pos)/*!< 0x0000007F */
4998+#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
4999+#define FLASH_WRP1BR_WRP1B_END_Pos (16U)
5000+#define FLASH_WRP1BR_WRP1B_END_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_END_Pos)/*!< 0x007F0000 */
5001+#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
5002+
5003+
5004+/****************** Bits definition for FLASH_SEC1R register **************/
5005+#define FLASH_SEC1R_SEC_SIZE1_Pos (0U)
5006+#define FLASH_SEC1R_SEC_SIZE1_Msk (0xFFUL << FLASH_SEC1R_SEC_SIZE1_Pos)/*!< 0x000000FF */
5007+#define FLASH_SEC1R_SEC_SIZE1 FLASH_SEC1R_SEC_SIZE1_Msk
5008+#define FLASH_SEC1R_BOOT_LOCK_Pos (16U)
5009+#define FLASH_SEC1R_BOOT_LOCK_Msk (0x1UL << FLASH_SEC1R_BOOT_LOCK_Pos)/*!< 0x00010000 */
5010+#define FLASH_SEC1R_BOOT_LOCK FLASH_SEC1R_BOOT_LOCK_Msk
5011+
5012+
5013+/******************************************************************************/
5014+/* */
5015+/* Filter Mathematical ACcelerator unit (FMAC) */
5016+/* */
5017+/******************************************************************************/
5018+/***************** Bit definition for FMAC_X1BUFCFG register ****************/
5019+#define FMAC_X1BUFCFG_X1_BASE_Pos (0U)
5020+#define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos) /*!< 0x000000FF */
5021+#define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk /*!< Base address of X1 buffer */
5022+#define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8U)
5023+#define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos)/*!< 0x0000FF00 */
5024+#define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */
5025+#define FMAC_X1BUFCFG_FULL_WM_Pos (24U)
5026+#define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos) /*!< 0x03000000 */
5027+#define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk /*!< Watermark for buffer full flag */
5028+/***************** Bit definition for FMAC_X2BUFCFG register ****************/
5029+#define FMAC_X2BUFCFG_X2_BASE_Pos (0U)
5030+#define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos) /*!< 0x000000FF */
5031+#define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk /*!< Base address of X2 buffer */
5032+#define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8U)
5033+#define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos)/*!< 0x0000FF00 */
5034+#define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */
5035+/***************** Bit definition for FMAC_YBUFCFG register *****************/
5036+#define FMAC_YBUFCFG_Y_BASE_Pos (0U)
5037+#define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos) /*!< 0x000000FF */
5038+#define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk /*!< Base address of Y buffer */
5039+#define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8U)
5040+#define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) /*!< 0x0000FF00 */
5041+#define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */
5042+#define FMAC_YBUFCFG_EMPTY_WM_Pos (24U)
5043+#define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos) /*!< 0x03000000 */
5044+#define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk /*!< Watermark for buffer empty flag */
5045+/****************** Bit definition for FMAC_PARAM register ******************/
5046+#define FMAC_PARAM_P_Pos (0U)
5047+#define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos) /*!< 0x000000FF */
5048+#define FMAC_PARAM_P FMAC_PARAM_P_Msk /*!< Input parameter P */
5049+#define FMAC_PARAM_Q_Pos (8U)
5050+#define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos) /*!< 0x0000FF00 */
5051+#define FMAC_PARAM_Q FMAC_PARAM_Q_Msk /*!< Input parameter Q */
5052+#define FMAC_PARAM_R_Pos (16U)
5053+#define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos) /*!< 0x00FF0000 */
5054+#define FMAC_PARAM_R FMAC_PARAM_R_Msk /*!< Input parameter R */
5055+#define FMAC_PARAM_FUNC_Pos (24U)
5056+#define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos) /*!< 0x7F000000 */
5057+#define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk /*!< Function */
5058+#define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos) /*!< 0x01000000 */
5059+#define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos) /*!< 0x02000000 */
5060+#define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos) /*!< 0x04000000 */
5061+#define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos) /*!< 0x08000000 */
5062+#define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos) /*!< 0x10000000 */
5063+#define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos) /*!< 0x20000000 */
5064+#define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos) /*!< 0x40000000 */
5065+#define FMAC_PARAM_START_Pos (31U)
5066+#define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos) /*!< 0x80000000 */
5067+#define FMAC_PARAM_START FMAC_PARAM_START_Msk /*!< Enable execution */
5068+/******************** Bit definition for FMAC_CR register *******************/
5069+#define FMAC_CR_RIEN_Pos (0U)
5070+#define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos) /*!< 0x00000001 */
5071+#define FMAC_CR_RIEN FMAC_CR_RIEN_Msk /*!< Enable read interrupt */
5072+#define FMAC_CR_WIEN_Pos (1U)
5073+#define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos) /*!< 0x00000002 */
5074+#define FMAC_CR_WIEN FMAC_CR_WIEN_Msk /*!< Enable write interrupt */
5075+#define FMAC_CR_OVFLIEN_Pos (2U)
5076+#define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos) /*!< 0x00000004 */
5077+#define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk /*!< Enable overflow error interrupts */
5078+#define FMAC_CR_UNFLIEN_Pos (3U)
5079+#define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos) /*!< 0x00000008 */
5080+#define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk /*!< Enable underflow error interrupts */
5081+#define FMAC_CR_SATIEN_Pos (4U)
5082+#define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos) /*!< 0x00000010 */
5083+#define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk /*!< Enable saturation error interrupts */
5084+#define FMAC_CR_DMAREN_Pos (8U)
5085+#define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos) /*!< 0x00000100 */
5086+#define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk /*!< Enable DMA read channel requests */
5087+#define FMAC_CR_DMAWEN_Pos (9U)
5088+#define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos) /*!< 0x00000200 */
5089+#define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk /*!< Enable DMA write channel requests */
5090+#define FMAC_CR_CLIPEN_Pos (15U)
5091+#define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos) /*!< 0x00008000 */
5092+#define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk /*!< Enable clipping */
5093+#define FMAC_CR_RESET_Pos (16U)
5094+#define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos) /*!< 0x00010000 */
5095+#define FMAC_CR_RESET FMAC_CR_RESET_Msk /*!< Reset filter mathematical accelerator unit */
5096+/******************* Bit definition for FMAC_SR register ********************/
5097+#define FMAC_SR_YEMPTY_Pos (0U)
5098+#define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos) /*!< 0x00000001 */
5099+#define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk /*!< Y buffer empty flag */
5100+#define FMAC_SR_X1FULL_Pos (1U)
5101+#define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos) /*!< 0x00000002 */
5102+#define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk /*!< X1 buffer full flag */
5103+#define FMAC_SR_OVFL_Pos (8U)
5104+#define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos) /*!< 0x00000100 */
5105+#define FMAC_SR_OVFL FMAC_SR_OVFL_Msk /*!< Overflow error flag */
5106+#define FMAC_SR_UNFL_Pos (9U)
5107+#define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos) /*!< 0x00000200 */
5108+#define FMAC_SR_UNFL FMAC_SR_UNFL_Msk /*!< Underflow error flag */
5109+#define FMAC_SR_SAT_Pos (10U)
5110+#define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos) /*!< 0x00000400 */
5111+#define FMAC_SR_SAT FMAC_SR_SAT_Msk /*!< Saturation error flag */
5112+/****************** Bit definition for FMAC_WDATA register ******************/
5113+#define FMAC_WDATA_WDATA_Pos (0U)
5114+#define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos) /*!< 0x0000FFFF */
5115+#define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk /*!< Write data */
5116+/****************** Bit definition for FMACX_RDATA register *****************/
5117+#define FMAC_RDATA_RDATA_Pos (0U)
5118+#define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */
5119+#define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */
5120+
5121+
5122+/******************************************************************************/
5123+/* */
5124+/* General Purpose IOs (GPIO) */
5125+/* */
5126+/******************************************************************************/
5127+/****************** Bits definition for GPIO_MODER register *****************/
5128+#define GPIO_MODER_MODE0_Pos (0U)
5129+#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
5130+#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
5131+#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
5132+#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
5133+#define GPIO_MODER_MODE1_Pos (2U)
5134+#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
5135+#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
5136+#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
5137+#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
5138+#define GPIO_MODER_MODE2_Pos (4U)
5139+#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
5140+#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
5141+#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
5142+#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
5143+#define GPIO_MODER_MODE3_Pos (6U)
5144+#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
5145+#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
5146+#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
5147+#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
5148+#define GPIO_MODER_MODE4_Pos (8U)
5149+#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
5150+#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
5151+#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
5152+#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
5153+#define GPIO_MODER_MODE5_Pos (10U)
5154+#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
5155+#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
5156+#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
5157+#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
5158+#define GPIO_MODER_MODE6_Pos (12U)
5159+#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
5160+#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
5161+#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
5162+#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
5163+#define GPIO_MODER_MODE7_Pos (14U)
5164+#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
5165+#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
5166+#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
5167+#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
5168+#define GPIO_MODER_MODE8_Pos (16U)
5169+#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
5170+#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
5171+#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
5172+#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
5173+#define GPIO_MODER_MODE9_Pos (18U)
5174+#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
5175+#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
5176+#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
5177+#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
5178+#define GPIO_MODER_MODE10_Pos (20U)
5179+#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
5180+#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
5181+#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
5182+#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
5183+#define GPIO_MODER_MODE11_Pos (22U)
5184+#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
5185+#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
5186+#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
5187+#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
5188+#define GPIO_MODER_MODE12_Pos (24U)
5189+#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
5190+#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
5191+#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
5192+#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
5193+#define GPIO_MODER_MODE13_Pos (26U)
5194+#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
5195+#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
5196+#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
5197+#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
5198+#define GPIO_MODER_MODE14_Pos (28U)
5199+#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
5200+#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
5201+#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
5202+#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
5203+#define GPIO_MODER_MODE15_Pos (30U)
5204+#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
5205+#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
5206+#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
5207+#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
5208+
5209+/* Legacy defines */
5210+#define GPIO_MODER_MODER0 GPIO_MODER_MODE0
5211+#define GPIO_MODER_MODER0_0 GPIO_MODER_MODE0_0
5212+#define GPIO_MODER_MODER0_1 GPIO_MODER_MODE0_1
5213+#define GPIO_MODER_MODER1 GPIO_MODER_MODE1
5214+#define GPIO_MODER_MODER1_0 GPIO_MODER_MODE1_0
5215+#define GPIO_MODER_MODER1_1 GPIO_MODER_MODE1_1
5216+#define GPIO_MODER_MODER2 GPIO_MODER_MODE2
5217+#define GPIO_MODER_MODER2_0 GPIO_MODER_MODE2_0
5218+#define GPIO_MODER_MODER2_1 GPIO_MODER_MODE2_1
5219+#define GPIO_MODER_MODER3 GPIO_MODER_MODE3
5220+#define GPIO_MODER_MODER3_0 GPIO_MODER_MODE3_0
5221+#define GPIO_MODER_MODER3_1 GPIO_MODER_MODE3_1
5222+#define GPIO_MODER_MODER4 GPIO_MODER_MODE4
5223+#define GPIO_MODER_MODER4_0 GPIO_MODER_MODE4_0
5224+#define GPIO_MODER_MODER4_1 GPIO_MODER_MODE4_1
5225+#define GPIO_MODER_MODER5 GPIO_MODER_MODE5
5226+#define GPIO_MODER_MODER5_0 GPIO_MODER_MODE5_0
5227+#define GPIO_MODER_MODER5_1 GPIO_MODER_MODE5_1
5228+#define GPIO_MODER_MODER6 GPIO_MODER_MODE6
5229+#define GPIO_MODER_MODER6_0 GPIO_MODER_MODE6_0
5230+#define GPIO_MODER_MODER6_1 GPIO_MODER_MODE6_1
5231+#define GPIO_MODER_MODER7 GPIO_MODER_MODE7
5232+#define GPIO_MODER_MODER7_0 GPIO_MODER_MODE7_0
5233+#define GPIO_MODER_MODER7_1 GPIO_MODER_MODE7_1
5234+#define GPIO_MODER_MODER8 GPIO_MODER_MODE8
5235+#define GPIO_MODER_MODER8_0 GPIO_MODER_MODE8_0
5236+#define GPIO_MODER_MODER8_1 GPIO_MODER_MODE8_1
5237+#define GPIO_MODER_MODER9 GPIO_MODER_MODE9
5238+#define GPIO_MODER_MODER9_0 GPIO_MODER_MODE9_0
5239+#define GPIO_MODER_MODER9_1 GPIO_MODER_MODE9_1
5240+#define GPIO_MODER_MODER10 GPIO_MODER_MODE10
5241+#define GPIO_MODER_MODER10_0 GPIO_MODER_MODE10_0
5242+#define GPIO_MODER_MODER10_1 GPIO_MODER_MODE10_1
5243+#define GPIO_MODER_MODER11 GPIO_MODER_MODE11
5244+#define GPIO_MODER_MODER11_0 GPIO_MODER_MODE11_0
5245+#define GPIO_MODER_MODER11_1 GPIO_MODER_MODE11_1
5246+#define GPIO_MODER_MODER12 GPIO_MODER_MODE12
5247+#define GPIO_MODER_MODER12_0 GPIO_MODER_MODE12_0
5248+#define GPIO_MODER_MODER12_1 GPIO_MODER_MODE12_1
5249+#define GPIO_MODER_MODER13 GPIO_MODER_MODE13
5250+#define GPIO_MODER_MODER13_0 GPIO_MODER_MODE13_0
5251+#define GPIO_MODER_MODER13_1 GPIO_MODER_MODE13_1
5252+#define GPIO_MODER_MODER14 GPIO_MODER_MODE14
5253+#define GPIO_MODER_MODER14_0 GPIO_MODER_MODE14_0
5254+#define GPIO_MODER_MODER14_1 GPIO_MODER_MODE14_1
5255+#define GPIO_MODER_MODER15 GPIO_MODER_MODE15
5256+#define GPIO_MODER_MODER15_0 GPIO_MODER_MODE15_0
5257+#define GPIO_MODER_MODER15_1 GPIO_MODER_MODE15_1
5258+
5259+/****************** Bits definition for GPIO_OTYPER register ****************/
5260+#define GPIO_OTYPER_OT0_Pos (0U)
5261+#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
5262+#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
5263+#define GPIO_OTYPER_OT1_Pos (1U)
5264+#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
5265+#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
5266+#define GPIO_OTYPER_OT2_Pos (2U)
5267+#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
5268+#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
5269+#define GPIO_OTYPER_OT3_Pos (3U)
5270+#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
5271+#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
5272+#define GPIO_OTYPER_OT4_Pos (4U)
5273+#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
5274+#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
5275+#define GPIO_OTYPER_OT5_Pos (5U)
5276+#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
5277+#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
5278+#define GPIO_OTYPER_OT6_Pos (6U)
5279+#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
5280+#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
5281+#define GPIO_OTYPER_OT7_Pos (7U)
5282+#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
5283+#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
5284+#define GPIO_OTYPER_OT8_Pos (8U)
5285+#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
5286+#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
5287+#define GPIO_OTYPER_OT9_Pos (9U)
5288+#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
5289+#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
5290+#define GPIO_OTYPER_OT10_Pos (10U)
5291+#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
5292+#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
5293+#define GPIO_OTYPER_OT11_Pos (11U)
5294+#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
5295+#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
5296+#define GPIO_OTYPER_OT12_Pos (12U)
5297+#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
5298+#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
5299+#define GPIO_OTYPER_OT13_Pos (13U)
5300+#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
5301+#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
5302+#define GPIO_OTYPER_OT14_Pos (14U)
5303+#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
5304+#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
5305+#define GPIO_OTYPER_OT15_Pos (15U)
5306+#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
5307+#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
5308+
5309+/* Legacy defines */
5310+#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
5311+#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
5312+#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
5313+#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
5314+#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
5315+#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
5316+#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
5317+#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
5318+#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
5319+#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
5320+#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
5321+#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
5322+#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
5323+#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
5324+#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
5325+#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
5326+
5327+/****************** Bits definition for GPIO_OSPEEDR register ***************/
5328+#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
5329+#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
5330+#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
5331+#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
5332+#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
5333+#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
5334+#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
5335+#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
5336+#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
5337+#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
5338+#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
5339+#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
5340+#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
5341+#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
5342+#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
5343+#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
5344+#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
5345+#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
5346+#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
5347+#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
5348+#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
5349+#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
5350+#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
5351+#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
5352+#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
5353+#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
5354+#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
5355+#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
5356+#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
5357+#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
5358+#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
5359+#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
5360+#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
5361+#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
5362+#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
5363+#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
5364+#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
5365+#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
5366+#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
5367+#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
5368+#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
5369+#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
5370+#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
5371+#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
5372+#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
5373+#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
5374+#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
5375+#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
5376+#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
5377+#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
5378+#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
5379+#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
5380+#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
5381+#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
5382+#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
5383+#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
5384+#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
5385+#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
5386+#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
5387+#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
5388+#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
5389+#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
5390+#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
5391+#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
5392+#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
5393+#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
5394+#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
5395+#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
5396+#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
5397+#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
5398+#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
5399+#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
5400+#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
5401+#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
5402+#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
5403+#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
5404+#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
5405+#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
5406+#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
5407+#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
5408+
5409+/* Legacy defines */
5410+#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
5411+#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
5412+#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
5413+#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
5414+#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
5415+#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
5416+#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
5417+#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
5418+#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
5419+#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
5420+#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
5421+#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
5422+#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
5423+#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
5424+#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
5425+#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
5426+#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
5427+#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
5428+#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
5429+#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
5430+#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
5431+#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
5432+#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
5433+#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
5434+#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
5435+#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
5436+#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
5437+#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
5438+#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
5439+#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
5440+#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
5441+#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
5442+#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
5443+#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
5444+#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
5445+#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
5446+#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
5447+#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
5448+#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
5449+#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
5450+#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
5451+#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
5452+#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
5453+#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
5454+#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
5455+#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
5456+#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
5457+#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
5458+
5459+/****************** Bits definition for GPIO_PUPDR register *****************/
5460+#define GPIO_PUPDR_PUPD0_Pos (0U)
5461+#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
5462+#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
5463+#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
5464+#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
5465+#define GPIO_PUPDR_PUPD1_Pos (2U)
5466+#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
5467+#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
5468+#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
5469+#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
5470+#define GPIO_PUPDR_PUPD2_Pos (4U)
5471+#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
5472+#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
5473+#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
5474+#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
5475+#define GPIO_PUPDR_PUPD3_Pos (6U)
5476+#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
5477+#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
5478+#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
5479+#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
5480+#define GPIO_PUPDR_PUPD4_Pos (8U)
5481+#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
5482+#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
5483+#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
5484+#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
5485+#define GPIO_PUPDR_PUPD5_Pos (10U)
5486+#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
5487+#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
5488+#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
5489+#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
5490+#define GPIO_PUPDR_PUPD6_Pos (12U)
5491+#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
5492+#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
5493+#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
5494+#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
5495+#define GPIO_PUPDR_PUPD7_Pos (14U)
5496+#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
5497+#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
5498+#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
5499+#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
5500+#define GPIO_PUPDR_PUPD8_Pos (16U)
5501+#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
5502+#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
5503+#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
5504+#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
5505+#define GPIO_PUPDR_PUPD9_Pos (18U)
5506+#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
5507+#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
5508+#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
5509+#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
5510+#define GPIO_PUPDR_PUPD10_Pos (20U)
5511+#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
5512+#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
5513+#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
5514+#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
5515+#define GPIO_PUPDR_PUPD11_Pos (22U)
5516+#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
5517+#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
5518+#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
5519+#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
5520+#define GPIO_PUPDR_PUPD12_Pos (24U)
5521+#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
5522+#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
5523+#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
5524+#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
5525+#define GPIO_PUPDR_PUPD13_Pos (26U)
5526+#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
5527+#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
5528+#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
5529+#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
5530+#define GPIO_PUPDR_PUPD14_Pos (28U)
5531+#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
5532+#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
5533+#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
5534+#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
5535+#define GPIO_PUPDR_PUPD15_Pos (30U)
5536+#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
5537+#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
5538+#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
5539+#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
5540+
5541+/* Legacy defines */
5542+#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
5543+#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
5544+#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
5545+#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
5546+#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
5547+#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
5548+#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
5549+#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
5550+#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
5551+#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
5552+#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
5553+#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
5554+#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
5555+#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
5556+#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
5557+#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
5558+#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
5559+#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
5560+#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
5561+#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
5562+#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
5563+#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
5564+#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
5565+#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
5566+#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
5567+#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
5568+#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
5569+#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
5570+#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
5571+#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
5572+#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
5573+#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
5574+#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
5575+#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
5576+#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
5577+#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
5578+#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
5579+#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
5580+#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
5581+#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
5582+#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
5583+#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
5584+#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
5585+#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
5586+#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
5587+#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
5588+#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
5589+#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
5590+
5591+/****************** Bits definition for GPIO_IDR register *******************/
5592+#define GPIO_IDR_ID0_Pos (0U)
5593+#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
5594+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
5595+#define GPIO_IDR_ID1_Pos (1U)
5596+#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
5597+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
5598+#define GPIO_IDR_ID2_Pos (2U)
5599+#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
5600+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
5601+#define GPIO_IDR_ID3_Pos (3U)
5602+#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
5603+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
5604+#define GPIO_IDR_ID4_Pos (4U)
5605+#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
5606+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
5607+#define GPIO_IDR_ID5_Pos (5U)
5608+#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
5609+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
5610+#define GPIO_IDR_ID6_Pos (6U)
5611+#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
5612+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
5613+#define GPIO_IDR_ID7_Pos (7U)
5614+#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
5615+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
5616+#define GPIO_IDR_ID8_Pos (8U)
5617+#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
5618+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
5619+#define GPIO_IDR_ID9_Pos (9U)
5620+#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
5621+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
5622+#define GPIO_IDR_ID10_Pos (10U)
5623+#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
5624+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
5625+#define GPIO_IDR_ID11_Pos (11U)
5626+#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
5627+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
5628+#define GPIO_IDR_ID12_Pos (12U)
5629+#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
5630+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
5631+#define GPIO_IDR_ID13_Pos (13U)
5632+#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
5633+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
5634+#define GPIO_IDR_ID14_Pos (14U)
5635+#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
5636+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
5637+#define GPIO_IDR_ID15_Pos (15U)
5638+#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
5639+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
5640+
5641+/* Legacy defines */
5642+#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
5643+#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
5644+#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
5645+#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
5646+#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
5647+#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
5648+#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
5649+#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
5650+#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
5651+#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
5652+#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
5653+#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
5654+#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
5655+#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
5656+#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
5657+#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
5658+
5659+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
5660+#define GPIO_OTYPER_IDR_0 GPIO_IDR_ID0
5661+#define GPIO_OTYPER_IDR_1 GPIO_IDR_ID1
5662+#define GPIO_OTYPER_IDR_2 GPIO_IDR_ID2
5663+#define GPIO_OTYPER_IDR_3 GPIO_IDR_ID3
5664+#define GPIO_OTYPER_IDR_4 GPIO_IDR_ID4
5665+#define GPIO_OTYPER_IDR_5 GPIO_IDR_ID5
5666+#define GPIO_OTYPER_IDR_6 GPIO_IDR_ID6
5667+#define GPIO_OTYPER_IDR_7 GPIO_IDR_ID7
5668+#define GPIO_OTYPER_IDR_8 GPIO_IDR_ID8
5669+#define GPIO_OTYPER_IDR_9 GPIO_IDR_ID9
5670+#define GPIO_OTYPER_IDR_10 GPIO_IDR_ID10
5671+#define GPIO_OTYPER_IDR_11 GPIO_IDR_ID11
5672+#define GPIO_OTYPER_IDR_12 GPIO_IDR_ID12
5673+#define GPIO_OTYPER_IDR_13 GPIO_IDR_ID13
5674+#define GPIO_OTYPER_IDR_14 GPIO_IDR_ID14
5675+#define GPIO_OTYPER_IDR_15 GPIO_IDR_ID15
5676+
5677+/****************** Bits definition for GPIO_ODR register *******************/
5678+#define GPIO_ODR_OD0_Pos (0U)
5679+#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
5680+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
5681+#define GPIO_ODR_OD1_Pos (1U)
5682+#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
5683+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
5684+#define GPIO_ODR_OD2_Pos (2U)
5685+#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
5686+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
5687+#define GPIO_ODR_OD3_Pos (3U)
5688+#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
5689+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
5690+#define GPIO_ODR_OD4_Pos (4U)
5691+#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
5692+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
5693+#define GPIO_ODR_OD5_Pos (5U)
5694+#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
5695+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
5696+#define GPIO_ODR_OD6_Pos (6U)
5697+#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
5698+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
5699+#define GPIO_ODR_OD7_Pos (7U)
5700+#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
5701+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
5702+#define GPIO_ODR_OD8_Pos (8U)
5703+#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
5704+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
5705+#define GPIO_ODR_OD9_Pos (9U)
5706+#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
5707+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
5708+#define GPIO_ODR_OD10_Pos (10U)
5709+#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
5710+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
5711+#define GPIO_ODR_OD11_Pos (11U)
5712+#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
5713+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
5714+#define GPIO_ODR_OD12_Pos (12U)
5715+#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
5716+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
5717+#define GPIO_ODR_OD13_Pos (13U)
5718+#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
5719+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
5720+#define GPIO_ODR_OD14_Pos (14U)
5721+#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
5722+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
5723+#define GPIO_ODR_OD15_Pos (15U)
5724+#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
5725+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
5726+
5727+/* Legacy defines */
5728+#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
5729+#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
5730+#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
5731+#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
5732+#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
5733+#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
5734+#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
5735+#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
5736+#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
5737+#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
5738+#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
5739+#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
5740+#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
5741+#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
5742+#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
5743+#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
5744+
5745+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
5746+#define GPIO_OTYPER_ODR_0 GPIO_ODR_OD0
5747+#define GPIO_OTYPER_ODR_1 GPIO_ODR_OD1
5748+#define GPIO_OTYPER_ODR_2 GPIO_ODR_OD2
5749+#define GPIO_OTYPER_ODR_3 GPIO_ODR_OD3
5750+#define GPIO_OTYPER_ODR_4 GPIO_ODR_OD4
5751+#define GPIO_OTYPER_ODR_5 GPIO_ODR_OD5
5752+#define GPIO_OTYPER_ODR_6 GPIO_ODR_OD6
5753+#define GPIO_OTYPER_ODR_7 GPIO_ODR_OD7
5754+#define GPIO_OTYPER_ODR_8 GPIO_ODR_OD8
5755+#define GPIO_OTYPER_ODR_9 GPIO_ODR_OD9
5756+#define GPIO_OTYPER_ODR_10 GPIO_ODR_OD10
5757+#define GPIO_OTYPER_ODR_11 GPIO_ODR_OD11
5758+#define GPIO_OTYPER_ODR_12 GPIO_ODR_OD12
5759+#define GPIO_OTYPER_ODR_13 GPIO_ODR_OD13
5760+#define GPIO_OTYPER_ODR_14 GPIO_ODR_OD14
5761+#define GPIO_OTYPER_ODR_15 GPIO_ODR_OD15
5762+
5763+/****************** Bits definition for GPIO_BSRR register ******************/
5764+#define GPIO_BSRR_BS0_Pos (0U)
5765+#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
5766+#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
5767+#define GPIO_BSRR_BS1_Pos (1U)
5768+#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
5769+#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
5770+#define GPIO_BSRR_BS2_Pos (2U)
5771+#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
5772+#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
5773+#define GPIO_BSRR_BS3_Pos (3U)
5774+#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
5775+#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
5776+#define GPIO_BSRR_BS4_Pos (4U)
5777+#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
5778+#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
5779+#define GPIO_BSRR_BS5_Pos (5U)
5780+#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
5781+#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
5782+#define GPIO_BSRR_BS6_Pos (6U)
5783+#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
5784+#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
5785+#define GPIO_BSRR_BS7_Pos (7U)
5786+#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
5787+#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
5788+#define GPIO_BSRR_BS8_Pos (8U)
5789+#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
5790+#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
5791+#define GPIO_BSRR_BS9_Pos (9U)
5792+#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
5793+#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
5794+#define GPIO_BSRR_BS10_Pos (10U)
5795+#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
5796+#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
5797+#define GPIO_BSRR_BS11_Pos (11U)
5798+#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
5799+#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
5800+#define GPIO_BSRR_BS12_Pos (12U)
5801+#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
5802+#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
5803+#define GPIO_BSRR_BS13_Pos (13U)
5804+#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
5805+#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
5806+#define GPIO_BSRR_BS14_Pos (14U)
5807+#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
5808+#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
5809+#define GPIO_BSRR_BS15_Pos (15U)
5810+#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
5811+#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
5812+#define GPIO_BSRR_BR0_Pos (16U)
5813+#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
5814+#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
5815+#define GPIO_BSRR_BR1_Pos (17U)
5816+#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
5817+#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
5818+#define GPIO_BSRR_BR2_Pos (18U)
5819+#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
5820+#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
5821+#define GPIO_BSRR_BR3_Pos (19U)
5822+#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
5823+#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
5824+#define GPIO_BSRR_BR4_Pos (20U)
5825+#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
5826+#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
5827+#define GPIO_BSRR_BR5_Pos (21U)
5828+#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
5829+#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
5830+#define GPIO_BSRR_BR6_Pos (22U)
5831+#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
5832+#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
5833+#define GPIO_BSRR_BR7_Pos (23U)
5834+#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
5835+#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
5836+#define GPIO_BSRR_BR8_Pos (24U)
5837+#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
5838+#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
5839+#define GPIO_BSRR_BR9_Pos (25U)
5840+#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
5841+#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
5842+#define GPIO_BSRR_BR10_Pos (26U)
5843+#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
5844+#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
5845+#define GPIO_BSRR_BR11_Pos (27U)
5846+#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
5847+#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
5848+#define GPIO_BSRR_BR12_Pos (28U)
5849+#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
5850+#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
5851+#define GPIO_BSRR_BR13_Pos (29U)
5852+#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
5853+#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
5854+#define GPIO_BSRR_BR14_Pos (30U)
5855+#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
5856+#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
5857+#define GPIO_BSRR_BR15_Pos (31U)
5858+#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
5859+#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
5860+
5861+/* Legacy defines */
5862+#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
5863+#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
5864+#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
5865+#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
5866+#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
5867+#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
5868+#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
5869+#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
5870+#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
5871+#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
5872+#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
5873+#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
5874+#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
5875+#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
5876+#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
5877+#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
5878+#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
5879+#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
5880+#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
5881+#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
5882+#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
5883+#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
5884+#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
5885+#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
5886+#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
5887+#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
5888+#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
5889+#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
5890+#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
5891+#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
5892+#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
5893+#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
5894+
5895+/****************** Bit definition for GPIO_LCKR register *********************/
5896+#define GPIO_LCKR_LCK0_Pos (0U)
5897+#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
5898+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
5899+#define GPIO_LCKR_LCK1_Pos (1U)
5900+#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
5901+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
5902+#define GPIO_LCKR_LCK2_Pos (2U)
5903+#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
5904+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
5905+#define GPIO_LCKR_LCK3_Pos (3U)
5906+#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
5907+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
5908+#define GPIO_LCKR_LCK4_Pos (4U)
5909+#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
5910+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
5911+#define GPIO_LCKR_LCK5_Pos (5U)
5912+#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
5913+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
5914+#define GPIO_LCKR_LCK6_Pos (6U)
5915+#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
5916+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
5917+#define GPIO_LCKR_LCK7_Pos (7U)
5918+#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
5919+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
5920+#define GPIO_LCKR_LCK8_Pos (8U)
5921+#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
5922+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
5923+#define GPIO_LCKR_LCK9_Pos (9U)
5924+#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
5925+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
5926+#define GPIO_LCKR_LCK10_Pos (10U)
5927+#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
5928+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
5929+#define GPIO_LCKR_LCK11_Pos (11U)
5930+#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
5931+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
5932+#define GPIO_LCKR_LCK12_Pos (12U)
5933+#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
5934+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
5935+#define GPIO_LCKR_LCK13_Pos (13U)
5936+#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
5937+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
5938+#define GPIO_LCKR_LCK14_Pos (14U)
5939+#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
5940+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
5941+#define GPIO_LCKR_LCK15_Pos (15U)
5942+#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
5943+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
5944+#define GPIO_LCKR_LCKK_Pos (16U)
5945+#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
5946+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
5947+
5948+/****************** Bit definition for GPIO_AFRL register *********************/
5949+#define GPIO_AFRL_AFSEL0_Pos (0U)
5950+#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
5951+#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
5952+#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
5953+#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
5954+#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
5955+#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
5956+#define GPIO_AFRL_AFSEL1_Pos (4U)
5957+#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
5958+#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
5959+#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
5960+#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
5961+#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
5962+#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
5963+#define GPIO_AFRL_AFSEL2_Pos (8U)
5964+#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
5965+#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
5966+#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
5967+#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
5968+#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
5969+#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
5970+#define GPIO_AFRL_AFSEL3_Pos (12U)
5971+#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
5972+#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
5973+#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
5974+#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
5975+#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
5976+#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
5977+#define GPIO_AFRL_AFSEL4_Pos (16U)
5978+#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
5979+#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
5980+#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
5981+#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
5982+#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
5983+#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
5984+#define GPIO_AFRL_AFSEL5_Pos (20U)
5985+#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
5986+#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
5987+#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
5988+#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
5989+#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
5990+#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
5991+#define GPIO_AFRL_AFSEL6_Pos (24U)
5992+#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
5993+#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
5994+#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
5995+#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
5996+#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
5997+#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
5998+#define GPIO_AFRL_AFSEL7_Pos (28U)
5999+#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
6000+#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
6001+#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
6002+#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
6003+#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
6004+#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
6005+
6006+/* Legacy defines */
6007+#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
6008+#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
6009+#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
6010+#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
6011+#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
6012+#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
6013+#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
6014+#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
6015+
6016+/****************** Bit definition for GPIO_AFRH register *********************/
6017+#define GPIO_AFRH_AFSEL8_Pos (0U)
6018+#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
6019+#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
6020+#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
6021+#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
6022+#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
6023+#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
6024+#define GPIO_AFRH_AFSEL9_Pos (4U)
6025+#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
6026+#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
6027+#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
6028+#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
6029+#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
6030+#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
6031+#define GPIO_AFRH_AFSEL10_Pos (8U)
6032+#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
6033+#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
6034+#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
6035+#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
6036+#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
6037+#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
6038+#define GPIO_AFRH_AFSEL11_Pos (12U)
6039+#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
6040+#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
6041+#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
6042+#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
6043+#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
6044+#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
6045+#define GPIO_AFRH_AFSEL12_Pos (16U)
6046+#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
6047+#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
6048+#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
6049+#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
6050+#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
6051+#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
6052+#define GPIO_AFRH_AFSEL13_Pos (20U)
6053+#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
6054+#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
6055+#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
6056+#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
6057+#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
6058+#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
6059+#define GPIO_AFRH_AFSEL14_Pos (24U)
6060+#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
6061+#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
6062+#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
6063+#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
6064+#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
6065+#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
6066+#define GPIO_AFRH_AFSEL15_Pos (28U)
6067+#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
6068+#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
6069+#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
6070+#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
6071+#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
6072+#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
6073+
6074+/* Legacy defines */
6075+#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
6076+#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
6077+#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
6078+#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
6079+#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
6080+#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
6081+#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
6082+#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
6083+
6084+/****************** Bits definition for GPIO_BRR register ******************/
6085+#define GPIO_BRR_BR0_Pos (0U)
6086+#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
6087+#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
6088+#define GPIO_BRR_BR1_Pos (1U)
6089+#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
6090+#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
6091+#define GPIO_BRR_BR2_Pos (2U)
6092+#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
6093+#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
6094+#define GPIO_BRR_BR3_Pos (3U)
6095+#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
6096+#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
6097+#define GPIO_BRR_BR4_Pos (4U)
6098+#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
6099+#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
6100+#define GPIO_BRR_BR5_Pos (5U)
6101+#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
6102+#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
6103+#define GPIO_BRR_BR6_Pos (6U)
6104+#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
6105+#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
6106+#define GPIO_BRR_BR7_Pos (7U)
6107+#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
6108+#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
6109+#define GPIO_BRR_BR8_Pos (8U)
6110+#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
6111+#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
6112+#define GPIO_BRR_BR9_Pos (9U)
6113+#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
6114+#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
6115+#define GPIO_BRR_BR10_Pos (10U)
6116+#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
6117+#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
6118+#define GPIO_BRR_BR11_Pos (11U)
6119+#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
6120+#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
6121+#define GPIO_BRR_BR12_Pos (12U)
6122+#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
6123+#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
6124+#define GPIO_BRR_BR13_Pos (13U)
6125+#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
6126+#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
6127+#define GPIO_BRR_BR14_Pos (14U)
6128+#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
6129+#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
6130+#define GPIO_BRR_BR15_Pos (15U)
6131+#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
6132+#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
6133+
6134+/* Legacy defines */
6135+#define GPIO_BRR_BR_0 GPIO_BRR_BR0
6136+#define GPIO_BRR_BR_1 GPIO_BRR_BR1
6137+#define GPIO_BRR_BR_2 GPIO_BRR_BR2
6138+#define GPIO_BRR_BR_3 GPIO_BRR_BR3
6139+#define GPIO_BRR_BR_4 GPIO_BRR_BR4
6140+#define GPIO_BRR_BR_5 GPIO_BRR_BR5
6141+#define GPIO_BRR_BR_6 GPIO_BRR_BR6
6142+#define GPIO_BRR_BR_7 GPIO_BRR_BR7
6143+#define GPIO_BRR_BR_8 GPIO_BRR_BR8
6144+#define GPIO_BRR_BR_9 GPIO_BRR_BR9
6145+#define GPIO_BRR_BR_10 GPIO_BRR_BR10
6146+#define GPIO_BRR_BR_11 GPIO_BRR_BR11
6147+#define GPIO_BRR_BR_12 GPIO_BRR_BR12
6148+#define GPIO_BRR_BR_13 GPIO_BRR_BR13
6149+#define GPIO_BRR_BR_14 GPIO_BRR_BR14
6150+#define GPIO_BRR_BR_15 GPIO_BRR_BR15
6151+
6152+
6153+/******************************************************************************/
6154+/* */
6155+/* Inter-integrated Circuit Interface (I2C) */
6156+/* */
6157+/******************************************************************************/
6158+/******************* Bit definition for I2C_CR1 register *******************/
6159+#define I2C_CR1_PE_Pos (0U)
6160+#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
6161+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
6162+#define I2C_CR1_TXIE_Pos (1U)
6163+#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
6164+#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
6165+#define I2C_CR1_RXIE_Pos (2U)
6166+#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
6167+#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
6168+#define I2C_CR1_ADDRIE_Pos (3U)
6169+#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
6170+#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
6171+#define I2C_CR1_NACKIE_Pos (4U)
6172+#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
6173+#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
6174+#define I2C_CR1_STOPIE_Pos (5U)
6175+#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
6176+#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
6177+#define I2C_CR1_TCIE_Pos (6U)
6178+#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
6179+#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
6180+#define I2C_CR1_ERRIE_Pos (7U)
6181+#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
6182+#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
6183+#define I2C_CR1_DNF_Pos (8U)
6184+#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
6185+#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
6186+#define I2C_CR1_ANFOFF_Pos (12U)
6187+#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
6188+#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
6189+#define I2C_CR1_SWRST_Pos (13U)
6190+#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
6191+#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
6192+#define I2C_CR1_TXDMAEN_Pos (14U)
6193+#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
6194+#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
6195+#define I2C_CR1_RXDMAEN_Pos (15U)
6196+#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
6197+#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
6198+#define I2C_CR1_SBC_Pos (16U)
6199+#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
6200+#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
6201+#define I2C_CR1_NOSTRETCH_Pos (17U)
6202+#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
6203+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
6204+#define I2C_CR1_WUPEN_Pos (18U)
6205+#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
6206+#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
6207+#define I2C_CR1_GCEN_Pos (19U)
6208+#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
6209+#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
6210+#define I2C_CR1_SMBHEN_Pos (20U)
6211+#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
6212+#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
6213+#define I2C_