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chibios: Commit


Commit MetaInfo

Revision14813 (tree)
Time2021-09-21 20:44:41
Authorgdisirio

Log Message

Added more clock handlers for RCCv2.

Change Summary

Incremental Difference

--- trunk/os/hal/ports/STM32/STM32MP1xx/hal_lld.h (revision 14812)
+++ trunk/os/hal/ports/STM32/STM32MP1xx/hal_lld.h (revision 14813)
@@ -92,15 +92,6 @@
9292 /** @} */
9393
9494 /**
95- * @name Internal clocks
96- * @{
97- */
98-#define STM32_HSICLK 64000000
99-#define STM32_CSICLK 4000000
100-#define STM32_LSICLK 32000
101-/** @} */
102-
103-/**
10495 * @name RCC_RCK3SELR register bits definitions
10596 * @{
10697 */
@@ -194,16 +185,40 @@
194185 #endif
195186
196187 /**
188+ * @brief Enables or disables the HSE clock source.
189+ * @note This initialization is performed only if TZEN=0
190+ * otherwise the setting must match the initialization performed
191+ * on the Cortex-A side.
192+ */
193+#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
194+#define STM32_HSE_ENABLED TRUE
195+#endif
196+
197+/**
198+ * @brief Enables or disables the HSI64 clock source.
199+ * @note This initialization is performed only if TZEN=0
200+ * otherwise the setting must match the initialization performed
201+ * on the Cortex-A side.
202+ */
203+#if !defined(STM32_HSI64_ENABLED) || defined(__DOXYGEN__)
204+#define STM32_HSI64_ENABLED TRUE
205+#endif
206+
207+/**
197208 * @brief Enables or disables the CSI clock source.
198- * @note This initialization is performed only if TZEN=0 or MCKPROT=0.
209+ * @note This initialization is performed only if TZEN=0 or MCKPROT=0
210+ * otherwise the setting must match the initialization performed
211+ * on the Cortex-A side.
199212 */
200213 #if !defined(STM32_CSI_ENABLED) || defined(__DOXYGEN__)
201-#define STM32_CSI_ENABLED FALSE
214+#define STM32_CSI_ENABLED TRUE
202215 #endif
203216
204217 /**
205218 * @brief Clock source for the PLL3.
206- * @note This initialization is performed only if TZEN=0 or MCKPROT=0.
219+ * @note This initialization is performed only if TZEN=0 or MCKPROT=0
220+ * otherwise the setting must match the initialization performed
221+ * on the Cortex-A side.
207222 */
208223 #if !defined(STM32_PLL3SRC) || defined(__DOXYGEN__)
209224 #define STM32_PLL3SRC STM32_PLL3SRC_HSE
@@ -212,7 +227,9 @@
212227 /**
213228 * @brief PLL3 M divider value.
214229 * @note The allowed values are 1..64.
215- * @note This initialization is performed only if TZEN=0 or MCKPROT=0.
230+ * @note This initialization is performed only if TZEN=0 or MCKPROT=0
231+ * otherwise the setting must match the initialization performed
232+ * on the Cortex-A side.
216233 */
217234 #if !defined(STM32_PLL3DIVM_VALUE) || defined(__DOXYGEN__)
218235 #define STM32_PLL3DIVM_VALUE 3
@@ -221,7 +238,9 @@
221238 /**
222239 * @brief PLL3 N multiplier value.
223240 * @note The allowed values are 25..200.
224- * @note This initialization is performed only if TZEN=0 or MCKPROT=0.
241+ * @note This initialization is performed only if TZEN=0 or MCKPROT=0
242+ * otherwise the setting must match the initialization performed
243+ * on the Cortex-A side.
225244 */
226245 #if !defined(STM32_PLL3DIVN_VALUE) || defined(__DOXYGEN__)
227246 #define STM32_PLL3DIVN_VALUE 50
@@ -230,7 +249,9 @@
230249 /**
231250 * @brief PLL3 P divider value or zero if disabled.
232251 * @note The allowed values are 1..128.
233- * @note This initialization is performed only if TZEN=0 or MCKPROT=0.
252+ * @note This initialization is performed only if TZEN=0 or MCKPROT=0
253+ * otherwise the setting must match the initialization performed
254+ * on the Cortex-A side.
234255 */
235256 #if !defined(STM32_PLL3DIVP_VALUE) || defined(__DOXYGEN__)
236257 #define STM32_PLL3DIVP_VALUE 2
@@ -239,7 +260,9 @@
239260 /**
240261 * @brief PLL3 Q divider value.
241262 * @note The allowed values are 1..128.
242- * @note This initialization is performed only if TZEN=0 or MCKPROT=0.
263+ * @note This initialization is performed only if TZEN=0 or MCKPROT=0
264+ * otherwise the setting must match the initialization performed
265+ * on the Cortex-A side.
243266 */
244267 #if !defined(STM32_PLL3DIVQ_VALUE) || defined(__DOXYGEN__)
245268 #define STM32_PLL3DIVQ_VALUE 4
@@ -248,7 +271,9 @@
248271 /**
249272 * @brief PLL3 R divider value.
250273 * @note The allowed values are 1..128.
251- * @note This initialization is performed only if TZEN=0 or MCKPROT=0.
274+ * @note This initialization is performed only if TZEN=0 or MCKPROT=0
275+ * otherwise the setting must match the initialization performed
276+ * on the Cortex-A side.
252277 */
253278 #if !defined(STM32_PLL3DIVR_VALUE) || defined(__DOXYGEN__)
254279 #define STM32_PLL3DIVR_VALUE 4
@@ -303,7 +328,9 @@
303328
304329 /**
305330 * @brief MCU divider setting.
306- * @note This initialization is performed only if TZEN=0 or MCKPROT=0.
331+ * @note This initialization is performed only if TZEN=0 or MCKPROT=0
332+ * otherwise the setting must match the initialization performed
333+ * on the Cortex-A side.
307334 */
308335 #if !defined(STM32_MCUDIV) || defined(__DOXYGEN__)
309336 #define STM32_MCUDIV 2222222222
@@ -311,7 +338,9 @@
311338
312339 /**
313340 * @brief MCU main clock source selection.
314- * @note This initialization is performed only if TZEN=0 or MCKPROT=0.
341+ * @note This initialization is performed only if TZEN=0 or MCKPROT=0
342+ * otherwise the setting must match the initialization performed
343+ * on the Cortex-A side.
315344 */
316345 #if !defined(STM32_MCUSSRC) || defined(__DOXYGEN__)
317346 #define STM32_MCUSSRC 2222222222
@@ -405,6 +434,12 @@
405434 * @{
406435 */
407436 #define STM32_MCUSS_CK_MAX 209000000
437+
438+#define STM32_HSECLK_MAX 48000000
439+#define STM32_HSECLK_MIN 8000000
440+#define STM32_HSECLK_BYP_MAX 48000000
441+#define STM32_HSECLK_BYP_MIN 8000000
442+
408443 #define STM32_PLL3INCLK_MAX 16000000
409444 #define STM32_PLL3INCLK_MIN 4000000
410445 #define STM32_PLL3INCLK_SD_MIN 8000000
@@ -443,8 +478,9 @@
443478 #endif
444479
445480 /* Clock handlers.*/
446-//#include "stm32_csi.inc"
447-//#include "stm32_hsi64.inc"
481+#include "stm32_csi.inc"
482+#include "stm32_hsi64.inc"
483+#include "stm32_hse.inc"
448484
449485 /*
450486 * CSI related checks.
@@ -469,7 +505,7 @@
469505 * @brief PLL3 input clock frequency.
470506 */
471507 #if (STM32_PLL3SRC == STM32_PLL3SRC_HSI) || defined(__DOXYGEN__)
472- #define STM32_PLL3MCLK STM32_HSICLK
508+ #define STM32_PLL3MCLK STM32_HSI64CLK
473509
474510 #elif STM32_PLL3SRC == STM32_PLL3SRC_HSE
475511 #define STM32_PLL3MCLK STM32_HSECLK
@@ -539,7 +575,7 @@
539575 * @brief PLL4 input clock frequency.
540576 */
541577 #if (STM32_PLL4SRC == STM32_PLL4SRC_HSI) || defined(__DOXYGEN__)
542- #define STM32_PLL4MCLK STM32_HSICLK
578+ #define STM32_PLL4MCLK STM32_HSI64CLK
543579
544580 #elif STM32_PLL4SRC == STM32_PLL4SRC_HSE
545581 #define STM32_PLL4MCLK STM32_HSECLK
--- trunk/os/hal/ports/STM32/STM32MP1xx/stm32_registry.h (revision 14812)
+++ trunk/os/hal/ports/STM32/STM32MP1xx/stm32_registry.h (revision 14813)
@@ -53,6 +53,9 @@
5353 defined(__DOXYGEN__)
5454
5555 /* RCC attributes.*/
56+#define STM32_RCC_HAS_CSI TRUE
57+#define STM32_RCC_HAS_HSI64 TRUE
58+#define STM32_RCC_HAS_HSE TRUE
5659 #define STM32_RCC_HAS_PLL3 TRUE
5760 #define STM32_RCC_PLL3_HAS_P TRUE
5861 #define STM32_RCC_PLL3_HAS_Q TRUE
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