OSDN -- Develop and Download Open Source Software
  • R/O
  • HTTP
  • SSH
  • HTTPS
Fork

common_source_project-fm7: Commit

Common Source Code Project for Qt (a.k.a for FM-7).


Commit MetaInfo

Revisionad3cc0f1503678974b89f890ed56458b56134e05 (tree)
Time2019-01-07 15:14:46
AuthorK.Ohta <whatisthis.sowhat@gmai...>
CommiterK.Ohta

Log Message

[VM][FMTOWNS][WIP] Implementing main memory.Still imcomplete.

Change Summary

Incremental Difference

--- a/source/src/vm/fmtowns/towns_memory.cpp
+++ b/source/src/vm/fmtowns/towns_memory.cpp
@@ -8,7 +8,7 @@
88 */
99
1010 #include "./towns_memory.h"
11-#include "i386.h"
11+#include "../i386.h"
1212
1313 void TOWNS_MEMORY::initialize()
1414 {
@@ -84,6 +84,9 @@ void TOWNS_MEMORY::initialize()
8484 // ToDo: More smart.
8585 vram_size = 0x80000; // OK?
8686
87+ //dma_addr_reg = dma_wrap_reg = 0;
88+ dma_addr_mask = 0x00ffffff; // ToDo
89+
8790 initialize_tables();
8891 }
8992
@@ -97,7 +100,7 @@ void TOWNS_MEMORY::reset()
97100 d_cpu->set_address_mask(0xffffffff);
98101 }
99102
100-bool TOWNS_MEMORY::bank_check(uint32_t addr, uint32_t *mask, uint32_t *offset, void** readfn, void** writefn, void** readp, void** writep)
103+bool TOWNS_MEMORY::check_bank(uint32_t addr, uint32_t *mask, uint32_t *offset, void** readfn, void** writefn, void** readp, void** writep)
101104 {
102105 uint8_t __type = (uint8_t)(type_bank_adrs_cx[banknum] >> 24);
103106 uint32_t __offset = type_bank_adrs_cx[banknum] & 0x00ffffff;
@@ -188,7 +191,7 @@ bool TOWNS_MEMORY::bank_check(uint32_t addr, uint32_t *mask, uint32_t *offset, v
188191 }
189192 break;
190193 case TOWNS_MEMORY_DICT_0D0:
191- if(bank0_dict) {
194+ if(bankd0_dict) {
192195 *readp = (void*)(&(dict_rom[(addr & 0x7fff) + (((uint32_t)(dict_bank & 0x0f)) << 15))]);
193196 *writep = (void*)(&(ram_0d0[addr & 0x7fff]));
194197 } else {
@@ -197,7 +200,7 @@ bool TOWNS_MEMORY::bank_check(uint32_t addr, uint32_t *mask, uint32_t *offset, v
197200 }
198201 break;
199202 case TOWNS_MEMORY_CMOS_0D8:
200- if(bank0_dict) {
203+ if(bankd0_dict) {
201204 *offset = 0;
202205 *mask = 0x1fff;
203206 *readfn = (void *)d_cmos;
@@ -231,22 +234,87 @@ bool TOWNS_MEMORY::bank_check(uint32_t addr, uint32_t *mask, uint32_t *offset, v
231234
232235 }
233236
234-uint32_t TOWNS_MEMORY::read_data8w(uint32_t addr, int *wait)
237+
238+uint32_t TOWNS_MEMORY::read_data_base(uint32_t addr, int* wait, int wordsize)
235239 {
236240 uint8_t *maddr;
237241 DEVICE *daddr;
238242 uint32_t banknum = addr >> 12;
243+ uint32_t _naddr;
244+ switch(wordsize) {
245+ case 2:
246+ _naddr = addr & 0xfffffffe;
247+ break;
248+ case 4:
249+ _naddr = addr & 0xfffffffc;
250+ break;
251+ dafault:
252+ _naddr = addr;
253+ break;
254+ }
255+
239256 maddr = read_bank_adrs_cx[banknum];
240257 if(maddr != NULL) {
241258 // Memory found.
242259 if(wait != NULL) *wait = mem_wait_val;
243- uint8_t *p = &maddr[addr & 0x00000fff];
244- return (uint32_t)(*p);
260+ uint8_t *p;
261+ switch(wordsize) {
262+ case 1:
263+ p = &maddr[addr & 0x00000fff];
264+ return (uint32_t)(*p);
265+ break;
266+ case 2:
267+ {
268+ pair16_t _d;
269+ p = &maddr[addr & 0x00000ffe];
270+#if defined(__LITTLE_ENDIAN__)
271+ uint16_t* pp = (uint16_t*)p;
272+ _d.u16 = *pp;
273+#else
274+ _d.l = p[0];
275+ _d.h = p[1];
276+#endif
277+ return _d.u16;
278+ }
279+ break;
280+ case 4:
281+ {
282+ pair32_t _d;
283+ p = &maddr[addr & 0x00000ffc];
284+#if defined(__LITTLE_ENDIAN__)
285+ uint32_t* pp = (uint32_t*)p;
286+ _d.u32 = *pp;
287+#else
288+ _d.l = p[0];
289+ _d.h = p[1];
290+ _d.h2 = p[2];
291+ _d.h3 = p[3];
292+#endif
293+ return _d.u32;
294+ }
295+ break;
296+ default:
297+ return 0xffffffff; // Word size error
298+ break;
299+ }
245300 } else {
246301 daddr = device_bank_adrs_cx[banknum];
247302 if(daddr != NULL) {
248303 // Device chained.
249- return daddr->read_data8w(addr, wait);
304+ switch(wordsize) {
305+ case 1:
306+ return daddr->read_data8w(addr, wait);
307+ break;
308+ case 2:
309+ return daddr->read_data16w(addr, wait);
310+ break;
311+ case 4:
312+ return daddr->read_data32w(addr, wait);
313+ break;
314+ default:
315+ return 0xffffffff;
316+ break;
317+ }
250318 } else {
251319 uint32_t _mask;
252320 uint32_t _offset;
@@ -254,76 +322,64 @@ uint32_t TOWNS_MEMORY::read_data8w(uint32_t addr, int *wait)
254322 DEVICE* writefn;
255323 uint8_t* readp;
256324 uint8_t* writep;
257- if(bank_check(addr, &_mask, &_offset, (void**)(&readfn), (void**)(&writefn), (void**)(&readp), (void**)(&writep))) {
258- if(readp != NULL) {
259- if(wait != NULL) *wait = mem_wait_val;
260- return (uint32_t)(*readp);
261- } else if(readfn != NULL) {
262- return readfn->read_data8w((addr & _mask) + _offset, wait);
263- }
264- // Function or memory don't exist this bank.
265- } else {
266- // Bank not registered.
267- if((addr >= 0x000cff80) && (addr <= 0x000cffff)) {
268- bool _hit;
269- uint32_t val;
270- val = read_mmio(addr, wait, &_hit);
271- if(!_hit) {
272- ///
325+ if(check_bank(_naddr, &_mask, &_offset, (void**)(&readfn), (void**)(&writefn), (void**)(&readp), (void**)(&writep))) {
326+ switch(wordsize)
327+ {
328+ case 1:
329+ if(readp != NULL) {
330+ if(wait != NULL) *wait = mem_wait_val;
331+ return (uint32_t)(*readp);
332+ } else if(readfn != NULL) {
333+ return readfn->read_data8w(_naddr, wait);
273334 } else {
274- return val;
335+ return 0xff;
275336 }
276- }
277- }
278- }
279- // Neither memory nor device nor bank.
280- }
281- return 0xff;
282-}
283-uint32_t TOWNS_MEMORY::read_data16w(uint32_t addr, int *wait)
284-{
285- uint8_t *maddr;
286- DEVICE *daddr;
287- uint32_t banknum = addr >> 12;
288- maddr = read_bank_adrs_cx[banknum];
289- if(maddr != NULL) {
290- // Memory found.
291- if(wait != NULL) *wait = mem_wait_val;
292- uint16_t *p = (uint16_t*)(&maddr[addr & 0x00000ffe]);
293-#if defined(__LITTLE_ENDIAN__)
294- return (uint32_t)(*p);
337+ break;
338+ case 2:
339+ if(readp != NULL) {
340+
341+ if(wait != NULL) *wait = mem_wait_val;
342+#if defined(__LITTLE_ENDIAN__)
343+ uint16_t *pp = (uint16_t*)readp;
344+ return (uint32_t)(*pp);
295345 #else
296- pair16_t d, n;
297- d.w = *p;
298- n.l = d.h;
299- n.h = d.l;
300- return (uint32_t)(n.w);
346+ pair16_t _d;
347+ pair16_t *pp = (pair16_t*)readp;
348+ _d.l = pp[0];
349+ _d.h = pp[1];
350+ return _d.u16;
301351 #endif
302- } else {
303- daddr = device_bank_adrs_cx[banknum];
304- if(daddr != NULL) {
305- // Device chained.
306- return daddr->read_data16w(addr, wait);
307- } else {
308- uint32_t _mask;
309- uint32_t _offset;
310- DEVICE* readfn;
311- DEVICE* writefn;
312- uint16_t* readp;
313- uint16_t* writep;
314- if(bank_check(addr & 0xfffffffe, &_mask, &_offset, (void**)(&readfn), (void**)(&writefn), (void**)(&readp), (void**)(&writep))) {
315- if(readp != NULL) {
316- if(wait != NULL) *wait = mem_wait_val;
317-#if defined(__LITTLE_ENDIAN__)
318- return (uint32_t)(*readp);
352+ } else if(readfn != NULL) {
353+ return readfn->read_data16w(_naddr, wait);
354+ } else {
355+ return 0xffff;
356+ }
357+ break;
358+ case 2:
359+ if(readp != NULL) {
360+
361+ if(wait != NULL) *wait = mem_wait_val;
362+#if defined(__LITTLE_ENDIAN__)
363+ uint32_t *pp = (uint32_t*)readp;
364+ return (uint32_t)(*pp);
319365 #else
320- pair16_t d, n;
321- d.w = *readp;
322-
323-
324- } else if(readfn != NULL) {
325- return readfn->read_data16w((addr & _mask) + _offset, wait);
326- }
366+ pair32_t _d;
367+ _d.l = readp[0];
368+ _d.h = readp[1];
369+ _d.h2 = readp[2];
370+ _d.h3 = readp[3];
371+ return _d.u32;
372+#endif
373+ } else if(readfn != NULL) {
374+ return readfn->read_data32w(_naddr, wait);
375+ } else {
376+ return 0xffffffff;
377+ }
378+ break;
379+ default:
380+ return 0xffffffff;
381+ break;
382+ }
327383 // Function or memory don't exist this bank.
328384 } else {
329385 // Bank not registered.
@@ -341,97 +397,105 @@ uint32_t TOWNS_MEMORY::read_data16w(uint32_t addr, int *wait)
341397 }
342398 // Neither memory nor device nor bank.
343399 }
344- return 0xffff;
400+ return 0xffffffff;
401+}
402+
403+uint32_t TOWNS_MEMORY::read_data8w(uint32_t addr, int *wait)
404+{
405+ return read_data_base(addr, wait, 1);
406+}
407+uint32_t TOWNS_MEMORY::read_data16w(uint32_t addr, int *wait)
408+{
409+ return read_data_base(addr, wait, 2);
345410 }
346411
347412 uint32_t TOWNS_MEMORY::read_data32w(uint32_t addr, int *wait)
348413 {
414+ return read_data_base(addr, wait, 4);
415+}
416+
417+void TOWNS_MEMORY::write_data_base(uint32_t addr, uint32_t data, int* wait, int wordsize)
418+{
349419 uint8_t *maddr;
350420 DEVICE *daddr;
351421 uint32_t banknum = addr >> 12;
352- maddr = read_bank_adrs_cx[banknum];
422+ uint32_t _naddr;
423+ switch(wordsize) {
424+ case 2:
425+ _naddr = addr & 0xfffffffe;
426+ break;
427+ case 4:
428+ _naddr = addr & 0xfffffffc;
429+ break;
430+ dafault:
431+ _naddr = addr;
432+ break;
433+ }
434+
435+ maddr = write_bank_adrs_cx[banknum];
353436 if(maddr != NULL) {
354437 // Memory found.
355438 if(wait != NULL) *wait = mem_wait_val;
356- uint32_t *p = (uint32_t*)(&maddr[addr & 0x00000ffc]);
357-#if defined(__LITTLE_ENDIAN__)
358- return (uint32_t)(*p);
439+ uint8_t *p;
440+ switch(wordsize) {
441+ case 1:
442+ p = &maddr[addr & 0x00000fff];
443+ *p = (uint8_t)data;
444+ return;
445+ break;
446+ case 2:
447+ {
448+ pair16_t _d;
449+ _d.u16 = (uint16_t)data;
450+ p = &maddr[addr & 0x00000ffe];
451+#if defined(__LITTLE_ENDIAN__)
452+ uint16_t* pp = (uint16_t*)p;
453+ *pp = _d.u16;
359454 #else
360- pair32_t d, n;
361- d.d = (uint32_t)*p;
362- n.l = d.h3;
363- n.h = d.h2;
364- n.h2 = d.h;
365- n.h3 = d.l;
366- return n.d;
455+ p[0] = _d.l;
456+ p[1] = _d.h;
367457 #endif
368- } else {
369- daddr = device_bank_adrs_cx[banknum];
370- if(daddr != NULL) {
371- // Device chained.
372- return daddr->read_data32w(addr, wait);
373- } else {
374- uint32_t _mask;
375- uint32_t _offset;
376- DEVICE* readfn;
377- DEVICE* writefn;
378- uint32_t* readp;
379- uint32_t* writep;
380- if(bank_check(addr & 0xfffffffc, &_mask, &_offset, (void**)(&readfn), (void**)(&writefn), (void**)(&readp), (void**)(&writep))) {
381- if(readp != NULL) {
382- if(wait != NULL) *wait = mem_wait_val;
383-#if defined(__LITTLE_ENDIAN__)
384- return *readp;
458+ return;
459+ }
460+ break;
461+ case 4:
462+ {
463+ pair32_t _d;
464+ _d.u32 = data;
465+ p = &maddr[addr & 0x00000ffc];
466+#if defined(__LITTLE_ENDIAN__)
467+ uint32_t* pp = (uint32_t*)p;
468+ *pp = data;
385469 #else
386- pair32_t d, n;
387- d.d = *readp;
388- n.h2 = d.l;
389- n.h1 = d.h;
390- n.h = d.h2;
391- n.l = d.h3;
392- return n.d;
470+ p[0] = _d.l;
471+ p[1] = _d.h;
472+ p[2] = _d.h2;
473+ p[3] = _d.h3;
393474 #endif
394- } else if(readfn != NULL) {
395- return readfn->read_data32w((addr & _mask) + _offset, wait);
396- }
397- // Function or memory don't exist this bank.
398- } else {
399- // Bank not registered.
400- if((addr >= 0x000cff80) && (addr <= 0x000cffff)) {
401- bool _hit;
402- uint32_t val;
403- val = read_mmio(addr, wait, &_hit);
404- if(!_hit) {
405- ///
406- } else {
407- return val;
408- }
409- }
475+ return;
410476 }
411- // Bank not registered.
477+ break;
478+ default:
479+ return; // Word size error
480+ break;
412481 }
413- // Neither memory nor device nor bank.
414- }
415- return 0xffffffff;
416-}
417-
418-void TOWNS_MEMORY::write_data8w(uint32_t addr, uint32_t data, int *wait)
419-{
420- uint8_t *maddr;
421- DEVICE *daddr;
422- uint32_t banknum = addr >> 12;
423- maddr = write_bank_adrs_cx[banknum];
424- if(maddr != NULL) {
425- // Memory found.
426- if(wait != NULL) *wait = mem_wait_val;
427- uint8_t *p = &maddr[addr & 0x00000fff];
428- *p = (uint8_t)(data & 0x000000ff);
429- return;
430482 } else {
431483 daddr = device_bank_adrs_cx[banknum];
432484 if(daddr != NULL) {
433485 // Device chained.
434- daddr->write_data8w(addr, data, wait);
486+ switch(wordsize) {
487+ case 1:
488+ daddr->write_data8w(addr, data, wait);
489+ break;
490+ case 2:
491+ daddr->write_data16w(addr, data, wait);
492+ break;
493+ case 4:
494+ daddr->write_data32w(addr, data, wait);
495+ break;
496+ default:
497+ break;
498+ }
435499 return;
436500 } else {
437501 uint32_t _mask;
@@ -440,211 +504,116 @@ void TOWNS_MEMORY::write_data8w(uint32_t addr, uint32_t data, int *wait)
440504 DEVICE* writefn;
441505 uint8_t* readp;
442506 uint8_t* writep;
443- if(bank_check(addr, &_mask, &_offset, (void**)(&readfn), (void**)(&writefn), (void**)(&readp), (void**)(&writep))) {
444- if(writep != NULL) {
445- if(wait != NULL) *wait = mem_wait_val;
446- *writep = (uint8_t)(data & 0x000000ff);
447- return;
448- } else if(writefn != NULL) {
449- writefn->write_data8w((addr & _mask) + _offset, data, wait);
450- return;
451- }
452- // Function or memory don't exist this bank.
453- } else {
454- // Bank not registered.
455- if((addr >= 0x000cff80) && (addr <= 0x000cffff)) {
456- bool _hit;
457- write_mmio(addr, data, wait, &_hit);
458- if(!_hit) {
459- ///
460- } else {
461- return val;
507+ if(check_bank(_naddr, &_mask, &_offset, (void**)(&readfn), (void**)(&writefn), (void**)(&readp), (void**)(&writep))) {
508+ switch(wordsize)
509+ {
510+ case 1:
511+ if(writep != NULL) {
512+ if(wait != NULL) *wait = mem_wait_val;
513+ *writep = (uint8_t)data;
514+ } else if(writefn != NULL) {
515+ writefn->write_data8w(_naddr, data, wait);
462516 }
463- }
464- }
465- // Bank not registered.
466- }
467- // Neither memory nor device nor bank.
468- }
469- return;
470-}
471-
472-void TOWNS_MEMORY::write_data16w(uint32_t addr, uint32_t data, int *wait)
473-{
474- uint8_t *maddr;
475- DEVICE *daddr;
476- uint32_t banknum = addr >> 12;
477- maddr = write_bank_adrs_cx[banknum];
478- if(maddr != NULL) {
479- // Memory found.
480- if(wait != NULL) *wait = mem_wait_val;
481-#if defined(__LITTLE_ENDIAN__)
482- uint16_t *p = (uint16_t*)(&maddr[addr & 0x00000ffe]); // OK?
483- *p = (uint16_t)(data & 0x0000ffff);
517+ break;
518+ case 2:
519+ if(writep != NULL) {
520+
521+ if(wait != NULL) *wait = mem_wait_val;
522+#if defined(__LITTLE_ENDIAN__)
523+ uint16_t *pp = (uint16_t*)writep;
524+ *pp = (uint16_t)data;
484525 #else
485- uint8_t *p = (uint8_t*)(&maddr[addr & 0x00000ffe]); // OK?
486- pair16_t d;
487- d.w = (uint16_t)(data & 0xffff);
488- p[0] = d.b.l;
489- p[1] = d.b.h;
526+ pair16_t _d;
527+ _d.u16 = (uint16_t)data;
528+ writep[0] = _d.l;
529+ writep[1] = _d.h;
490530 #endif
491- return;
492- } else {
493- daddr = device_bank_adrs_cx[banknum];
494- if(daddr != NULL) {
495- // Device chained.
496- daddr->write_data16w(addr, data, wait);
497- return;
498- } else {
499- uint32_t _mask;
500- uint32_t _offset;
501- DEVICE* readfn;
502- DEVICE* writefn;
503- uint16_t* readp;
504- uint16_t* writep;
505- if(bank_check(addr & 0xfffffffe, &_mask, &_offset, (void**)(&readfn), (void**)(&writefn), (void**)(&readp), (void**)(&writep))) {
506- if(writep != NULL) {
507- if(wait != NULL) *wait = mem_wait_val;
508-#if defined(__LITTLE_ENDIAN__)
509- *writep = (uint16_t)(data & 0x0000ffff);
531+ } else if(writefn != NULL) {
532+ writefn->write_data16w(_naddr, data, wait);
533+ }
534+ break;
535+ case 4:
536+ if(writep != NULL) {
537+
538+ if(wait != NULL) *wait = mem_wait_val;
539+#if defined(__LITTLE_ENDIAN__)
540+ uint32_t *pp = (uint32_t*)writep;
541+ *pp = (uint32_t)data;
510542 #else
511- uint8_t *p = (uint8_t*)writep;
512- pair16_t d;
513- d.w = (uint16_t)(data & 0xffff);
514- p[0] = d.b.l;
515- p[1] = d.b.h;
543+ pair32_t _d;
544+ _d.u32 = data;
545+ writep[0] = _d.l;
546+ writep[1] = _d.h;
547+ writep[2] = _d.h2;
548+ writep[3] = _d.h3;
516549 #endif
517- return;
518- } else if(writefn != NULL) {
519- writefn->write_data16w((addr & _mask) + _offset, data, wait);
520- return;
521- }
550+ } else if(writefn != NULL) {
551+ writefn->write_data32w(_naddr, data, wait);
552+ }
553+ break;
554+ default:
555+ break;
556+ }
557+ return;
522558 // Function or memory don't exist this bank.
523559 } else {
524560 // Bank not registered.
525561 if((addr >= 0x000cff80) && (addr <= 0x000cffff)) {
526562 bool _hit;
527- write_mmio(addr, data, wait, &_hit);
528- if(!_hit) {
529- ///
530- return; // NOP?Exception?
531- } else {
532- return;
533- }
563+ write_mmio(addr, data, wait, &_hit); // ToDo: Not Hit
534564 }
535565 }
536- // Bank not registered.
537566 }
538567 // Neither memory nor device nor bank.
539568 }
540569 return;
570+}
571+
572+void TOWNS_MEMORY::write_data8w(uint32_t addr, uint32_t data, int *wait)
573+{
574+ write_data_base(addr, data, wait, 1);
541575 }
542576
543-void TOWNS_MEMORY::write_data32w(uint32_t addr, uint32_t data, int *wait)
577+void TOWNS_MEMORY::write_data16w(uint32_t addr, uint32_t data, int *wait)
544578 {
545- uint8_t *maddr;
546- DEVICE *daddr;
547- uint32_t banknum = addr >> 12;
548- maddr = write_bank_adrs_cx[banknum];
549- if(maddr != NULL) {
550- // Memory found.
551- if(wait != NULL) *wait = mem_wait_val;
552-#if defined(__LITTLE_ENDIAN__)
553- uint32_t *p = (uint32_t*)(&maddr[addr & 0x00000ffc]);
554- *p = data;
555-#else
556- uint8_t *p = (uint8_t*)(&maddr[addr & 0x00000ffc]);
557- pair32_t d;
558- d.d = data;
559- p[0] = d.b.l;
560- p[1] = d.b.h;
561- p[2] = d.b.h2;
562- p[3] = d.b.h3;
563-#endif
564- return;
565- } else {
566- daddr = device_bank_adrs_cx[banknum];
567- if(daddr != NULL) {
568- // Device chained.
569- daddr->write_data32w(addr, data, wait);
570- return;
571- } else {
572- uint32_t _mask;
573- uint32_t _offset;
574- DEVICE* readfn;
575- DEVICE* writefn;
576- uint32_t* readp;
577- uint32_t* writep;
578- if(bank_check(addr & 0xfffffffc, &_mask, &_offset, (void**)(&readfn), (void**)(&writefn), (void**)(&readp), (void**)(&writep))) {
579- if(writep != NULL) {
580- if(wait != NULL) *wait = mem_wait_val;
581-#if defined(__LITTLE_ENDIAN__)
582- *writep = data;
583-#else
584- uint8_t *p = (uint8_t*)writep;
585- pair32_t d;
586- d.d = data;
587- p[0] = d.b.l;
588- p[1] = d.b.h;
589- p[2] = d.b.h2;
590- p[3] = d.b.h3;
591-#endif
579+ write_data_base(addr, data, wait, 2);
580+}
592581
593- return;
594- } else if(writefn != NULL) {
595- writefn->write_data32w((addr & _mask) + _offset, data, wait);
596- return;
597- }
598- // Function or memory don't exist this bank.
599- } else {
600- // Bank not registered.
601- if((addr >= 0x000cff80) && (addr <= 0x000cffff)) {
602- bool _hit;
603- write_mmio(addr, data, wait, &_hit);
604- if(!_hit) {
605- ///
606- } else {
607- return val;
608- }
609- }
610- }
611- // Bank not registered.
612- }
613- // Neither memory nor device nor bank.
614- }
615- return;
582+void TOWNS_MEMORY::write_data32w(uint32_t addr, uint32_t data, int *wait)
583+{
584+ write_data_base(addr, data, wait, 4);
616585 }
617586
618587
619588
620589 uint32_t TOWNS_MEMORY::read_data8(uint32_t addr)
621590 {
622- return read_data8w(addr, NULL);
591+ return read_data_base(addr, NULL, 1);
623592 }
624593
625594 uint32_t TOWNS_MEMORY::read_data16(uint32_t addr)
626595 {
627- return read_data16w(addr, NULL);
596+ return read_data_base(addr, NULL, 2);
628597 }
629598
630599 uint32_t TOWNS_MEMORY::read_data32(uint32_t addr)
631600 {
632- return read_data32w(addr, NULL);
601+ return read_data_base(addr, NULL, 4);
633602 }
634603
635604 void TOWNS_MEMORY::write_data8(uint32_t addr, uint32_t data)
636605 {
637- return write_data8w(addr, data, NULL);
606+ write_data_base(addr, data, NULL, 1);
638607 }
639608
640609 void TOWNS_MEMORY::write_data16(uint32_t addr, uint32_t data)
641610 {
642- return write_data16w(addr, data, NULL);
611+ write_data_base(addr, data, NULL, 2);
643612 }
644613
645614 void TOWNS_MEMORY::write_data32(uint32_t addr, uint32_t data)
646615 {
647- return write_data32w(addr, data, NULL);
616+ write_data_base(addr, data, NULL, 4);
648617 }
649618
650619 // Address (TOWNS BASIC):
@@ -686,7 +655,7 @@ uint32_t TOWNS_MEMORY::read_io8(uint32_t addr)
686655 val = (bankc0_vram) ? 0x7f : 0xff;
687656 break;
688657 case 0x0480: // MEMORY BANK REGISTER
689- val = val & ((bank0_dict) ? 0xff : 0xfe);
658+ val = val & ((bankd0_dict) ? 0xff : 0xfe);
690659 val = val & ((bankf8_ram) ? 0xff : 0xfd);
691660 break;
692661 case 0x0484:
@@ -762,12 +731,13 @@ void TOWNS_MEMORY::write_io8(uint32_t addr, uint32_t data)
762731 case 0x0022:
763732 if((data & 0x40) != 0) {
764733 d_cpu->set_shutdown_flag(1);
765- emu->power_off;
734+ emu->power_off();
766735 }
767736 // Power register
768737 break;
769738 case 0x006c: // Wait register.
770739 if(machine_id >= 0x0300) { // After UX*/10F/20F/40H/80H
740+ if(event_wait_1us != -1) cancel_event(this, event_wait_1us);
771741 register_event(this, EVENT_1US_WAIT, 1.0, false, &event_wait_1us);
772742 d_cpu->write_signal(SIG_CPU_BUSREQ, 1, 1);
773743 }
@@ -776,7 +746,7 @@ void TOWNS_MEMORY::write_io8(uint32_t addr, uint32_t data)
776746 bankc0_vram = ((data & 0x80) != 0);
777747 break;
778748 case 0x0480: // MEMORY BANK REGISTER
779- bank0_dict = ((data & 0x01) != 0);
749+ bankd0_dict = ((data & 0x01) != 0);
780750 bankf8_ram = ((data & 0x02) != 0);
781751 break;
782752 case 0x0484:
@@ -792,8 +762,9 @@ void TOWNS_MEMORY::event_callback(int id, int err)
792762 {
793763 switch(id) {
794764 case EVENT_1US_WAIT:
765+ cvent_wait_1us = -1;
795766 if(machine_id >= 0x0300) { // After UX*/10F/20F/40H/80H
796- d_cpu->write_signal(SIG_CPU_BUSREQ, 1, 1);
767+ d_cpu->write_signal(SIG_CPU_BUSREQ, 0, 1);
797768 }
798769 break;
799770 default:
@@ -1107,76 +1078,78 @@ void TOWNS_MEMORY::write_signal(int id, uint32_t data, uint32_t mask)
11071078 d_cpu->write_signal(SIG_I386_A20, data, mask);
11081079 }
11091080 }
1081+// ToDo: DMA
1082+
1083+#define STATE_VERSION 1
11101084
1111-void TOWNS_MEMORY::update_dma_addr_mask()
1085+bool TOWNS_MEMORY::process_state(FILEIO* state_fio, bool loading)
11121086 {
1113- switch(dma_addr_reg & 3) {
1114- case 0:
1115- dma_addr_mask = d_cpu->get_address_mask();
1116- break;
1117- case 1:
1118- if(!(dma_wrap_reg & 1) && d_cpu->get_address_mask() == 0x000fffff) {
1119- dma_addr_mask = 0x000fffff;
1087+ if(!state_fio->StateCheckUint32(STATE_VERSION)) {
1088+ return false;
1089+ }
1090+ if(!state_fio->StateCheckInt32(this_device_id)) {
1091+ return false;
1092+ }
1093+ state_fio->StateValue(bankc0_vram);
1094+ state_fio->StateValue(bankf8_vram);
1095+ state_fio->StateValue(bankd0_dict);
1096+ state_fio->StateValue(ankcg_enabled);
1097+ state_fio->StateValue(dict_bank);
1098+ state_fio->StateValue(machine_id);
1099+ state_fio->StateValue(cpu_id);
1100+
1101+ state_fio->StateValue(dma_addr_mask);
1102+ //state_fio->StateValue(dma_addr_reg);
1103+ //state_fio->StateValue(dma_wrap_reg);
1104+
1105+ state_fio->StateArray(ram_page0, sizeof(ram_page0), 1);
1106+ state_fio->StateArray(ram_0c0, sizeof(ram_0c0), 1);
1107+ state_fio->StateArray(ram_0c8, sizeof(ram_0c8), 1);
1108+ state_fio->StateArray(ram_0ca, sizeof(ram_0ca), 1);
1109+ state_fio->StateArray(ram_0cb, sizeof(ram_0cb), 1);
1110+ state_fio->StateArray(ram_0cc, sizeof(ram_0cc), 1);
1111+
1112+ state_fio->StateArray(ram_0d0, sizeof(ram_0d0), 1);
1113+ state_fio->StateArray(ram_0d8, sizeof(ram_0d8), 1);
1114+ state_fio->StateArray(ram_0da, sizeof(ram_0da), 1);
1115+
1116+ state_fio->StateArray(ram_0f0, sizeof(ram_0f0), 1);
1117+ state_fio->StateArray(ram_0f8, sizeof(ram_0f8), 1);
1118+
1119+ if(loading) {
1120+ uint32_t length_tmp = state_fio->FgetUint32_LE();
1121+ if(extram != NULL) {
1122+ free(extram);
1123+ extram = NULL;
1124+ }
1125+ length_tmp = length_tmp & 0x3ff00000;
1126+ extram_size = length_tmp;
1127+ if(length_tmp > 0) {
1128+ extram = (uint8_t*)malloc(length_tmp);
1129+ }
1130+ if(extram == NULL) {
1131+ extram_size = 0;
1132+ return false;
11201133 } else {
1121- dma_addr_mask = 0x00ffffff;
1134+ state_fio->Fread(extram, extram_size, 1);
11221135 }
1123- break;
1124- default:
1125- if(!(dma_wrap_reg & 1) && d_cpu->get_address_mask() == 0x000fffff) {
1126- dma_addr_mask = 0x000fffff;
1136+ } else {
1137+ if(extram == NULL) {
1138+ state_fio->FputUint32_LE(0);
11271139 } else {
1128- dma_addr_mask = 0xffffffff;
1140+ state_fio->FputUint32_LE(extram_size & 0x3ff00000);
1141+ state_fio->Fwrite(extram, extram_size, 1);
11291142 }
1130- break;
11311143 }
1132-}
1133-
1134-#define STATE_VERSION 2
1144+
1145+ state_fio->StateValue(vram_wait_val);
1146+ state_fio->StateValue(mem_wait_val);
1147+ state_fio->StateValue(vram_size);
11351148
1136-#include "../../statesub.h"
1137-
1138-void TOWNS_MEMORY::decl_state()
1139-{
1140- enter_decl_state(STATE_VERSION);
1141-
1142- DECL_STATE_ENTRY_BOOL(bankf8_ram);
1143- DECL_STATE_ENTRY_BOOL(bankd0_dict);
1144- DECL_STATE_ENTRY_UINT32(dicrom_bank);
1145- DECL_STATE_ENTRY_UINT8(machine_id);
1146-
1147- DECL_STATE_ENTRY_UINT32(vram_wait_val);
1148- DECL_STATE_ENTRY_UINT32(mem_wait_val);
1149-
1150- DECL_STATE_ENTRY_UINT32(extram_size);
1151- DECL_STATE_ENTRY_1D_ARRAY(ram_page0, sizeof(ram_page0));
1152- DECL_STATE_ENTRY_1D_ARRAY(ram_0f0, sizeof(ram_0f0));
1153- DECL_STATE_ENTRY_1D_ARRAY(ram_0f8, sizeof(ram_0f8));
1154- DECL_STATE_ENTRY_VARARRAY_VAR(extram, extram_size);
1155-
1156- leave_decl_state();
1157-
1158-}
1159-void TOWNS_MEMORY::save_state(FILEIO* state_fio)
1160-{
1161- if(state_entry != NULL) {
1162- state_entry->save_state(state_fio);
1163- }
1164-}
1149+ // ToDo: Do save ROMs?
11651150
1166-bool TOWNS_MEMORY::load_state(FILEIO* state_fio)
1167-{
1168-
1169- bool mb = false;
1170- if(state_entry != NULL) {
1171- mb = state_entry->load_state(state_fio);
1172- this->out_debug_log(_T("Load State: MAINMEM: id=%d stat=%s\n"), this_device_id, (mb) ? _T("OK") : _T("NG"));
1173- if(!mb) return false;
1151+ if(loading) {
1152+ initialize_tables();
11741153 }
1175-
1176- // post process
1177- //update_bank();
1178- initialize_tables();
1179-
1180- return mb;
1154+ return true;
11811155 }
1182-
--- a/source/src/vm/fmtowns/towns_memory.h
+++ b/source/src/vm/fmtowns/towns_memory.h
@@ -82,12 +82,17 @@ protected:
8282
8383 bool bankc0_vram;
8484 bool bankf8_ram;
85- bool bank0_dict;
85+ bool bankd0_dict;
8686 bool ankcg_enabled;
8787 uint8_t dict_bank;
8888
8989 uint16_t machine_id;
9090 uint8_t cpu_id;
91+
92+ // ToDo: around DMA
93+ uint32_t dma_addr_mask;
94+ //uint8_t dma_addr_reg;
95+ //uint8_t dma_wrap_reg;
9196
9297 // RAM
9398 uint8_t ram_page0[0xc0000]; // 0x00000000 - 0x000bffff : RAM
@@ -124,14 +129,21 @@ protected:
124129 uint8_t rom_font20[0x80000];
125130 #endif
126131 // misc
127- uint8_t machine_id;
128- uint32_t dicrom_bank;
129132 uint32_t vram_size; // Normally 512KB.
130133
131134 uint8_t* read_bank_adrs_cx[0x100000]; // Per 4KB.
132135 uint8_t* write_bank_adrs_cx[0x100000]; // Per 4KB.
133136 DEVICE* device_bank_adrs_cx[0x100000]; // Per 4KB.
134137 uint32_t type_bank_adrs_cx[0x100000]; // Per 4KB.
138+
139+ void write_data_base(uint32_t addr, uint32_t data, int* wait, int wordsize);
140+ uint32_t read_data_base(uint32_t addr, int* wait, int wordsize);
141+ bool check_bank(uint32_t addr, uint32_t *mask, uint32_t *offset, void** readfn, void** writefn, void** readp, void** writep);
142+ virtual void initialize_tables(void);
143+
144+ virtual uint32_t read_mmio(uint32_t addr, int *wait, bool *hit);
145+ virtual void write_mmio(uint32_t addr, uint32_t data, int *wait, bool *hit);
146+
135147 public:
136148 TOWNS_MEMORY(VM_TEMPLATE* parent_vm, EMU* parent_emu) : DEVICE(parent_vm, parent_emu) {
137149 set_device_name(_T("FMTOWNS_MEMORY"));
@@ -170,12 +182,11 @@ public:
170182 void write_dma_data16(uint32_t addr, uint32_t data);
171183 uint32_t read_dma_data16(uint32_t addr);
172184
173- void write_io8(uint32_t addr, uint32_t data);
174- uint32_t read_io8(uint32_t addr);
185+ virtual void write_io8(uint32_t addr, uint32_t data);
186+ virtual uint32_t read_io8(uint32_t addr);
175187 void write_signal(int id, uint32_t data, uint32_t mask);
176188 void event_frame();
177- void save_state(FILEIO* state_fio);
178- bool load_state(FILEIO* state_fio);
189+ bool process_state(FILEIO* state_fio, bool loading);
179190
180191 // unique functions
181192 void set_context_cpu(I386* device)
Show on old repository browser