Common Source Code Project for Qt (a.k.a for FM-7).
Revision | bd40bc32b3954cc4687603d76e630762f5069cc4 (tree) |
---|---|
Time | 2019-04-24 19:03:53 |
Author | K.Ohta <whatisthis.sowhat@gmai...> |
Commiter | K.Ohta |
[VM][NEWDEV] .
@@ -22,11 +22,13 @@ | ||
22 | 22 | #define MAX_OUTPUT 16 |
23 | 23 | |
24 | 24 | // common signal id |
25 | -#define SIG_CPU_IRQ 101 | |
26 | -#define SIG_CPU_FIRQ 102 | |
27 | -#define SIG_CPU_NMI 103 | |
28 | -#define SIG_CPU_BUSREQ 104 | |
29 | -#define SIG_CPU_DEBUG 105 | |
25 | +#define SIG_CPU_IRQ 101 | |
26 | +#define SIG_CPU_FIRQ 102 | |
27 | +#define SIG_CPU_NMI 103 | |
28 | +#define SIG_CPU_BUSREQ 104 | |
29 | +#define SIG_CPU_HALTREQ 105 | |
30 | +#define SIG_CPU_DEBUG 106 | |
31 | +#define SIG_CPU_ADDRESS_DIRTY 107 | |
30 | 32 | |
31 | 33 | #define SIG_PRINTER_DATA 201 |
32 | 34 | #define SIG_PRINTER_STROBE 202 |
@@ -9,241 +9,13 @@ | ||
9 | 9 | ***************************************************************************/ |
10 | 10 | |
11 | 11 | #pragma once |
12 | +#include "../../device.h" | |
12 | 13 | |
13 | -//#ifndef __EMU_H__ | |
14 | -//#error Dont include this file directly; include emu.h instead. | |
15 | -//#endif | |
16 | - | |
17 | -#ifndef MAME_EMU_EMUMEM_H | |
18 | -#define MAME_EMU_EMUMEM_H | |
19 | - | |
20 | -#include <type_traits> | |
21 | - | |
22 | -using s8 = std::int8_t; | |
23 | -using u8 = std::uint8_t; | |
24 | -using s16 = std::int16_t; | |
25 | -using u16 = std::uint16_t; | |
26 | -using s32 = std::int32_t; | |
27 | -using u32 = std::uint32_t; | |
28 | -using s64 = std::int64_t; | |
29 | -using u64 = std::uint64_t; | |
30 | - | |
31 | -//************************************************************************** | |
32 | -// CONSTANTS | |
33 | -//************************************************************************** | |
34 | - | |
35 | -// address space names for common use | |
36 | -constexpr int AS_PROGRAM = 0; // program address space | |
37 | -constexpr int AS_DATA = 1; // data address space | |
38 | -constexpr int AS_IO = 2; // I/O address space | |
39 | -constexpr int AS_OPCODES = 3; // (decrypted) opcodes, when separate from data accesses | |
40 | - | |
41 | -// read or write constants | |
42 | -enum class read_or_write | |
43 | -{ | |
44 | - READ = 1, | |
45 | - WRITE = 2, | |
46 | - READWRITE = 3 | |
47 | -}; | |
48 | - | |
49 | - | |
50 | - | |
51 | -//************************************************************************** | |
52 | -// TYPE DEFINITIONS | |
53 | -//************************************************************************** | |
54 | - | |
55 | -// offsets and addresses are 32-bit (for now...) | |
56 | -using offs_t = u32; | |
57 | - | |
58 | -// address map constructors are delegates that build up an address_map | |
59 | -using address_map_constructor = named_delegate<void (address_map &)>; | |
60 | - | |
61 | -// struct with function pointers for accessors; use is generally discouraged unless necessary | |
62 | -struct data_accessors | |
63 | -{ | |
64 | - u8 (*read_byte)(address_space &space, offs_t address); | |
65 | - u16 (*read_word)(address_space &space, offs_t address); | |
66 | - u16 (*read_word_masked)(address_space &space, offs_t address, u16 mask); | |
67 | - u32 (*read_dword)(address_space &space, offs_t address); | |
68 | - u32 (*read_dword_masked)(address_space &space, offs_t address, u32 mask); | |
69 | - u64 (*read_qword)(address_space &space, offs_t address); | |
70 | - u64 (*read_qword_masked)(address_space &space, offs_t address, u64 mask); | |
71 | - | |
72 | - void (*write_byte)(address_space &space, offs_t address, u8 data); | |
73 | - void (*write_word)(address_space &space, offs_t address, u16 data); | |
74 | - void (*write_word_masked)(address_space &space, offs_t address, u16 data, u16 mask); | |
75 | - void (*write_dword)(address_space &space, offs_t address, u32 data); | |
76 | - void (*write_dword_masked)(address_space &space, offs_t address, u32 data, u32 mask); | |
77 | - void (*write_qword)(address_space &space, offs_t address, u64 data); | |
78 | - void (*write_qword_masked)(address_space &space, offs_t address, u64 data, u64 mask); | |
79 | -}; | |
80 | - | |
81 | - | |
82 | -// =====================-> The root class of all handlers | |
83 | - | |
84 | -// Handlers the refcounting as part of the interface | |
85 | - | |
86 | -class handler_entry | |
87 | -{ | |
88 | - DISABLE_COPYING(handler_entry); | |
89 | - | |
90 | - template<int Width, int AddrShift, endianness_t Endian> friend class address_space_specific; | |
91 | - | |
92 | -public: | |
93 | - // Typing flags | |
94 | - static constexpr u32 F_DISPATCH = 0x00000001; // handler that forwards the access to other handlers | |
95 | - static constexpr u32 F_UNITS = 0x00000002; // handler that merges/splits an access among multiple handlers (unitmask support) | |
96 | - static constexpr u32 F_PASSTHROUGH = 0x00000004; // handler that passes through the request to another handler | |
97 | - | |
98 | - // Start/end of range flags | |
99 | - static constexpr u8 START = 1; | |
100 | - static constexpr u8 END = 2; | |
101 | - | |
102 | - // Intermediary structure for reference count checking | |
103 | - class reflist { | |
104 | - public: | |
105 | - void add(const handler_entry *entry); | |
106 | - | |
107 | - void propagate(); | |
108 | - void check(); | |
109 | - | |
110 | - private: | |
111 | - std::unordered_map<const handler_entry *, u32> refcounts; | |
112 | - std::unordered_set<const handler_entry *> seen; | |
113 | - std::unordered_set<const handler_entry *> todo; | |
114 | - }; | |
115 | - | |
116 | - handler_entry(address_space *space, u32 flags) { m_space = space; m_refcount = 1; m_flags = flags; } | |
117 | - virtual ~handler_entry() {} | |
118 | - | |
119 | - inline void ref(int count = 1) const { m_refcount += count; } | |
120 | - inline void unref(int count = 1) const { m_refcount -= count; if(!m_refcount) delete this; } | |
121 | - inline u32 flags() const { return m_flags; } | |
122 | - | |
123 | - inline bool is_dispatch() const { return m_flags & F_DISPATCH; } | |
124 | - inline bool is_units() const { return m_flags & F_UNITS; } | |
125 | - inline bool is_passthrough() const { return m_flags & F_PASSTHROUGH; } | |
126 | - | |
127 | - virtual void dump_map(std::vector<memory_entry> &map) const; | |
128 | - | |
129 | - virtual std::string name() const = 0; | |
130 | - virtual void enumerate_references(handler_entry::reflist &refs) const; | |
131 | - u32 get_refcount() const { return m_refcount; } | |
132 | - | |
133 | -protected: | |
134 | - // Address range storage | |
135 | - struct range { | |
136 | - offs_t start; | |
137 | - offs_t end; | |
138 | - | |
139 | - inline void set(offs_t _start, offs_t _end) { | |
140 | - start = _start; | |
141 | - end = _end; | |
142 | - } | |
143 | - | |
144 | - inline void intersect(offs_t _start, offs_t _end) { | |
145 | - if(_start > start) | |
146 | - start = _start; | |
147 | - if(_end < end) | |
148 | - end = _end; | |
149 | - } | |
150 | - }; | |
151 | - | |
152 | - address_space *m_space; | |
153 | - mutable u32 m_refcount; | |
154 | - u32 m_flags; | |
155 | -}; | |
156 | - | |
157 | -template<int Width, int AddrShift, int Endian> class memory_access_cache | |
158 | -{ | |
159 | - //using NativeType = typename emu::detail::handler_entry_size<Width>::uX; | |
160 | - static constexpr u32 NATIVE_BYTES = 1 << Width; | |
161 | - static constexpr u32 NATIVE_MASK = Width + AddrShift >= 0 ? (1 << (Width + AddrShift)) - 1 : 0; | |
162 | - | |
163 | -public: | |
164 | - // construction/destruction | |
165 | - memory_access_cache(address_space &space, | |
166 | - handler_entry_read <Width, AddrShift, Endian> *root_read, | |
167 | - handler_entry_write<Width, AddrShift, Endian> *root_write); | |
168 | - | |
169 | - ~memory_access_cache(); | |
170 | - | |
171 | - // getters | |
172 | - address_space &space() const { return m_space; } | |
173 | - | |
174 | - // see if an address is within bounds, update it if not | |
175 | - void check_address_r(offs_t address) { | |
176 | - if(address >= m_addrstart_r && address <= m_addrend_r) | |
177 | - return; | |
178 | - m_root_read->lookup(address, m_addrstart_r, m_addrend_r, m_cache_r); | |
179 | - } | |
180 | - | |
181 | - void check_address_w(offs_t address) { | |
182 | - if(address >= m_addrstart_w && address <= m_addrend_w) | |
183 | - return; | |
184 | - m_root_write->lookup(address, m_addrstart_w, m_addrend_w, m_cache_w); | |
185 | - } | |
186 | - | |
187 | - // accessor methods | |
188 | - | |
189 | - void *read_ptr(offs_t address) { | |
190 | - check_address_r(address); | |
191 | - return m_cache_r->get_ptr(address); | |
192 | - } | |
193 | - | |
194 | - u8 read_data8(offs_t address) { address &= m_addrmask; return Width == 0 ? read_native(address & ~NATIVE_MASK) : memory_read_generic<Width, AddrShift, Endian, 0, true>([this](offs_t offset, NativeType mask) -> NativeType { return read_native(offset, mask); }, address, 0xff); } | |
195 | - u16 read_data16(offs_t address) { address &= m_addrmask; return Width == 1 ? read_native(address & ~NATIVE_MASK) : memory_read_generic<Width, AddrShift, Endian, 1, true>([this](offs_t offset, NativeType mask) -> NativeType { return read_native(offset, mask); }, address, 0xffff); } | |
196 | - u16 read_data16(offs_t address, u16 mask) { address &= m_addrmask; return memory_read_generic<Width, AddrShift, Endian, 1, true>([this](offs_t offset, NativeType mask) -> NativeType { return read_native(offset, mask); }, address, mask); } | |
197 | - u16 read_data16_unaligned(offs_t address) { address &= m_addrmask; return memory_read_generic<Width, AddrShift, Endian, 1, false>([this](offs_t offset, NativeType mask) -> NativeType { return read_native(offset, mask); }, address, 0xffff); } | |
198 | - u16 read_data16_unaligned(offs_t address, u16 mask) { address &= m_addrmask; return memory_read_generic<Width, AddrShift, Endian, 1, false>([this](offs_t offset, NativeType mask) -> NativeType { return read_native(offset, mask); }, address, mask); } | |
199 | - u32 read_data32(offs_t address) { address &= m_addrmask; return Width == 2 ? read_native(address & ~NATIVE_MASK) : memory_read_generic<Width, AddrShift, Endian, 2, true>([this](offs_t offset, NativeType mask) -> NativeType { return read_native(offset, mask); }, address, 0xffffffff); } | |
200 | - u32 read_data32(offs_t address, u32 mask) { address &= m_addrmask; return memory_read_generic<Width, AddrShift, Endian, 2, true>([this](offs_t offset, NativeType mask) -> NativeType { return read_native(offset, mask); }, address, mask); } | |
201 | - u32 read_data32_unaligned(offs_t address) { address &= m_addrmask; return memory_read_generic<Width, AddrShift, Endian, 2, false>([this](offs_t offset, NativeType mask) -> NativeType { return read_native(offset, mask); }, address, 0xffffffff); } | |
202 | - u32 read_data32_unaligned(offs_t address, u32 mask) { address &= m_addrmask; return memory_read_generic<Width, AddrShift, Endian, 2, false>([this](offs_t offset, NativeType mask) -> NativeType { return read_native(offset, mask); }, address, mask); } | |
203 | - u64 read_data64(offs_t address) { address &= m_addrmask; return Width == 3 ? read_native(address & ~NATIVE_MASK) : memory_read_generic<Width, AddrShift, Endian, 3, true>([this](offs_t offset, NativeType mask) -> NativeType { return read_native(offset, mask); }, address, 0xffffffffffffffffU); } | |
204 | - u64 read_data64(offs_t address, u64 mask) { address &= m_addrmask; return memory_read_generic<Width, AddrShift, Endian, 3, true>([this](offs_t offset, NativeType mask) -> NativeType { return read_native(offset, mask); }, address, mask); } | |
205 | - u64 read_data64_unaligned(offs_t address) { address &= m_addrmask; return memory_read_generic<Width, AddrShift, Endian, 3, false>([this](offs_t offset, NativeType mask) -> NativeType { return read_native(offset, mask); }, address, 0xffffffffffffffffU); } | |
206 | - u64 read_data64_unaligned(offs_t address, u64 mask) { address &= m_addrmask; return memory_read_generic<Width, AddrShift, Endian, 3, false>([this](offs_t offset, NativeType mask) -> NativeType { return read_native(offset, mask); }, address, mask); } | |
207 | - | |
208 | - void write_data8(offs_t address, u8 data) { address &= m_addrmask; if (Width == 0) write_native(address & ~NATIVE_MASK, data); else memory_write_generic<Width, AddrShift, Endian, 0, true>([this](offs_t offset, NativeType data, NativeType mask) { write_native(offset, data, mask); }, address, data, 0xff); } | |
209 | - void write_data16(offs_t address, u16 data) { address &= m_addrmask; if (Width == 1) write_native(address & ~NATIVE_MASK, data); else memory_write_generic<Width, AddrShift, Endian, 1, true>([this](offs_t offset, NativeType data, NativeType mask) { write_native(offset, data, mask); }, address, data, 0xffff); } | |
210 | - void write_data16(offs_t address, u16 data, u16 mask) { address &= m_addrmask; memory_write_generic<Width, AddrShift, Endian, 1, true>([this](offs_t offset, NativeType data, NativeType mask) { write_native(offset, data, mask); }, address, data, mask); } | |
211 | - void write_data16_unaligned(offs_t address, u16 data) { address &= m_addrmask; memory_write_generic<Width, AddrShift, Endian, 1, false>([this](offs_t offset, NativeType data, NativeType mask) { write_native(offset, data, mask); }, address, data, 0xffff); } | |
212 | - void write_data16_unaligned(offs_t address, u16 data, u16 mask) { address &= m_addrmask; memory_write_generic<Width, AddrShift, Endian, 1, false>([this](offs_t offset, NativeType data, NativeType mask) { write_native(offset, data, mask); }, address, data, mask); } | |
213 | - void write_data32(offs_t address, u32 data) { address &= m_addrmask; if (Width == 2) write_native(address & ~NATIVE_MASK, data); else memory_write_generic<Width, AddrShift, Endian, 2, true>([this](offs_t offset, NativeType data, NativeType mask) { write_native(offset, data, mask); }, address, data, 0xffffffff); } | |
214 | - void write_data32(offs_t address, u32 data, u32 mask) { address &= m_addrmask; memory_write_generic<Width, AddrShift, Endian, 2, true>([this](offs_t offset, NativeType data, NativeType mask) { write_native(offset, data, mask); }, address, data, mask); } | |
215 | - void write_data32_unaligned(offs_t address, u32 data) { address &= m_addrmask; memory_write_generic<Width, AddrShift, Endian, 2, false>([this](offs_t offset, NativeType data, NativeType mask) { write_native(offset, data, mask); }, address, data, 0xffffffff); } | |
216 | - void write_data32_unaligned(offs_t address, u32 data, u32 mask) { address &= m_addrmask; memory_write_generic<Width, AddrShift, Endian, 2, false>([this](offs_t offset, NativeType data, NativeType mask) { write_native(offset, data, mask); }, address, data, mask); } | |
217 | - void write_data64(offs_t address, u64 data) { address &= m_addrmask; if (Width == 3) write_native(address & ~NATIVE_MASK, data); else memory_write_generic<Width, AddrShift, Endian, 3, true>([this](offs_t offset, NativeType data, NativeType mask) { write_native(offset, data, mask); }, address, data, 0xffffffffffffffffU); } | |
218 | - void write_data64(offs_t address, u64 data, u64 mask) { address &= m_addrmask; memory_write_generic<Width, AddrShift, Endian, 3, true>([this](offs_t offset, NativeType data, NativeType mask) { write_native(offset, data, mask); }, address, data, mask); } | |
219 | - void write_data64_unaligned(offs_t address, u64 data) { address &= m_addrmask; memory_write_generic<Width, AddrShift, Endian, 3, false>([this](offs_t offset, NativeType data, NativeType mask) { write_native(offset, data, mask); }, address, data, 0xffffffffffffffffU); } | |
220 | - void write_data64_unaligned(offs_t address, u64 data, u64 mask) { address &= m_addrmask; memory_write_generic<Width, AddrShift, Endian, 3, false>([this](offs_t offset, NativeType data, NativeType mask) { write_native(offset, data, mask); }, address, data, mask); } | |
221 | - | |
222 | -private: | |
223 | - address_space & m_space; | |
224 | - | |
225 | - //int m_notifier_id; // id to remove the notifier on destruction | |
226 | - | |
227 | - offs_t m_addrmask; // address mask | |
228 | - offs_t m_addrstart_r; // minimum valid address for reading | |
229 | - offs_t m_addrend_r; // maximum valid address for reading | |
230 | - offs_t m_addrstart_w; // minimum valid address for writing | |
231 | - offs_t m_addrend_w; // maximum valid address for writing | |
232 | - handler_entry_read<Width, AddrShift, Endian> *m_cache_r; // read cache | |
233 | - handler_entry_write<Width, AddrShift, Endian> *m_cache_w; // write cache | |
234 | - | |
235 | - handler_entry_read <Width, AddrShift, Endian> *m_root_read; // decode tree roots | |
236 | - handler_entry_write<Width, AddrShift, Endian> *m_root_write; | |
237 | - | |
238 | - uint8_t read_native(offs_t address, uint8_t mask = 0xff); | |
239 | - uint16_t read_native(offs_t address, uint16_t mask = 0xffff); | |
240 | - uint32_t read_native(offs_t address, uint32_t mask = 0xffffffff); | |
241 | - uint64_t read_native(offs_t address, uint64_t mask = 0xffffffffffffffff); | |
242 | - | |
243 | - void write_native(offs_t address, uint8_t data, uint8_t mask = 0xff); | |
244 | - void write_native(offs_t address, uint16_t data, uint16_t mask = 0xffff); | |
245 | - void write_native(offs_t address, uint32_t data, uint32_t mask = 0xffffffff); | |
246 | - void write_native(offs_t address, uint64_t data, uint64_t mask = 0xffffffffffffffff); | |
14 | +enum { | |
15 | + CACHE_LINE_NOCACHE = 0, | |
16 | + CACHE_LINE_READ = 1, | |
17 | + CACHE_LINE_WRITE = 2, | |
18 | + CACHE_LINE_READ_WRITE =3 | |
247 | 19 | }; |
248 | 20 | |
249 | 21 | class DEVICE; |
@@ -256,11 +28,12 @@ private: | ||
256 | 28 | bool enabled; |
257 | 29 | uint32_t start_addr; |
258 | 30 | uint32_t end_addr; |
31 | + int access_type; | |
259 | 32 | uint8_t *cache_data; |
260 | 33 | bool *is_exists; |
261 | 34 | bool is_little_endian; |
262 | 35 | public: |
263 | - cache_line(uint32_t start, uint32_t line_size, int prefetch_size = -1) | |
36 | + cache_line(uint32_t start, uint32_t line_size, DEVICE* dev = NULL, int type = CACHE_LINE_READ_WRITE, int prefetch_size = -1) | |
264 | 37 | { |
265 | 38 | prefetch_enabled = (prefetch_size > 0) ? true : false; |
266 | 39 | prefetch_block_size = prefetch_size; |
@@ -269,7 +42,8 @@ public: | ||
269 | 42 | is_exists = nullptr; |
270 | 43 | start_addr = start; |
271 | 44 | end_addr = start_addr; |
272 | - d_device = NULL; | |
45 | + access_type = type; | |
46 | + d_device = dev; | |
273 | 47 | if(line_size > 0) { |
274 | 48 | cache_data = new uint8_t[line_size]; |
275 | 49 | is_exists = new bool[line_size]; |
@@ -341,6 +115,10 @@ public: | ||
341 | 115 | } |
342 | 116 | return false; |
343 | 117 | } |
118 | + int set_prefetch_block_size(int bytes) | |
119 | + { | |
120 | + prefetch_block_size = bytes; | |
121 | + } | |
344 | 122 | bool request_prefetch(uint32_t start) |
345 | 123 | { |
346 | 124 | if(prefetch_block_size <= 0) return false; |
@@ -396,11 +174,32 @@ public: | ||
396 | 174 | } |
397 | 175 | return true; |
398 | 176 | } |
399 | - uint32_t read_data8w(uint32_t addr, int* wait, bool *is_hit) | |
177 | + void clear_all() | |
178 | + { | |
179 | + if(end_addr < start_addr) return; | |
180 | + uint32_t _size = end_addr - start_addr + 1; | |
181 | + memset(cache_data, 0x00, _size * sizeof(uint8_t)); | |
182 | + for(uint32\t i = 0; i < _size; i++) { | |
183 | + is_exists[i] = false; | |
184 | + } | |
185 | + } | |
186 | + void change_access_mode(int new_mode) | |
187 | + { | |
188 | + int old_mode = access_type; | |
189 | + if((old_mode & 3) == (new_mode & 3)) return; | |
190 | + if((old_mode & CACHE_LINE_READ) != (new_mode & CACHE_LINE_READ)) { // Discard cache. | |
191 | + clear_all(); | |
192 | + } | |
193 | + access_type = new_mode; | |
194 | + } | |
195 | + inline uint32_t read_data8w(uint32_t addr, int* wait) | |
400 | 196 | { |
197 | + if((access_type & CACHE_LINE_READ) == 0) { | |
198 | + is_exists[addr - start_addr] = false; | |
199 | + return d_device->read_data8w(addr, wait); | |
200 | + } | |
401 | 201 | if(cache_hit(addr)) { |
402 | 202 | if(wait != nullptr) *wait = 0; |
403 | - if(is_hit != nullptr) *is_hit = true; | |
404 | 203 | return (uint32_t)(cache_data[addr - start_addr]); |
405 | 204 | } |
406 | 205 |
@@ -409,69 +208,80 @@ public: | ||
409 | 208 | uint32_t data = d_device->read_data8w(addr, wait); |
410 | 209 | cache_data[addr - start_addr] = (uint8_t)data; |
411 | 210 | is_exists[addr - start_addr] = true; |
412 | - if(is_hit != nullptr) *is_hit = true; | |
413 | 211 | return data; |
414 | 212 | } else { |
415 | - cache_data[addr - start_addr] = (uint8_t)0x00; | |
213 | + cache_data[addr - start_addr] = (uint8_t)0xff; | |
416 | 214 | is_exists[addr - start_addr] = false; |
417 | - if(is_hit != nullptr) *is_hit = true; | |
418 | 215 | return 0xff; |
419 | 216 | } |
420 | 217 | } |
421 | - if(is_hit != nullptr) *is_hit = false; | |
422 | 218 | return 0xff; |
423 | 219 | } |
424 | 220 | // ToDo: endian |
425 | - uint32_t read_data16w(uint32_t addr, int* wait, bool *is_hit) | |
221 | + uint32_t read_data16w(uint32_t addr, int* wait) | |
426 | 222 | { |
427 | 223 | pair16_t n; |
224 | + if((access_type & CACHE_LINE_READ) == 0) { | |
225 | + //is_exists[addr - start_addr] = false; | |
226 | + //is_exists[addr - start_addr + 1] = false; | |
227 | + return d_device->read_data16w(addr, wait); | |
228 | + } | |
428 | 229 | if(cache_hit_range(addr, 2)) { |
230 | + if(wait != nullptr) *wait = 0; | |
429 | 231 | n.b.l = cache_data[addr - start_addr + 0]; |
430 | 232 | n.b.h = cache_data[addr - start_addr + 1]; |
431 | - if(is_hit != NULL) *is_hit = true; | |
432 | 233 | return (uint32_t)(n.w); |
433 | 234 | } else { |
434 | - bool bl, bh; | |
435 | - n.b.l = read_data8w(addr + 0, wait, &bl); | |
436 | - n.b.h = read_data8w(addr + 0, wait, &bh); | |
437 | - if(is_hit != NULL) *is_hit = (bl & bh); | |
438 | - if((bl) && (bh)) return (uint32_t)(n.w); | |
235 | + n.b.l = read_data8w(addr + 0, wait); | |
236 | + n.b.h = read_data8w(addr + 0, wait); | |
237 | + return (uint32_t)(n.w); | |
439 | 238 | } |
440 | 239 | return 0xffff; |
441 | 240 | } |
442 | - uint32_t read_data32w(uint32_t addr, int* wait, bool *is_hit) | |
241 | + uint32_t read_data32w(uint32_t addr, int* wait) | |
443 | 242 | { |
444 | 243 | pair32_t n; |
244 | + if((access_type & CACHE_LINE_READ) == 0) { | |
245 | + return d_device->read_data32w(addr, wait); | |
246 | + } | |
445 | 247 | if(cache_hit_range(addr, 4)) { |
248 | + if(wait != nullptr) *wait = 0; | |
446 | 249 | n.b.l = cache_data[addr - start_addr + 0]; |
447 | 250 | n.b.h = cache_data[addr - start_addr + 1]; |
448 | 251 | n.b.h2 = cache_data[addr - start_addr + 2]; |
449 | 252 | n.b.h3 = cache_data[addr - start_addr + 3]; |
450 | - if(is_hit != NULL) *is_hit = true; | |
451 | 253 | return n.d; |
452 | 254 | } else { |
453 | - bool bl, bh, bh2, bh3; | |
454 | - n.b.l = read_data8w(addr + 0, wait, &bl); | |
455 | - n.b.h = read_data8w(addr + 1, wait, &bh); | |
456 | - n.b.h2 = read_data8w(addr + 2, wait, &bh2); | |
457 | - n.b.h2 = read_data8w(addr + 2, wait, &bh3); | |
458 | - if(is_hit != NULL) *is_hit = (bl & bh & bh2 & bh3); | |
459 | - if((bl) && (bh) && (bh2) && (bh3)) { | |
460 | - return n.d; | |
461 | - } | |
255 | + n.b.l = read_data8w(addr + 0, wait); | |
256 | + n.b.h = read_data8w(addr + 1, wait); | |
257 | + n.b.h2 = read_data8w(addr + 2, wait); | |
258 | + n.b.h3 = read_data8w(addr + 3, wait); | |
259 | + return n.d; | |
462 | 260 | } |
463 | 261 | return 0xffffffff; |
464 | 262 | } |
465 | - void write_data8w(uint32_t addr, uint32_t data, int* wait) | |
263 | + inline void write_data8w(uint32_t addr, uint32_t data, int* wait) | |
466 | 264 | { |
467 | 265 | if(region_check(addr)) { |
468 | - if(d_device != NULL) { | |
469 | - d_device->write_data8w(addr, wait); | |
470 | - cache_data[addr - start_addr] = (uint8_t)data; | |
471 | - is_exists[addr - start_addr] = true; | |
472 | - } else { | |
473 | - if(wait != nullptr) *wait = 0; | |
474 | - cache_data[addr - start_addr] = (uint8_t)0xff; | |
266 | + if((access_type & CACHE_TYPE_WRITE) != 0) { | |
267 | + if(d_device != NULL) { | |
268 | + d_device->write_data8w(addr, data, wait); | |
269 | + } else { | |
270 | + if(wait != nullptr) *wait = 0; | |
271 | + data = 0xff; | |
272 | + } | |
273 | + if((access_type & CACHE_LINE_READ) != 0) { | |
274 | + cache_data[addr - start_addr] = (uint8_t)data; | |
275 | + is_exists[addr - start_addr] = true; | |
276 | + } | |
277 | + } else if((access_type & CACHE_TYPE_READ) != 0) { // read Only | |
278 | + if(is_exists[addr - start_addr]) return; | |
279 | + if(d_device != NULL) { | |
280 | + cache_data[addr - start_addr] = d_device->read_data8w(addr, wait); | |
281 | + } else { | |
282 | + if(wait != nullptr) *wait = 0; | |
283 | + cache_data[addr - start_addr] = 0xff; | |
284 | + } | |
475 | 285 | is_exists[addr - start_addr] = true; |
476 | 286 | } |
477 | 287 | } |