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leon-mjpeg: Commit

motionJPEG play on LEON processor


Commit MetaInfo

Revision771f684cfd9d8362f66569267cf58cf56a2261cf (tree)
Time2012-01-15 17:40:42
AuthorKenichi Kurimoto <kurimoto12@user...>
CommiterKenichi Kurimoto

Log Message

add branch work_amba

Change Summary

Incremental Difference

--- /dev/null
+++ b/grlib-gpl-1.0.22-b4095/designs/work_amba/.config
@@ -0,0 +1,321 @@
1+#
2+# Automatically generated make config: don't edit
3+#
4+
5+#
6+# Synthesis
7+#
8+# CONFIG_SYN_INFERRED is not set
9+# CONFIG_SYN_STRATIX is not set
10+# CONFIG_SYN_STRATIXII is not set
11+# CONFIG_SYN_STRATIXIII is not set
12+CONFIG_SYN_CYCLONEIII=y
13+# CONFIG_SYN_ALTERA is not set
14+# CONFIG_SYN_AXCEL is not set
15+# CONFIG_SYN_AXDSP is not set
16+# CONFIG_SYN_PROASIC is not set
17+# CONFIG_SYN_PROASICPLUS is not set
18+# CONFIG_SYN_PROASIC3 is not set
19+# CONFIG_SYN_IGLOO is not set
20+# CONFIG_SYN_UT025CRH is not set
21+# CONFIG_SYN_ATC18 is not set
22+# CONFIG_SYN_ATC18RHA is not set
23+# CONFIG_SYN_CUSTOM1 is not set
24+# CONFIG_SYN_EASIC90 is not set
25+# CONFIG_SYN_IHP25 is not set
26+# CONFIG_SYN_IHP25RH is not set
27+# CONFIG_SYN_LATTICE is not set
28+# CONFIG_SYN_ECLIPSE is not set
29+# CONFIG_SYN_PEREGRINE is not set
30+# CONFIG_SYN_RH_LIB18T is not set
31+# CONFIG_SYN_RHUMC is not set
32+# CONFIG_SYN_SMIC13 is not set
33+# CONFIG_SYN_SPARTAN2 is not set
34+# CONFIG_SYN_SPARTAN3 is not set
35+# CONFIG_SYN_SPARTAN3E is not set
36+# CONFIG_SYN_VIRTEX is not set
37+# CONFIG_SYN_VIRTEXE is not set
38+# CONFIG_SYN_VIRTEX2 is not set
39+# CONFIG_SYN_VIRTEX4 is not set
40+# CONFIG_SYN_VIRTEX5 is not set
41+# CONFIG_SYN_UMC is not set
42+# CONFIG_SYN_TSMC90 is not set
43+# CONFIG_SYN_INFER_RAM is not set
44+# CONFIG_SYN_INFER_PADS is not set
45+# CONFIG_SYN_NO_ASYNC is not set
46+# CONFIG_SYN_SCAN is not set
47+
48+#
49+# Clock generation
50+#
51+# CONFIG_CLK_INFERRED is not set
52+# CONFIG_CLK_HCLKBUF is not set
53+CONFIG_CLK_ALTDLL=y
54+# CONFIG_CLK_LATDLL is not set
55+# CONFIG_CLK_PRO3PLL is not set
56+# CONFIG_CLK_LIB18T is not set
57+# CONFIG_CLK_RHUMC is not set
58+# CONFIG_CLK_CLKDLL is not set
59+# CONFIG_CLK_DCM is not set
60+CONFIG_CLK_MUL=5
61+CONFIG_CLK_DIV=5
62+# CONFIG_PCI_SYSCLK is not set
63+CONFIG_LEON3=y
64+CONFIG_PROC_NUM=1
65+
66+#
67+# Processor
68+#
69+
70+#
71+# Integer unit
72+#
73+CONFIG_IU_NWINDOWS=8
74+CONFIG_IU_V8MULDIV=y
75+# CONFIG_IU_MUL_LATENCY_2 is not set
76+# CONFIG_IU_MUL_LATENCY_4 is not set
77+CONFIG_IU_MUL_LATENCY_5=y
78+# CONFIG_IU_MUL_MAC is not set
79+# CONFIG_IU_SVT is not set
80+CONFIG_IU_LDELAY=1
81+CONFIG_IU_WATCHPOINTS=2
82+# CONFIG_PWD is not set
83+CONFIG_IU_RSTADDR=00000
84+
85+#
86+# Floating-point unit
87+#
88+# CONFIG_FPU_ENABLE is not set
89+
90+#
91+# Cache system
92+#
93+CONFIG_ICACHE_ENABLE=y
94+# CONFIG_ICACHE_ASSO1 is not set
95+CONFIG_ICACHE_ASSO2=y
96+# CONFIG_ICACHE_ASSO3 is not set
97+# CONFIG_ICACHE_ASSO4 is not set
98+# CONFIG_ICACHE_SZ1 is not set
99+# CONFIG_ICACHE_SZ2 is not set
100+CONFIG_ICACHE_SZ4=y
101+# CONFIG_ICACHE_SZ8 is not set
102+# CONFIG_ICACHE_SZ16 is not set
103+# CONFIG_ICACHE_SZ32 is not set
104+# CONFIG_ICACHE_SZ64 is not set
105+# CONFIG_ICACHE_SZ128 is not set
106+# CONFIG_ICACHE_SZ256 is not set
107+# CONFIG_ICACHE_LZ16 is not set
108+CONFIG_ICACHE_LZ32=y
109+# CONFIG_ICACHE_ALGORND is not set
110+CONFIG_ICACHE_ALGOLRR=y
111+# CONFIG_ICACHE_ALGOLRU is not set
112+# CONFIG_ICACHE_LOCK is not set
113+CONFIG_DCACHE_ENABLE=y
114+# CONFIG_DCACHE_ASSO1 is not set
115+CONFIG_DCACHE_ASSO2=y
116+# CONFIG_DCACHE_ASSO3 is not set
117+# CONFIG_DCACHE_ASSO4 is not set
118+# CONFIG_DCACHE_SZ1 is not set
119+# CONFIG_DCACHE_SZ2 is not set
120+CONFIG_DCACHE_SZ4=y
121+# CONFIG_DCACHE_SZ8 is not set
122+# CONFIG_DCACHE_SZ16 is not set
123+# CONFIG_DCACHE_SZ32 is not set
124+# CONFIG_DCACHE_SZ64 is not set
125+# CONFIG_DCACHE_SZ128 is not set
126+# CONFIG_DCACHE_SZ256 is not set
127+CONFIG_DCACHE_LZ16=y
128+# CONFIG_DCACHE_LZ32 is not set
129+# CONFIG_DCACHE_ALGORND is not set
130+CONFIG_DCACHE_ALGOLRR=y
131+# CONFIG_DCACHE_ALGOLRU is not set
132+# CONFIG_DCACHE_LOCK is not set
133+CONFIG_DCACHE_SNOOP=y
134+# CONFIG_DCACHE_SNOOP_FAST is not set
135+# CONFIG_DCACHE_SNOOP_SEPTAG is not set
136+CONFIG_CACHE_FIXED=0
137+
138+#
139+# MMU
140+#
141+CONFIG_MMU_ENABLE=y
142+# CONFIG_MMU_COMBINED is not set
143+CONFIG_MMU_SPLIT=y
144+# CONFIG_MMU_REPARRAY is not set
145+CONFIG_MMU_REPINCREMENT=y
146+# CONFIG_MMU_I2 is not set
147+# CONFIG_MMU_I4 is not set
148+CONFIG_MMU_I8=y
149+# CONFIG_MMU_I16 is not set
150+# CONFIG_MMU_I32 is not set
151+# CONFIG_MMU_D2 is not set
152+# CONFIG_MMU_D4 is not set
153+CONFIG_MMU_D8=y
154+# CONFIG_MMU_D16 is not set
155+# CONFIG_MMU_D32 is not set
156+CONFIG_MMU_FASTWB=y
157+CONFIG_MMU_PAGE_4K=y
158+# CONFIG_MMU_PAGE_8K is not set
159+# CONFIG_MMU_PAGE_16K is not set
160+# CONFIG_MMU_PAGE_32K is not set
161+# CONFIG_MMU_PAGE_PROG is not set
162+
163+#
164+# Debug Support Unit
165+#
166+CONFIG_DSU_ENABLE=y
167+CONFIG_DSU_ITRACE=y
168+# CONFIG_DSU_ITRACESZ1 is not set
169+CONFIG_DSU_ITRACESZ2=y
170+# CONFIG_DSU_ITRACESZ4 is not set
171+# CONFIG_DSU_ITRACESZ8 is not set
172+# CONFIG_DSU_ITRACESZ16 is not set
173+CONFIG_DSU_ATRACE=y
174+# CONFIG_DSU_ATRACESZ1 is not set
175+CONFIG_DSU_ATRACESZ2=y
176+# CONFIG_DSU_ATRACESZ4 is not set
177+# CONFIG_DSU_ATRACESZ8 is not set
178+# CONFIG_DSU_ATRACESZ16 is not set
179+
180+#
181+# Fault-tolerance
182+#
183+
184+#
185+# VHDL debug settings
186+#
187+# CONFIG_IU_DISAS is not set
188+# CONFIG_DEBUG_PC32 is not set
189+
190+#
191+# AMBA configuration
192+#
193+CONFIG_AHB_DEFMST=0
194+CONFIG_AHB_RROBIN=y
195+# CONFIG_AHB_SPLIT is not set
196+CONFIG_AHB_IOADDR=FFF
197+CONFIG_APB_HADDR=800
198+# CONFIG_AHB_MON is not set
199+
200+#
201+# Debug Link
202+#
203+# CONFIG_DSU_UART is not set
204+CONFIG_DSU_JTAG=y
205+CONFIG_DSU_ETH=y
206+# CONFIG_DSU_ETHSZ1 is not set
207+CONFIG_DSU_ETHSZ2=y
208+# CONFIG_DSU_ETHSZ4 is not set
209+# CONFIG_DSU_ETHSZ8 is not set
210+# CONFIG_DSU_ETHSZ16 is not set
211+CONFIG_DSU_IPMSB=C0A8
212+CONFIG_DSU_IPLSB=0039
213+CONFIG_DSU_ETHMSB=020000
214+CONFIG_DSU_ETHLSB=000011
215+# CONFIG_DSU_ETH_PROG is not set
216+
217+#
218+# Peripherals
219+#
220+
221+#
222+# Memory controllers
223+#
224+
225+#
226+# Leon2 memory controller
227+#
228+CONFIG_MCTRL_LEON2=y
229+# CONFIG_MCTRL_8BIT is not set
230+CONFIG_MCTRL_16BIT=y
231+# CONFIG_MCTRL_5CS is not set
232+# CONFIG_MCTRL_SDRAM is not set
233+
234+#
235+# Synchronous SRAM controller
236+#
237+# CONFIG_SSCTRL is not set
238+
239+#
240+# DDR266 SDRAM controller
241+#
242+CONFIG_DDRSP=y
243+CONFIG_DDRSP_INIT=y
244+CONFIG_DDRSP_FREQ=100
245+CONFIG_DDRSP_COL=9
246+CONFIG_DDRSP_MBYTE=8
247+CONFIG_DDRSP_RSKEW=2500
248+
249+#
250+# SPI memory controller
251+#
252+# CONFIG_SPIMCTRL is not set
253+
254+#
255+# On-chip RAM/ROM
256+#
257+# CONFIG_AHBROM_ENABLE is not set
258+# CONFIG_AHBRAM_ENABLE is not set
259+
260+#
261+# Ethernet
262+#
263+CONFIG_GRETH_ENABLE=y
264+# CONFIG_GRETH_GIGA is not set
265+# CONFIG_GRETH_FIFO4 is not set
266+# CONFIG_GRETH_FIFO8 is not set
267+# CONFIG_GRETH_FIFO16 is not set
268+# CONFIG_GRETH_FIFO32 is not set
269+CONFIG_GRETH_FIFO64=y
270+
271+#
272+# UARTs, timers and irq control
273+#
274+CONFIG_UART1_ENABLE=y
275+# CONFIG_UA1_FIFO1 is not set
276+# CONFIG_UA1_FIFO2 is not set
277+# CONFIG_UA1_FIFO4 is not set
278+CONFIG_UA1_FIFO8=y
279+# CONFIG_UA1_FIFO16 is not set
280+# CONFIG_UA1_FIFO32 is not set
281+CONFIG_IRQ3_ENABLE=y
282+# CONFIG_IRQ3_SEC is not set
283+CONFIG_GPT_ENABLE=y
284+CONFIG_GPT_NTIM=2
285+CONFIG_GPT_SW=8
286+CONFIG_GPT_TW=32
287+CONFIG_GPT_IRQ=8
288+CONFIG_GPT_SEPIRQ=y
289+# CONFIG_GPT_WDOGEN is not set
290+CONFIG_GRGPIO_ENABLE=y
291+CONFIG_GRGPIO_WIDTH=5
292+CONFIG_GRGPIO_IMASK=0
293+
294+#
295+# Serial interfaces; I2C, PS/2 and SPI
296+#
297+CONFIG_I2C_ENABLE=y
298+CONFIG_PS2_ENABLE=y
299+
300+#
301+# SPI controller
302+#
303+CONFIG_SPICTRL_ENABLE=y
304+CONFIG_SPICTRL_SLVS=1
305+CONFIG_SPICTRL_FIFO=2
306+CONFIG_SPICTRL_SLVREG=y
307+# CONFIG_SPICTRL_ASEL is not set
308+# CONFIG_SPICTRL_AM is not set
309+# CONFIG_SPICTRL_ODMODE is not set
310+
311+#
312+# LCD and VGA DAC
313+#
314+CONFIG_LCD_ENABLE=y
315+CONFIG_LCD3T_ENABLE=y
316+# CONFIG_SVGA_ENABLE is not set
317+
318+#
319+# VHDL Debugging
320+#
321+# CONFIG_DEBUG_UART is not set
--- /dev/null
+++ b/grlib-gpl-1.0.22-b4095/designs/work_amba/Makefile
@@ -0,0 +1,32 @@
1+GRLIB=../..
2+TOP=bus_amba
3+BOARD=altera-ep3c25-eek
4+include $(GRLIB)/boards/$(BOARD)/Makefile.inc
5+DEVICE=$(PART)-$(PACKAGE)$(SPEED)
6+UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
7+QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
8+EFFORT=std
9+XSTOPT=
10+SYNPOPT="set_option -pipe 1; set_option -retiming 1"
11+VHDLSYNFILES=config.vhd bus_amba.vhd sample_ambacore.vhd sim_amba2.vhd
12+VHDLSIMFILES=sim_amba1.vhd
13+SIMTOP=sim_amba
14+SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
15+BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
16+CLEAN=soft-clean
17+
18+TECHLIBS = altera altera_mf cycloneiii
19+LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
20+ tmtc openchip hynix cypress ihp gleichmann opencores micron\
21+ stratixii stratixiii usbhc spw \
22+ eth fmf spansion gsi
23+DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan pci leon3ft can \
24+ grusbhc spacewire hcan ddr net greth haps leon3 ata usb uart jtag arith
25+FILESKIP = grcan.vhd i2cmst.vhd
26+
27+include $(GRLIB)/software/leon3/Makefile
28+include $(GRLIB)/bin/Makefile
29+
30+
31+################## project specific targets ##########################
32+
--- /dev/null
+++ b/grlib-gpl-1.0.22-b4095/designs/work_amba/bus_amba.vhd
@@ -0,0 +1,120 @@
1+------------------------------------------------------------------------------
2+-- Copyright (C) 2010, Kenichi Kurimoto
3+--
4+-- This program is free software; you can redistribute it and/or modify
5+-- it under the terms of the GNU General Public License as published by
6+-- the Free Software Foundation; either version 2 of the License, or
7+-- (at your option) any later version.
8+--
9+-- This program is distributed in the hope that it will be useful,
10+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12+-- GNU General Public License for more details.
13+--
14+-- You should have received a copy of the GNU General Public License
15+-- along with this program; if not, write to the Free Software
16+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17+-----------------------------------------------------------------------------
18+
19+
20+
21+
22+
23+library ieee;
24+use ieee.std_logic_1164.all;
25+
26+library grlib,techmap;
27+use grlib.amba.all;
28+use grlib.stdlib.all;
29+use techmap.gencomp.all;
30+library gaisler;
31+use gaisler.misc.all;
32+--use gaisler.ambatest.all;
33+use gaisler.ahbtbp.all;
34+library kuri;
35+use kuri.mjpeg.all;
36+
37+use work.config.all;
38+
39+entity bus_amba is
40+ port (
41+ rstn : in std_ulogic;
42+ clk : in std_ulogic;
43+ ctrl_in1 : in ahbtbm_ctrl_in_type;
44+ ctrl_out1 : out ahbtbm_ctrl_out_type;
45+ ctrl_in2 : in ahbtbm_ctrl_in_type;
46+ ctrl_out2 : out ahbtbm_ctrl_out_type);
47+end;
48+
49+architecture rtl of bus_amba is
50+
51+ component sample_ambacore
52+ generic (
53+ memtech : integer := DEFMEMTECH;
54+ fifo_depth : integer := 32;
55+ burst_num : integer := 16;
56+ shindex : integer := 0;
57+ haddr : integer := 0;
58+ hmask : integer := 16#fff#;
59+ hirq : integer := 0;
60+ pindex : integer := 0;
61+ paddr : integer := 0;
62+ pmask : integer := 16#fff#;
63+ mhindex : integer := 0;
64+ chprot : integer := 3);
65+ port (
66+ rst : in std_ulogic;
67+ clk : in std_ulogic;
68+ ahbmi : in ahb_mst_in_type;
69+ ahbmo : out ahb_mst_out_type;
70+ ahbsi : in ahb_slv_in_type;
71+ ahbso : out ahb_slv_out_type;
72+ apbi : in apb_slv_in_type;
73+ apbo : out apb_slv_out_type
74+ );
75+ end component;
76+
77+
78+ signal apbi : apb_slv_in_type;
79+ signal apbo : apb_slv_out_vector := (others => apb_none);
80+ signal ahbsi : ahb_slv_in_type;
81+ signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
82+ signal ahbmi : ahb_mst_in_type;
83+ signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
84+
85+-- signal rst : std_ulogic;
86+
87+
88+
89+begin -- rtl
90+
91+
92+-- rst <= not rstn;
93+
94+ sampleinst : sample_ambacore
95+ generic map(shindex => 2, haddr => 16#900#, pindex => 2, paddr => 2, mhindex => 3, hirq => 2)
96+ port map (rstn, clk, ahbmi, ahbmo(3), ahbsi, ahbso(2), apbi, apbo(2));
97+
98+ apb0 : apbctrl
99+ generic map (hindex => 4, haddr => 16#800#)
100+ port map(rstn, clk, ahbsi, ahbso(4), apbi, apbo);
101+
102+ ahbcontroller : ahbctrl -- AHB arbiter/multiplexer
103+ generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
104+ enbusmon => 0,rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO)
105+ port map (rstn, clk, ahbmi, ahbmo, ahbsi, ahbso);
106+
107+ ram0 : ahbram
108+ generic map (hindex => 7, haddr => 16#a00#, tech => CFG_MEMTECH, kbytes => 24)
109+ port map (rstn, clk, ahbsi, ahbso(7));
110+
111+ mast_em : ahbtbm
112+ generic map(hindex => 0)
113+ port map (rstn, clk, ctrl_in1, ctrl_out1, ahbmi, ahbmo(0));
114+
115+ mast_em2 : ahbtbm
116+ generic map(hindex => 1)
117+ port map (rstn, clk, ctrl_in2, ctrl_out2, ahbmi, ahbmo(1));
118+
119+end rtl;
120+
--- /dev/null
+++ b/grlib-gpl-1.0.22-b4095/designs/work_amba/bus_huffdctycc.vhd
@@ -0,0 +1,94 @@
1+------------------------------------------------------------------------------
2+-- Copyright (C) 2010, Kenichi Kurimoto
3+--
4+-- This program is free software; you can redistribute it and/or modify
5+-- it under the terms of the GNU General Public License as published by
6+-- the Free Software Foundation; either version 2 of the License, or
7+-- (at your option) any later version.
8+--
9+-- This program is distributed in the hope that it will be useful,
10+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12+-- GNU General Public License for more details.
13+--
14+-- You should have received a copy of the GNU General Public License
15+-- along with this program; if not, write to the Free Software
16+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17+-----------------------------------------------------------------------------
18+
19+
20+
21+
22+
23+library ieee;
24+use ieee.std_logic_1164.all;
25+
26+library grlib,techmap;
27+use grlib.amba.all;
28+use grlib.stdlib.all;
29+use techmap.gencomp.all;
30+library gaisler;
31+use gaisler.misc.all;
32+--use gaisler.ambatest.all;
33+use gaisler.ahbtbp.all;
34+library kuri;
35+use kuri.mjpeg.all;
36+
37+use work.config.all;
38+
39+entity bus_huffdctycc is
40+ port (
41+ rstn : in std_ulogic;
42+ clk : in std_ulogic;
43+ ctrl_in1 : in ahbtbm_ctrl_in_type;
44+ ctrl_out1 : out ahbtbm_ctrl_out_type);
45+end;
46+
47+architecture rtl of bus_huffdctycc is
48+
49+
50+ signal apbi : apb_slv_in_type;
51+ signal apbo : apb_slv_out_vector := (others => apb_none);
52+ signal ahbsi : ahb_slv_in_type;
53+ signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
54+ signal ahbmi : ahb_mst_in_type;
55+ signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
56+
57+-- signal rst : std_ulogic;
58+
59+
60+
61+begin -- rtl
62+
63+
64+-- rst <= not rstn;
65+
66+ jpginst : huffdctycc
67+ generic map(shindex => 2, haddr => 16#900#, pindex => 2, paddr => 2, mhindex => 3, hirq => 2)
68+ port map (rstn, clk, ahbmi, ahbmo(3), ahbsi, ahbso(2), apbi, apbo(2));
69+
70+ apb0 : apbctrl
71+ generic map (hindex => 4, haddr => 16#800#)
72+ port map(rstn, clk, ahbsi, ahbso(4), apbi, apbo);
73+
74+ ahbcontroller : ahbctrl -- AHB arbiter/multiplexer
75+ generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
76+ enbusmon => 0,rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO)
77+ port map (rstn, clk, ahbmi, ahbmo, ahbsi, ahbso);
78+
79+ ram0 : ahbram
80+ generic map (hindex => 7, haddr => 16#a00#, tech => CFG_MEMTECH, kbytes => 24)
81+ port map (rstn, clk, ahbsi, ahbso(7));
82+
83+ mast_em : ahbtbm
84+ generic map(hindex => 0)
85+ port map (rstn, clk, ctrl_in1, ctrl_out1, ahbmi, ahbmo(0));
86+
87+
88+
89+-- mast_em2 : ahbtbm
90+-- generic map(hindex => 1)
91+-- port map (rstn, clk, ctrl_in2, ctrl_out2, ahbmi, ahbmo(1));
92+
93+end rtl;
94+
--- /dev/null
+++ b/grlib-gpl-1.0.22-b4095/designs/work_amba/config.help
@@ -0,0 +1,1016 @@
1+
2+
3+Prompt for target technology
4+CONFIG_SYN_INFERRED
5+ Selects the target technology for memory and pads.
6+ The following are available:
7+
8+ - Inferred: Generic FPGA or ASIC targets if your synthesis tool
9+ is capable of inferring RAMs and pads automatically.
10+
11+ - Actel ProAsic/P/3, IGLOO and Axcelerator FPGAs
12+ - Aeroflex UT25CRH Rad-Hard 0.25 um CMOS
13+ - Altera: Most Altera FPGA families
14+ - Altera-Stratix: Altera Stratix FPGA family
15+ - Altera-StratixII: Altera Stratix-II FPGA family
16+ - ATC18: Atmel-Nantes 0.18 um rad-hard CMOS
17+ - IHP25: IHP 0.25 um CMOS
18+ - IHP25RH: IHP Rad-Hard 0.25 um CMOS
19+ - Lattice : EC/ECP/XP FPGAs
20+ - Quicklogic : Eclipse/E/II FPGAs
21+ - UMC-0.18 : UMC 0.18 um CMOS with Virtual Silicon libraries
22+ - Xilinx-Spartan/2/3: Xilinx Spartan/2/3 libraries
23+ - Xilinx-Spartan3E: Xilinx Spartan3E libraries
24+ - Xilinx-Virtex/E: Xilinx Virtex/E libraries
25+ - Xilinx-Virtex2/4/5: Xilinx Virtex2/4/5 libraries
26+
27+
28+Ram library
29+CONFIG_MEM_VIRAGE
30+ Select RAM generators for ASIC targets.
31+
32+Infer ram
33+CONFIG_SYN_INFER_RAM
34+ Say Y here if you want the synthesis tool to infer your
35+ RAM automatically. Say N to directly instantiate technology-
36+ specific RAM cells for the selected target technology package.
37+
38+Infer pads
39+CONFIG_SYN_INFER_PADS
40+ Say Y here if you want the synthesis tool to infer pads.
41+ Say N to directly instantiate technology-specific pads from
42+ the selected target technology package.
43+
44+No async reset
45+CONFIG_SYN_NO_ASYNC
46+ Say Y here if you disable asynchronous reset in some of the IP cores.
47+ Might be necessary if the target library does not have cells with
48+ asynchronous set/reset.
49+
50+Scan support
51+CONFIG_SYN_SCAN
52+ Say Y here to enable scan support in some cores. This will enable
53+ the scan support generics where available and add logic to make
54+ the design testable using full-scan.
55+
56+Use Virtex CLKDLL for clock synchronisation
57+CONFIG_CLK_INFERRED
58+ Certain target technologies include clock generators to scale or
59+ phase-adjust the system and SDRAM clocks. This is currently supported
60+ for Xilinx, Altera and Proasic3 FPGAs. Depending on technology, you
61+ can select to use the Xilinx CKLDLL macro (Virtex, VirtexE, Spartan1/2),
62+ the Xilinx DCM (Virtex-2, Spartan3, Virtex-4), the Altera ALTDLL
63+ (Stratix, Cyclone), or the Proasic3 PLL. Choose the 'inferred'
64+ option to skip a clock generator.
65+
66+Clock multiplier
67+CONFIG_CLK_MUL
68+ When using the Xilinx DCM or Altera ALTPLL, the system clock can
69+ be multiplied with a factor of 2 - 32, and divided by a factor of
70+ 1 - 32. This makes it possible to generate almost any desired
71+ processor frequency. When using the Xilinx CLKDLL generator,
72+ the resulting frequency scale factor (mul/div) must be one of
73+ 1/2, 1 or 2. On Proasic3, the factor can be 1 - 128.
74+
75+ WARNING: The resulting clock must be within the limits specified
76+ by the target FPGA family.
77+
78+Clock divider
79+CONFIG_CLK_DIV
80+ When using the Xilinx DCM or Altera ALTPLL, the system clock can
81+ be multiplied with a factor of 2 - 32, and divided by a factor of
82+ 1 - 32. This makes it possible to generate almost any desired
83+ processor frequency. When using the Xilinx CLKDLL generator,
84+ the resulting frequency scale factor (mul/div) must be one of
85+ 1/2, 1 or 2. On Proasic3, the factor can be 1 - 128.
86+
87+ WARNING: The resulting clock must be within the limits specified
88+ by the target FPGA family.
89+
90+Output clock divider
91+CONFIG_OCLK_DIV
92+ When using the Proasic3 PLL, the system clock is generated by three
93+ parameters: input clock multiplication, input clock division and
94+ output clock division. Only certain values of these parameters
95+ are allowed, but unfortunately this is not documented by Actel.
96+ To find the correct values, run the Libero Smartgen tool and
97+ insert you desired input and output clock frequencies in the
98+ Static PLL configurator. The mul/div factors can then be read
99+ out from tool.
100+
101+System clock multiplier
102+CONFIG_CLKDLL_1_2
103+ The Xilinx CLKDLL can scale the input clock with a factor of 0.5, 1.0,
104+ or 2.0. Useful when the target board has an oscillator with a too high
105+ (or low) frequency for your design. The divided clock will be used as the
106+ main clock for the whole processor (except PCI and ethernet clocks).
107+
108+System clock multiplier
109+CONFIG_DCM_2_3
110+ The Xilinx DCM and Altera ALTDLL can scale the input clock with a large
111+ range of factors. Useful when the target board has an oscillator with a
112+ too high (or low) frequency for your design. The divided clock will
113+ be used as the main clock for the whole processor (except PCI and
114+ ethernet clocks). NOTE: the resulting frequency must be at least
115+ 24 MHz or the DCM and ALTDLL might not work.
116+
117+Enable CLKDLL for PCI clock
118+CONFIG_PCI_CLKDLL
119+ Say Y here to re-synchronize the PCI clock using a
120+ Virtex BUFGDLL macro. Will improve PCI clock-to-output
121+ delays on the expense of input-setup requirements.
122+
123+Use PCI clock system clock
124+CONFIG_PCI_SYSCLK
125+ Say Y here to the PCI clock to generate the system clock.
126+ The PCI clock can be scaled using the DCM or CLKDLL to
127+ generate a suitable processor clock.
128+
129+External SDRAM clock feedback
130+CONFIG_CLK_NOFB
131+ Say Y here to disable the external clock feedback to synchronize the
132+ SDRAM clock. This option is necessary if your board or design does not
133+ have an external clock feedback that is connected to the pllref input
134+ of the clock generator.
135+
136+Number of processors
137+CONFIG_PROC_NUM
138+ The number of processor cores. The LEON3MP design can accomodate
139+ up to 4 LEON3 processor cores. Use 1 unless you know what you are
140+ doing ...
141+
142+Number of SPARC register windows
143+CONFIG_IU_NWINDOWS
144+ The SPARC architecture (and LEON) allows 2 - 32 register windows.
145+ However, any number except 8 will require that you modify and
146+ recompile your run-time system or kernel. Unless you know what
147+ you are doing, use 8.
148+
149+SPARC V8 multiply and divide instruction
150+CONFIG_IU_V8MULDIV
151+ If you say Y here, the SPARC V8 multiply and divide instructions
152+ will be implemented. The instructions are: UMUL, UMULCC, SMUL,
153+ SMULCC, UDIV, UDIVCC, SDIV, SDIVCC. In code containing frequent
154+ integer multiplications and divisions, significant performance
155+ increase can be achieved. Emulated floating-point operations will
156+ also benefit from this option.
157+
158+ By default, the gcc compiler does not emit multiply or divide
159+ instructions and your code must be compiled with -mv8 to see any
160+ performance increase. On the other hand, code compiled with -mv8
161+ will generate an illegal instruction trap when executed on processors
162+ with this option disabled.
163+
164+ The divider consumes approximately 2 kgates, the multiplier 6 kgates.
165+
166+Multiplier latency
167+CONFIG_IU_MUL_LATENCY_2
168+ Implementation options for the integer multiplier.
169+
170+ Type Implementation issue-rate/latency
171+ 2-clocks 32x32 pipelined multiplier 1/2
172+ 4-clocks 16x16 standard multiplier 4/4
173+ 5-clocks 16x16 pipelined multiplier 4/5
174+
175+Multiplier latency
176+CONFIG_IU_MUL_MAC
177+ If you say Y here, the SPARC V8e UMAC/SMAC (multiply-accumulate)
178+ instructions will be enabled. The instructions implement a
179+ single-cycle 16x16->32 bits multiply with a 40-bits accumulator.
180+ The details of these instructions can be found in the LEON manual,
181+ This option is only available when 16x16 multiplier is used.
182+
183+Single vector trapping
184+CONFIG_IU_SVT
185+ Single-vector trapping is a SPARC V8e option to reduce code-size
186+ in small applications. If enabled, the processor will jump to
187+ the address of trap 0 (tt = 0x00) for all traps. No trap table
188+ is then needed. The trap type is present in %psr.tt and must
189+ be decoded by the O/S. Saves 4 Kbyte of code, but increases
190+ trap and interrupt overhead. Currently, the only O/S supporting
191+ this option is eCos. To enable SVT, the O/S must also set bit 13
192+ in %asr17.
193+
194+Load latency
195+CONFIG_IU_LDELAY
196+ Defines the pipeline load delay (= pipeline cycles before the data
197+ from a load instruction is available for the next instruction).
198+ One cycle gives best performance, but might create a critical path
199+ on targets with slow (data) cache memories. A 2-cycle delay can
200+ improve timing but will reduce performance with about 5%.
201+
202+Reset address
203+CONFIG_IU_RSTADDR
204+ By default, a SPARC processor starts execution at address 0.
205+ With this option, any 4-kbyte aligned reset start address can be
206+ choosen. Keep at 0 unless you really know what you are doing.
207+
208+Power-down
209+CONFIG_PWD
210+ Say Y here to enable the power-down feature of the processor.
211+ Might reduce the maximum frequency slightly on FPGA targets.
212+ For details on the power-down operation, see the LEON3 manual.
213+
214+Hardware watchpoints
215+CONFIG_IU_WATCHPOINTS
216+ The processor can have up to 4 hardware watchpoints, allowing to
217+ create both data and instruction breakpoints at any memory location,
218+ also in PROM. Each watchpoint will use approximately 500 gates.
219+ Use 0 to disable the watchpoint function.
220+
221+Floating-point enable
222+CONFIG_FPU_ENABLE
223+ Say Y here to enable the floating-point interface for the MEIKO
224+ or GRFPU. Note that no FPU's are provided with the GPL version
225+ of GRLIB. Both the Gaisler GRFPU and the Meiko FPU are commercial
226+ cores and must be obtained separately.
227+
228+FPU selection
229+CONFIG_FPU_GRFPU
230+ Select between Gaisler Research's GRFPU and GRFPU-lite FPUs or the Sun
231+ Meiko FPU core. All cores are fully IEEE-754 compatible and support
232+ all SPARC FPU instructions.
233+
234+GRFPU Multiplier
235+CONFIG_FPU_GRFPU_INFMUL
236+ On FPGA targets choose inferred multiplier. For ASIC implementations
237+ choose between Synopsys Design Ware (DW) multiplier or Module
238+ Generator (ModGen) multiplier. The DW multiplier gives better results
239+ (smaller area and better timing) but requires a DW license.
240+ The ModGen multiplier is part of GRLIB and does not require a license.
241+ The Technology Specific multiplier option selects a pre-designed
242+ multiplier using technology specific macrocells when available, else
243+ an inferred multiplier is used.
244+
245+Shared GRFPU
246+CONFIG_FPU_GRFPU_SH
247+ If enabled multiple CPU cores will share one GRFPU.
248+
249+GRFPC Configuration
250+CONFIG_FPU_GRFPC0
251+ Configures the GRFPU-LITE controller.
252+
253+ In simple configuration controller executes FP instructions
254+ in parallel with integer instructions. FP operands are fetched
255+ in the register file stage and the result is written in the write
256+ stage. This option uses least area resources.
257+
258+ Data forwarding configuration gives ~ 10 % higher FP performance than
259+ the simple configuration by adding data forwarding between the pipeline
260+ stages.
261+
262+ Non-blocking controller allows FP load and store instructions to
263+ execute in parallel with FP instructions. The performance increase is
264+ ~ 20 % for FP applications. This option uses most logic resources and
265+ is suitable for ASIC implementations.
266+
267+Floating-point netlist
268+CONFIG_FPU_NETLIST
269+ Say Y here to use a VHDL netlist of the GRFPU-Lite. This is
270+ only available in certain versions of grlib.
271+
272+Enable Instruction cache
273+CONFIG_ICACHE_ENABLE
274+ The instruction cache should always be enabled to allow
275+ maximum performance. Some low-end system might want to
276+ save area and disable the cache, but this will reduce
277+ the performance with a factor of 2 - 3.
278+
279+Enable Data cache
280+CONFIG_DCACHE_ENABLE
281+ The data cache should always be enabled to allow
282+ maximum performance. Some low-end system might want to
283+ save area and disable the cache, but this will reduce
284+ the performance with a factor of 2 at least.
285+
286+Instruction cache associativity
287+CONFIG_ICACHE_ASSO1
288+ The instruction cache can be implemented as a multi-set cache with
289+ 1 - 4 sets. Higher associativity usually increases the cache hit
290+ rate and thereby the performance. The downside is higher power
291+ consumption and increased gate-count for tag comparators.
292+
293+ Note that a 1-set cache is effectively a direct-mapped cache.
294+
295+Instruction cache set size
296+CONFIG_ICACHE_SZ1
297+ The size of each set in the instuction cache (kbytes). Valid values
298+ are 1 - 64 in binary steps. Note that the full range is only supported
299+ by the generic and virtex2 targets. Most target packages are limited
300+ to 2 - 16 kbyte. Large set size gives higher performance but might
301+ affect the maximum frequency (on ASIC targets). The total instruction
302+ cache size is the number of set multiplied with the set size.
303+
304+Instruction cache line size
305+CONFIG_ICACHE_LZ16
306+ The instruction cache line size. Can be set to either 16 or 32
307+ bytes per line. Instruction caches typically benefit from larger
308+ line sizes, but on small caches it migh be better with 16 bytes/line
309+ to limit eviction miss rate.
310+
311+Instruction cache replacement algorithm
312+CONFIG_ICACHE_ALGORND
313+ Cache replacement algorithm for caches with 2 - 4 sets. The 'random'
314+ algorithm selects the set to evict randomly. The least-recently-replaced
315+ (LRR) algorithm evicts the set least recently replaced. The least-
316+ recently-used (LRU) algorithm evicts the set least recently accessed.
317+ The random algorithm uses a simple 1- or 2-bit counter to select
318+ the eviction set and has low area overhead. The LRR scheme uses one
319+ extra bit in the tag ram and has therefore also low area overhead.
320+ However, the LRR scheme can only be used with 2-set caches. The LRU
321+ scheme has typically the best performance but also highest area overhead.
322+ A 2-set LRU uses 1 flip-flop per line, a 3-set LRU uses 3 flip-flops
323+ per line, and a 4-set LRU uses 5 flip-flops per line to store the access
324+ history.
325+
326+Instruction cache locking
327+CONFIG_ICACHE_LOCK
328+ Say Y here to enable cache locking in the instruction cache.
329+ Locking can be done on cache-line level, but will increase the
330+ width of the tag ram with one bit. If you don't know what
331+ locking is good for, it is safe to say N.
332+
333+Data cache associativity
334+CONFIG_DCACHE_ASSO1
335+ The data cache can be implemented as a multi-set cache with
336+ 1 - 4 sets. Higher associativity usually increases the cache hit
337+ rate and thereby the performance. The downside is higher power
338+ consumption and increased gate-count for tag comparators.
339+
340+ Note that a 1-set cache is effectively a direct-mapped cache.
341+
342+Data cache set size
343+CONFIG_DCACHE_SZ1
344+ The size of each set in the data cache (kbytes). Valid values are
345+ 1 - 64 in binary steps. Note that the full range is only supported
346+ by the generic and virtex2 targets. Most target packages are limited
347+ to 2 - 16 kbyte. A large cache gives higher performance but the
348+ data cache is timing critical an a too large setting might affect
349+ the maximum frequency (on ASIC targets). The total data cache size
350+ is the number of set multiplied with the set size.
351+
352+Data cache line size
353+CONFIG_DCACHE_LZ16
354+ The data cache line size. Can be set to either 16 or 32 bytes per
355+ line. A smaller line size gives better associativity and higher
356+ cache hit rate, but requires a larger tag memory.
357+
358+Data cache replacement algorithm
359+CONFIG_DCACHE_ALGORND
360+ See the explanation for instruction cache replacement algorithm.
361+
362+Data cache locking
363+CONFIG_DCACHE_LOCK
364+ Say Y here to enable cache locking in the data cache.
365+ Locking can be done on cache-line level, but will increase the
366+ width of the tag ram with one bit. If you don't know what
367+ locking is good for, it is safe to say N.
368+
369+Data cache snooping
370+CONFIG_DCACHE_SNOOP
371+ Say Y here to enable data cache snooping on the AHB bus. Is only
372+ useful if you have additional AHB masters such as the DSU or a
373+ target PCI interface. Note that the target technology must support
374+ dual-port RAMs for this option to be enabled. Dual-port RAMS are
375+ currently supported on Virtex/2, Virage and Actel targets.
376+
377+Data cache snooping implementation
378+CONFIG_DCACHE_SNOOP_FAST
379+ The default snooping implementation is 'slow', which works if you
380+ don't have AHB slaves in cacheable areas capable of zero-waitstates
381+ non-sequential write accesses. Otherwise use 'fast' and suffer a
382+ few kgates extra area. This option is currently only needed in
383+ multi-master systems with the SSRAM or DDR memory controllers.
384+
385+Separate snoop tags
386+CONFIG_DCACHE_SNOOP_SEPTAG
387+ Enable a separate memory to store the data tags used for snooping.
388+ This is necessary when snooping support is wanted in systems
389+ with MMU, typically for SMP systems. In this case, the snoop
390+ tags will contain the physical tag address while the normal
391+ tags contain the virtual tag address. This option can also be
392+ together with the 'fast snooping' option to enable snooping
393+ support on technologies without dual-port RAMs. In such case,
394+ the snoop tag RAM will be implemented using a two-port RAM.
395+
396+Fixed cacheability map
397+CONFIG_CACHE_FIXED
398+ If this variable is 0, the cacheable memory regions are defined
399+ by the AHB plug&play information (default). To overriden the
400+ plug&play settings, this variable can be set to indicate which
401+ areas should be cached. The value is treated as a 16-bit hex value
402+ with each bit defining if a 256 Mbyte segment should be cached or not.
403+ The right-most (LSB) bit defines the cacheability of AHB address
404+ 0 - 256 MByte, while the left-most bit (MSB) defines AHB address
405+ 3840 - 4096 MByte. If the bit is set, the corresponding area is
406+ cacheable. A value of 00F3 defines address 0 - 0x20000000 and
407+ 0x40000000 - 0x80000000 as cacheable.
408+
409+Local data ram
410+CONFIG_DCACHE_LRAM
411+ Say Y here to add a local ram to the data cache controller.
412+ Accesses to the ram (load/store) will be performed at 0 waitstates
413+ and store data will never be written back to the AHB bus.
414+
415+Size of local data ram
416+CONFIG_DCACHE_LRAM_SZ1
417+ Defines the size of the local data ram in Kbytes. Note that most
418+ technology libraries do not support larger rams than 16 Kbyte.
419+
420+Start address of local data ram
421+CONFIG_DCACHE_LRSTART
422+ Defines the 8 MSB bits of start address of the local data ram.
423+ By default set to 8f (start address = 0x8f000000), but any value
424+ (except 0) is possible. Note that the local data ram 'shadows'
425+ a 16 Mbyte block of the address space.
426+
427+MMU enable
428+CONFIG_MMU_ENABLE
429+ Say Y here to enable the Memory Management Unit.
430+
431+MMU split icache/dcache table lookaside buffer
432+CONFIG_MMU_COMBINED
433+ Select "combined" for a combined icache/dcache table lookaside buffer,
434+ "split" for a split icache/dcache table lookaside buffer
435+
436+MMU tlb replacement scheme
437+CONFIG_MMU_REPARRAY
438+ Select "LRU" to use the "least recently used" algorithm for TLB
439+ replacement, or "Increment" for a simple incremental replacement
440+ scheme.
441+
442+Combined i/dcache tlb
443+CONFIG_MMU_I2
444+ Select the number of entries for the instruction TLB, or the
445+ combined icache/dcache TLB if such is used.
446+
447+Split tlb, dcache
448+CONFIG_MMU_D2
449+ Select the number of entries for the dcache TLB.
450+
451+Fast writebuffer
452+CONFIG_MMU_FASTWB
453+ Only selectable if split tlb is enabled. In case fast writebuffer is
454+ enabled the tlb hit will be made concurrent to the cache hit. This
455+ leads to higher store performance, but increased power and area.
456+
457+MMU pagesize
458+CONFIG_MMU_PAGE_4K
459+ The deafult SPARC V8 SRMMU page size is 4 Kbyte. This limits the
460+ cache way size to 4 Kbyte, and total data cache size to 16 Kbyte,
461+ when the MMU is used. To increase the maximum data cache size,
462+ the MMU pages size can be increased to up 32 Kbyte. This will
463+ give a maximum data cache size of 128 Kbyte.
464+
465+ Note that an MMU page size different than 4 Kbyte will require
466+ a special linux tool-chain if glibc is used. If you don't know
467+ what you are doing, stay with 4 Kbyte ...
468+
469+DSU enable
470+CONFIG_DSU_ENABLE
471+ The debug support unit (DSU) allows non-intrusive debugging and tracing
472+ of both executed instructions and AHB transfers. If you want to enable
473+ the DSU, say Y here and select the configuration below.
474+
475+Trace buffer enable
476+CONFIG_DSU_TRACEBUF
477+ Say Y to enable the trace buffer. The buffer is not necessary for
478+ debugging, only for tracing instructions and data transfers.
479+
480+Enable instruction tracing
481+CONFIG_DSU_ITRACE
482+ If you say Y here, an instruction trace buffer will be implemented
483+ in each processor. The trace buffer will trace executed instructions
484+ and their results, and place them in a circular buffer. The buffer
485+ can be read out by any AHB master, and in particular by the debug
486+ communication link.
487+
488+Size of trace buffer
489+CONFIG_DSU_ITRACESZ1
490+ Select the buffer size (in kbytes) for the instruction trace buffer.
491+ Each line in the buffer needs 16 bytes. A 128-entry buffer will thus
492+ need 2 kbyte.
493+
494+Enable AHB tracing
495+CONFIG_DSU_ATRACE
496+ If you say Y here, an AHB trace buffer will be implemented in the
497+ debug support unit processor. The AHB buffer will trace all transfers
498+ on the AHB bus and save them in a circular buffer. The trace buffer
499+ can be read out by any AHB master, and in particular by the debug
500+ communication link.
501+
502+Size of trace buffer
503+CONFIG_DSU_ATRACESZ1
504+ Select the buffer size (in kbytes) for the AHB trace buffer.
505+ Each line in the buffer needs 16 bytes. A 128-entry buffer will thus
506+ need 2 kbyte.
507+
508+
509+LEON3FT enable
510+CONFIG_LEON3FT_EN
511+ Say Y here to use the fault-tolerant LEON3FT core instead of the
512+ standard non-FT LEON3.
513+
514+IU Register file protection
515+CONFIG_IUFT_NONE
516+ Select the FT implementation in the LEON3FT integer unit
517+ register file. The options include parity, parity with
518+ sparing, 7-bit BCH and TMR.
519+
520+FPU Register file protection
521+CONFIG_FPUFT_EN
522+ Say Y to enable SEU protection of the FPU register file.
523+ The GRFPU will be protected using 8-bit parity without restart, while
524+ the GRFPU-Lite will be protected with 4-bit parity with restart. If
525+ disabled the FPU register file will be implemented using flip-flops.
526+
527+Cache memory error injection
528+CONFIG_RF_ERRINJ
529+ Say Y here to enable error injection in to the IU/FPU regfiles.
530+ Affects only simulation.
531+
532+Cache memory protection
533+CONFIG_CACHE_FT_EN
534+ Enable SEU error-correction in the cache memories.
535+
536+Cache memory error injection
537+CONFIG_CACHE_ERRINJ
538+ Say Y here to enable error injection in to the cache memories.
539+ Affects only simulation.
540+
541+Leon3ft netlist
542+CONFIG_LEON3_NETLIST
543+ Say Y here to use a VHDL netlist of the LEON3FT. This is
544+ only available in certain versions of grlib.
545+
546+IU assembly printing
547+CONFIG_IU_DISAS
548+ Enable printing of executed instructions to the console.
549+
550+IU assembly printing in netlist
551+CONFIG_IU_DISAS_NET
552+ Enable printing of executed instructions to the console also
553+ when simulating a netlist. NOTE: with this option enabled, it
554+ will not be possible to pass place&route.
555+
556+32-bit program counters
557+CONFIG_DEBUG_PC32
558+ Since the LSB 2 bits of the program counters always are zero, they are
559+ normally not implemented. If you say Y here, the program counters will
560+ be implemented with full 32 bits, making debugging of the VHDL model
561+ much easier. Turn of this option for synthesis or you will be wasting
562+ area.
563+CONFIG_AHB_DEFMST
564+ Sets the default AHB master (see AMBA 2.0 specification for definition).
565+ Should not be set to a value larger than the number of AHB masters - 1.
566+ For highest processor performance, leave it at 0.
567+
568+Default AHB master
569+CONFIG_AHB_RROBIN
570+ Say Y here to enable round-robin arbitration of the AHB bus. A N will
571+ select fixed priority, with the master with the highest bus index having
572+ the highest priority.
573+
574+Support AHB split-transactions
575+CONFIG_AHB_SPLIT
576+ Say Y here to enable AHB split-transaction support in the AHB arbiter.
577+ Unless you actually have an AHB slave that can generate AHB split
578+ responses, say N and save some gates.
579+
580+Default AHB master
581+CONFIG_AHB_IOADDR
582+ Selects the MSB adddress (HADDR[31:20]) of the AHB IO area, as defined
583+ in the plug&play extentions of the AMBA bus. Should be kept to FFF
584+ unless you really know what you are doing.
585+
586+APB bridge address
587+CONFIG_APB_HADDR
588+ Selects the MSB adddress (HADDR[31:20]) of the APB bridge. Should be
589+ kept at 800 for software compatibility.
590+
591+AHB monitor
592+CONFIG_AHB_MON
593+ Say Y to enable the AHB bus monitor. The monitor will check for
594+ illegal AHB transactions during simulation. It has no impact on
595+ synthesis.
596+
597+Report AHB errors
598+CONFIG_AHB_MONERR
599+ Print out detected AHB violations on console.
600+
601+Report AHB warnings
602+CONFIG_AHB_MONWAR
603+ Print out detected AHB warnings on console.
604+
605+
606+DSU enable
607+CONFIG_DSU_UART
608+ Say Y to enable the AHB uart (serial-to-AHB). This is the most
609+ commonly used debug communication link.
610+
611+JTAG Enable
612+CONFIG_DSU_JTAG
613+ Say Y to enable the JTAG debug link (JTAG-to-AHB). Debugging is done
614+ with GRMON through the boards JTAG chain at speeds of up to 800 kbits/s.
615+ Supported JTAG cables are Xilinx Parallel Cable III and IV,
616+ Xilinx Platform cables (USB), and Altera parallel and USB cables.
617+
618+Ethernet DSU enable
619+CONFIG_DSU_ETH
620+ Say Y to enable the Ethernet Debug Communication Link (EDCL). The link
621+ provides a DSU gateway between ethernet and the AHB bus. Debugging is
622+ done at 10 or 100 Mbit/s, using the GRMON debug monitor. You must
623+ enable the GRETH Ethernet MAC for this option to become active.
624+
625+Size of EDCL trace buffer
626+CONFIG_DSU_ETHSZ1
627+ Select the buffer size (in kbytes) for the EDCL. 1 or 2 kbyte is
628+ usually enough, while a larger buffer will increase the transfer rate.
629+ When operating at 100 Mbit, use a buffer size of at least 8 kbyte for
630+ maximum throughput.
631+
632+MSB IP address
633+CONFIG_DSU_IPMSB
634+ Set the MSB 16 bits of the IP address of the EDCL.
635+
636+LSB IP address
637+CONFIG_DSU_IPLSB
638+ Set the LSB 16 bits of the IP address of the EDCL.
639+
640+MSB ethernet address
641+CONFIG_DSU_ETHMSB
642+ Set the MSB 24 bits of the ethernet address of the EDCL.
643+
644+LSB ethernet address
645+CONFIG_DSU_ETHLSB
646+ Set the LSB 24 bits of the ethernet address of the EDCL.
647+
648+Programmable MAC/IP address
649+CONFIG_DSU_ETH_PROG
650+ Say Y to make the LSB 4 bits of the EDCL MAC and IP address
651+ configurable using the ethi.edcladdr inputs.
652+Leon2 memory controller
653+CONFIG_MCTRL_LEON2
654+ Say Y here to enable the LEON2 memory controller. The controller
655+ can access PROM, I/O, SRAM and SDRAM. The bus width for PROM
656+ and SRAM is programmable to 8-, 16- or 32-bits.
657+
658+8-bit memory support
659+CONFIG_MCTRL_8BIT
660+ If you say Y here, the PROM/SRAM memory controller will support
661+ 8-bit mode, i.e. operate from 8-bit devices as if they were 32-bit.
662+ Say N to save a few hundred gates.
663+
664+16-bit memory support
665+CONFIG_MCTRL_16BIT
666+ If you say Y here, the PROM/SRAM memory controller will support
667+ 16-bit mode, i.e. operate from 16-bit devices as if they were 32-bit.
668+ Say N to save a few hundred gates.
669+
670+Write strobe feedback
671+CONFIG_MCTRL_WFB
672+ If you say Y here, the PROM/SRAM write strobes (WRITEN, WEN) will
673+ be used to enable the data bus drivers during write cycles. This
674+ will guarantee that the data is still valid on the rising edge of
675+ the write strobe. If you say N, the write strobes and the data bus
676+ drivers will be clocked on the rising edge, potentially creating
677+ a hold time problem in external memory or I/O. However, in all
678+ practical cases, there is enough capacitance in the data bus lines
679+ to keep the value stable for a few (many?) nano-seconds after the
680+ buffers have been disabled, making it safe to say N and remove a
681+ combinational path in the netlist that might be difficult to
682+ analyze.
683+
684+Write strobe feedback
685+CONFIG_MCTRL_5CS
686+ If you say Y here, the 5th (RAMSN[4]) SRAM chip select signal will
687+ be enabled. If you don't intend to use it, say N and save some gates.
688+
689+SDRAM controller enable
690+CONFIG_MCTRL_SDRAM
691+ Say Y here to enabled the PC100/PC133 SDRAM controller. If you don't
692+ intend to use SDRAM, say N and save about 1 kgates.
693+
694+SDRAM controller inverted clock
695+CONFIG_MCTRL_SDRAM_INVCLK
696+ If you say Y here, the SDRAM controller output signals will be delayed
697+ with 1/2 clock in respect to the SDRAM clock. This will allow the used
698+ of an SDRAM clock which in not strictly in phase with the internal
699+ clock. This option will limit the SDRAM frequency to 40 - 50 MHz.
700+
701+ On FPGA targets without SDRAM clock synchronizations through PLL/DLL,
702+ say Y. On ASIC targets, say N and tell your foundry to balance the
703+ SDRAM clock output.
704+
705+SDRAM separate address buses
706+CONFIG_MCTRL_SDRAM_SEPBUS
707+ Say Y here if your SDRAM is connected through separate address
708+ and data buses (SA & SD). This is the case on the GR-CPCI-XC2V6000
709+ board, but not on the GR-PCI-XC2V3000 or Avnet XCV1500E boards.
710+
711+64-bit data bus
712+CONFIG_MCTRL_SDRAM_BUS64
713+ Say Y here to enable 64-bit SDRAM data bus.
714+
715+Page burst enable
716+CONFIG_MCTRL_PAGE
717+ Say Y here to enable SDRAM page burst operation. This will implement
718+ read operations using page bursts rather than 8-word bursts and save
719+ about 500 gates (100 LUTs). Note that not all SDRAM supports page
720+ burst, so use this option with care.
721+
722+Programmable page burst enable
723+CONFIG_MCTRL_PROGPAGE
724+ Say Y here to enable programmable SDRAM page burst operation. This
725+ will allow to dynamically enable/disable page burst by setting
726+ bit 17 in MCFG2.
727+
728+SDRAM controller enable
729+CONFIG_SSCTRL
730+ Say Y here to enabled a 32-bit synchronous SRAM (SSRAM) controller.
731+ The controller is designed for piplined ZBT SSRAM.
732+
733+CONFIG_SSCTRL_PROM16
734+ Say Y here to enabled a 16-bit PROM support. The PROM should be
735+ connected to D[31:16] of the data bus.
736+
737+SDRAM controller enable
738+CONFIG_DDRSP
739+ Say Y here to enabled a 16-bit DDR266 SDRAM controller.
740+
741+Power-on init
742+CONFIG_DDRSP_INIT
743+ Say Y here to enable the automatic DDR initialization sequence.
744+ If disabled, the sequencemust be performed in software before
745+ the DDR can be used. If unsure, say Y.
746+
747+Memory frequency
748+CONFIG_DDRSP_FREQ
749+ Enter the frequency of the DDR clock (in MHz). The value is
750+ typically between 80 - 133, depending on system configuration.
751+ Some template design (such as the leon3-avnet-eval-lx25)
752+ calculate this value automatically and this value is not used.
753+
754+Column bits
755+CONFIG_DDRSP_COL
756+ Select the number of colomn address bits of the DDR memory.
757+ Typical values are 8 - 11. Only needed when automatic DDR
758+ initialisation is choosen. The column size can always be
759+ programmed by software as well.
760+
761+Chip select size
762+CONFIG_DDRSP_MBYTE
763+ Select the memory size (Mbytes) that each chip select should decode.
764+ Only needed when automatic DDR initialisation is choosen. The chip
765+ select size can always be programmed by software as well.
766+
767+Read clock phase shift
768+CONFIG_DDRSP_RSKEW
769+ On Xilinx targets, the read clock is de-skewed and phase-shifted
770+ using a DCM connected to the feed-back clock input. On some boards,
771+ the de-skewing does not work perfectly, and some extra phase shifting
772+ must be added manually. The entered value is set to the PHASE_SHIFT
773+ generic on the Xilinx DCM. The Digilent Sparten3E-1600 board typically
774+ needs a value of 35, while the Avnet Virtex4 Eval board needs -90.
775+ For Altera CycloneIII, the entered value is set to the PHASE_SHIFT of
776+ the PLL in ps (e.g 2500 for 90' shift in 100MHz)
777+SPI memory controller
778+CONFIG_SPIMCTRL
779+ Say Y here to enable a simple SPI memory controller.
780+ The controller maps a SPI memory device into AMBA address space and
781+ also has a simple interface that allows sending commands directly
782+ to the SPI device.
783+
784+SD card support
785+CONFIG_SPIMCTRL_SDCARD
786+ Memory device connected to controller is SD card.
787+
788+Read command
789+CONFIG_SPIMCTRL_READCMD
790+ Read instruction for SPI memory device
791+
792+Dummy byte
793+CONFIG_SPIMCTRL_DUMMYBYTE
794+ Output dummy byte after address when issuing read instruction.
795+
796+Dual output
797+CONFIG_SPIMCTRL_DUALOUTPUT
798+ Memory device supports dual output when reading data.
799+
800+Clock scaler
801+CONFIG_SPIMCTRL_SCALER
802+ Selects the divisor used when dividing the system clock to produce
803+ the memory device clock. The divisor used is two to the power of the
804+ specified value. This value must be at least 1.
805+
806+Alternate clock scaler
807+CONFIG_SPIMCTRL_ASCALER
808+ Selects the divisor used when dividing the system clock to produce
809+ the alternate memory device clock. If the selected memory device is
810+ a SD Card this clock will be used during card initialization. The
811+ divisor used is two to the power of the specified value. This
812+ value must be at least 1.
813+
814+Power-up cnt
815+CONFIG_SPIMCTRL_PWRUPCNT
816+ Number of system clock cycles to wait before issuing first command.
817+On-chip rom
818+CONFIG_AHBROM_ENABLE
819+ Say Y here to add a block on on-chip rom to the AHB bus. The ram
820+ provides 0-waitstates read access, burst support, and 8-, 16-
821+ and 32-bit data size. The rom will be syntheised into block rams
822+ on Xilinx and Altera FPGA devices, and into gates on ASIC
823+ technologies. GRLIB includes a utility to automatically create
824+ the rom VHDL model (ahbrom.vhd) from an ELF file. Refer to the GRLIB
825+ documentation for details.
826+
827+On-chip rom address
828+CONFIG_AHBROM_START
829+ Set the start address of AHB ROM (HADDR[31:20]). The ROM will occupy
830+ a 1 Mbyte slot at the selected address. Default is 000, corresponding
831+ to AHB address 0x00000000. When address 0x0 is selected, the rom area
832+ of any other memory controller is set to 0x10000000 to avoid conflicts.
833+
834+Enable pipeline register for on-chip rom
835+CONFIG_AHBROM_PIPE
836+ Say Y here to add a data pipeline register to the on-chip rom.
837+ This should be done when the rom is implemenented in (ASIC) gates,
838+ or in logic cells on FPGAs. Do not use this option when the rom is
839+ implemented in block rams. If enabled, the rom will operate with
840+ one waitstate.
841+
842+On-chip ram
843+CONFIG_AHBRAM_ENABLE
844+ Say Y here to add a block on on-chip ram to the AHB bus. The ram
845+ provides 0-waitstates read access and 0/1 waitstates write access.
846+ All AHB burst types are supported, as well as 8-, 16- and 32-bit
847+ data size.
848+
849+On-chip ram size
850+CONFIG_AHBRAM_SZ1
851+ Set the size of the on-chip AHB ram. The ram is infered/instantiated
852+ as four byte-wide ram slices to allow byte and half-word write
853+ accesses. It is therefore essential that the target package can
854+ infer byte-wide rams. This is currently supported on the generic,
855+ virtex, virtex2, proasic and axellerator targets.
856+
857+On-chip ram address
858+CONFIG_AHBRAM_START
859+ Set the start address of AHB RAM (HADDR[31:20]). The RAM will occupy
860+ a 1 Mbyte slot at the selected address. Default is A00, corresponding
861+ to AHB address 0xA0000000.
862+
863+Gaisler Ethernet MAC enable
864+CONFIG_GRETH_ENABLE
865+ Say Y here to enable the Gaisler Research Ethernet MAC . The MAC has
866+ one AHB master interface to read and write packets to memory, and one
867+ APB slave interface for accessing the control registers.
868+
869+Gaisler Ethernet 1G MAC enable
870+CONFIG_GRETH_GIGA
871+ Say Y here to enable the Gaisler Research 1000 Mbit Ethernet MAC .
872+ The 1G MAC is only available in the commercial version of GRLIB,
873+ so do NOT enable it if you are using the GPL version.
874+
875+CONFIG_GRETH_FIFO4
876+ Set the depth of the receive and transmit FIFOs in the MAC core.
877+ The MAC core will perform AHB burst read/writes with half the
878+ size of the FIFO depth.
879+
880+
881+UART1 enable
882+CONFIG_UART1_ENABLE
883+ Say Y here to enable UART1, or the console UART. This is needed to
884+ get any print-out from LEON3 systems regardless of operating system.
885+
886+UART1 FIFO
887+CONFIG_UA1_FIFO1
888+ The UART has configurable transmitt and receive FIFO's, which can
889+ be set to 1 - 32 bytes. Use 1 for minimum area, or 8 - 32 for
890+ maximum throughput.
891+
892+
893+LEON3 interrupt controller
894+CONFIG_IRQ3_ENABLE
895+ Say Y here to enable the LEON3 interrupt controller. This is needed
896+ if you want to be able to receive interrupts. Operating systems like
897+ Linux, RTEMS and eCos needs this option to be enabled. If you intend
898+ to use the Bare-C run-time and not use interrupts, you could disable
899+ the interrupt controller and save about 500 gates.
900+
901+LEON3 interrupt controller broadcast
902+CONFIG_IRQ3_BROADCAST_ENABLE
903+ If enabled the broadcast register is used to determine which
904+ interrupt should be sent to all cpus instead of just the first
905+ one that consumes it.
906+
907+Secondary interrupts
908+CONFIG_IRQ3_SEC
909+ The interrupt controller handles 15 interrupts by default (1 - 15).
910+ These correspond to the 15 SPARC asyncronous traps (0x11 - 0x1F),
911+ and AMBA interrupts 1 - 15. This option will enable 16 additional
912+ (secondary) interrupts, corresponding to AMBA interrupts 16 - 31.
913+ The secondary interrupts will be multiplexed onto one of the first
914+ 15 interrupts. The total number of handled interrupts can then
915+ be up to 30 (14 primary and 16 secondary).
916+
917+Number of interrupts
918+CONFIG_IRQ3_NSEC
919+ Defines which of the first 15 interrupts should be used for the
920+ secondary (16 - 31) interrupts. Interrupt 15 should be avoided
921+ since it is not maskable by the processor.
922+Timer module enable
923+CONFIG_GPT_ENABLE
924+ Say Y here to enable the Modular Timer Unit. The timer unit consists
925+ of one common scaler and up to 7 independent timers. The timer unit
926+ is needed for Linux, RTEMS, eCos and the Bare-C run-times.
927+
928+Timer module enable
929+CONFIG_GPT_NTIM
930+ Set the number of timers in the timer unit (1 - 7).
931+
932+Scaler width
933+CONFIG_GPT_SW
934+ Set the width if the common pre-scaler (2 - 16 bits). The scaler
935+ is used to divide the system clock down to 1 MHz, so 8 bits should
936+ be sufficient for most implementations (allows clocks up to 256 MHz).
937+
938+Timer width
939+CONFIG_GPT_TW
940+ Set the width if the timers (2 - 32 bits). 32 bits is recommended
941+ for the Bare-C run-time, lower values (e.g. 16 bits) can work with
942+ RTEMS and Linux.
943+
944+Timer Interrupt
945+CONFIG_GPT_IRQ
946+ Set the interrupt number for the first timer. Remaining timers will
947+ have incrementing interrupts, unless the separate-interrupts option
948+ below is disabled.
949+
950+Watchdog enable
951+CONFIG_GPT_WDOGEN
952+ Say Y here to enable the watchdog functionality in the timer unit.
953+
954+Watchdog time-out value
955+CONFIG_GPT_WDOG
956+ This value will be loaded in the watchdog timer at reset.
957+
958+GPIO port
959+CONFIG_GRGPIO_ENABLE
960+ Say Y here to enable a general purpose I/O port. The port can be
961+ configured from 1 - 32 bits, whith each port signal individually
962+ programmable as input or output. The port signals can also serve
963+ as interrupt inputs.
964+
965+GPIO port witdth
966+CONFIG_GRGPIO_WIDTH
967+ Number of bits in the I/O port. Must be in the range of 1 - 32.
968+
969+GPIO interrupt mask
970+CONFIG_GRGPIO_IMASK
971+ The I/O port interrupt mask defines which bits in the I/O port
972+ should be able to create an interrupt.
973+
974+OpenCores I2C Master
975+CONFIG_I2C_ENABLE
976+ Say Y here to enable the OpenCores I2C master.
977+PS2 interface
978+CONFIG_PS2_ENABLE
979+ Say Y here to enable a PS/2 keyboard or mouse interface.
980+
981+Gaisler Research SPI controller
982+CONFIG_SPICTRL_ENABLE
983+ Say Y here to enable the SPI controller
984+LCD frame buffer
985+CONFIG_LCD_ENABLE
986+ Say Y here to enable a graphical frame buffer. The frame buffer
987+ can be configured up to 1024x768 pixels and 8-, 16- or 32-bit
988+ colour depth.
989+
990+LCD 3-wire serial interface and touch panel support
991+CONFIG_LCD3T_ENABLE
992+ Say Y here to instantiate a SPI controller that allows LCD touch
993+ panel and LCD 3-wire serial interface support
994+
995+SVGA frame buffer
996+CONFIG_SVGA_ENABLE
997+ Say Y here to enable a graphical frame buffer. The frame buffer
998+ can be configured up to 1024x768 pixels and 8-, 16- or 32-bit
999+ colour depth.
1000+
1001+UART debugging
1002+CONFIG_DEBUG_UART
1003+ During simulation, the output from the UARTs is printed on the
1004+ simulator console. Since the ratio between the system clock and
1005+ UART baud-rate is quite high, simulating UART output will be very
1006+ slow. If you say Y here, the UARTs will print a character as soon
1007+ as it is stored in the transmitter data register. The transmitter
1008+ ready flag will be permanently set, speeding up simulation. However,
1009+ the output on the UART tx line will be garbled. Has not impact on
1010+ synthesis, but will cause the LEON test bench to fail.
1011+
1012+FPU register tracing
1013+CONFIG_DEBUG_FPURF
1014+ If you say Y here, all writes to the floating-point unit register file
1015+ will be printed on the simulator console.
1016+
--- /dev/null
+++ b/grlib-gpl-1.0.22-b4095/designs/work_amba/config.in
@@ -0,0 +1,82 @@
1+#
2+# LEON3 configuration written in linux configuration language
3+#
4+# Written by Jiri Gaisler, Gaisler Research
5+#
6+# Comments and bug reports to jiri@gaisler.com
7+#
8+#
9+
10+#define_bool CONFIG_MCTRL_RMW y
11+
12+mainmenu_name "LEON3 Altera EP3C25-EEK Design Configuration"
13+
14+mainmenu_option next_comment
15+ comment 'Synthesis '
16+ source lib/techmap/gencomp/tech.in
17+endmenu
18+
19+mainmenu_option next_comment
20+ comment 'Clock generation'
21+ source lib/techmap/clocks/clkgen.in
22+endmenu
23+
24+source lib/gaisler/leon3/leon3.in
25+source lib/grlib/amba/amba.in
26+
27+mainmenu_option next_comment
28+ comment 'Debug Link '
29+ source lib/gaisler/uart/dcom.in
30+ source lib/gaisler/jtag/jtag.in
31+ source lib/gaisler/net/edcl.in
32+endmenu
33+
34+mainmenu_option next_comment
35+comment 'Peripherals '
36+
37+ mainmenu_option next_comment
38+ comment 'Memory controllers '
39+ source lib/esa/memoryctrl/mctrl.in
40+ source lib/gaisler/memctrl/ssrctrl.in
41+ source lib/gaisler/ddr/ddrsp.in
42+ source lib/gaisler/memctrl/spimctrl.in
43+ endmenu
44+
45+ mainmenu_option next_comment
46+ comment 'On-chip RAM/ROM '
47+ source lib/gaisler/misc/ahbrom.in
48+ source lib/gaisler/misc/ahbram.in
49+ endmenu
50+
51+ mainmenu_option next_comment
52+ comment 'Ethernet '
53+ source lib/gaisler/greth/greth.in
54+ endmenu
55+
56+ mainmenu_option next_comment
57+ comment 'UARTs, timers and irq control '
58+ source lib/gaisler/uart/uart1.in
59+ source lib/gaisler/leon3/irqmp.in
60+ source lib/gaisler/misc/gptimer.in
61+ source lib/gaisler/misc/grgpio.in
62+ endmenu
63+
64+ mainmenu_option next_comment
65+ comment 'Serial interfaces; I2C, PS/2 and SPI '
66+ source lib/gaisler/misc/i2c.in
67+ source lib/gaisler/misc/ps2.in
68+ source lib/gaisler/misc/spictrl.in
69+ endmenu
70+
71+ mainmenu_option next_comment
72+ comment 'LCD and VGA DAC '
73+ source designs/leon3-altera-ep3c25-eek/lcd.in
74+ source lib/gaisler/misc/svgactrl.in
75+ endmenu
76+
77+endmenu
78+
79+mainmenu_option next_comment
80+comment 'VHDL Debugging '
81+ source lib/grlib/util/debug.in
82+endmenu
--- /dev/null
+++ b/grlib-gpl-1.0.22-b4095/designs/work_amba/config.vhd
@@ -0,0 +1,194 @@
1+
2+
3+
4+
5+-----------------------------------------------------------------------------
6+-- LEON3 Demonstration design test bench configuration
7+-- Copyright (C) 2009 Aeroflex Gaisler
8+------------------------------------------------------------------------------
9+
10+
11+library techmap;
12+use techmap.gencomp.all;
13+
14+package config is
15+-- Technology and synthesis options
16+ constant CFG_FABTECH : integer := cyclone3;
17+ constant CFG_MEMTECH : integer := cyclone3;
18+ constant CFG_PADTECH : integer := cyclone3;
19+ constant CFG_NOASYNC : integer := 0;
20+ constant CFG_SCAN : integer := 0;
21+-- Clock generator
22+ constant CFG_CLKTECH : integer := cyclone3;
23+ constant CFG_CLKMUL : integer := (5);
24+ constant CFG_CLKDIV : integer := (5);
25+ constant CFG_OCLKDIV : integer := 2;
26+ constant CFG_PCIDLL : integer := 0;
27+ constant CFG_PCISYSCLK: integer := 0;
28+ constant CFG_CLK_NOFB : integer := 0;
29+-- LEON3 processor core
30+ constant CFG_LEON3 : integer := 1;
31+ constant CFG_NCPU : integer := (1);
32+ constant CFG_NWIN : integer := (8);
33+ constant CFG_V8 : integer := 2;
34+ constant CFG_MAC : integer := 0;
35+ constant CFG_SVT : integer := 0;
36+ constant CFG_RSTADDR : integer := 16#00000#;
37+ constant CFG_LDDEL : integer := (1);
38+ constant CFG_NWP : integer := (2);
39+ constant CFG_PWD : integer := 0*2;
40+ constant CFG_FPU : integer := 0 + 16*0;
41+ constant CFG_GRFPUSH : integer := 0;
42+ constant CFG_ICEN : integer := 1;
43+ constant CFG_ISETS : integer := 2;
44+ constant CFG_ISETSZ : integer := 4;
45+ constant CFG_ILINE : integer := 8;
46+ constant CFG_IREPL : integer := 1;
47+ constant CFG_ILOCK : integer := 0;
48+ constant CFG_ILRAMEN : integer := 0;
49+ constant CFG_ILRAMADDR: integer := 16#8E#;
50+ constant CFG_ILRAMSZ : integer := 1;
51+ constant CFG_DCEN : integer := 1;
52+ constant CFG_DSETS : integer := 2;
53+ constant CFG_DSETSZ : integer := 4;
54+ constant CFG_DLINE : integer := 4;
55+ constant CFG_DREPL : integer := 1;
56+ constant CFG_DLOCK : integer := 0;
57+ constant CFG_DSNOOP : integer := 1 + 0 + 4*0;
58+ constant CFG_DFIXED : integer := 16#0#;
59+ constant CFG_DLRAMEN : integer := 0;
60+ constant CFG_DLRAMADDR: integer := 16#8F#;
61+ constant CFG_DLRAMSZ : integer := 1;
62+ constant CFG_MMUEN : integer := 1;
63+ constant CFG_ITLBNUM : integer := 8;
64+ constant CFG_DTLBNUM : integer := 8;
65+ constant CFG_TLB_TYPE : integer := 0 + 1*2;
66+ constant CFG_TLB_REP : integer := 1;
67+ constant CFG_MMU_PAGE : integer := 0;
68+ constant CFG_DSU : integer := 1;
69+ constant CFG_ITBSZ : integer := 2;
70+ constant CFG_ATBSZ : integer := 2;
71+ constant CFG_LEON3FT_EN : integer := 0;
72+ constant CFG_IUFT_EN : integer := 0;
73+ constant CFG_FPUFT_EN : integer := 0;
74+ constant CFG_RF_ERRINJ : integer := 0;
75+ constant CFG_CACHE_FT_EN : integer := 0;
76+ constant CFG_CACHE_ERRINJ : integer := 0;
77+ constant CFG_LEON3_NETLIST: integer := 0;
78+ constant CFG_DISAS : integer := 0 + 0;
79+ constant CFG_PCLOW : integer := 2;
80+-- AMBA settings
81+ constant CFG_DEFMST : integer := (0);
82+ constant CFG_RROBIN : integer := 1;
83+ constant CFG_SPLIT : integer := 0;
84+ constant CFG_AHBIO : integer := 16#FFF#;
85+ constant CFG_APBADDR : integer := 16#800#;
86+ constant CFG_AHB_MON : integer := 0;
87+ constant CFG_AHB_MONERR : integer := 0;
88+ constant CFG_AHB_MONWAR : integer := 0;
89+-- DSU UART
90+ constant CFG_AHB_UART : integer := 0;
91+-- JTAG based DSU interface
92+ constant CFG_AHB_JTAG : integer := 1;
93+-- Ethernet DSU
94+ constant CFG_DSU_ETH : integer := 1 + 0;
95+ constant CFG_ETH_BUF : integer := 2;
96+ constant CFG_ETH_IPM : integer := 16#C0A8#;
97+ constant CFG_ETH_IPL : integer := 16#0039#;
98+ constant CFG_ETH_ENM : integer := 16#020000#;
99+ constant CFG_ETH_ENL : integer := 16#000011#;
100+-- LEON2 memory controller
101+ constant CFG_MCTRL_LEON2 : integer := 1;
102+ constant CFG_MCTRL_RAM8BIT : integer := 0;
103+ constant CFG_MCTRL_RAM16BIT : integer := 1;
104+ constant CFG_MCTRL_5CS : integer := 0;
105+ constant CFG_MCTRL_SDEN : integer := 0;
106+ constant CFG_MCTRL_SEPBUS : integer := 0;
107+ constant CFG_MCTRL_INVCLK : integer := 0;
108+ constant CFG_MCTRL_SD64 : integer := 0;
109+ constant CFG_MCTRL_PAGE : integer := 0 + 0;
110+-- SSRAM controller
111+ constant CFG_SSCTRL : integer := 0;
112+ constant CFG_SSCTRLP16 : integer := 0;
113+-- DDR controller
114+ constant CFG_DDRSP : integer := 1;
115+ constant CFG_DDRSP_INIT : integer := 1;
116+ constant CFG_DDRSP_FREQ : integer := (100);
117+ constant CFG_DDRSP_COL : integer := (9);
118+ constant CFG_DDRSP_SIZE : integer := (8);
119+ constant CFG_DDRSP_RSKEW : integer := (2500);
120+-- SPI memory controller
121+ constant CFG_SPIMCTRL : integer := 0;
122+ constant CFG_SPIMCTRL_SDCARD : integer := 0;
123+ constant CFG_SPIMCTRL_READCMD : integer := 16#0#;
124+ constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
125+ constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
126+ constant CFG_SPIMCTRL_SCALER : integer := 1;
127+ constant CFG_SPIMCTRL_ASCALER : integer := 1;
128+ constant CFG_SPIMCTRL_PWRUPCNT : integer := 0;
129+-- AHB ROM
130+ constant CFG_AHBROMEN : integer := 0;
131+ constant CFG_AHBROPIP : integer := 0;
132+ constant CFG_AHBRODDR : integer := 16#000#;
133+ constant CFG_ROMADDR : integer := 16#000#;
134+ constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
135+-- AHB RAM
136+ constant CFG_AHBRAMEN : integer := 0;
137+ constant CFG_AHBRSZ : integer := 1;
138+ constant CFG_AHBRADDR : integer := 16#A00#;
139+
140+-- Gaisler Ethernet core
141+ constant CFG_GRETH : integer := 1;
142+ constant CFG_GRETH1G : integer := 0;
143+ constant CFG_ETH_FIFO : integer := 64;
144+
145+-- UART 1
146+ constant CFG_UART1_ENABLE : integer := 1;
147+ constant CFG_UART1_FIFO : integer := 8;
148+
149+-- LEON3 interrupt controller
150+ constant CFG_IRQ3_ENABLE : integer := 1;
151+ constant CFG_IRQ3_NSEC : integer := 0;
152+
153+-- Modular timer
154+ constant CFG_GPT_ENABLE : integer := 1;
155+ constant CFG_GPT_NTIM : integer := (2);
156+ constant CFG_GPT_SW : integer := (8);
157+ constant CFG_GPT_TW : integer := (32);
158+ constant CFG_GPT_IRQ : integer := (8);
159+ constant CFG_GPT_SEPIRQ : integer := 1;
160+ constant CFG_GPT_WDOGEN : integer := 0;
161+ constant CFG_GPT_WDOG : integer := 16#0#;
162+
163+-- GPIO port
164+ constant CFG_GRGPIO_ENABLE : integer := 1;
165+ constant CFG_GRGPIO_IMASK : integer := 16#0#;
166+ constant CFG_GRGPIO_WIDTH : integer := (5);
167+
168+-- I2C master
169+ constant CFG_I2C_ENABLE : integer := 1;
170+
171+-- PS/2 interface
172+ constant CFG_PS2_ENABLE : integer := 1;
173+
174+-- SPI controller
175+ constant CFG_SPICTRL_ENABLE : integer := 1;
176+ constant CFG_SPICTRL_SLVS : integer := (1);
177+ constant CFG_SPICTRL_FIFO : integer := (2);
178+ constant CFG_SPICTRL_SLVREG : integer := 1;
179+ constant CFG_SPICTRL_ODMODE : integer := 0;
180+ constant CFG_SPICTRL_AM : integer := 0;
181+ constant CFG_SPICTRL_ASEL : integer := 0;
182+
183+-- LCD SVGA controller
184+ constant CFG_LCD_ENABLE : integer := 1;
185+
186+-- LCD 3-wire serial interface
187+ constant CFG_LCD3T_ENABLE : integer := 1;
188+
189+-- SVGA controller
190+ constant CFG_SVGA_ENABLE : integer := 0;
191+
192+-- GRLIB debugging
193+ constant CFG_DUART : integer := 0;
194+end;
--- /dev/null
+++ b/grlib-gpl-1.0.22-b4095/designs/work_amba/config.vhd.h
@@ -0,0 +1,192 @@
1+-- Technology and synthesis options
2+ constant CFG_FABTECH : integer := CONFIG_SYN_TECH;
3+ constant CFG_MEMTECH : integer := CFG_RAM_TECH;
4+ constant CFG_PADTECH : integer := CFG_PAD_TECH;
5+ constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC;
6+ constant CFG_SCAN : integer := CONFIG_SYN_SCAN;
7+
8+-- Clock generator
9+ constant CFG_CLKTECH : integer := CFG_CLK_TECH;
10+ constant CFG_CLKMUL : integer := CONFIG_CLK_MUL;
11+ constant CFG_CLKDIV : integer := CONFIG_CLK_DIV;
12+ constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV;
13+ constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL;
14+ constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK;
15+ constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB;
16+
17+-- LEON3 processor core
18+ constant CFG_LEON3 : integer := CONFIG_LEON3;
19+ constant CFG_NCPU : integer := CONFIG_PROC_NUM;
20+ constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS;
21+ constant CFG_V8 : integer := CFG_IU_V8;
22+ constant CFG_MAC : integer := CONFIG_IU_MUL_MAC;
23+ constant CFG_SVT : integer := CONFIG_IU_SVT;
24+ constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#;
25+ constant CFG_LDDEL : integer := CONFIG_IU_LDELAY;
26+ constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS;
27+ constant CFG_PWD : integer := CONFIG_PWD*2;
28+ constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST;
29+ constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED;
30+ constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE;
31+ constant CFG_ISETS : integer := CFG_IU_ISETS;
32+ constant CFG_ISETSZ : integer := CFG_ICACHE_SZ;
33+ constant CFG_ILINE : integer := CFG_ILINE_SZ;
34+ constant CFG_IREPL : integer := CFG_ICACHE_ALGORND;
35+ constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK;
36+ constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM;
37+ constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#;
38+ constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE;
39+ constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE;
40+ constant CFG_DSETS : integer := CFG_IU_DSETS;
41+ constant CFG_DSETSZ : integer := CFG_DCACHE_SZ;
42+ constant CFG_DLINE : integer := CFG_DLINE_SZ;
43+ constant CFG_DREPL : integer := CFG_DCACHE_ALGORND;
44+ constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK;
45+ constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG;
46+ constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#;
47+ constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM;
48+ constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#;
49+ constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE;
50+ constant CFG_MMUEN : integer := CONFIG_MMUEN;
51+ constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM;
52+ constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM;
53+ constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2;
54+ constant CFG_TLB_REP : integer := CONFIG_TLB_REP;
55+ constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE;
56+ constant CFG_DSU : integer := CONFIG_DSU_ENABLE;
57+ constant CFG_ITBSZ : integer := CFG_DSU_ITB;
58+ constant CFG_ATBSZ : integer := CFG_DSU_ATB;
59+ constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN;
60+ constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN;
61+ constant CFG_FPUFT_EN : integer := CONFIG_FPUFT;
62+ constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ;
63+ constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN;
64+ constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ;
65+ constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST;
66+ constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET;
67+ constant CFG_PCLOW : integer := CFG_DEBUG_PC32;
68+
69+-- AMBA settings
70+ constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST;
71+ constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN;
72+ constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT;
73+ constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#;
74+ constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#;
75+ constant CFG_AHB_MON : integer := CONFIG_AHB_MON;
76+ constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR;
77+ constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR;
78+
79+-- DSU UART
80+ constant CFG_AHB_UART : integer := CONFIG_DSU_UART;
81+
82+-- JTAG based DSU interface
83+ constant CFG_AHB_JTAG : integer := CONFIG_DSU_JTAG;
84+
85+-- Ethernet DSU
86+ constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG;
87+ constant CFG_ETH_BUF : integer := CFG_DSU_ETHB;
88+ constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#;
89+ constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#;
90+ constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#;
91+ constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#;
92+
93+-- LEON2 memory controller
94+ constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2;
95+ constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT;
96+ constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT;
97+ constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS;
98+ constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM;
99+ constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS;
100+ constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK;
101+ constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64;
102+ constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE;
103+
104+-- SSRAM controller
105+ constant CFG_SSCTRL : integer := CONFIG_SSCTRL;
106+ constant CFG_SSCTRLP16 : integer := CONFIG_SSCTRL_PROM16;
107+
108+-- DDR controller
109+ constant CFG_DDRSP : integer := CONFIG_DDRSP;
110+ constant CFG_DDRSP_INIT : integer := CONFIG_DDRSP_INIT;
111+ constant CFG_DDRSP_FREQ : integer := CONFIG_DDRSP_FREQ;
112+ constant CFG_DDRSP_COL : integer := CONFIG_DDRSP_COL;
113+ constant CFG_DDRSP_SIZE : integer := CONFIG_DDRSP_MBYTE;
114+ constant CFG_DDRSP_RSKEW : integer := CONFIG_DDRSP_RSKEW;
115+
116+-- SPI memory controller
117+ constant CFG_SPIMCTRL : integer := CONFIG_SPIMCTRL;
118+ constant CFG_SPIMCTRL_SDCARD : integer := CONFIG_SPIMCTRL_SDCARD;
119+ constant CFG_SPIMCTRL_READCMD : integer := 16#CONFIG_SPIMCTRL_READCMD#;
120+ constant CFG_SPIMCTRL_DUMMYBYTE : integer := CONFIG_SPIMCTRL_DUMMYBYTE;
121+ constant CFG_SPIMCTRL_DUALOUTPUT : integer := CONFIG_SPIMCTRL_DUALOUTPUT;
122+ constant CFG_SPIMCTRL_SCALER : integer := CONFIG_SPIMCTRL_SCALER;
123+ constant CFG_SPIMCTRL_ASCALER : integer := CONFIG_SPIMCTRL_ASCALER;
124+ constant CFG_SPIMCTRL_PWRUPCNT : integer := CONFIG_SPIMCTRL_PWRUPCNT;
125+
126+-- AHB ROM
127+ constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE;
128+ constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE;
129+ constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#;
130+ constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#;
131+ constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#;
132+
133+-- AHB RAM
134+ constant CFG_AHBRAMEN : integer := CONFIG_AHBRAM_ENABLE;
135+ constant CFG_AHBRSZ : integer := CFG_AHBRAMSZ;
136+ constant CFG_AHBRADDR : integer := 16#CONFIG_AHBRAM_START#;
137+
138+-- Gaisler Ethernet core
139+ constant CFG_GRETH : integer := CONFIG_GRETH_ENABLE;
140+ constant CFG_GRETH1G : integer := CONFIG_GRETH_GIGA;
141+ constant CFG_ETH_FIFO : integer := CFG_GRETH_FIFO;
142+
143+-- UART 1
144+ constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE;
145+ constant CFG_UART1_FIFO : integer := CFG_UA1_FIFO;
146+
147+-- LEON3 interrupt controller
148+ constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE;
149+ constant CFG_IRQ3_NSEC : integer := CONFIG_IRQ3_NSEC;
150+
151+-- Modular timer
152+ constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE;
153+ constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM;
154+ constant CFG_GPT_SW : integer := CONFIG_GPT_SW;
155+ constant CFG_GPT_TW : integer := CONFIG_GPT_TW;
156+ constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ;
157+ constant CFG_GPT_SEPIRQ : integer := CONFIG_GPT_SEPIRQ;
158+ constant CFG_GPT_WDOGEN : integer := CONFIG_GPT_WDOGEN;
159+ constant CFG_GPT_WDOG : integer := 16#CONFIG_GPT_WDOG#;
160+
161+-- GPIO port
162+ constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE;
163+ constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#;
164+ constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH;
165+
166+-- I2C master
167+ constant CFG_I2C_ENABLE : integer := CONFIG_I2C_ENABLE;
168+
169+-- PS/2 interface
170+ constant CFG_PS2_ENABLE : integer := CONFIG_PS2_ENABLE;
171+
172+-- SPI controller
173+ constant CFG_SPICTRL_ENABLE : integer := CONFIG_SPICTRL_ENABLE;
174+ constant CFG_SPICTRL_SLVS : integer := CONFIG_SPICTRL_SLVS;
175+ constant CFG_SPICTRL_FIFO : integer := CONFIG_SPICTRL_FIFO;
176+ constant CFG_SPICTRL_SLVREG : integer := CONFIG_SPICTRL_SLVREG;
177+ constant CFG_SPICTRL_ODMODE : integer := CONFIG_SPICTRL_ODMODE;
178+ constant CFG_SPICTRL_AM : integer := CONFIG_SPICTRL_AM;
179+ constant CFG_SPICTRL_ASEL : integer := CONFIG_SPICTRL_ASEL;
180+
181+-- LCD SVGA controller
182+ constant CFG_LCD_ENABLE : integer := CONFIG_LCD_ENABLE;
183+
184+-- LCD 3-wire serial interface
185+ constant CFG_LCD3T_ENABLE : integer := CONFIG_LCD3T_ENABLE;
186+
187+-- SVGA controller
188+ constant CFG_SVGA_ENABLE : integer := CONFIG_SVGA_ENABLE;
189+
190+-- GRLIB debugging
191+ constant CFG_DUART : integer := CONFIG_DEBUG_UART;
192+
--- /dev/null
+++ b/grlib-gpl-1.0.22-b4095/designs/work_amba/config.vhd.in
@@ -0,0 +1,16 @@
1+#include "config.h"
2+#include "tkconfig.h"
3+-----------------------------------------------------------------------------
4+-- LEON3 Demonstration design test bench configuration
5+-- Copyright (C) 2009 Aeroflex Gaisler
6+------------------------------------------------------------------------------
7+
8+
9+library techmap;
10+use techmap.gencomp.all;
11+
12+package config is
13+
14+#include "config.vhd.h"
15+
16+end;
--- /dev/null
+++ b/grlib-gpl-1.0.22-b4095/designs/work_amba/config_test.h
@@ -0,0 +1,75 @@
1+/*
2+ * Processor
3+ */
4+/*
5+ * Integer unit
6+ */
7+#define CONFIG_IU_NWINDOWS (8)
8+#undef CONFIG_IU_V8MULDIV
9+/*
10+ * Cache system
11+ */
12+#define CONFIG_ICACHE_ENABLE 1
13+#define CONFIG_ICACHE_SZ1 1
14+#undef CONFIG_ICACHE_SZ2
15+#undef CONFIG_ICACHE_SZ4
16+#undef CONFIG_ICACHE_SZ8
17+#undef CONFIG_ICACHE_SZ16
18+#undef CONFIG_ICACHE_SZ32
19+#undef CONFIG_ICACHE_SZ64
20+#undef CONFIG_ICACHE_LRAM
21+#define CONFIG_DCACHE_ENABLE 1
22+#define CONFIG_DCACHE_SZ1 1
23+#undef CONFIG_DCACHE_SZ2
24+#undef CONFIG_DCACHE_SZ4
25+#undef CONFIG_DCACHE_SZ8
26+#undef CONFIG_DCACHE_SZ16
27+#undef CONFIG_DCACHE_SZ32
28+#undef CONFIG_DCACHE_SZ64
29+#undef CONFIG_DCACHE_LRAM
30+/*
31+ * MMU
32+ */
33+#undef CONFIG_MMU_ENABLE
34+/*
35+ * Debug Support Unit
36+ */
37+#define CONFIG_DSU_ENABLE 1
38+#undef CONFIG_DSU_ITRACE
39+#undef CONFIG_DSU_ATRACE
40+/*
41+ * Debug Link
42+ */
43+#define CONFIG_DSU_UART 1
44+#define CONFIG_DSU_ETH 1
45+#undef CONFIG_DSU_ETHSZ1
46+#define CONFIG_DSU_ETHSZ2 1
47+#undef CONFIG_DSU_ETHSZ4
48+#undef CONFIG_DSU_ETHSZ8
49+#undef CONFIG_DSU_ETHSZ16
50+/*
51+ * Peripherals
52+ */
53+/*
54+ * Memory controllers
55+ */
56+#undef CONFIG_MCTRL_NONE
57+#define CONFIG_MCTRL_LEON2 1
58+#define CONFIG_MCTRL_SDRAM 1
59+/*
60+ * Ethernet
61+ */
62+#undef CONFIG_ETH_ENABLE
63+/*
64+ * PCI
65+ */
66+#undef CONFIG_PCI_ENABLE
67+/*
68+ * CAN
69+ */
70+#undef CONFIG_CAN_ENABLE
71+/*
72+ * UARTs, timers and irq control
73+ */
74+#define CONFIG_UART1_ENABLE 1
75+#define CONFIG_GPT_ENABLE 1
--- /dev/null
+++ b/grlib-gpl-1.0.22-b4095/designs/work_amba/defconfig
@@ -0,0 +1,252 @@
1+#
2+# Automatically generated make config: don't edit
3+#
4+
5+#
6+# Synthesis
7+#
8+# CONFIG_SYN_INFERRED is not set
9+# CONFIG_SYN_STRATIX is not set
10+# CONFIG_SYN_STRATIXII is not set
11+# CONFIG_SYN_STRATIXIII is not set
12+CONFIG_SYN_CYCLONEIII=y
13+# CONFIG_SYN_ALTERA is not set
14+# CONFIG_SYN_AXCEL is not set
15+# CONFIG_SYN_PROASIC is not set
16+# CONFIG_SYN_PROASICPLUS is not set
17+# CONFIG_SYN_PROASIC3 is not set
18+# CONFIG_SYN_UT025CRH is not set
19+# CONFIG_SYN_ATC18 is not set
20+# CONFIG_SYN_CUSTOM1 is not set
21+# CONFIG_SYN_IHP25 is not set
22+# CONFIG_SYN_IHP25RH is not set
23+# CONFIG_SYN_LATTICE is not set
24+# CONFIG_SYN_ECLIPSE is not set
25+# CONFIG_SYN_PEREGRINE is not set
26+# CONFIG_SYN_RH_LIB18T is not set
27+# CONFIG_SYN_RHUMC is not set
28+# CONFIG_SYN_SPARTAN2 is not set
29+# CONFIG_SYN_SPARTAN3 is not set
30+# CONFIG_SYN_SPARTAN3E is not set
31+# CONFIG_SYN_VIRTEX is not set
32+# CONFIG_SYN_VIRTEXE is not set
33+# CONFIG_SYN_VIRTEX2 is not set
34+# CONFIG_SYN_VIRTEX4 is not set
35+# CONFIG_SYN_VIRTEX5 is not set
36+# CONFIG_SYN_INFER_RAM is not set
37+# CONFIG_SYN_INFER_PADS is not set
38+# CONFIG_SYN_NO_ASYNC is not set
39+
40+#
41+# Clock generation
42+#
43+# CONFIG_CLK_INFERRED is not set
44+# CONFIG_CLK_HCLKBUF is not set
45+CONFIG_CLK_ALTDLL=y
46+# CONFIG_CLK_LATDLL is not set
47+# CONFIG_CLK_PRO3PLL is not set
48+# CONFIG_CLK_LIB18T is not set
49+# CONFIG_CLK_CLKDLL is not set
50+# CONFIG_CLK_DCM is not set
51+CONFIG_CLK_MUL=2
52+CONFIG_CLK_DIV=2
53+# CONFIG_PCI_SYSCLK is not set
54+CONFIG_LEON3=y
55+CONFIG_PROC_NUM=1
56+
57+#
58+# Processor
59+#
60+
61+#
62+# Integer unit
63+#
64+CONFIG_IU_NWINDOWS=8
65+CONFIG_IU_V8MULDIV=y
66+# CONFIG_IU_MUL_LATENCY_4 is not set
67+CONFIG_IU_MUL_LATENCY_5=y
68+# CONFIG_IU_MUL_MAC is not set
69+# CONFIG_IU_SVT is not set
70+CONFIG_IU_LDELAY=1
71+CONFIG_IU_WATCHPOINTS=2
72+# CONFIG_PWD is not set
73+CONFIG_IU_RSTADDR=00000
74+
75+#
76+# Floating-point unit
77+#
78+# CONFIG_FPU_ENABLE is not set
79+
80+#
81+# Cache system
82+#
83+CONFIG_ICACHE_ENABLE=y
84+# CONFIG_ICACHE_ASSO1 is not set
85+CONFIG_ICACHE_ASSO2=y
86+# CONFIG_ICACHE_ASSO3 is not set
87+# CONFIG_ICACHE_ASSO4 is not set
88+# CONFIG_ICACHE_SZ1 is not set
89+# CONFIG_ICACHE_SZ2 is not set
90+# CONFIG_ICACHE_SZ4 is not set
91+CONFIG_ICACHE_SZ8=y
92+# CONFIG_ICACHE_SZ16 is not set
93+# CONFIG_ICACHE_SZ32 is not set
94+# CONFIG_ICACHE_SZ64 is not set
95+# CONFIG_ICACHE_SZ128 is not set
96+# CONFIG_ICACHE_SZ256 is not set
97+# CONFIG_ICACHE_LZ16 is not set
98+CONFIG_ICACHE_LZ32=y
99+# CONFIG_ICACHE_ALGORND is not set
100+# CONFIG_ICACHE_ALGOLRR is not set
101+CONFIG_ICACHE_ALGOLRU=y
102+# CONFIG_ICACHE_LOCK is not set
103+CONFIG_DCACHE_ENABLE=y
104+# CONFIG_DCACHE_ASSO1 is not set
105+CONFIG_DCACHE_ASSO2=y
106+# CONFIG_DCACHE_ASSO3 is not set
107+# CONFIG_DCACHE_ASSO4 is not set
108+# CONFIG_DCACHE_SZ1 is not set
109+# CONFIG_DCACHE_SZ2 is not set
110+CONFIG_DCACHE_SZ4=y
111+# CONFIG_DCACHE_SZ8 is not set
112+# CONFIG_DCACHE_SZ16 is not set
113+# CONFIG_DCACHE_SZ32 is not set
114+# CONFIG_DCACHE_SZ64 is not set
115+# CONFIG_DCACHE_SZ128 is not set
116+# CONFIG_DCACHE_SZ256 is not set
117+CONFIG_DCACHE_LZ16=y
118+# CONFIG_DCACHE_LZ32 is not set
119+# CONFIG_DCACHE_ALGORND is not set
120+# CONFIG_DCACHE_ALGOLRR is not set
121+CONFIG_DCACHE_ALGOLRU=y
122+# CONFIG_DCACHE_LOCK is not set
123+CONFIG_DCACHE_SNOOP=y
124+# CONFIG_DCACHE_SNOOP_FAST is not set
125+# CONFIG_DCACHE_SNOOP_SEPTAG is not set
126+CONFIG_CACHE_FIXED=0
127+
128+#
129+# MMU
130+#
131+CONFIG_MMU_ENABLE=y
132+# CONFIG_MMU_COMBINED is not set
133+CONFIG_MMU_SPLIT=y
134+# CONFIG_MMU_REPARRAY is not set
135+CONFIG_MMU_REPINCREMENT=y
136+# CONFIG_MMU_I2 is not set
137+# CONFIG_MMU_I4 is not set
138+CONFIG_MMU_I8=y
139+# CONFIG_MMU_I16 is not set
140+# CONFIG_MMU_I32 is not set
141+# CONFIG_MMU_D2 is not set
142+# CONFIG_MMU_D4 is not set
143+CONFIG_MMU_D8=y
144+# CONFIG_MMU_D16 is not set
145+# CONFIG_MMU_D32 is not set
146+
147+#
148+# Debug Support Unit
149+#
150+CONFIG_DSU_ENABLE=y
151+CONFIG_DSU_ITRACE=y
152+# CONFIG_DSU_ITRACESZ1 is not set
153+CONFIG_DSU_ITRACESZ2=y
154+# CONFIG_DSU_ITRACESZ4 is not set
155+# CONFIG_DSU_ITRACESZ8 is not set
156+# CONFIG_DSU_ITRACESZ16 is not set
157+CONFIG_DSU_ATRACE=y
158+# CONFIG_DSU_ATRACESZ1 is not set
159+CONFIG_DSU_ATRACESZ2=y
160+# CONFIG_DSU_ATRACESZ4 is not set
161+# CONFIG_DSU_ATRACESZ8 is not set
162+# CONFIG_DSU_ATRACESZ16 is not set
163+
164+#
165+# Fault-tolerance
166+#
167+
168+#
169+# VHDL debug settings
170+#
171+# CONFIG_IU_DISAS is not set
172+# CONFIG_DEBUG_PC32 is not set
173+
174+#
175+# AMBA configuration
176+#
177+CONFIG_AHB_DEFMST=0
178+CONFIG_AHB_RROBIN=y
179+# CONFIG_AHB_SPLIT is not set
180+CONFIG_AHB_IOADDR=FFF
181+CONFIG_APB_HADDR=800
182+# CONFIG_AHB_MON is not set
183+
184+#
185+# Debug Link
186+#
187+# CONFIG_DSU_UART is not set
188+CONFIG_DSU_JTAG=y
189+
190+#
191+# Peripherals
192+#
193+
194+#
195+# Memory controllers
196+#
197+
198+#
199+# Leon2 memory controller
200+#
201+# CONFIG_MCTRL_LEON2 is not set
202+
203+#
204+# Synchronous SRAM controller
205+#
206+CONFIG_SSCTRL=y
207+CONFIG_SSCTRL_PROM16=y
208+
209+#
210+# DDR266 SDRAM controller
211+#
212+# CONFIG_DDRSP is not set
213+
214+#
215+# On-chip RAM/ROM
216+#
217+# CONFIG_AHBROM_ENABLE is not set
218+# CONFIG_AHBRAM_ENABLE is not set
219+
220+#
221+# UARTs, timers and irq control
222+#
223+CONFIG_UART1_ENABLE=y
224+# CONFIG_UA1_FIFO1 is not set
225+# CONFIG_UA1_FIFO2 is not set
226+# CONFIG_UA1_FIFO4 is not set
227+CONFIG_UA1_FIFO8=y
228+# CONFIG_UA1_FIFO16 is not set
229+# CONFIG_UA1_FIFO32 is not set
230+CONFIG_IRQ3_ENABLE=y
231+CONFIG_GPT_ENABLE=y
232+CONFIG_GPT_NTIM=2
233+CONFIG_GPT_SW=8
234+CONFIG_GPT_TW=32
235+CONFIG_GPT_IRQ=8
236+CONFIG_GPT_SEPIRQ=y
237+# CONFIG_GPT_WDOGEN is not set
238+CONFIG_GRGPIO_ENABLE=y
239+CONFIG_GRGPIO_WIDTH=3
240+CONFIG_GRGPIO_IMASK=6
241+
242+#
243+# ATA Controller
244+#
245+CONFIG_ATA_ENABLE=y
246+CONFIG_ATAIO=A00
247+CONFIG_ATAIRQ=10
248+
249+#
250+# VHDL Debugging
251+#
252+# CONFIG_DEBUG_UART is not set
--- /dev/null
+++ b/grlib-gpl-1.0.22-b4095/designs/work_amba/indata
@@ -0,0 +1,2370 @@
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--- /dev/null
+++ b/grlib-gpl-1.0.22-b4095/designs/work_amba/inter_dct.txtU
@@ -0,0 +1,9600 @@
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