| Revision | d2bb61ba48a30853955c72124d7d94a22e5e2570 (tree) |
|---|---|
| Time | 2011-02-15 23:52:48 |
| Author | Kenichi Kurimoto <kurimoto12@user...> |
| Commiter | Kenichi Kurimoto |
work around Xilinx bug -- huff.vhd
grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/huff.vhd (diff)| @@ -181,18 +181,7 @@ begin | ||
| 181 | 181 | tmp := to_integer(signed('0' & data(10 downto 0))); |
| 182 | 182 | outb := std_logic_vector(to_signed(tmp, 12)); |
| 183 | 183 | end if; |
| 184 | --- elsif(bitnum = "1100")then | |
| 185 | --- if(data(11) = '0)then | |
| 186 | --- tmp := to_integer(signed('1' & data(11 downto 0))) + 1; | |
| 187 | --- outb := std_logic_vector(to_signed(tmp, 12)); | |
| 188 | --- else | |
| 189 | --- tmp := to_integer(signed('0' & data(11 downto 0))); | |
| 190 | --- outb := std_logic_vector(to_signed(tmp, 12)); | |
| 191 | --- end if; | |
| 192 | --- elsif(bitnum ="0000")then | |
| 193 | --- outb := (others => '0'); | |
| 194 | 184 | else |
| 195 | --- report "sign extention over flow" severity note; | |
| 196 | 185 | outb := (others => '0'); |
| 197 | 186 | end if; |
| 198 | 187 |
| @@ -240,13 +229,11 @@ type control_reg is record | ||
| 240 | 229 | hreg : ahbs_reg; |
| 241 | 230 | fifo_rp : std_logic_vector(8 downto 0); |
| 242 | 231 | fifo_wp : std_logic_vector(8 downto 0); |
| 243 | - counter : std_logic_vector(1 downto 0); | |
| 244 | 232 | fetch_reg : std_logic_vector(31 downto 0); |
| 245 | 233 | marker_reg : std_logic_vector(7 downto 0); |
| 246 | 234 | valuebit : std_logic_vector(5 downto 0); |
| 247 | 235 | byteselect : std_logic_vector(1 downto 0); |
| 248 | 236 | reqbit_keep : std_logic_vector(3 downto 0); |
| 249 | - runlength_keep : std_logic_vector(3 downto 0); | |
| 250 | 237 | valbit_keep : std_logic_vector(3 downto 0); |
| 251 | 238 | dcac : std_logic; |
| 252 | 239 | serial_counter : std_logic_vector(4 downto 0); |
| @@ -289,14 +276,7 @@ signal servaldin : std_logic_vector(7 downto 0); | ||
| 289 | 276 | signal servaldout : std_logic_vector(7 downto 0); |
| 290 | 277 | signal servalen,servalwr : std_logic; |
| 291 | 278 | |
| 292 | -signal debug_shiftnum : std_logic_vector(4 downto 0); | |
| 293 | -signal debug_sign_exin : std_logic_vector(10 downto 0); | |
| 294 | -signal debug_serialin : std_logic_vector(16 downto 0); | |
| 295 | -signal debug_vcache_symbit : std_logic_vector(4 downto 0); | |
| 296 | -signal debug_vcache_runlength : std_logic_vector(3 downto 0); | |
| 297 | -signal debug_vcache_valbit : std_logic_vector(3 downto 0); | |
| 298 | -signal debug_va : std_logic; | |
| 299 | -signal debug_fifoready : std_logic; | |
| 279 | +signal debug_vmemaddcnt : std_logic_vector(5 downto 0); | |
| 300 | 280 | |
| 301 | 281 | begin |
| 302 | 282 | ramscan : syncram_2p generic map(tech => memtech, abits => 9, dbits => 32,sepclk => 0) |
| @@ -364,7 +344,6 @@ comb_fetch : process(r, rst, ahbsi, apbi, data_out_fifo, dccachedout, accachedou | ||
| 364 | 344 | variable vint_sercnt : integer; |
| 365 | 345 | variable vshiftout : std_logic_vector(15 downto 0); |
| 366 | 346 | variable vtmpshiftout : std_logic_vector(31 downto 0); |
| 367 | - variable va : std_logic; | |
| 368 | 347 | variable vid : std_logic; |
| 369 | 348 | variable vcompid : std_logic_vector(1 downto 0); |
| 370 | 349 | variable vkstrobe : std_logic; |
| @@ -559,7 +538,6 @@ end if; | ||
| 559 | 538 | else |
| 560 | 539 | vsready := '1'; |
| 561 | 540 | end if; |
| 562 | - debug_fifoready <= vsready; | |
| 563 | 541 | |
| 564 | 542 | vhrdata := vsready & "0000000000000000000000000000000"; |
| 565 | 543 | if(r.hreg.rdscan = '1')then |
| @@ -784,12 +762,10 @@ end if; | ||
| 784 | 762 | end if; |
| 785 | 763 | end if; |
| 786 | 764 | |
| 787 | - -- runlength_keep valbit_keep register calculation | |
| 765 | + -- valbit_keep register calculation | |
| 788 | 766 | if(r.dec_state = serialfinish)then |
| 789 | - v.runlength_keep := vserial_runlength; | |
| 790 | 767 | v.valbit_keep := vserial_valbit; |
| 791 | 768 | elsif(r.dec_state = symcheck)then |
| 792 | - v.runlength_keep := vcache_runlength; | |
| 793 | 769 | v.valbit_keep := vcache_valbit; |
| 794 | 770 | end if; |
| 795 | 771 |
| @@ -815,28 +791,15 @@ end if; | ||
| 815 | 791 | vshiftnum := std_logic_vector(to_unsigned(vintshift,5)); |
| 816 | 792 | |
| 817 | 793 | -- shifter instantiation |
| 818 | -debug_shiftnum <= vshiftnum; | |
| 819 | 794 | vtmpshiftout := std_logic_vector(shift_right(unsigned(r.fetch_reg), vintshift)); |
| 820 | 795 | vshiftout := vtmpshiftout(15 downto 0); |
| 821 | 796 | |
| 822 | --- write memory address generation | |
| 823 | - if (r.dec_state = symcheck and unsigned(vcache_symbit) <= unsigned(r.valuebit) and vcache_symbit /= "00000")then | |
| 824 | - va := '1'; | |
| 825 | - else | |
| 826 | - va := '0'; | |
| 827 | - end if; | |
| 828 | -debug_va <= va; | |
| 829 | -debug_vcache_symbit <= vcache_symbit; | |
| 830 | -debug_vcache_runlength <= vcache_runlength; | |
| 831 | -debug_vcache_valbit <= vcache_valbit; | |
| 832 | - | |
| 833 | --- if((va = '1' or r.dec_state = serialfinish) and r.memaddcnt = "111111")then | |
| 834 | 797 | if(r.dcac = '1')then |
| 835 | 798 | v.memaddcnt := "000000"; |
| 836 | - elsif((va = '1' and vcache_runlength = "0000" and vcache_valbit = "0000") | |
| 799 | + elsif(((r.dec_state = symcheck and unsigned(vcache_symbit) <= unsigned(r.valuebit) and vcache_symbit /= "00000") and vcache_runlength = "0000" and vcache_valbit = "0000") | |
| 837 | 800 | or (r.dec_state = serialfinish and vserial_runlength = "0000" and vserial_valbit = "0000")) then |
| 838 | 801 | v.memaddcnt := "111111"; |
| 839 | - elsif(va = '1')then | |
| 802 | + elsif(r.dec_state = symcheck and unsigned(vcache_symbit) <= unsigned(r.valuebit) and vcache_symbit /= "00000")then | |
| 840 | 803 | v.memaddcnt := r.memaddcnt + vcache_runlength + "0001"; |
| 841 | 804 | elsif(r.dec_state = serialfinish)then |
| 842 | 805 | v.memaddcnt := r.memaddcnt + vserial_runlength + "0001"; |
| @@ -950,7 +913,7 @@ debug_vcache_valbit <= vcache_valbit; | ||
| 950 | 913 | vserial_mask := "01111111111111111"; |
| 951 | 914 | end if; |
| 952 | 915 | vserial_tmpin := ('0' & vshiftout) and vserial_mask; |
| 953 | - debug_serialin <= vserial_tmpin; | |
| 916 | + | |
| 954 | 917 | if(r.dec_state = symcheck or r.dec_state = serialcheck or r.dec_state = serialwait or r.dec_state = serialfinish)then |
| 955 | 918 | vsermaxadd := r.dcac & vid & r.serial_counter; |
| 956 | 919 | end if; |
| @@ -980,7 +943,6 @@ debug_vcache_valbit <= vcache_valbit; | ||
| 980 | 943 | end if; |
| 981 | 944 | |
| 982 | 945 | -- Sign extention & zigzag memory access |
| 983 | - debug_sign_exin <= vshiftout(10 downto 0); | |
| 984 | 946 | vkdata := sign_ex(vshiftout(10 downto 0), r.valbit_keep ); |
| 985 | 947 | if(r.dec_state = valout and r.dcac = '1')then |
| 986 | 948 | if(vcompid = "00")then |
| @@ -1113,13 +1075,11 @@ end if; | ||
| 1113 | 1075 | v.dec_state := standby; |
| 1114 | 1076 | v.fifo_rp := (others => '0'); |
| 1115 | 1077 | v.fifo_wp := (others => '0'); |
| 1116 | - v.counter := (others => '0'); | |
| 1117 | 1078 | v.fetch_reg := (others => '0'); |
| 1118 | 1079 | v.marker_reg := (others => '0'); |
| 1119 | 1080 | v.valuebit := (others => '0'); |
| 1120 | 1081 | v.byteselect := (others => '0'); |
| 1121 | 1082 | v.reqbit_keep := (others => '0'); |
| 1122 | - v.runlength_keep := (others => '0'); | |
| 1123 | 1083 | v.valbit_keep := (others => '0'); |
| 1124 | 1084 | v.dcac := '1'; |
| 1125 | 1085 | v.serial_counter := (others => '0'); |
| @@ -1197,6 +1157,15 @@ end if; | ||
| 1197 | 1157 | kaddress <= r.memaddcnt; |
| 1198 | 1158 | kaddq <= vkaddq; |
| 1199 | 1159 | krdq <= vkrdq; |
| 1160 | + | |
| 1161 | + | |
| 1162 | + | |
| 1163 | +-- Work around for ISE | |
| 1164 | +-- I don't know why ISE can't work correctly without this sentence. | |
| 1165 | +-- Quartus works well without this sentence. | |
| 1166 | + debug_vmemaddcnt <= v.memaddcnt; | |
| 1167 | + | |
| 1168 | + | |
| 1200 | 1169 | end process; |
| 1201 | 1170 | |
| 1202 | 1171 | apbo.pirq <= (others => '0'); |
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