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leon-mjpeg: Commit

motionJPEG play on LEON processor


Commit MetaInfo

Revisionf13704bfeb0748575992042d83ee8b98016fbc53 (tree)
Time2011-02-15 13:18:18
AuthorKenichi Kurimoto <kurimoto12@user...>
CommiterKenichi Kurimoto

Log Message

startgen singal control backport net-mjpeg

Change Summary

Incremental Difference

--- a/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/dctmem2cont.vhd
+++ b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/dctmem2cont.vhd
@@ -46,7 +46,8 @@ entity dctmem2cont is
4646 kready2 : in std_logic;
4747 kstrobe2 : out std_logic;
4848 kdata2 : out std_logic_vector(15 downto 0);
49- error : out std_logic
49+ error : out std_logic;
50+ startgen : in std_logic
5051 );
5152 end;
5253
@@ -78,7 +79,7 @@ begin
7879 yram1 : syncram generic map(tech => memtech, abits => 6, dbits => 16)
7980 port map( clk, m1address, m1datain, m1dataout, m1enable, m1write);
8081
81-comb : process (r, rst, kstrobe1, kdata1, kready2, m0dataout, m1dataout)
82+comb : process (r, rst, kstrobe1, kdata1, kready2, m0dataout, m1dataout, startgen)
8283 variable v : control_reg;
8384 variable vkready1 : std_logic;
8485 variable verror : std_logic;
@@ -202,7 +203,7 @@ comb : process (r, rst, kstrobe1, kdata1, kready2, m0dataout, m1dataout)
202203 end if;
203204
204205 -- reset part
205- if rst = '0' then
206+ if rst = '0' or startgen = '1' then
206207 v.swf := mem0;
207208 v.swb := mem0;
208209 v.mem0state := empty;
--- a/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/huff.vhd
+++ b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/huff.vhd
@@ -181,7 +181,18 @@ begin
181181 tmp := to_integer(signed('0' & data(10 downto 0)));
182182 outb := std_logic_vector(to_signed(tmp, 12));
183183 end if;
184+-- elsif(bitnum = "1100")then
185+-- if(data(11) = '0)then
186+-- tmp := to_integer(signed('1' & data(11 downto 0))) + 1;
187+-- outb := std_logic_vector(to_signed(tmp, 12));
188+-- else
189+-- tmp := to_integer(signed('0' & data(11 downto 0)));
190+-- outb := std_logic_vector(to_signed(tmp, 12));
191+-- end if;
192+-- elsif(bitnum ="0000")then
193+-- outb := (others => '0');
184194 else
195+-- report "sign extention over flow" severity note;
185196 outb := (others => '0');
186197 end if;
187198
@@ -229,11 +240,13 @@ type control_reg is record
229240 hreg : ahbs_reg;
230241 fifo_rp : std_logic_vector(8 downto 0);
231242 fifo_wp : std_logic_vector(8 downto 0);
243+ counter : std_logic_vector(1 downto 0);
232244 fetch_reg : std_logic_vector(31 downto 0);
233245 marker_reg : std_logic_vector(7 downto 0);
234246 valuebit : std_logic_vector(5 downto 0);
235247 byteselect : std_logic_vector(1 downto 0);
236248 reqbit_keep : std_logic_vector(3 downto 0);
249+ runlength_keep : std_logic_vector(3 downto 0);
237250 valbit_keep : std_logic_vector(3 downto 0);
238251 dcac : std_logic;
239252 serial_counter : std_logic_vector(4 downto 0);
@@ -276,7 +289,14 @@ signal servaldin : std_logic_vector(7 downto 0);
276289 signal servaldout : std_logic_vector(7 downto 0);
277290 signal servalen,servalwr : std_logic;
278291
279-signal debug_memaddcnt : std_logic_vector(5 downto 0);
292+signal debug_shiftnum : std_logic_vector(4 downto 0);
293+signal debug_sign_exin : std_logic_vector(10 downto 0);
294+signal debug_serialin : std_logic_vector(16 downto 0);
295+signal debug_vcache_symbit : std_logic_vector(4 downto 0);
296+signal debug_vcache_runlength : std_logic_vector(3 downto 0);
297+signal debug_vcache_valbit : std_logic_vector(3 downto 0);
298+signal debug_va : std_logic;
299+signal debug_fifoready : std_logic;
280300
281301 begin
282302 ramscan : syncram_2p generic map(tech => memtech, abits => 9, dbits => 32,sepclk => 0)
@@ -344,6 +364,7 @@ comb_fetch : process(r, rst, ahbsi, apbi, data_out_fifo, dccachedout, accachedou
344364 variable vint_sercnt : integer;
345365 variable vshiftout : std_logic_vector(15 downto 0);
346366 variable vtmpshiftout : std_logic_vector(31 downto 0);
367+ variable va : std_logic;
347368 variable vid : std_logic;
348369 variable vcompid : std_logic_vector(1 downto 0);
349370 variable vkstrobe : std_logic;
@@ -538,7 +559,7 @@ end if;
538559 else
539560 vsready := '1';
540561 end if;
541-
562+ debug_fifoready <= vsready;
542563
543564 vhrdata := vsready & "0000000000000000000000000000000";
544565 if(r.hreg.rdscan = '1')then
@@ -763,10 +784,12 @@ end if;
763784 end if;
764785 end if;
765786
766- -- valbit_keep register calculation
787+ -- runlength_keep valbit_keep register calculation
767788 if(r.dec_state = serialfinish)then
789+ v.runlength_keep := vserial_runlength;
768790 v.valbit_keep := vserial_valbit;
769791 elsif(r.dec_state = symcheck)then
792+ v.runlength_keep := vcache_runlength;
770793 v.valbit_keep := vcache_valbit;
771794 end if;
772795
@@ -792,15 +815,28 @@ end if;
792815 vshiftnum := std_logic_vector(to_unsigned(vintshift,5));
793816
794817 -- shifter instantiation
818+debug_shiftnum <= vshiftnum;
795819 vtmpshiftout := std_logic_vector(shift_right(unsigned(r.fetch_reg), vintshift));
796820 vshiftout := vtmpshiftout(15 downto 0);
797821
822+-- write memory address generation
823+ if (r.dec_state = symcheck and unsigned(vcache_symbit) <= unsigned(r.valuebit) and vcache_symbit /= "00000")then
824+ va := '1';
825+ else
826+ va := '0';
827+ end if;
828+debug_va <= va;
829+debug_vcache_symbit <= vcache_symbit;
830+debug_vcache_runlength <= vcache_runlength;
831+debug_vcache_valbit <= vcache_valbit;
832+
833+-- if((va = '1' or r.dec_state = serialfinish) and r.memaddcnt = "111111")then
798834 if(r.dcac = '1')then
799835 v.memaddcnt := "000000";
800- elsif(((r.dec_state = symcheck and unsigned(vcache_symbit) <= unsigned(r.valuebit) and vcache_symbit /= "00000") and vcache_runlength = "0000" and vcache_valbit = "0000")
836+ elsif((va = '1' and vcache_runlength = "0000" and vcache_valbit = "0000")
801837 or (r.dec_state = serialfinish and vserial_runlength = "0000" and vserial_valbit = "0000")) then
802838 v.memaddcnt := "111111";
803- elsif(r.dec_state = symcheck and unsigned(vcache_symbit) <= unsigned(r.valuebit) and vcache_symbit /= "00000")then
839+ elsif(va = '1')then
804840 v.memaddcnt := r.memaddcnt + vcache_runlength + "0001";
805841 elsif(r.dec_state = serialfinish)then
806842 v.memaddcnt := r.memaddcnt + vserial_runlength + "0001";
@@ -914,6 +950,7 @@ end if;
914950 vserial_mask := "01111111111111111";
915951 end if;
916952 vserial_tmpin := ('0' & vshiftout) and vserial_mask;
953+ debug_serialin <= vserial_tmpin;
917954 if(r.dec_state = symcheck or r.dec_state = serialcheck or r.dec_state = serialwait or r.dec_state = serialfinish)then
918955 vsermaxadd := r.dcac & vid & r.serial_counter;
919956 end if;
@@ -943,7 +980,7 @@ end if;
943980 end if;
944981
945982 -- Sign extention & zigzag memory access
946- --debug_sign_exin <= vshiftout(10 downto 0);
983+ debug_sign_exin <= vshiftout(10 downto 0);
947984 vkdata := sign_ex(vshiftout(10 downto 0), r.valbit_keep );
948985 if(r.dec_state = valout and r.dcac = '1')then
949986 if(vcompid = "00")then
@@ -1070,15 +1107,19 @@ end if;
10701107 v.hreg.rdoffset := '0';
10711108 v.hreg.getval := '0';
10721109 v.hreg.rdval := '0';
1110+ v.hreg.hselff := '0';
1111+ v.hreg.hreadyff := '0';
10731112 v.fetch_state := memwait;
10741113 v.dec_state := standby;
10751114 v.fifo_rp := (others => '0');
10761115 v.fifo_wp := (others => '0');
1116+ v.counter := (others => '0');
10771117 v.fetch_reg := (others => '0');
10781118 v.marker_reg := (others => '0');
10791119 v.valuebit := (others => '0');
10801120 v.byteselect := (others => '0');
10811121 v.reqbit_keep := (others => '0');
1122+ v.runlength_keep := (others => '0');
10821123 v.valbit_keep := (others => '0');
10831124 v.dcac := '1';
10841125 v.serial_counter := (others => '0');
@@ -1156,13 +1197,6 @@ end if;
11561197 kaddress <= r.memaddcnt;
11571198 kaddq <= vkaddq;
11581199 krdq <= vkrdq;
1159-
1160- -- Workaround for ISE
1161- -- I don't know why ISE needs this.
1162- -- Quartus works correctly without this sentense
1163- debug_memaddcnt <= v.memaddcnt;
1164-
1165-
11661200 end process;
11671201
11681202 apbo.pirq <= (others => '0');
--- /dev/null
+++ b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/huff.vhd.bak
@@ -0,0 +1,1218 @@
1+------------------------------------------------------------------------------
2+-- Copyright (C) 2011, Kenichi Kurimoto
3+--
4+-- This program is free software; you can redistribute it and/or modify
5+-- it under the terms of the GNU General Public License as published by
6+-- the Free Software Foundation; either version 2 of the License, or
7+-- (at your option) any later version.
8+--
9+-- This program is distributed in the hope that it will be useful,
10+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12+-- GNU General Public License for more details.
13+--
14+-- You should have received a copy of the GNU General Public License
15+-- along with this program; if not, write to the Free Software
16+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17+-----------------------------------------------------------------------------
18+-- Entity: huff
19+-- File: huff.vhd
20+-- Author: Kenichi Kurimoto
21+-- Description: AMBA slave interface and huffman decoder for jpeg decode
22+------------------------------------------------------------------------------
23+
24+library ieee;
25+use ieee.std_logic_1164.all;
26+use ieee.numeric_std.all;
27+
28+library grlib;
29+use grlib.amba.all;
30+use grlib.stdlib.all;
31+use grlib.devices.all;
32+
33+library techmap;
34+use techmap.gencomp.all;
35+
36+library kuri;
37+use kuri.mjpeg.all;
38+
39+entity huff is
40+ generic (
41+ memtech : integer := DEFMEMTECH;
42+ shindex : integer := 0;
43+ haddr : integer := 0;
44+ hmask : integer := 16#fff#;
45+ hirq : integer := 0;
46+ pindex : integer := 0;
47+ paddr : integer := 0;
48+ pmask : integer := 16#fff#;
49+ mhindex : integer := 0;
50+ chprot : integer := 3);
51+ port (
52+ rst : in std_ulogic;
53+ clk : in std_ulogic;
54+ ahbsi : in ahb_slv_in_type;
55+ ahbso : out ahb_slv_out_type;
56+ apbi : in apb_slv_in_type;
57+ apbo : out apb_slv_out_type;
58+ kready : in std_logic;
59+ kstrobe : out std_logic;
60+ kdata : out std_logic_vector(11 downto 0);
61+ kaddress : out std_logic_vector(5 downto 0);
62+ jpg_setting : out jpg_set_type;
63+ error : in std_logic_vector(2 downto 0);
64+ startgen : out std_logic;
65+ kstrobeq : out std_logic;
66+ kdataq : out std_logic_vector(7 downto 0);
67+ kaddq : out std_logic_vector(7 downto 0);
68+ krddataq : in std_logic_vector(7 downto 0);
69+ krdq : out std_logic
70+ );
71+end;
72+
73+architecture rtl of huff is
74+
75+constant shconfig : ahb_config_type := (
76+ 0 => ahb_device_reg( VENDOR_CONTRIB, CONTRIB_CORE1, 0, 0, hirq),
77+ 4 => ahb_membar(haddr, '0', '0', hmask),
78+ others => zero32);
79+
80+constant pconfig : apb_config_type := (
81+ 0 => ahb_device_reg( VENDOR_CONTRIB, CONTRIB_CORE1, 0, 0, 0),
82+ 1 => apb_iobar(paddr, pmask));
83+
84+constant fdepth : integer := 512;
85+
86+constant const_4b4 : std_logic_vector(3 downto 0) := "0100";
87+constant const_4b5 : std_logic_vector(3 downto 0) := "0101";
88+constant const_4b6 : std_logic_vector(3 downto 0) := "0110";
89+constant const_6b8 : std_logic_vector(5 downto 0) := "001000";
90+constant const_u6b24 : UNSIGNED(5 downto 0) := "011000";
91+
92+function sign_ex(data, bitnum : std_logic_vector) return std_logic_vector is
93+ variable outb : std_logic_vector(11 downto 0);
94+ variable minusjudge : std_logic;
95+ variable tmp : integer;
96+begin
97+ minusjudge := '0';
98+ if(bitnum = "0001")then
99+ if(data(0) = '0')then
100+ outb := "111111111111";
101+ else
102+ outb := "000000000001";
103+ end if;
104+ elsif(bitnum = "0010")then
105+ if(data(1) = '0')then
106+ tmp := to_integer(signed('1' & data(1 downto 0))) + 1;
107+ outb := std_logic_vector(to_signed(tmp, 12));
108+ else
109+ tmp := to_integer(signed('0' & data(1 downto 0)));
110+ outb := std_logic_vector(to_signed(tmp, 12));
111+ end if;
112+ elsif(bitnum = "0011")then
113+ if(data(2) = '0')then
114+ tmp := to_integer(signed('1' & data(2 downto 0))) + 1;
115+ outb := std_logic_vector(to_signed(tmp, 12));
116+ else
117+ tmp := to_integer(signed('0' & data(2 downto 0)));
118+ outb := std_logic_vector(to_signed(tmp, 12));
119+ end if;
120+ elsif(bitnum = "0100")then
121+ if(data(3) = '0')then
122+ tmp := to_integer(signed('1' & data(3 downto 0))) + 1;
123+ outb := std_logic_vector(to_signed(tmp, 12));
124+ else
125+ tmp := to_integer(signed('0' & data(3 downto 0)));
126+ outb := std_logic_vector(to_signed(tmp, 12));
127+ end if;
128+ elsif(bitnum = "0101")then
129+ if(data(4) = '0')then
130+ tmp := to_integer(signed('1' & data(4 downto 0))) + 1;
131+ outb := std_logic_vector(to_signed(tmp, 12));
132+ else
133+ tmp := to_integer(signed('0' & data(4 downto 0)));
134+ outb := std_logic_vector(to_signed(tmp, 12));
135+ end if;
136+ elsif(bitnum = "0110")then
137+ if(data(5) = '0')then
138+ tmp := to_integer(signed('1' & data(5 downto 0))) + 1;
139+ outb := std_logic_vector(to_signed(tmp, 12));
140+ else
141+ tmp := to_integer(signed('0' & data(5 downto 0)));
142+ outb := std_logic_vector(to_signed(tmp, 12));
143+ end if;
144+ elsif(bitnum = "0111")then
145+ if(data(6) = '0')then
146+ tmp := to_integer(signed('1' & data(6 downto 0))) + 1;
147+ outb := std_logic_vector(to_signed(tmp, 12));
148+ else
149+ tmp := to_integer(signed('0' & data(6 downto 0)));
150+ outb := std_logic_vector(to_signed(tmp, 12));
151+ end if;
152+ elsif(bitnum = "1000")then
153+ if(data(7) = '0')then
154+ tmp := to_integer(signed('1' & data(7 downto 0))) + 1;
155+ outb := std_logic_vector(to_signed(tmp, 12));
156+ else
157+ tmp := to_integer(signed('0' & data(7 downto 0)));
158+ outb := std_logic_vector(to_signed(tmp, 12));
159+ end if;
160+ elsif(bitnum = "1001")then
161+ if(data(8) = '0')then
162+ tmp := to_integer(signed('1' & data(8 downto 0))) + 1;
163+ outb := std_logic_vector(to_signed(tmp, 12));
164+ else
165+ tmp := to_integer(signed('0' & data(8 downto 0)));
166+ outb := std_logic_vector(to_signed(tmp, 12));
167+ end if;
168+ elsif(bitnum = "1010")then
169+ if(data(9) = '0')then
170+ tmp := to_integer(signed('1' & data(9 downto 0))) + 1;
171+ outb := std_logic_vector(to_signed(tmp, 12));
172+ else
173+ tmp := to_integer(signed('0' & data(9 downto 0)));
174+ outb := std_logic_vector(to_signed(tmp, 12));
175+ end if;
176+ elsif(bitnum = "1011")then
177+ if(data(10) = '0')then
178+ tmp := to_integer(signed('1' & data(10 downto 0))) + 1;
179+ outb := std_logic_vector(to_signed(tmp, 12));
180+ else
181+ tmp := to_integer(signed('0' & data(10 downto 0)));
182+ outb := std_logic_vector(to_signed(tmp, 12));
183+ end if;
184+-- elsif(bitnum = "1100")then
185+-- if(data(11) = '0)then
186+-- tmp := to_integer(signed('1' & data(11 downto 0))) + 1;
187+-- outb := std_logic_vector(to_signed(tmp, 12));
188+-- else
189+-- tmp := to_integer(signed('0' & data(11 downto 0)));
190+-- outb := std_logic_vector(to_signed(tmp, 12));
191+-- end if;
192+-- elsif(bitnum ="0000")then
193+-- outb := (others => '0');
194+ else
195+-- report "sign extention over flow" severity note;
196+ outb := (others => '0');
197+ end if;
198+
199+ return(outb);
200+end;
201+
202+type fstate_type is (memwait, bytefetch, ffmemwait, ffcheck, markermode);
203+type dstate_type is (symreq, symcheck, valout, symng, symokvalng, serialwait, serialcheck, serialfinish, standby);
204+
205+type ahbs_reg is record
206+ getscan : std_logic;
207+ rdscan : std_logic;
208+ getq : std_logic;
209+ rdq : std_logic;
210+ getcache : std_logic;
211+ rdacache : std_logic;
212+ rddcache : std_logic;
213+ getmax : std_logic;
214+ rdmax : std_logic;
215+ getoffset : std_logic;
216+ rdoffset : std_logic;
217+ getval : std_logic;
218+ rdval : std_logic;
219+ hreadyff : std_logic;
220+ hselff : std_logic;
221+ haddkeep : std_logic_vector(15 downto 0);
222+end record;
223+
224+type apbs_reg is record
225+ sampf : std_logic;
226+ xmcumax : std_logic_vector(5 downto 0);
227+ ymcumax : std_logic_vector(4 downto 0);
228+ incaddy : std_logic_vector(15 downto 0);
229+ incaddmcux : std_logic_vector(15 downto 0);
230+ incaddmcuy : std_logic_vector(10 downto 0);
231+ fbstartadd : std_logic_vector(31 downto 0);
232+ through_bit : std_logic;
233+ hardonly : std_logic;
234+end record;
235+
236+type control_reg is record
237+ fetch_state : fstate_type;
238+ dec_state : dstate_type;
239+ preg : apbs_reg;
240+ hreg : ahbs_reg;
241+ fifo_rp : std_logic_vector(8 downto 0);
242+ fifo_wp : std_logic_vector(8 downto 0);
243+-- counter : std_logic_vector(1 downto 0);
244+ fetch_reg : std_logic_vector(31 downto 0);
245+ marker_reg : std_logic_vector(7 downto 0);
246+ valuebit : std_logic_vector(5 downto 0);
247+ byteselect : std_logic_vector(1 downto 0);
248+ reqbit_keep : std_logic_vector(3 downto 0);
249+-- runlength_keep : std_logic_vector(3 downto 0);
250+ valbit_keep : std_logic_vector(3 downto 0);
251+ dcac : std_logic;
252+ serial_counter : std_logic_vector(4 downto 0);
253+ idcounter : std_logic_vector(3 downto 0);
254+ memaddcnt : std_logic_vector(5 downto 0);
255+ lastdc0 : std_logic_vector(11 downto 0);
256+ lastdc1 : std_logic_vector(11 downto 0);
257+ lastdc2 : std_logic_vector(11 downto 0);
258+ byte3keep : std_logic_vector(23 downto 0);
259+ cntdown : std_logic;
260+ capture : std_logic_vector(1 downto 0);
261+ skipcnt : std_logic_vector(15 downto 0);
262+end record;
263+
264+signal r, rin : control_reg;
265+signal read_en_fifo, write_en_fifo : std_logic;
266+signal read_pointer_fifo : std_logic_vector(8 downto 0);
267+signal write_pointer_fifo : std_logic_vector(8 downto 0);
268+signal data_out_fifo : std_logic_vector(31 downto 0);
269+signal data_in_fifo : std_logic_vector(31 downto 0);
270+
271+signal dccacheadd : std_logic_vector(9 downto 0);
272+signal dccachedin : std_logic_vector(7 downto 0);
273+signal dccachedout : std_logic_vector(7 downto 0);
274+signal dccacheen,dccachewr : std_logic;
275+signal accacheadd : std_logic_vector(9 downto 0);
276+signal accachedin : std_logic_vector(11 downto 0);
277+signal accachedout : std_logic_vector(11 downto 0);
278+signal accacheen,accachewr : std_logic;
279+signal sermaxadd : std_logic_vector(6 downto 0);
280+signal sermaxdin : std_logic_vector(16 downto 0);
281+signal sermaxdout : std_logic_vector(16 downto 0);
282+signal sermaxen,sermaxwr : std_logic;
283+signal seroffadd : std_logic_vector(6 downto 0);
284+signal seroffdin : std_logic_vector(16 downto 0);
285+signal seroffdout : std_logic_vector(16 downto 0);
286+signal seroffen,seroffwr : std_logic;
287+signal servaladd : std_logic_vector(9 downto 0);
288+signal servaldin : std_logic_vector(7 downto 0);
289+signal servaldout : std_logic_vector(7 downto 0);
290+signal servalen,servalwr : std_logic;
291+
292+signal debug_shiftnum : std_logic_vector(4 downto 0);
293+signal debug_sign_exin : std_logic_vector(10 downto 0);
294+signal debug_serialin : std_logic_vector(16 downto 0);
295+signal debug_vcache_symbit : std_logic_vector(4 downto 0);
296+signal debug_vcache_runlength : std_logic_vector(3 downto 0);
297+signal debug_vcache_valbit : std_logic_vector(3 downto 0);
298+signal debug_va : std_logic;
299+signal debug_fifoready : std_logic;
300+
301+begin
302+ ramscan : syncram_2p generic map(tech => memtech, abits => 9, dbits => 32,sepclk => 0)
303+ port map( clk, read_en_fifo, read_pointer_fifo, data_out_fifo,
304+ clk, write_en_fifo, write_pointer_fifo, data_in_fifo);
305+ huffdccache : syncram generic map(tech => memtech, abits => 10, dbits => 8)
306+ port map( clk, dccacheadd, dccachedin, dccachedout, dccacheen, dccachewr);
307+ huffaccache : syncram generic map(tech => memtech, abits => 10, dbits => 12)
308+ port map( clk, accacheadd, accachedin, accachedout, accacheen, accachewr);
309+ serialmax : syncram generic map(tech => memtech, abits => 7, dbits => 17)
310+ port map( clk, sermaxadd, sermaxdin, sermaxdout, sermaxen, sermaxwr);
311+ serialoffset : syncram generic map(tech => memtech, abits => 7, dbits => 17)
312+ port map( clk, seroffadd, seroffdin, seroffdout, seroffen, seroffwr);
313+ serialval : syncram generic map(tech => memtech, abits => 10, dbits => 8)
314+ port map( clk, servaladd, servaldin, servaldout, servalen, servalwr);
315+
316+
317+comb_fetch : process(r, rst, ahbsi, apbi, data_out_fifo, dccachedout, accachedout, sermaxdout, seroffdout, servaldout, kready, error, krddataq)
318+ variable v : control_reg;
319+ variable virq : std_logic_vector(NAHBIRQ-1 downto 0);
320+ variable vsready : std_logic;
321+ variable write_point : integer;
322+ variable read_point : integer;
323+ variable num_ele : integer;
324+ variable apbwrite : std_logic;
325+ variable vprdata : std_logic_vector(31 downto 0);
326+ variable vhrdata : std_logic_vector(31 downto 0);
327+ variable vwriting :std_logic;
328+ variable vreading : std_logic;
329+ variable vdccacheadd : std_logic_vector(9 downto 0);
330+ variable vdccachewr : std_logic;
331+ variable vaccacheadd : std_logic_vector(9 downto 0);
332+ variable vaccachewr : std_logic;
333+ variable vsermaxadd : std_logic_vector(6 downto 0);
334+ variable vsermaxwr : std_logic;
335+ variable vseroffadd : std_logic_vector(6 downto 0);
336+ variable vseroffwr : std_logic;
337+ variable vservaladd : std_logic_vector(9 downto 0);
338+ variable vservalwr : std_logic;
339+
340+ variable vbytedata : std_logic_vector(7 downto 0);
341+ variable vinsertdata : std_logic_vector(7 downto 0);
342+ variable vbyte0, vbyte1, vbyte2, vbyte3 : std_logic_vector(7 downto 0);
343+ variable vfetching : std_logic;
344+
345+ variable vcache_symbit : std_logic_vector(4 downto 0);
346+ variable vcache_runlength : std_logic_vector(3 downto 0);
347+ variable vcache_valbit : std_logic_vector(3 downto 0);
348+
349+ variable vint_plusv : integer;
350+ variable vint_minusv : integer;
351+
352+ variable vserial_symbit : std_logic_vector(4 downto 0);
353+ variable vserial_runlength : std_logic_vector(3 downto 0);
354+ variable vserial_valbit : std_logic_vector(3 downto 0);
355+ variable vserial_tmpin : std_logic_vector(16 downto 0);
356+ variable vserial_mask : std_logic_vector(16 downto 0);
357+ variable vserial_judge : std_logic;
358+ variable vserial_tmpadd : std_logic_vector(16 downto 0);
359+
360+ variable vintshift : integer;
361+ variable vshiftnum : std_logic_vector(4 downto 0);
362+ variable vint_valuebit : integer;
363+ variable vint_valbkp : integer;
364+ variable vint_sercnt : integer;
365+ variable vshiftout : std_logic_vector(15 downto 0);
366+ variable vtmpshiftout : std_logic_vector(31 downto 0);
367+-- variable va : std_logic;
368+ variable vid : std_logic;
369+ variable vcompid : std_logic_vector(1 downto 0);
370+ variable vkstrobe : std_logic;
371+ variable vkdata : std_logic_vector(11 downto 0);
372+ variable vint_csymbit : integer;
373+ variable vint_reqbitkp : integer;
374+ variable vint_cvalbit : integer;
375+ variable vint_sersym : integer;
376+ variable vint_serval : integer;
377+
378+ variable vkaddq : std_logic_vector(7 downto 0);
379+ variable vkrdq : std_logic;
380+ variable vgetbyte : std_logic;
381+ variable vstartgen : std_logic;
382+ begin
383+
384+ v := r;
385+ virq := (others => '0');
386+ vdccachewr := '0'; vdccacheadd := (others => '0');
387+ vaccachewr := '0'; vaccacheadd := (others => '0');
388+ vsermaxwr := '0'; vsermaxadd := (others => '0');
389+ vseroffwr := '0'; vseroffadd := (others => '0');
390+ vservalwr := '0'; vservaladd := (others => '0');
391+ vkaddq := (others => '0'); vkrdq := '0';
392+ vserial_judge := '0';
393+ vkstrobe := '0'; vstartgen := '0';
394+
395+-- apb controle part
396+ apbwrite := apbi.psel(pindex) and apbi.pwrite and apbi.penable;
397+ vprdata := (others => '0');
398+ case apbi.paddr(5 downto 2) is
399+ when "0000" =>
400+ if apbwrite = '1' then
401+ v.preg.fbstartadd := apbi.pwdata(31 downto 0);
402+ end if;
403+ vprdata := r.preg.fbstartadd(31 downto 0);
404+ when "0001" =>
405+ if apbwrite = '1' then
406+ v.preg.sampf := apbi.pwdata(22);
407+ v.preg.ymcumax := apbi.pwdata(21 downto 17);
408+ v.preg.xmcumax := apbi.pwdata(16 downto 11);
409+ v.preg.incaddmcuy := apbi.pwdata(10 downto 0);
410+ end if;
411+ vprdata := "000000000" & r.preg.sampf & r.preg.ymcumax & r.preg.xmcumax & r.preg.incaddmcuy;
412+ when "0010" =>
413+ if apbwrite = '1' then
414+ v.preg.incaddy := apbi.pwdata(31 downto 16);
415+ v.preg.incaddmcux := apbi.pwdata(15 downto 0);
416+ end if;
417+ vprdata := r.preg.incaddy & r.preg.incaddmcux;
418+ when "0011" =>
419+ if apbwrite = '1' then
420+ if apbi.pwdata(31) = '1' then
421+ vstartgen := '1';
422+ end if;
423+ v.preg.through_bit := apbi.pwdata(15);
424+ v.preg.hardonly := apbi.pwdata(14);
425+ v.marker_reg := apbi.pwdata(23 downto 16);
426+ end if;
427+ vprdata := "00000000" & r.marker_reg & r.preg.through_bit & r.preg.hardonly &"00000000000000" ;
428+ when others =>
429+ end case;
430+
431+if(r.hreg.getcache = '1' or r.hreg.hreadyff = '0')then
432+ if (r.hreg.haddkeep(15) = '1') then
433+ vdccachewr := '1';
434+ vdccacheadd := r.hreg.haddkeep(11 downto 2);
435+ else
436+ vaccachewr := '1';
437+ vaccacheadd := r.hreg.haddkeep(11 downto 2);
438+ end if;
439+else
440+ vdccacheadd := ahbsi.haddr(11 downto 2);
441+ vaccacheadd := ahbsi.haddr(11 downto 2);
442+end if;
443+if(r.hreg.getq = '1' or r.hreg.hreadyff = '0')then
444+ vkaddq := r.hreg.haddkeep(9 downto 2);
445+else
446+ vkaddq := ahbsi.haddr(9 downto 2);
447+ vkrdq := '1';
448+end if;
449+if(r.hreg.getmax = '1' or r.hreg.hreadyff = '0')then
450+ vsermaxwr := '1';
451+ vsermaxadd := r.hreg.haddkeep(8 downto 2);
452+else
453+ vsermaxadd := ahbsi.haddr(8 downto 2);
454+end if;
455+if(r.hreg.getoffset = '1' or r.hreg.hreadyff = '0')then
456+ vseroffwr := '1';
457+ vseroffadd := r.hreg.haddkeep(8 downto 2);
458+else
459+ vseroffadd := ahbsi.haddr(8 downto 2);
460+end if;
461+if(r.hreg.getval = '1' or r.hreg.hreadyff = '0')then
462+ vservalwr := '1';
463+ vservaladd := r.hreg.haddkeep(11 downto 2);
464+else
465+ vservaladd := ahbsi.haddr(11 downto 2);
466+end if;
467+
468+if(ahbsi.hready = '1' ) then
469+ v.hreg.getscan := '0';
470+ v.hreg.rdscan := '0';
471+ v.hreg.getq := '0';
472+ v.hreg.rdq := '0';
473+ v.hreg.getcache := '0';
474+ v.hreg.rdacache := '0';
475+ v.hreg.rddcache := '0';
476+ v.hreg.getmax := '0';
477+ v.hreg.rdmax := '0';
478+ v.hreg.getoffset := '0';
479+ v.hreg.rdoffset := '0';
480+ v.hreg.getval := '0';
481+ v.hreg.rdval := '0';
482+
483+ v.hreg.hselff := ahbsi.hsel(shindex) and ahbsi.htrans(1);
484+ vwriting := ahbsi.hwrite and v.hreg.hselff;
485+ vreading := (not ahbsi.hwrite) and v.hreg.hselff;
486+ if(ahbsi.haddr(19 downto 8) = "000000000000")then
487+ if(vwriting = '1')then
488+ v.hreg.getscan := '1';
489+ elsif(vreading = '1')then
490+ v.hreg.rdscan := '1';
491+ end if;
492+ end if;
493+ if(ahbsi.haddr(15 downto 12) = "1100" )then
494+ if(vwriting = '1')then
495+ v.hreg.getq := '1';
496+ elsif(vreading = '1')then
497+ v.hreg.rdq := '1';
498+ end if;
499+ end if;
500+ if(ahbsi.haddr(15 downto 12) = "0100" or ahbsi.haddr(15 downto 12) = "0101")then
501+ if(vwriting = '1')then
502+ v.hreg.getcache := '1';
503+ elsif(vreading = '1')then
504+ v.hreg.rdacache := '1';
505+ end if;
506+ end if;
507+ if(ahbsi.haddr(15 downto 12) = "1000" or ahbsi.haddr(15 downto 12) = "1001")then
508+ if(vwriting = '1')then
509+ v.hreg.getcache := '1';
510+ elsif(vreading = '1')then
511+ v.hreg.rddcache := '1';
512+ end if;
513+ end if;
514+ if(ahbsi.haddr(15 downto 10) = "000001")then
515+ if(vwriting = '1')then
516+ v.hreg.getmax := '1';
517+ elsif(vreading = '1')then
518+ v.hreg.rdmax := '1';
519+ end if;
520+ end if;
521+ if(ahbsi.haddr(15 downto 10) = "000010")then
522+ if(vwriting = '1')then
523+ v.hreg.getoffset := '1';
524+ elsif(vreading = '1')then
525+ v.hreg.rdoffset := '1';
526+ end if;
527+ end if;
528+ if(ahbsi.haddr(15 downto 13) = "001")then
529+ if(vwriting = '1')then
530+ v.hreg.getval := '1';
531+ elsif(vreading = '1')then
532+ v.hreg.rdval := '1';
533+ end if;
534+ end if;
535+ v.hreg.haddkeep := ahbsi.haddr(15 downto 0);
536+end if;
537+
538+if( v.hreg.getscan = '1' or v.hreg.getq = '1' or v.hreg.getcache = '1'
539+ or v.hreg.getmax = '1' or v.hreg.getoffset = '1' or v.hreg.getval = '1')then
540+ v.hreg.hreadyff := not(v.hreg.hselff and not ahbsi.hwrite);
541+ v.hreg.getscan := v.hreg.getscan and v.hreg.hreadyff;
542+ v.hreg.getq := v.hreg.getq and v.hreg.hreadyff;
543+ v.hreg.getcache := v.hreg.getcache and v.hreg.hreadyff;
544+ v.hreg.getmax := v.hreg.getmax and v.hreg.hreadyff;
545+ v.hreg.getoffset := v.hreg.getoffset and v.hreg.hreadyff;
546+ v.hreg.getval := v.hreg.getval and v.hreg.hreadyff;
547+end if;
548+
549+-- FIFO # of element calculation
550+ write_point := to_integer(unsigned(r.fifo_wp));
551+ read_point := to_integer(unsigned(r.fifo_rp));
552+ if (write_point >= read_point) then
553+ num_ele := write_point - read_point;
554+ else
555+ num_ele := fdepth - read_point + write_point;
556+ end if;
557+ if num_ele > fdepth/2 then
558+ vsready := '0';
559+ else
560+ vsready := '1';
561+ end if;
562+ debug_fifoready <= vsready;
563+
564+ vhrdata := vsready & "0000000000000000000000000000000";
565+ if(r.hreg.rdscan = '1')then
566+ vhrdata := data_out_fifo;
567+ elsif(r.hreg.rdq ='1')then
568+ vhrdata := "000000000000000000000000" &krddataq;
569+ elsif(r.hreg.rdacache = '1')then
570+ vhrdata := "00000000000000000000" & accachedout;
571+ elsif(r.hreg.rddcache = '1')then
572+ vhrdata := "000000000000000000000000" & dccachedout;
573+ elsif(r.hreg.rdmax = '1')then
574+ vhrdata := "000000000000000" & sermaxdout;
575+ elsif(r.hreg.rdoffset = '1')then
576+ vhrdata := "000000000000000" & seroffdout;
577+ elsif(r.hreg.rdval = '1')then
578+ vhrdata := "000000000000000000000000" & servaldout;
579+ end if;
580+
581+--FIFO writing
582+ if r.hreg.getscan = '1' then
583+ write_point := write_point + 1;
584+ if write_point = fdepth then
585+ write_point := 0;
586+ end if;
587+ end if;
588+ v.fifo_wp := std_logic_vector(to_unsigned(write_point,9));
589+
590+--FIFO reading
591+ if((r.fetch_state = bytefetch and r.byteselect = "00" and num_ele >= 1 and unsigned(r.valuebit)<= const_u6b24)
592+ or (r.fetch_state = ffcheck and r.byteselect = "00" and num_ele >= 1 and unsigned(r.valuebit)<= const_u6b24)) then
593+ read_point := read_point + 1;
594+ if read_point = fdepth then
595+ read_point := 0;
596+ end if;
597+ v.byte3keep(23 downto 0) := data_out_fifo(23 downto 0);
598+ end if;
599+ v.fifo_rp := std_logic_vector(to_unsigned(read_point,9));
600+
601+-- byte select from FIFO output
602+ if(r.byteselect = "00") then
603+ vbytedata := data_out_fifo(31 downto 24);
604+ elsif(r.byteselect = "01") then
605+ vbytedata := r.byte3keep(23 downto 16);
606+ elsif(r.byteselect = "10") then
607+ vbytedata := r.byte3keep(15 downto 8);
608+ else
609+ vbytedata := r.byte3keep(7 downto 0);
610+ end if;
611+
612+ vgetbyte := '0';
613+ if((r.fetch_state = bytefetch and unsigned(r.valuebit) <= const_u6b24 )
614+ or (r.fetch_state = ffcheck and unsigned(r.valuebit) <= const_u6b24))then
615+ v.byteselect := v.byteselect + 1;
616+ vgetbyte := '1';
617+ end if;
618+
619+--data FF
620+ if(r.fetch_state = ffcheck) then
621+ vinsertdata := "11111111";
622+ else
623+ vinsertdata := vbytedata;
624+ end if;
625+
626+-- byte fetching to 32bit fetch_register
627+ if( (r.fetch_state = bytefetch and vbytedata /= "11111111" and unsigned(r.valuebit) <= const_u6b24 and r.preg.through_bit = '0' )
628+ or (r.fetch_state = ffcheck and vbytedata = "00000000" and unsigned(r.valuebit) <= const_u6b24 and r.preg.through_bit = '0')) then
629+ vfetching := '1';
630+ else
631+ vfetching := '0';
632+ end if;
633+
634+ if(vfetching = '1') then
635+ vbyte0 := vinsertdata;
636+ vbyte1 := r.fetch_reg(7 downto 0);
637+ vbyte2 := r.fetch_reg(15 downto 8);
638+ vbyte3 := r.fetch_reg(23 downto 16);
639+ else
640+ vbyte0 := r.fetch_reg(7 downto 0);
641+ vbyte1 := r.fetch_reg(15 downto 8);
642+ vbyte2 := r.fetch_reg(23 downto 16);
643+ vbyte3 := r.fetch_reg(31 downto 24);
644+ end if;
645+ v.fetch_reg := vbyte3 & vbyte2 & vbyte1 & vbyte0;
646+
647+-- Marker register
648+ if(r.fetch_state = ffcheck and vbytedata /= "00000000" and r.preg.through_bit = '0') then
649+ v.marker_reg := vbytedata;
650+ end if;
651+ if(r.marker_reg /= "00000000")then
652+ virq(hirq) := '1';
653+ end if;
654+
655+-- Through bit & skip counter calculation
656+-- This part is for "motion"-JPEG".
657+-- It's not beautiful implementation, but.....
658+ if(r.fetch_state = ffcheck and r.preg.through_bit = '1' and vbytedata = "11011010")then
659+ v.cntdown := '1';
660+ v.capture := "10";
661+ end if;
662+ if(r.capture = "10")then
663+ v.skipcnt(15 downto 8) := vbytedata;
664+ end if;
665+ if(r.capture = "01")then
666+ v.skipcnt(7 downto 0) := vbytedata;
667+ end if;
668+ if(r.cntdown = '1' and vgetbyte = '1')then
669+ if(r.capture = "10")then
670+ v.capture := "01";
671+ end if;
672+ if(r.capture = "01")then
673+ v.capture := "00";
674+ end if;
675+ if(r.capture = "00")then
676+ v.skipcnt := r.skipcnt - 1;
677+ end if;
678+ if(r.skipcnt = "0000000000000011")then
679+ v.preg.through_bit := '0';
680+ v.cntdown := '0';
681+ v.skipcnt := (others => '0');
682+ end if;
683+ end if;
684+
685+-- State machine transition (fetch part)
686+ case r.fetch_state is
687+ when memwait =>
688+ if (num_ele /= 0 and unsigned(r.valuebit) <= const_u6b24) then
689+ v.fetch_state := bytefetch;
690+ end if;
691+ when bytefetch =>
692+ if(r.byteselect = "11" and unsigned(r.valuebit) <= const_u6b24 and num_ele = 0 and vbytedata /= "11111111") then
693+ v.fetch_state := memwait;
694+ elsif( vbytedata = "11111111" and r.byteselect = "11" and num_ele = 0 and unsigned(r.valuebit) <= const_u6b24) then
695+ v.fetch_state := ffmemwait;
696+ elsif( vbytedata = "11111111" and unsigned(r.valuebit) <= const_u6b24 and (r.byteselect /= "11" or (r.byteselect = "11" and num_ele /= 0))) then
697+ v.fetch_state := ffcheck;
698+ end if;
699+ when ffmemwait =>
700+ if(num_ele /= 0) then
701+ v.fetch_state := ffcheck;
702+ end if;
703+ when ffcheck =>
704+ if( (vbytedata = "00000000" and unsigned(r.valuebit) <=const_u6b24 and (r.byteselect /= "11" or num_ele /= 0))
705+ or (r.preg.through_bit = '1' and unsigned(r.valuebit)<=const_u6b24 and (r.byteselect /= "11" or num_ele /= 0) )) then
706+ v.fetch_state := bytefetch;
707+ elsif( (vbytedata = "00000000" and unsigned(r.valuebit)<=const_u6b24 and (r.byteselect = "11" and num_ele = 0))
708+ or( r.preg.through_bit = '1' and unsigned(r.valuebit)<=const_u6b24 and r.byteselect = "11" and num_ele = 0 )) then
709+ v.fetch_state := memwait;
710+ elsif ( vbytedata /= "00000000") then
711+ v.fetch_state := markermode;
712+ end if;
713+ when markermode =>
714+ if(r.marker_reg = "00000000" and (r.byteselect /= "11" or( r.byteselect = "11" and num_ele /= 0))) then
715+ v.fetch_state := bytefetch;
716+ elsif(r.marker_reg = "00000000" and (r.byteselect = "11" and num_ele =0)) then
717+ v.fetch_state := memwait;
718+ end if;
719+ if(r.preg.hardonly = '1' and r.marker_reg = x"D9")then
720+ if(r.byteselect /= "11" or( r.byteselect = "11" and num_ele /= 0))then
721+ v.marker_reg := "00000000";
722+ v.preg.through_bit := '1';
723+ elsif(r.byteselect = "11" and num_ele =0)then
724+ v.marker_reg := "00000000";
725+ v.preg.through_bit := '1';
726+ end if;
727+ end if;
728+ when others =>
729+ end case;
730+
731+ -- cache, serial mem output
732+ if(r.dcac = '1') then
733+ vcache_symbit := "0" & dccachedout(7 downto 4);
734+ vcache_valbit := dccachedout(3 downto 0);
735+ vcache_runlength := "0000";
736+ else
737+ vcache_symbit := "0" & accachedout(11 downto 8);
738+ vcache_runlength := accachedout(7 downto 4);
739+ vcache_valbit := accachedout(3 downto 0);
740+ end if;
741+ vserial_symbit := r.serial_counter - "00010";
742+ vserial_runlength := servaldout(7 downto 4);
743+ vserial_valbit := servaldout(3 downto 0);
744+
745+ -- valuebit calculation
746+ if(vfetching = '1') then
747+ vint_plusv := 8;
748+ else
749+ vint_plusv := 0;
750+ end if;
751+ if(r.dec_state = symcheck) then
752+ if(unsigned(r.reqbit_keep) >= unsigned(vcache_symbit) )then
753+ vint_minusv := to_integer(unsigned(vcache_symbit));
754+ else
755+ vint_minusv := 0;
756+ end if;
757+ elsif(r.dec_state = serialfinish) then
758+ vint_minusv := to_integer(unsigned(vserial_symbit));
759+ elsif(r.dec_state = valout) then
760+ vint_minusv := to_integer(unsigned(r.valbit_keep));
761+ else
762+ vint_minusv := 0;
763+ end if;
764+
765+ v.valuebit := std_logic_vector(to_unsigned((to_integer(unsigned(r.valuebit)) + vint_plusv - vint_minusv), 6));
766+
767+ -- Padding bit for Markers
768+ if(r.fetch_state = markermode or r.preg.through_bit = '1') then
769+ if((r.valuebit = "000001" and r.fetch_reg(0) = '1')
770+ or (r.valuebit = "000010" and r.fetch_reg(1 downto 0) = "11")
771+ or (r.valuebit = "000011" and r.fetch_reg(2 downto 0) = "111")
772+ or (r.valuebit = "000100" and r.fetch_reg(3 downto 0) = "1111")
773+ or (r.valuebit = "000101" and r.fetch_reg(4 downto 0) = "11111")
774+ or (r.valuebit = "000110" and r.fetch_reg(5 downto 0) = "111111")
775+ or (r.valuebit = "000111" and r.fetch_reg(6 downto 0) = "1111111")) then
776+ v.valuebit := "000000";
777+ end if;
778+ end if;
779+ if(r.dec_state = symreq)then
780+ if(r.valuebit >= const_6b8)then
781+ v.reqbit_keep := "1000";
782+ else
783+ v.reqbit_keep := r.valuebit(3 downto 0);
784+ end if;
785+ end if;
786+
787+ -- runlength_keep valbit_keep register calculation
788+ if(r.dec_state = serialfinish)then
789+ -- v.runlength_keep := vserial_runlength;
790+ v.valbit_keep := vserial_valbit;
791+ elsif(r.dec_state = symcheck)then
792+ -- v.runlength_keep := vcache_runlength;
793+ v.valbit_keep := vcache_valbit;
794+ end if;
795+
796+ -- shiftnum calculation
797+ vint_valuebit := to_integer(unsigned(r.valuebit));
798+ vint_valbkp := to_integer(unsigned(r.valbit_keep));
799+ vint_sercnt := to_integer(unsigned(r.serial_counter));
800+ vintshift := 0;
801+
802+ if(r.dec_state = symreq)then
803+ if(vint_valuebit >= 8)then
804+ vintshift := vint_valuebit - 8;
805+ else
806+ vintshift := 0;
807+ end if;
808+ elsif(r.dec_state = valout)then
809+ vintshift := vint_valuebit - vint_valbkp;
810+ elsif(r.dec_state = serialcheck)then
811+ vintshift := 1 + vint_valuebit - vint_sercnt;
812+ elsif(r.dec_state = serialwait)then
813+ vintshift := 1 + vint_valuebit - vint_sercnt;
814+ end if;
815+ vshiftnum := std_logic_vector(to_unsigned(vintshift,5));
816+
817+-- shifter instantiation
818+debug_shiftnum <= vshiftnum;
819+ vtmpshiftout := std_logic_vector(shift_right(unsigned(r.fetch_reg), vintshift));
820+ vshiftout := vtmpshiftout(15 downto 0);
821+
822+-- write memory address generation
823+-- if (r.dec_state = symcheck and unsigned(vcache_symbit) <= unsigned(r.valuebit) and vcache_symbit /= "00000")then
824+-- va := '1';
825+-- else
826+-- va := '0';
827+-- end if;
828+--debug_va <= va;
829+--debug_vcache_symbit <= vcache_symbit;
830+--debug_vcache_runlength <= vcache_runlength;
831+--debug_vcache_valbit <= vcache_valbit;
832+
833+
834+ if(r.dcac = '1')then
835+ v.memaddcnt := "000000";
836+ elsif(((r.dec_state = symcheck and unsigned(vcache_symbit) <= unsigned(r.valuebit) and vcache_symbit /= "00000") and vcache_runlength = "0000" and vcache_valbit = "0000")
837+ or (r.dec_state = serialfinish and vserial_runlength = "0000" and vserial_valbit = "0000")) then
838+ v.memaddcnt := "111111";
839+ elsif(r.dec_state = symcheck and unsigned(vcache_symbit) <= unsigned(r.valuebit) and vcache_symbit /= "00000")then
840+ v.memaddcnt := r.memaddcnt + vcache_runlength + "0001";
841+ elsif(r.dec_state = serialfinish)then
842+ v.memaddcnt := r.memaddcnt + vserial_runlength + "0001";
843+ end if;
844+
845+-- id, dcac calculation
846+ if(r.dec_state = valout and r.memaddcnt = "000000")then
847+ v.dcac := '0';
848+ elsif(r.dec_state = valout and r.memaddcnt = "111111") then
849+ v.dcac := '1';
850+ end if;
851+
852+ if(r.dec_state = valout and r.memaddcnt = "111111") then
853+ v.idcounter := r.idcounter + '1';
854+ if(r.preg.sampf = '0')then
855+ if(v.idcounter = "0110")then
856+ v.idcounter := "0000";
857+ end if;
858+ else
859+ if(v.idcounter = "1000")then
860+ v.idcounter := "0000";
861+ end if;
862+ end if;
863+ end if;
864+ if(r.preg.sampf = '0')then
865+ if(r.idcounter < const_4b4 )then
866+ vid := '0';
867+ vcompid := "00";
868+ elsif(r.idcounter < const_4b5)then
869+ vid := '1';
870+ vcompid := "01";
871+ else
872+ vid := '1';
873+ vcompid := "10";
874+ end if;
875+ else
876+ if(r.idcounter < const_4b4)then
877+ vid := '0';
878+ vcompid := "00";
879+ elsif(r.idcounter < const_4b6)then
880+ vid := '1';
881+ vcompid := "01";
882+ else
883+ vid := '1';
884+ vcompid := "10";
885+ end if;
886+ end if;
887+
888+-- cache access
889+ if(r.dec_state = symreq)then
890+ if(r.dcac = '1')then
891+ if(vint_valuebit >7)then
892+ vdccacheadd := vid & '0' & vshiftout(7 downto 0);
893+ elsif(vint_valuebit = 7)then
894+ vdccacheadd := vid & "10" & vshiftout(6 downto 0);
895+ elsif(vint_valuebit = 6)then
896+ vdccacheadd := vid & "110" & vshiftout(5 downto 0);
897+ elsif(vint_valuebit = 5)then
898+ vdccacheadd := vid & "1110" & vshiftout(4 downto 0);
899+ elsif(vint_valuebit = 4)then
900+ vdccacheadd := vid & "11110" & vshiftout(3 downto 0);
901+ elsif(vint_valuebit = 3)then
902+ vdccacheadd := vid & "111110" & vshiftout(2 downto 0);
903+ elsif(vint_valuebit = 2)then
904+ vdccacheadd := vid & "1111110" & vshiftout(1 downto 0);
905+ elsif(vint_valuebit = 1)then
906+ vdccacheadd := vid & "11111110" & vshiftout(0);
907+ end if;
908+ vdccachewr := '0';
909+ else
910+ if(vint_valuebit >7)then
911+ vaccacheadd := vid & '0' & vshiftout(7 downto 0);
912+ elsif(vint_valuebit = 7)then
913+ vaccacheadd := vid & "10" & vshiftout(6 downto 0);
914+ elsif(vint_valuebit = 6)then
915+ vaccacheadd := vid & "110" & vshiftout(5 downto 0);
916+ elsif(vint_valuebit = 5)then
917+ vaccacheadd := vid & "1110" & vshiftout(4 downto 0);
918+ elsif(vint_valuebit = 4)then
919+ vaccacheadd := vid & "11110" & vshiftout(3 downto 0);
920+ elsif(vint_valuebit = 3)then
921+ vaccacheadd := vid & "111110" & vshiftout(2 downto 0);
922+ elsif(vint_valuebit = 2)then
923+ vaccacheadd := vid & "1111110" & vshiftout(1 downto 0);
924+ elsif(vint_valuebit = 1)then
925+ vaccacheadd := vid & "11111110" & vshiftout(0);
926+ end if;
927+ vaccachewr := '0';
928+ end if;
929+ end if;
930+
931+ -- Serial Part
932+ vserial_mask := "00000000000000000";
933+ if(r.serial_counter = "01001")then
934+ vserial_mask := "00000000011111111";
935+ elsif(r.serial_counter = "01010")then
936+ vserial_mask := "00000000111111111";
937+ elsif(r.serial_counter = "01011")then
938+ vserial_mask := "00000001111111111";
939+ elsif(r.serial_counter = "01100")then
940+ vserial_mask := "00000011111111111";
941+ elsif(r.serial_counter = "01101")then
942+ vserial_mask := "00000111111111111";
943+ elsif(r.serial_counter = "01110")then
944+ vserial_mask := "00001111111111111";
945+ elsif(r.serial_counter = "01111")then
946+ vserial_mask := "00011111111111111";
947+ elsif(r.serial_counter = "10000")then
948+ vserial_mask := "00111111111111111";
949+ elsif(r.serial_counter = "10001")then
950+ vserial_mask := "01111111111111111";
951+ end if;
952+ vserial_tmpin := ('0' & vshiftout) and vserial_mask;
953+ debug_serialin <= vserial_tmpin;
954+ if(r.dec_state = symcheck or r.dec_state = serialcheck or r.dec_state = serialwait or r.dec_state = serialfinish)then
955+ vsermaxadd := r.dcac & vid & r.serial_counter;
956+ end if;
957+
958+ if(r.dec_state = symcheck or r.dec_state = serialcheck or r.dec_state = serialwait or r.dec_state = serialfinish)then
959+ vseroffadd := r.dcac & vid & r.serial_counter;
960+ end if;
961+
962+ if(signed(vserial_tmpin) <= to_01(signed(sermaxdout)))then
963+ vserial_judge := '1';
964+ end if;
965+ vserial_tmpadd := std_logic_vector(signed(vserial_tmpin) + signed(seroffdout));
966+ if(r.dec_state = serialcheck or r.dec_state = serialwait or r.dec_state = serialfinish)then
967+ vservaladd := r.dcac & vid & vserial_tmpadd(7 downto 0);
968+ end if;
969+ if(r.dec_state = serialwait or r.dec_state = serialcheck or r.dec_state = serialfinish)then
970+ vservalwr := '0';
971+ end if;
972+
973+ if(r.dec_state = symreq)then
974+ v.serial_counter := "01001";
975+ elsif((r.dec_state = symcheck and vint_valuebit > 8)
976+ or (r.dec_state = serialcheck and to_integer(unsigned(r.serial_counter))<= vint_valuebit)
977+ or (r.dec_state = serialwait and to_integer(unsigned(r.serial_counter))<= vint_valuebit ))
978+ or (r.dec_state = serialcheck and vserial_judge = '1')then
979+ v.serial_counter := r.serial_counter + 1;
980+ end if;
981+
982+ -- Sign extention & zigzag memory access
983+ debug_sign_exin <= vshiftout(10 downto 0);
984+ vkdata := sign_ex(vshiftout(10 downto 0), r.valbit_keep );
985+ if(r.dec_state = valout and r.dcac = '1')then
986+ if(vcompid = "00")then
987+ vkdata := std_logic_vector(signed(vkdata) + signed(r.lastdc0));
988+ v.lastdc0 := vkdata;
989+ elsif(vcompid = "01")then
990+ vkdata := std_logic_vector(signed(vkdata) + signed(r.lastdc1));
991+ v.lastdc1 := vkdata;
992+ else
993+ vkdata := std_logic_vector(signed(vkdata) + signed(r.lastdc2));
994+ v.lastdc2 := vkdata;
995+ end if;
996+ end if;
997+ if(r.dec_state = valout)then
998+ vkstrobe := '1';
999+ else
1000+ vkstrobe := '0';
1001+ end if;
1002+
1003+if(vstartgen = '1' or r.marker_reg = x"D9")then
1004+ v.lastdc0 := (others => '0');
1005+ v.lastdc1 := (others => '0');
1006+ v.lastdc2 := (others => '0');
1007+end if;
1008+
1009+-- Decord part state-machine
1010+-- state = symreq, symcheck, valout, symng, symokvalng, serialwait, serialcheck, serialfinish, standby
1011+ vint_csymbit := 0; vint_reqbitkp := 0; vint_cvalbit := 0;
1012+ vint_sersym := 0; vint_serval := 0;
1013+
1014+ if notx(vcache_symbit) then
1015+ vint_csymbit := to_integer(unsigned(vcache_symbit));
1016+ end if;
1017+ if notx(r.reqbit_keep) then
1018+ vint_reqbitkp := to_integer(unsigned(r.reqbit_keep));
1019+ end if;
1020+ if notx(vcache_valbit) then
1021+ vint_cvalbit := to_integer(unsigned(vcache_valbit));
1022+ end if;
1023+ if notx(vserial_symbit) then
1024+ vint_sersym := to_integer(unsigned(vserial_symbit));
1025+ end if;
1026+ if notx(vserial_valbit) then
1027+ vint_serval := to_integer(unsigned(vserial_valbit));
1028+ end if;
1029+
1030+ case r.dec_state is
1031+ when standby =>
1032+ if(kready = '1' and r.valuebit /= "000000")then
1033+ v.dec_state := symreq;
1034+ end if;
1035+ when symreq =>
1036+ if(r.valuebit = "000000")then
1037+ v.dec_state := symreq;
1038+ else
1039+ v.dec_state := symcheck;
1040+ end if;
1041+ when symcheck =>
1042+ if(vint_csymbit /= 0 and vint_csymbit <= vint_reqbitkp and vint_csymbit + vint_cvalbit <= vint_valuebit )then
1043+ v.dec_state := valout;
1044+ elsif(vint_csymbit /= 0 and vint_csymbit <= vint_reqbitkp and vint_csymbit + vint_cvalbit > vint_valuebit )then
1045+ v.dec_state := symokvalng;
1046+ elsif(vint_reqbitkp = 8 and vint_csymbit = 0 and vint_valuebit >= 9)then
1047+ v.dec_state := serialcheck;
1048+ elsif(vint_reqbitkp = 8 and vint_csymbit = 0 and vint_valuebit < 9)then
1049+ v.dec_state := serialwait;
1050+ elsif(vint_reqbitkp < 8 and (vint_csymbit = 0 or vint_csymbit > vint_reqbitkp))then
1051+ v.dec_state := symng;
1052+ end if;
1053+ when symng =>
1054+ if(vint_reqbitkp = vint_valuebit)then
1055+ v.dec_state := symng;
1056+ else
1057+ v.dec_state := symreq;
1058+ end if;
1059+ when valout =>
1060+ if(r.memaddcnt = "111111")then
1061+ v.dec_state := standby;
1062+ else
1063+ v.dec_state := symreq;
1064+ end if;
1065+ when symokvalng =>
1066+ if(vint_valbkp <= vint_valuebit)then
1067+ v.dec_state := valout;
1068+ else
1069+ v.dec_state := symokvalng;
1070+ end if;
1071+ when serialwait =>
1072+ if(vint_sercnt > vint_valuebit) then
1073+ v.dec_state := serialwait;
1074+ else
1075+ v.dec_state := serialcheck;
1076+ end if;
1077+ when serialcheck =>
1078+ if(vserial_judge = '1')then
1079+ v.dec_state := serialfinish;
1080+ elsif(vint_sercnt > vint_valuebit)then
1081+ v.dec_state := serialwait;
1082+ else
1083+ v.dec_state := serialcheck;
1084+ end if;
1085+ when serialfinish =>
1086+ if(vint_valuebit < vint_sersym + vint_serval)then
1087+ v.dec_state := symokvalng;
1088+ else
1089+ v.dec_state := valout;
1090+ end if;
1091+ when others =>
1092+ end case;
1093+
1094+-- reset part
1095+ if rst = '0' or vstartgen = '1' then
1096+ v.hreg.getscan := '0';
1097+ v.hreg.rdscan := '0';
1098+ v.hreg.getq := '0';
1099+ v.hreg.rdq := '0';
1100+ v.hreg.getcache := '0';
1101+ v.hreg.rdacache := '0';
1102+ v.hreg.rddcache := '0';
1103+ v.hreg.haddkeep := (others => '0');
1104+ v.hreg.getmax := '0';
1105+ v.hreg.rdmax := '0';
1106+ v.hreg.getoffset := '0';
1107+ v.hreg.rdoffset := '0';
1108+ v.hreg.getval := '0';
1109+ v.hreg.rdval := '0';
1110+ v.fetch_state := memwait;
1111+ v.dec_state := standby;
1112+ v.fifo_rp := (others => '0');
1113+ v.fifo_wp := (others => '0');
1114+ -- v.counter := (others => '0');
1115+ v.fetch_reg := (others => '0');
1116+ v.marker_reg := (others => '0');
1117+ v.valuebit := (others => '0');
1118+ v.byteselect := (others => '0');
1119+ v.reqbit_keep := (others => '0');
1120+ -- v.runlength_keep := (others => '0');
1121+ v.valbit_keep := (others => '0');
1122+ v.dcac := '1';
1123+ v.serial_counter := (others => '0');
1124+ v.idcounter := (others => '0');
1125+ v.memaddcnt := (others => '0');
1126+ v.lastdc0 := (others => '0');
1127+ v.lastdc1 := (others => '0');
1128+ v.lastdc2 := (others => '0');
1129+ v.byte3keep := (others => '0');
1130+ v.cntdown := '0';
1131+ v.capture := "00";
1132+ v.skipcnt := (others => '0');
1133+ end if;
1134+ if rst = '0' then
1135+ v.preg.sampf := '0';
1136+ v.preg.xmcumax := (others => '0');
1137+ v.preg.ymcumax := (others => '0');
1138+ v.preg.incaddy := (others => '0');
1139+ v.preg.incaddmcux := (others => '0');
1140+ v.preg.incaddmcuy := (others => '0');
1141+ v.preg.fbstartadd := (others => '0');
1142+ v.preg.through_bit := '0';
1143+ v.preg.hardonly := '0';
1144+ end if;
1145+
1146+
1147+-- signals
1148+ rin <= v;
1149+ write_en_fifo <= r.hreg.getscan;
1150+ write_pointer_fifo <= r.fifo_wp;
1151+ data_in_fifo <= ahbsi.hwdata;
1152+ read_en_fifo <= '1';
1153+ read_pointer_fifo <= r.fifo_rp;
1154+
1155+ dccachedin <= ahbsi.hwdata(7 downto 0);
1156+ dccacheadd <= vdccacheadd;
1157+ dccacheen <= '1';
1158+ dccachewr <= vdccachewr;
1159+ accachedin <= ahbsi.hwdata(11 downto 0);
1160+ accacheadd <= vaccacheadd;
1161+ accacheen <= '1';
1162+ accachewr <= vaccachewr;
1163+ sermaxdin <= ahbsi.hwdata(16 downto 0);
1164+ sermaxadd <= vsermaxadd;
1165+ sermaxen <= '1';
1166+ sermaxwr <= vsermaxwr;
1167+ seroffdin <= ahbsi.hwdata(16 downto 0);
1168+ seroffadd <= vseroffadd;
1169+ seroffen <= '1';
1170+ seroffwr <= vseroffwr;
1171+ seroffdin <= ahbsi.hwdata(16 downto 0);
1172+ servaladd <= vservaladd;
1173+ servalen <= '1';
1174+ servalwr <= vservalwr;
1175+ servaldin <= ahbsi.hwdata(7 downto 0);
1176+
1177+ jpg_setting.xmcumax <= r.preg.xmcumax;
1178+ jpg_setting.ymcumax <= r.preg.ymcumax;
1179+ jpg_setting.incaddy <= r.preg.incaddy;
1180+ jpg_setting.incaddmcux <= r.preg.incaddmcux;
1181+ jpg_setting.incaddmcuy <= r.preg.incaddmcuy;
1182+ jpg_setting.fbstartadd <= r.preg.fbstartadd;
1183+ startgen <= vstartgen;
1184+ jpg_setting.samp_fact <= r.preg.sampf;
1185+
1186+ kstrobeq <= r.hreg.getq;
1187+ kdataq <= ahbsi.hwdata(7 downto 0);
1188+
1189+ apbo.prdata <= vprdata;
1190+ ahbso.hirq <= virq;
1191+ ahbso.hrdata <= vhrdata;
1192+
1193+ kdata <= vkdata;
1194+ kstrobe <= vkstrobe;
1195+ kaddress <= r.memaddcnt;
1196+ kaddq <= vkaddq;
1197+ krdq <= vkrdq;
1198+ end process;
1199+
1200+ apbo.pirq <= (others => '0');
1201+ apbo.pindex <= pindex;
1202+ apbo.pconfig <= pconfig;
1203+ ahbso.hconfig <= shconfig;
1204+ ahbso.hresp <= "00";
1205+ ahbso.hsplit <= (others => '0');
1206+ ahbso.hcache <= '0';
1207+ ahbso.hready <= '1';
1208+ ahbso.hindex <= shindex;
1209+
1210+ -- registers
1211+ reg : process(clk)
1212+ begin
1213+ if rising_edge(clk) then
1214+ r <= rin;
1215+ end if;
1216+ end process;
1217+
1218+end;
--- a/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/huffdctycc.vhd
+++ b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/huffdctycc.vhd
@@ -110,26 +110,26 @@ begin
110110 port map(rst => rst, clk => clk, kready1 => kready1, kstrobe1 => kstrobe1, kaddress1 => kaddress1, kdata1 => kdata1, kready2 => kready2,
111111 kstrobe2 => kstrobe2, kdata2 => kdata2, error =>error(0), samp_fact => jpg_setting.samp_fact,
112112 kstrobeq1 => kstrobeq, kdataq1 => kdataq1, kdataq2 => kdataq2,
113- kaddq => kaddq, krdq => krdq, krddataq => krddataq);
113+ kaddq => kaddq, krdq => krdq, krddataq => krddataq, startgen => startgen);
114114
115115 dct1 : idct1
116116 port map(rst => rst, clk => clk, ready1 => kready2, strobe1 => kstrobe2, coeffin => kdata2,
117- quantin => kdataq2, outdata => kdata3, ready2 => kready3, strobe2 => kstrobe3);
117+ quantin => kdataq2, outdata => kdata3, ready2 => kready3, strobe2 => kstrobe3, startgen => startgen);
118118
119119 dctmem2 : dctmem2cont
120120 generic map(memtech => memtech)
121121 port map(rst => rst, clk => clk, kready1 => kready3, kstrobe1 => kstrobe3, kdata1 => kdata3,
122- kready2 => kready4, kstrobe2 => kstrobe4, kdata2 => kdata4, error => error(1) );
122+ kready2 => kready4, kstrobe2 => kstrobe4, kdata2 => kdata4, error => error(1), startgen => startgen);
123123
124124 dct2 : idct2
125125 port map(rst => rst, clk => clk, ready1 => kready4, strobe1 => kstrobe4, coeffin => kdata4,
126- outdata => kdata5, ready2 => kready5, strobe2 => kstrobe5);
126+ outdata => kdata5, ready2 => kready5, strobe2 => kstrobe5, startgen => startgen);
127127
128128 yccmem : yccmemcont
129129 generic map(memtech => memtech)
130130 port map(rst => rst, clk => clk, kready1 => kready5, kstrobe1 => kstrobe5, kdata1 => kdata5,
131131 kready2 => kready6, kstrobe2 => kstrobe6, kdata2 => kdata6, samp_fact => jpg_setting.samp_fact,
132- error => error(2));
132+ error => error(2), startgen => startgen);
133133
134134 ycb : yccrgb
135135 generic map(memtech => memtech, hirq => hirq, mhindex => mhindex,
--- /dev/null
+++ b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/huffdctycc.vhd.bak
@@ -0,0 +1,223 @@
1+------------------------------------------------------------------------------
2+-- Copyright (C) 2011, Kenichi Kurimoto
3+--
4+-- This program is free software; you can redistribute it and/or modify
5+-- it under the terms of the GNU General Public License as published by
6+-- the Free Software Foundation; either version 2 of the License, or
7+-- (at your option) any later version.
8+--
9+-- This program is distributed in the hope that it will be useful,
10+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12+-- GNU General Public License for more details.
13+--
14+-- You should have received a copy of the GNU General Public License
15+-- along with this program; if not, write to the Free Software
16+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17+-----------------------------------------------------------------------------
18+-- Entity: huffdctycc
19+-- File: huffdctycc.vhd
20+-- Author: Kenichi Kurimoto
21+-- Description: huffman decoder,2D-DCT,upsample,and YCbCr-RGB translation
22+-- for jpeg decode
23+------------------------------------------------------------------------------
24+
25+
26+
27+
28+library ieee;
29+use ieee.std_logic_1164.all;
30+use ieee.numeric_std.all;
31+use std.textio.all;
32+use ieee.std_logic_textio.all;
33+
34+library grlib;
35+use grlib.amba.all;
36+use grlib.stdlib.all;
37+use grlib.devices.all;
38+
39+library techmap;
40+use techmap.gencomp.all;
41+
42+library kuri;
43+use kuri.mjpeg.all;
44+
45+entity huffdctycc is
46+ generic (
47+ memtech : integer := DEFMEMTECH;
48+ shindex : integer := 0;
49+ haddr : integer := 0;
50+ hmask : integer := 16#fff#;
51+ hirq : integer := 0;
52+ pindex : integer := 0;
53+ paddr : integer := 0;
54+ pmask : integer := 16#fff#;
55+ mhindex : integer := 0;
56+ chprot : integer := 3);
57+
58+ port (
59+ rst : in std_ulogic;
60+ clk : in std_ulogic;
61+ ahbmi : in ahb_mst_in_type;
62+ ahbmo : out ahb_mst_out_type;
63+ ahbsi : in ahb_slv_in_type;
64+ ahbso : out ahb_slv_out_type;
65+ apbi : in apb_slv_in_type;
66+ apbo : out apb_slv_out_type;
67+ logan_sig : out std_logic_vector(31 downto 0)
68+ );
69+end;
70+
71+architecture rtl of huffdctycc is
72+
73+signal kready1, kready2, kready3, kready4, kready5, kready6,
74+ kstrobe1, kstrobeq, kstrobe2, kstrobe3, kstrobe4, kstrobe5, kstrobe6: std_logic;
75+signal kdata1 : std_logic_vector(11 downto 0);
76+signal kaddress1 : std_logic_vector(5 downto 0);
77+signal kdata2 : std_logic_vector(11 downto 0);
78+signal kdataq1 : std_logic_vector(7 downto 0);
79+signal kdataq2 : std_logic_vector(7 downto 0);
80+signal kdata3 : std_logic_vector(15 downto 0);
81+signal kdata4 : std_logic_vector(15 downto 0);
82+signal kdata5 : std_logic_vector(7 downto 0);
83+signal kdata6 : std_logic_vector(23 downto 0);
84+signal error : std_logic_vector(2 downto 0);
85+signal jpg_setting : jpg_set_type;
86+signal startgen : std_logic;
87+signal kaddq : std_logic_vector(7 downto 0);
88+signal krdq : std_logic;
89+signal krddataq : std_logic_vector(7 downto 0);
90+
91+signal count_r, count_rin :std_logic_vector(31 downto 0);
92+
93+signal logan_sig2 : std_logic_vector(31 downto 0);
94+
95+-- pragma translate_off
96+file out_file1 : text open write_mode is "aft_huff.txt";
97+file out_file2 : text open write_mode is "aft_huffmem.txt";
98+file out_file3 : text open write_mode is "aft_dct1.txt";
99+file out_file4 : text open write_mode is "aft_dctmem.txt";
100+file out_file5 : text open write_mode is "aft_dct2.txt";
101+file out_file6 : text open write_mode is "aft_yccmem.txt";
102+-- pragma translate_on
103+
104+begin
105+ huffman : huff
106+ generic map(memtech => memtech,shindex => shindex , haddr => haddr, hmask => hmask,
107+ hirq => hirq, pindex => pindex, paddr => paddr, pmask => pmask)
108+ port map(rst => rst, clk => clk, ahbsi => ahbsi, ahbso => ahbso, apbi => apbi, apbo => apbo,
109+ kready => kready1, kstrobe => kstrobe1, kdata => kdata1, kaddress => kaddress1, jpg_setting => jpg_setting,
110+ error => error, startgen => startgen, kstrobeq => kstrobeq, kdataq => kdataq1,
111+ kaddq => kaddq, krddataq => krddataq, krdq => krdq, logan_sig2 => logan_sig2);
112+
113+ dctmem1 : huffmemcont
114+ generic map(memtech => memtech)
115+ port map(rst => rst, clk => clk, kready1 => kready1, kstrobe1 => kstrobe1, kaddress1 => kaddress1, kdata1 => kdata1, kready2 => kready2,
116+ kstrobe2 => kstrobe2, kdata2 => kdata2, error =>error(0), samp_fact => jpg_setting.samp_fact,
117+ kstrobeq1 => kstrobeq, kdataq1 => kdataq1, kdataq2 => kdataq2,
118+ kaddq => kaddq, krdq => krdq, krddataq => krddataq, startgen => startgen);
119+
120+ dct1 : idct1
121+ port map(rst => rst, clk => clk, ready1 => kready2, strobe1 => kstrobe2, coeffin => kdata2,
122+ quantin => kdataq2, outdata => kdata3, ready2 => kready3, strobe2 => kstrobe3, startgen => startgen);
123+
124+ dctmem2 : dctmem2cont
125+ generic map(memtech => memtech)
126+ port map(rst => rst, clk => clk, kready1 => kready3, kstrobe1 => kstrobe3, kdata1 => kdata3,
127+ kready2 => kready4, kstrobe2 => kstrobe4, kdata2 => kdata4, error => error(1), startgen => startgen);
128+
129+ dct2 : idct2
130+ port map(rst => rst, clk => clk, ready1 => kready4, strobe1 => kstrobe4, coeffin => kdata4,
131+ outdata => kdata5, ready2 => kready5, strobe2 => kstrobe5, startgen => startgen);
132+
133+ yccmem : yccmemcont
134+ generic map(memtech => memtech)
135+ port map(rst => rst, clk => clk, kready1 => kready5, kstrobe1 => kstrobe5, kdata1 => kdata5,
136+ kready2 => kready6, kstrobe2 => kstrobe6, kdata2 => kdata6, samp_fact => jpg_setting.samp_fact,
137+ error => error(2), startgen => startgen);
138+
139+ ycb : yccrgb
140+ generic map(memtech => memtech, hirq => hirq, mhindex => mhindex,
141+ chprot => chprot)
142+ port map(rst => rst, clk => clk, ahbmi => ahbmi, ahbmo => ahbmo, kready => kready6,
143+ kstrobe => kstrobe6, kdata => kdata6, xmcumax => jpg_setting.xmcumax, ymcumax => jpg_setting.ymcumax,
144+ incaddy => jpg_setting.incaddy, incaddmcux => jpg_setting.incaddmcux, incaddmcuy => jpg_setting.incaddmcuy,
145+ fbstartadd => jpg_setting.fbstartadd, startgen => startgen);
146+
147+
148+huffcounter : process(clk, rst, kstrobe1, kaddress1, count_r)
149+ variable count_v :std_logic_vector(31 downto 0);
150+begin
151+ count_v := count_r;
152+ if(kstrobe1 = '1' and kaddress1 = "111111") then
153+ count_v := count_v + 1;
154+ end if;
155+ if (rst='0')then
156+ count_v := (others=>'0');
157+ end if;
158+end process;
159+
160+reg :process(clk)
161+begin
162+ if rising_edge(clk) then
163+ count_r <= count_rin;
164+ end if;
165+end process;
166+
167+logan_sig <= logan_sig2
168+--logan_sig <= kstrobe2 & kdata2 & kstrobe1 & kaddress1 & kdata1 ;
169+-- logan_sig <= count_r(16 downto 2) & kstrobe3 & kdata3 & kstrobe2 & kdata2 & kstrobe1 & kaddress1 & kdata1 ;
170+
171+-- 15 1 16 1 12 1 6 12
172+
173+
174+
175+
176+-- pragma translate_off
177+writeout : process(clk,kstrobe1, kstrobe2, kstrobe3, kstrobe4, kstrobe5,kstrobe6, kdata1, kdata2, kdata3,kdata4,kdata5,kdata6)
178+variable lc1 : line;
179+variable lc2 : line;
180+variable lc3 : line;
181+variable lc4 : line;
182+variable lc5 : line;
183+variable lc6 : line;
184+variable data1 : std_logic_vector(11 downto 0);
185+variable data2 : std_logic_vector(11 downto 0);
186+variable data3 : std_logic_vector(15 downto 0);
187+variable data4 : std_logic_vector(15 downto 0);
188+variable data5 : std_logic_vector(7 downto 0);
189+variable data6 : std_logic_vector(23 downto 0);
190+
191+begin
192+ if rising_edge(clk)then
193+ if (kstrobe1 = '1')then
194+-- data1 := kdata1;
195+ hwrite(lc1, kdata1, RIGHT, 3);
196+ writeline(out_file1,lc1);
197+ end if;
198+ if (kstrobe2 = '1')then
199+ hwrite(lc2, kdata2, RIGHT, 3);
200+ writeline(out_file2,lc2);
201+ end if;
202+ if(kstrobe3 = '1')then
203+ hwrite(lc3, kdata3, RIGHT, 4);
204+ writeline(out_file3,lc3);
205+ end if;
206+ if (kstrobe4 = '1')then
207+ hwrite(lc4, kdata4, RIGHT, 4);
208+ writeline(out_file4,lc4);
209+ end if;
210+ if(kstrobe5 = '1')then
211+ hwrite(lc5, kdata5, RIGHT, 2);
212+ writeline(out_file5,lc5);
213+ end if;
214+ if(kstrobe6 = '1')then
215+ hwrite(lc6, kdata6, RIGHT, 6);
216+ writeline(out_file6, lc6);
217+ end if;
218+ end if;
219+end process;
220+-- pragma translate_on
221+
222+end;
223+
--- a/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/huffmemcont.vhd
+++ b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/huffmemcont.vhd
@@ -54,7 +54,9 @@ entity huffmemcont is
5454
5555 kaddq : in std_logic_vector(7 downto 0);
5656 krdq : in std_logic;
57- krddataq : out std_logic_vector(7 downto 0)
57+ krddataq : out std_logic_vector(7 downto 0);
58+
59+ startgen : in std_logic
5860 );
5961 end;
6062
@@ -120,7 +122,7 @@ begin
120122 qram : syncram generic map(tech => memtech, abits => 8, dbits => 8)
121123 port map( clk, qaddress, qdatain, qdataout, qenable, qwrite);
122124
123-comb : process (r, rst, kstrobe1, kaddress1, kdata1, kready2, m0dataout, m1dataout, kstrobeq1, kdataq1, kaddq, krdq)
125+comb : process (r, rst, kstrobe1, kaddress1, kdata1, kready2, m0dataout, m1dataout, kstrobeq1, kdataq1, kaddq, krdq, samp_fact, startgen)
124126 variable v : control_reg;
125127 variable vkready1 : std_logic;
126128 variable verror : std_logic;
@@ -331,7 +333,7 @@ debug_bcountup <= bcountup;
331333
332334
333335 -- reset part
334- if rst = '0' then
336+ if rst = '0' or startgen= '1' then
335337 v.swf := mem0;
336338 v.swb := mem0;
337339 v.mem0state := fill0;
--- a/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/idct1.vhd
+++ b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/idct1.vhd
@@ -37,7 +37,8 @@ entity idct1 is
3737 quantin : in std_logic_vector (7 downto 0);
3838 outdata : out std_logic_vector (15 downto 0);
3939 ready2 : in std_logic;
40- strobe2 : out std_logic
40+ strobe2 : out std_logic;
41+ startgen : in std_logic
4142 );
4243 end idct1;
4344
@@ -168,7 +169,7 @@ signal r, rin : all_reg;
168169
169170 begin
170171
171-comb : process(r, rst, strobe1, ready2, coeffin, quantin)
172+comb : process(r, rst, strobe1, ready2, coeffin, quantin, startgen)
172173 variable v : all_reg;
173174 variable node0 : std_logic_vector(20 downto 0);
174175 variable node1 : node1_array;
@@ -295,7 +296,7 @@ begin
295296 end if;
296297
297298 -- reset part
298- if rst = '0' then
299+ if rst = '0' or startgen = '1' then
299300 v.data_reg.inreg := (others => '0');
300301 for i in 0 to 7 loop
301302 v.data_reg.accumulator(i) := (others => '0');
--- /dev/null
+++ b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/idct1.vhd.bak
@@ -0,0 +1,435 @@
1+------------------------------------------------------------------------------
2+-- Copyright (C) 2011, Kenichi Kurimoto
3+--
4+-- This program is free software; you can redistribute it and/or modify
5+-- it under the terms of the GNU General Public License as published by
6+-- the Free Software Foundation; either version 2 of the License, or
7+-- (at your option) any later version.
8+--
9+-- This program is distributed in the hope that it will be useful,
10+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12+-- GNU General Public License for more details.
13+--
14+-- You should have received a copy of the GNU General Public License
15+-- along with this program; if not, write to the Free Software
16+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17+-----------------------------------------------------------------------------
18+-- Entity: idct1
19+-- File: idct1.vhd
20+-- Author: Kenichi Kurimoto
21+-- Description: 1st IDCT calculation for jpeg decode
22+------------------------------------------------------------------------------
23+
24+library ieee;
25+use ieee.std_logic_1164.all;
26+use ieee.numeric_std.all;
27+
28+library grlib;
29+use grlib.stdlib.all;
30+
31+entity idct1 is
32+ port ( rst : in std_ulogic;
33+ clk : in std_ulogic;
34+ ready1 : out std_logic;
35+ strobe1 : in std_logic;
36+ coeffin : in std_logic_vector (11 downto 0);
37+ quantin : in std_logic_vector (7 downto 0);
38+ outdata : out std_logic_vector (15 downto 0);
39+ ready2 : in std_logic;
40+ strobe2 : out std_logic;
41+ startgen : in std_logic
42+ );
43+end idct1;
44+
45+architecture rtl of idct1 is
46+
47+function mysigned_mul(a,b : std_logic_vector) return std_logic_vector is
48+variable z : std_logic_vector(a'length + b'length -1 downto 0);
49+begin
50+ z := std_logic_vector(signed(a) * signed(b));
51+ return(z);
52+end;
53+
54+function mysigned_add(a,b : std_logic_vector) return std_logic_vector is
55+variable ex_a : std_logic_vector(a'length downto 0);
56+variable ex_b : std_logic_vector(b'length downto 0);
57+variable z1 : std_logic_vector(a'length downto 0);
58+variable z2 : std_logic_vector(b'length downto 0);
59+begin
60+ ex_a := a(a'left) & a;
61+ ex_b := b(b'left) & b;
62+ if( a'length > b'length)then
63+ z1 := std_logic_vector(signed(ex_a) + signed(ex_b));
64+ return(z1);
65+ else
66+ z2 := std_logic_vector(signed(ex_a) + signed(ex_b));
67+ return(z2);
68+ end if;
69+end;
70+
71+function round1(indata : std_logic_vector(34 downto 0)) return std_logic_vector is
72+variable judge :std_logic;
73+variable z : std_logic_vector(22 downto 0);
74+begin
75+ judge := indata(11);
76+ if (judge = '0') then
77+ z := indata(34 downto 12);
78+ else
79+ z := indata(34 downto 12) + 1;
80+ end if;
81+ return(z);
82+end;
83+
84+function round2(indata : std_logic_vector(34 downto 0); pol : std_logic) return std_logic_vector is
85+variable judge : std_logic;
86+variable tmpdata : std_logic_vector(34 downto 0);
87+variable z : std_logic_vector(22 downto 0);
88+begin
89+ if (pol = '1') then
90+ tmpdata := (not indata) + 1 ;
91+ else
92+ tmpdata := indata;
93+ end if;
94+ judge := tmpdata(11);
95+ if (judge = '1') then
96+ z := tmpdata(34 downto 12) + 1;
97+ else
98+ z := tmpdata(34 downto 12);
99+ end if;
100+ return(z);
101+end;
102+
103+function round3(indata : std_logic_vector(25 downto 0)) return std_logic_vector is
104+variable judge : std_logic;
105+variable z : std_logic_vector(15 downto 0);
106+begin
107+ judge := indata(4);
108+ if (judge = '0') then
109+ z := indata(20 downto 5);
110+ else
111+ z := indata(20 downto 5) + 1;
112+ end if;
113+ return(z);
114+end;
115+
116+
117+function mysigned_mul23x12(a,b : std_logic_vector) return std_logic_vector is
118+variable sum : std_logic_vector(34 downto 0);
119+variable p0 : std_logic_vector(34 downto 0);
120+variable p1 : std_logic_vector(34 downto 0);
121+variable p2 : std_logic_vector(34 downto 0);
122+variable p3 : std_logic_vector(34 downto 0);
123+variable p4 : std_logic_vector(34 downto 0);
124+variable p5 : std_logic_vector(34 downto 0);
125+variable p6 : std_logic_vector(34 downto 0);
126+variable p7 : std_logic_vector(34 downto 0);
127+variable p8 : std_logic_vector(34 downto 0);
128+variable p9 : std_logic_vector(34 downto 0);
129+variable p10 : std_logic_vector(34 downto 0);
130+variable p11 : std_logic_vector(34 downto 0);
131+variable plus_p : std_logic_vector(34 downto 0);
132+begin
133+ p0 := "000000000000" & not(a(22) and b(0))& (a(21) and b(0))& (a(20) and b(0))& (a(19) and b(0))
134+ & (a(18) and b(0))& (a(17) and b(0))& (a(16) and b(0))& (a(15) and b(0))& (a(14) and b(0))
135+ & (a(13) and b(0))& (a(12) and b(0))& (a(11) and b(0))& (a(10) and b(0))& (a(9) and b(0))& (a(8) and b(0))
136+ & (a(7) and b(0)) & (a(6) and b(0))& (a(5) and b(0)) & (a(4) and b(0))
137+ & (a(3) and b(0)) & (a(2) and b(0))& (a(1) and b(0)) & (a(0) and b(0));
138+
139+ p1 := "00000000000" & not(a(22) and b(1))& (a(21) and b(1))& (a(20) and b(1))& (a(19) and b(1))
140+ & (a(18) and b(1))& (a(17) and b(1))& (a(16) and b(1))& (a(15) and b(1))& (a(14) and b(1))
141+ & (a(13) and b(1))& (a(12) and b(1))& (a(11) and b(1))& (a(10) and b(1))& (a(9) and b(1))& (a(8) and b(1))
142+ & (a(7) and b(1)) & (a(6) and b(1))& (a(5) and b(1)) & (a(4) and b(1))
143+ & (a(3) and b(1)) & (a(2) and b(1))& (a(1) and b(1)) & (a(0) and b(1)) & '0';
144+
145+ p2 := "0000000000" & not(a(22) and b(2))& (a(21) and b(2))& (a(20) and b(2))& (a(19) and b(2))
146+ & (a(18) and b(2))& (a(17) and b(2))& (a(16) and b(2))& (a(15) and b(2))& (a(14) and b(2))
147+ & (a(13) and b(2))& (a(12) and b(2))& (a(11) and b(2))& (a(10) and b(2))& (a(9) and b(2))& (a(8) and b(2))
148+ & (a(7) and b(2)) & (a(6) and b(2))& (a(5) and b(2)) & (a(4) and b(2))
149+ & (a(3) and b(2)) & (a(2) and b(2))& (a(1) and b(2)) & (a(0) and b(2)) & "00";
150+
151+ p3 := "000000000" & not(a(22) and b(3))& (a(21) and b(3))& (a(20) and b(3))& (a(19) and b(3))
152+ & (a(18) and b(3))& (a(17) and b(3))& (a(16) and b(3))& (a(15) and b(3))& (a(14) and b(3))
153+ & (a(13) and b(3))& (a(12) and b(3))& (a(11) and b(3))& (a(10) and b(3))& (a(9) and b(3))& (a(8) and b(3))
154+ & (a(7) and b(3)) & (a(6) and b(3))& (a(5) and b(3)) & (a(4) and b(3))
155+ & (a(3) and b(3)) & (a(2) and b(3))& (a(1) and b(3)) & (a(0) and b(3)) & "000";
156+
157+ p4 := "00000000" & not(a(22) and b(4))& (a(21) and b(4))& (a(20) and b(4))& (a(19) and b(4))
158+ & (a(18) and b(4))& (a(17) and b(4))& (a(16) and b(4))& (a(15) and b(4))& (a(14) and b(4))
159+ & (a(13) and b(4))& (a(12) and b(4))& (a(11) and b(4))& (a(10) and b(4))& (a(9) and b(4))& (a(8) and b(4))
160+ & (a(7) and b(4)) & (a(6) and b(4))& (a(5) and b(4)) & (a(4) and b(4))
161+ & (a(3) and b(4)) & (a(2) and b(4))& (a(1) and b(4)) & (a(0) and b(4)) & "0000";
162+
163+ p5 := "0000000" & not(a(22) and b(5))& (a(21) and b(5))& (a(20) and b(5))& (a(19) and b(5))
164+ & (a(18) and b(5))& (a(17) and b(5))& (a(16) and b(5))& (a(15) and b(5))& (a(14) and b(5))
165+ & (a(13) and b(5))& (a(12) and b(5))& (a(11) and b(5))& (a(10) and b(5))& (a(9) and b(5))& (a(8) and b(5))
166+ & (a(7) and b(5)) & (a(6) and b(5))& (a(5) and b(5)) & (a(4) and b(5))
167+ & (a(3) and b(5)) & (a(2) and b(5))& (a(1) and b(5)) & (a(0) and b(5)) & "00000";
168+
169+ p6 := "000000" & not(a(22) and b(6))& (a(21) and b(6))& (a(20) and b(6))& (a(19) and b(6))
170+ & (a(18) and b(6))& (a(17) and b(6))& (a(16) and b(6))& (a(15) and b(6))& (a(14) and b(6))
171+ & (a(13) and b(6))& (a(12) and b(6))& (a(11) and b(6))& (a(10) and b(6))& (a(9) and b(6))& (a(8) and b(6))
172+ & (a(7) and b(6)) & (a(6) and b(6))& (a(5) and b(6)) & (a(4) and b(6))
173+ & (a(3) and b(6)) & (a(2) and b(6))& (a(1) and b(6)) & (a(0) and b(6)) & "000000";
174+
175+ p7 := "00000" & not(a(22) and b(7))& (a(21) and b(7))& (a(20) and b(7))& (a(19) and b(7))
176+ & (a(18) and b(7))& (a(17) and b(7))& (a(16) and b(7))& (a(15) and b(7))& (a(14) and b(7))
177+ & (a(13) and b(7))& (a(12) and b(7))& (a(11) and b(7))& (a(10) and b(7))& (a(9) and b(7))& (a(8) and b(7))
178+ & (a(7) and b(7)) & (a(6) and b(7))& (a(5) and b(7)) & (a(4) and b(7))
179+ & (a(3) and b(7)) & (a(2) and b(7))& (a(1) and b(7)) & (a(0) and b(7)) & "0000000";
180+
181+ p8 := "0000" & not(a(22) and b(8))& (a(21) and b(8))& (a(20) and b(8))& (a(19) and b(8))
182+ & (a(18) and b(8))& (a(17) and b(8))& (a(16) and b(8))& (a(15) and b(8))& (a(14) and b(8))
183+ & (a(13) and b(8))& (a(12) and b(8))& (a(11) and b(8))& (a(10) and b(8))& (a(9) and b(8))& (a(8) and b(8))
184+ & (a(7) and b(8)) & (a(6) and b(8))& (a(5) and b(8)) & (a(4) and b(8))
185+ & (a(3) and b(8)) & (a(2) and b(8))& (a(1) and b(8)) & (a(0) and b(8)) & "00000000";
186+
187+ p9 := "000" & not(a(22) and b(9))& (a(21) and b(9))& (a(20) and b(9))& (a(19) and b(9))
188+ & (a(18) and b(9))& (a(17) and b(9))& (a(16) and b(9))& (a(15) and b(9))& (a(14) and b(9))
189+ & (a(13) and b(9))& (a(12) and b(9))& (a(11) and b(9))& (a(10) and b(9))& (a(9) and b(9))& (a(8) and b(9))
190+ & (a(7) and b(9)) & (a(6) and b(9))& (a(5) and b(9)) & (a(4) and b(9))
191+ & (a(3) and b(9)) & (a(2) and b(9))& (a(1) and b(9)) & (a(0) and b(9)) & "000000000";
192+
193+ p10 := "00" & not(a(22) and b(10))& (a(21) and b(10))& (a(20) and b(10))& (a(19) and b(10))
194+ & (a(18) and b(10))& (a(17) and b(10))& (a(16) and b(10))& (a(15) and b(10))& (a(14) and b(10))
195+ & (a(13) and b(10))& (a(12) and b(10))& (a(11) and b(10))& (a(10) and b(10))& (a(9) and b(10))& (a(8) and b(10))
196+ & (a(7) and b(10)) & (a(6) and b(10))& (a(5) and b(10)) & (a(4) and b(10))
197+ & (a(3) and b(10)) & (a(2) and b(10))& (a(1) and b(10)) & (a(0) and b(10)) & "0000000000";
198+
199+ p11 := "1" & (a(22) and b(11))& not(a(21) and b(11))& not(a(20) and b(11))& not(a(19) and b(11))
200+ & not(a(18) and b(11))& not(a(17) and b(11))& not(a(16) and b(11))& not(a(15) and b(11))& not(a(14) and b(11))
201+ & not(a(13) and b(11))& not(a(12) and b(11))& not(a(11) and b(11))& not(a(10) and b(11))& not(a(9) and b(11))& not(a(8) and b(11))
202+ & not(a(7) and b(11)) & not(a(6) and b(11))& not(a(5) and b(11)) & not(a(4) and b(11))
203+ & not(a(3) and b(11)) & not(a(2) and b(11))& not(a(1) and b(11)) & not(a(0) and b(11)) & "00000000000";
204+
205+ plus_p := "000000000000" & "1" & "0000000000" & "1" & "00000000000"
206+-- plus_p := "001111111111" & "1" & "0000000000" & "1" & "0000000000" &
207+ sum := std_logic_vector((unsigned(p0) + unsigned(p1)) + (unsigned(p2) + unsigned(p3)) + (unsigned(p4)
208+ + unsigned(p5)) + (unsigned(p6) + unsigned(p7)) + (unsigned(p8) + unsigned(p9)) + (unsigned(p10) + unsigned(p11)) + unsigned(plus_p) );
209+ return(sum);
210+end;
211+
212+
213+
214+
215+subtype coeff23 is std_logic_vector(22 downto 0);
216+type coeff_array1 is array(0 to 31) of coeff23;
217+constant coeff_rom : coeff_array1 :=
218+
219+("01011010100000100111101","01011010100000100111101","01011010100000100111101","01011010100000100111101",
220+ "01111101100010100110000","01101010011011011001100","01000111000111001110110","00011000111110001011100",
221+ "01110110010000011011000","00110000111110111100011","11001111000001000011110","10001001101111100101001",
222+ "01101010011011011001100","11100111000001110100100","10000010011101011010001","10111000111000110001010",
223+ "01011010100000100111101","10100101011111011000100","10100101011111011000100","01011010100000100111101",
224+ "01000111000111001110110","10000010011101011010001","00011000111110001011100","01101010011011011001100",
225+ "00110000111110111100011","10001001101111100101001","01110110010000011011000","11001111000001000011110",
226+ "00011000111110001011100","10111000111000110001010","01101010011011011001100","10000010011101011010001");
227+
228+type tablereg_type is array (0 to 3) of std_logic_vector(22 downto 0);
229+type accumulator_type is array (0 to 7) of std_logic_vector(25 downto 0);
230+type resultreg_type is array (0 to 7) of std_logic_vector(15 downto 0);
231+
232+type d_reg is record
233+ inreg : std_logic_vector(11 downto 0);
234+ accumulator : accumulator_type;
235+ result_reg : resultreg_type;
236+end record;
237+
238+type c_reg is record
239+ counter : std_logic_vector(6 downto 0);
240+end record;
241+
242+type all_reg is record
243+ data_reg : d_reg;
244+ control_reg : c_reg;
245+end record;
246+
247+type node1_array is array (0 to 3) of std_logic_vector(22 downto 0);
248+type node2_array is array (0 to 3) of std_logic_vector(34 downto 0);
249+type node3_array is array (0 to 7) of std_logic_vector(22 downto 0);
250+type node4_array is array (0 to 7) of std_logic_vector(25 downto 0);
251+type node5_array is array (0 to 7) of std_logic_vector(26 downto 0);
252+type node6_array is array (0 to 7) of std_logic_vector(15 downto 0);
253+
254+signal r, rin : all_reg;
255+--signal sig_node1_0 : std_logic_vector(22 downto 0);
256+--signal sig_node2_0 : std_logic_vector(34 downto 0);
257+--signal sig_node3_0 : std_logic_vector(22 downto 0);
258+--signal sig_node4_0 : std_logic_vector(25 downto 0);
259+--signal sig_node5_0 : std_logic_vector(26 downto 0);
260+--signal sig_node6_0 : std_logic_vector(15 downto 0);
261+--signal sig_node1_1 : std_logic_vector(22 downto 0);
262+--signal sig_node2_1 : std_logic_vector(34 downto 0);
263+--signal sig_node3_6 : std_logic_vector(22 downto 0);
264+--signal sig_node4_6 : std_logic_vector(25 downto 0);
265+--signal sig_node5_6 : std_logic_vector(26 downto 0);
266+--signal sig_node6_6 : std_logic_vector(15 downto 0);
267+
268+begin
269+
270+comb : process(r, rst, strobe1, ready2, coeffin, quantin, startgen)
271+ variable v : all_reg;
272+ variable node0 : std_logic_vector(20 downto 0);
273+ variable node1 : node1_array;
274+ variable node2 : node2_array;
275+ variable node3 : node3_array;
276+ variable node4 : node4_array;
277+ variable node5 : node5_array;
278+ variable node6 : node6_array;
279+ variable pol : std_logic;
280+ variable count_num : integer;
281+ variable vstrobe2 : std_logic;
282+ variable vready1 : std_logic;
283+begin
284+
285+ v := r;
286+ vstrobe2 := '0';
287+ count_num := to_integer(unsigned(r.control_reg.counter));
288+
289+ node0 := mysigned_mul(coeffin, '0' & quantin);
290+ v.data_reg.inreg := node0(11 downto 0);
291+
292+ case count_num is
293+ when 2 | 10 | 18 | 26 | 34 | 42 | 50 | 58 =>
294+ node1(0) := coeff_rom(4);
295+ node1(1) := coeff_rom(5);
296+ node1(2) := coeff_rom(6);
297+ node1(3) := coeff_rom(7);
298+ when 3 | 11 | 19 | 27 | 35 | 43 | 51 | 59 =>
299+ node1(0) := coeff_rom(8);
300+ node1(1) := coeff_rom(9);
301+ node1(2) := coeff_rom(10);
302+ node1(3) := coeff_rom(11);
303+ when 4 | 12 | 20 | 28 | 36 | 44 | 52 | 60 =>
304+ node1(0) := coeff_rom(12);
305+ node1(1) := coeff_rom(13);
306+ node1(2) := coeff_rom(14);
307+ node1(3) := coeff_rom(15);
308+ when 5 | 13 | 21 | 29 | 37 | 45 | 53 | 61 =>
309+ node1(0) := coeff_rom(16);
310+ node1(1) := coeff_rom(17);
311+ node1(2) := coeff_rom(18);
312+ node1(3) := coeff_rom(19);
313+ when 6 | 14 | 22 | 30 | 38 | 46 | 54 | 62 =>
314+ node1(0) := coeff_rom(20);
315+ node1(1) := coeff_rom(21);
316+ node1(2) := coeff_rom(22);
317+ node1(3) := coeff_rom(23);
318+ when 7 | 15 | 23 | 31 | 39 | 47 | 55 | 63 =>
319+ node1(0) := coeff_rom(24);
320+ node1(1) := coeff_rom(25);
321+ node1(2) := coeff_rom(26);
322+ node1(3) := coeff_rom(27);
323+ when 8 | 16 | 24 | 32 | 40 | 48 | 56 | 64 =>
324+ node1(0) := coeff_rom(28);
325+ node1(1) := coeff_rom(29);
326+ node1(2) := coeff_rom(30);
327+ node1(3) := coeff_rom(31);
328+ when others =>
329+ node1(0) := coeff_rom(0);
330+ node1(1) := coeff_rom(1);
331+ node1(2) := coeff_rom(2);
332+ node1(3) := coeff_rom(3);
333+ end case;
334+
335+ for i in 0 to 3 loop
336+ node2(i) := mysigned_mul23x12(node1(i), r.data_reg.inreg);
337+ node3(i) := round1(node2(i));
338+ end loop;
339+
340+-- when 3 | 5 | 7 | 9 | 11 | 13 | 15 | 17 | 19 | 21 | 23 | ..... | 65
341+-- when 2 4 6 8 10 12 14 16 18 20 22 64
342+ if((count_num mod 2) = 0 and (count_num >= 2) and (count_num <= 64))then
343+ pol := '1';
344+ else
345+ pol := '0';
346+ end if;
347+
348+ node3(4) := round2(node2(3), pol);
349+ node3(5) := round2(node2(2), pol);
350+ node3(6) := round2(node2(1), pol);
351+ node3(7) := round2(node2(0), pol);
352+
353+ if((count_num = 1) or (count_num = 9) or (count_num = 17) or (count_num = 25) or (count_num = 33) or (count_num = 41) or (count_num = 49) or (count_num = 57)) then
354+ for i in 0 to 7 loop
355+ node4(i) := (others => '0');
356+ end loop;
357+ else
358+ for i in 0 to 7 loop
359+ node4(i) := r.data_reg.accumulator(i);
360+ end loop;
361+ end if;
362+
363+ for i in 0 to 7 loop
364+ node5(i) := mysigned_add(node3(i), node4(i));
365+ v.data_reg.accumulator(i) := node5(i)(25 downto 0);
366+ node6(i) := round3(r.data_reg.accumulator(i));
367+ end loop;
368+
369+ if((count_num = 9) or (count_num = 17) or (count_num = 25) or (count_num = 33) or (count_num = 41) or (count_num = 49) or (count_num = 57) or (count_num = 65)) then
370+ for i in 0 to 7 loop
371+ v.data_reg.result_reg(i) := node6(i);
372+ end loop;
373+ else
374+ for i in 0 to 6 loop
375+ v.data_reg.result_reg(i) := r.data_reg.result_reg(i+1);
376+ end loop;
377+ v.data_reg.result_reg(7) := (others => '0');
378+ end if;
379+
380+ if((count_num >= 10) and (count_num <= 73))then
381+ vstrobe2 := '1';
382+ end if;
383+
384+-- controller part
385+ if ((count_num = 0 and strobe1 = '1') or count_num /= 0) then
386+ v.control_reg.counter := std_logic_vector(to_unsigned(count_num + 1,7));
387+ if(count_num = 73)then
388+ v.control_reg.counter := (others => '0');
389+ end if;
390+ end if;
391+ vready1 := '0';
392+ if(ready2 = '1' and count_num <= 63) then
393+ vready1 := '1';
394+ end if;
395+
396+-- reset part
397+ if rst = '0' or startgen = '1' then
398+ v.data_reg.inreg := (others => '0');
399+ for i in 0 to 7 loop
400+ v.data_reg.accumulator(i) := (others => '0');
401+ v.data_reg.result_reg(i) := (others => '0');
402+ end loop;
403+ v.control_reg.counter := (others => '0');
404+ end if;
405+
406+-- signal
407+ outdata <= r.data_reg.result_reg(0);
408+ strobe2 <= vstrobe2;
409+ ready1 <= vready1;
410+ rin <= v;
411+
412+-- debug
413+-- sig_node1_0 <= node1(0);
414+-- sig_node2_0 <= node2(0);
415+-- sig_node3_0 <= node3(0);
416+-- sig_node4_0 <= node4(0);
417+-- sig_node5_0 <= node5(0);
418+-- sig_node6_0 <= node6(0);
419+-- sig_node1_1 <= node1(1);
420+-- sig_node2_1 <= node2(1);
421+-- sig_node3_6 <= node3(6);
422+-- sig_node4_6 <= node4(6);
423+-- sig_node5_6 <= node5(6);
424+-- sig_node6_6 <= node6(6);
425+end process;
426+-- registers
427+reg : process(clk)
428+begin
429+ if rising_edge(clk) then
430+ r <= rin;
431+ end if;
432+end process;
433+
434+end rtl;
435+
--- a/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/idct2.vhd
+++ b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/idct2.vhd
@@ -36,7 +36,8 @@ entity idct2 is
3636 coeffin : in std_logic_vector (15 downto 0);
3737 outdata : out std_logic_vector (7 downto 0);
3838 ready2 : in std_logic;
39- strobe2 : out std_logic
39+ strobe2 : out std_logic;
40+ startgen : in std_logic
4041 );
4142 end idct2;
4243
@@ -184,7 +185,7 @@ signal r, rin : all_reg;
184185
185186 begin
186187
187-comb : process(r, rst, strobe1, ready2, coeffin)
188+comb : process(r, rst, strobe1, ready2, coeffin, startgen)
188189 variable v : all_reg;
189190 variable node1 : node1_array;
190191 variable node2 : node2_array;
@@ -316,7 +317,8 @@ begin
316317 end if;
317318
318319 -- reset part
319- if rst = '0' then
320+ if rst = '0' or startgen = '1' then
321+ v.data_reg.inreg := (others => '0');
320322 for i in 0 to 7 loop
321323 v.data_reg.accumulator(i) := (others => '0');
322324 v.data_reg.result_reg(i) := (others => '0');
--- /dev/null
+++ b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/idct2.vhd.bak
@@ -0,0 +1,359 @@
1+------------------------------------------------------------------------------
2+-- Copyright (C) 2011, Kenichi Kurimoto
3+--
4+-- This program is free software; you can redistribute it and/or modify
5+-- it under the terms of the GNU General Public License as published by
6+-- the Free Software Foundation; either version 2 of the License, or
7+-- (at your option) any later version.
8+--
9+-- This program is distributed in the hope that it will be useful,
10+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12+-- GNU General Public License for more details.
13+--
14+-- You should have received a copy of the GNU General Public License
15+-- along with this program; if not, write to the Free Software
16+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17+-----------------------------------------------------------------------------
18+-- Entity: idct2
19+-- File: idct2.vhd
20+-- Author: Kenichi Kurimoto
21+-- Description: 2nd IDCT calculation for jpeg decode
22+------------------------------------------------------------------------------
23+
24+library ieee;
25+use ieee.std_logic_1164.all;
26+use ieee.numeric_std.all;
27+
28+library grlib;
29+use grlib.stdlib.all;
30+
31+entity idct2 is
32+ port ( rst : in std_ulogic;
33+ clk : in std_ulogic;
34+ ready1 : out std_logic;
35+ strobe1 : in std_logic;
36+ coeffin : in std_logic_vector (15 downto 0);
37+ outdata : out std_logic_vector (7 downto 0);
38+ ready2 : in std_logic;
39+ strobe2 : out std_logic;
40+ startgen : in std_logic
41+ );
42+end idct2;
43+
44+architecture rtl of idct2 is
45+
46+function mysigned_mul(a,b : std_logic_vector) return std_logic_vector is
47+variable z : std_logic_vector(a'length + b'length -1 downto 0);
48+begin
49+ z := std_logic_vector(signed(a) * signed(b));
50+ return(z);
51+end;
52+
53+
54+function mysigned_add(a,b : std_logic_vector) return std_logic_vector is
55+variable ex_a : std_logic_vector(a'length downto 0);
56+variable ex_b : std_logic_vector(b'length downto 0);
57+variable z1 : std_logic_vector(a'length downto 0);
58+variable z2 : std_logic_vector(b'length downto 0);
59+begin
60+ ex_a := a(a'left) & a;
61+ ex_b := b(b'left) & b;
62+ if( a'length > b'length)then
63+ z1 := std_logic_vector(signed(ex_a) + signed(ex_b));
64+ return(z1);
65+ else
66+ z2 := std_logic_vector(signed(ex_a) + signed(ex_b));
67+ return(z2);
68+ end if;
69+end;
70+
71+function round1(indata : std_logic_vector(32 downto 0)) return std_logic_vector is
72+variable judge :std_logic;
73+variable z : std_logic_vector(14 downto 0);
74+begin
75+ judge := indata(17);
76+ if (judge = '0') then
77+ z := indata(32 downto 18);
78+ else
79+ z := indata(32 downto 18) + 1;
80+ end if;
81+ return(z);
82+end;
83+
84+function round2(indata : std_logic_vector(32 downto 0); pol : std_logic) return std_logic_vector is
85+variable judge : std_logic;
86+variable tmpdata : std_logic_vector(32 downto 0);
87+variable z : std_logic_vector(14 downto 0);
88+begin
89+ if (pol = '1') then
90+ tmpdata := not indata + 1 ;
91+ else
92+ tmpdata := indata;
93+ end if;
94+ judge := tmpdata(17);
95+ if (judge = '1') then
96+ z := tmpdata(32 downto 18) + 1;
97+ else
98+ z := tmpdata(32 downto 18);
99+ end if;
100+ return(z);
101+end;
102+
103+constant S_ZERO : SIGNED := "0000000000";
104+constant S_TWOFIVEFIVE : SIGNED := "0011111111";
105+
106+function round3(indata : std_logic_vector(17 downto 0)) return std_logic_vector is
107+variable judge : std_logic;
108+variable z : std_logic_vector(12 downto 0);
109+variable value : integer;
110+begin
111+ judge := indata(4);
112+ value := 0;
113+ if (judge = '0') then
114+ z := indata(17 downto 5);
115+ else
116+ z := indata(17 downto 5) + 1;
117+ end if;
118+ if notx(z) then value := to_integer(signed(z)); end if;
119+ if (value < -128) then
120+ return("10000000");
121+ end if;
122+ if(value > 127) then
123+ return("01111111");
124+ end if;
125+ return(z(7 downto 0));
126+end;
127+
128+
129+
130+subtype coeff23 is std_logic_vector(16 downto 0);
131+type coeff_array1 is array(0 to 31) of coeff23;
132+constant coeff_rom : coeff_array1 :=
133+
134+("01011010100000101","01011010100000101","01011010100000101","01011010100000101",
135+ "01111101100010101","01101010011011011","01000111000111010","00011000111110001",
136+ "01110110010000011","00110000111111000","11001111000001001","10001001101111101",
137+ "01101010011011011","11100111000001111","10000010011101100","10111000111000111",
138+ "01011010100000101","10100101011111100","10100101011111100","01011010100000101",
139+ "01000111000111010","10000010011101100","00011000111110001","01101010011011011",
140+ "00110000111111000","10001001101111101","01110110010000011","11001111000001001",
141+ "00011000111110001","10111000111000111","01101010011011011","10000010011101100");
142+
143+
144+type tablereg_type is array (0 to 3) of std_logic_vector(16 downto 0);
145+type accumulator_type is array (0 to 7) of std_logic_vector(17 downto 0);
146+type resultreg_type is array (0 to 7) of std_logic_vector(7 downto 0);
147+
148+
149+type d_reg is record
150+ inreg : std_logic_vector(15 downto 0);
151+ accumulator : accumulator_type;
152+ result_reg : resultreg_type;
153+end record;
154+
155+type c_reg is record
156+ counter : std_logic_vector(6 downto 0);
157+end record;
158+
159+type all_reg is record
160+ data_reg : d_reg;
161+ control_reg : c_reg;
162+end record;
163+
164+type node1_array is array (0 to 3) of std_logic_vector(16 downto 0);
165+type node2_array is array (0 to 3) of std_logic_vector(32 downto 0);
166+type node3_array is array (0 to 7) of std_logic_vector(14 downto 0);
167+type node4_array is array (0 to 7) of std_logic_vector(17 downto 0);
168+type node5_array is array (0 to 7) of std_logic_vector(18 downto 0);
169+type node6_array is array (0 to 7) of std_logic_vector(7 downto 0);
170+
171+signal r, rin : all_reg;
172+--signal sig_node1_0 : std_logic_vector(16 downto 0);
173+--signal sig_node2_0 : std_logic_vector(32 downto 0);
174+--signal sig_node3_0 : std_logic_vector(14 downto 0);
175+--signal sig_node4_0 : std_logic_vector(17 downto 0);
176+--signal sig_node5_0 : std_logic_vector(18 downto 0);
177+--signal sig_node6_0 : std_logic_vector(7 downto 0);
178+--signal sig_node1_3 : std_logic_vector(16 downto 0);
179+--signal sig_node2_3 : std_logic_vector(32 downto 0);
180+--signal sig_node3_4 : std_logic_vector(14 downto 0);
181+--signal sig_node4_4 : std_logic_vector(17 downto 0);
182+--signal sig_node5_4 : std_logic_vector(18 downto 0);
183+--signal sig_node6_4 : std_logic_vector(7 downto 0);
184+
185+
186+begin
187+
188+comb : process(r, rst, strobe1, ready2, coeffin, startgen)
189+ variable v : all_reg;
190+ variable node1 : node1_array;
191+ variable node2 : node2_array;
192+ variable node3 : node3_array;
193+ variable node4 : node4_array;
194+ variable node5 : node5_array;
195+ variable node6 : node6_array;
196+ variable node7 : std_logic_vector(9 downto 0);
197+ variable node8 : std_logic_vector(9 downto 0);
198+ variable pol : std_logic;
199+
200+ variable count_num : integer;
201+ variable vstrobe2 : std_logic;
202+ variable vready1 : std_logic;
203+begin
204+
205+ v := r;
206+ vstrobe2 := '0';
207+ count_num := to_integer(unsigned(r.control_reg.counter));
208+
209+ v.data_reg.inreg := coeffin;
210+
211+ case count_num is
212+ when 2 | 10 | 18 | 26 | 34 | 42 | 50 | 58 =>
213+ node1(0) := coeff_rom(4);
214+ node1(1) := coeff_rom(5);
215+ node1(2) := coeff_rom(6);
216+ node1(3) := coeff_rom(7);
217+ when 3 | 11 | 19 | 27 | 35 | 43 | 51 | 59 =>
218+ node1(0) := coeff_rom(8);
219+ node1(1) := coeff_rom(9);
220+ node1(2) := coeff_rom(10);
221+ node1(3) := coeff_rom(11);
222+ when 4 | 12 | 20 | 28 | 36 | 44 | 52 | 60 =>
223+ node1(0) := coeff_rom(12);
224+ node1(1) := coeff_rom(13);
225+ node1(2) := coeff_rom(14);
226+ node1(3) := coeff_rom(15);
227+ when 5 | 13 | 21 | 29 | 37 | 45 | 53 | 61 =>
228+ node1(0) := coeff_rom(16);
229+ node1(1) := coeff_rom(17);
230+ node1(2) := coeff_rom(18);
231+ node1(3) := coeff_rom(19);
232+ when 6 | 14 | 22 | 30 | 38 | 46 | 54 | 62 =>
233+ node1(0) := coeff_rom(20);
234+ node1(1) := coeff_rom(21);
235+ node1(2) := coeff_rom(22);
236+ node1(3) := coeff_rom(23);
237+ when 7 | 15 | 23 | 31 | 39 | 47 | 55 | 63 =>
238+ node1(0) := coeff_rom(24);
239+ node1(1) := coeff_rom(25);
240+ node1(2) := coeff_rom(26);
241+ node1(3) := coeff_rom(27);
242+ when 8 | 16 | 24 | 32 | 40 | 48 | 56 | 64 =>
243+ node1(0) := coeff_rom(28);
244+ node1(1) := coeff_rom(29);
245+ node1(2) := coeff_rom(30);
246+ node1(3) := coeff_rom(31);
247+ when others =>
248+ node1(0) := coeff_rom(0);
249+ node1(1) := coeff_rom(1);
250+ node1(2) := coeff_rom(2);
251+ node1(3) := coeff_rom(3);
252+ end case;
253+
254+ for i in 0 to 3 loop
255+ node2(i) := mysigned_mul(node1(i), r.data_reg.inreg);
256+ node3(i) := round1(node2(i));
257+ end loop;
258+
259+
260+-- when 3 | 5 | 7 | 9 | 11 | 13 | 15 | 17 | 19 | 21 | 23 | ..... | 65
261+-- when 2 4 6 8 10 12 14 16 18 20 22 64
262+
263+ if((count_num mod 2) = 0 and (count_num >= 2) and (count_num <= 64))then
264+ pol := '1';
265+ else
266+ pol := '0';
267+ end if;
268+
269+ node3(4) := round2(node2(3), pol);
270+ node3(5) := round2(node2(2), pol);
271+ node3(6) := round2(node2(1), pol);
272+ node3(7) := round2(node2(0), pol);
273+
274+ if((count_num = 1) or (count_num = 9) or (count_num = 17) or (count_num = 25) or (count_num = 33) or (count_num = 41) or (count_num = 49) or (count_num = 57)) then
275+ for i in 0 to 7 loop
276+ node4(i) := (others => '0');
277+ end loop;
278+ else
279+ for i in 0 to 7 loop
280+ node4(i) := r.data_reg.accumulator(i);
281+ end loop;
282+ end if;
283+
284+ for i in 0 to 7 loop
285+ node5(i) := mysigned_add(node3(i), node4(i));
286+ v.data_reg.accumulator(i) := node5(i)(17 downto 0);
287+ node6(i) := round3(r.data_reg.accumulator(i));
288+ end loop;
289+
290+ if((count_num = 9) or (count_num = 17) or (count_num = 25) or (count_num = 33) or (count_num = 41) or (count_num = 49) or (count_num = 57) or (count_num = 65)) then
291+ for i in 0 to 7 loop
292+ v.data_reg.result_reg(i) := node6(i);
293+ end loop;
294+ else
295+ for i in 0 to 6 loop
296+ v.data_reg.result_reg(i) := r.data_reg.result_reg(i+1);
297+ end loop;
298+ v.data_reg.result_reg(7) := (others => '0');
299+ end if;
300+
301+ node7 := mysigned_add(r.data_reg.result_reg(0),"010000000");
302+
303+ if((count_num >= 10) and (count_num <= 73))then
304+ vstrobe2 := '1';
305+ end if;
306+
307+-- controller part
308+ if ((count_num = 0 and strobe1 = '1') or count_num /= 0) then
309+ v.control_reg.counter := std_logic_vector(to_unsigned(count_num + 1,7));
310+ if(count_num = 73)then
311+ v.control_reg.counter := (others => '0');
312+ end if;
313+ end if;
314+ vready1 := '0';
315+ if(ready2 = '1' and count_num <= 63)then
316+ vready1 := '1';
317+ end if;
318+
319+-- reset part
320+ if rst = '0' or startgen = '1' then
321+ v.data_reg.inreg := (others => '0');
322+ for i in 0 to 7 loop
323+ v.data_reg.accumulator(i) := (others => '0');
324+ v.data_reg.result_reg(i) := (others => '0');
325+ end loop;
326+ v.control_reg.counter := (others => '0');
327+ end if;
328+
329+-- signal
330+ outdata <= node7(7 downto 0);
331+ strobe2 <= vstrobe2;
332+ ready1 <= vready1;
333+ rin <= v;
334+
335+-- debug
336+-- sig_node1_0 <= node1(0);
337+-- sig_node2_0 <= node2(0);
338+-- sig_node3_0 <= node3(0);
339+-- sig_node4_0 <= node4(0);
340+-- sig_node5_0 <= node5(0);
341+-- sig_node6_0 <= node6(0);
342+-- sig_node1_3 <= node1(3);
343+-- sig_node2_3 <= node2(3);
344+-- sig_node3_4 <= node3(4);
345+-- sig_node4_4 <= node4(4);
346+-- sig_node5_4 <= node5(4);
347+-- sig_node6_4 <= node6(4);
348+end process;
349+
350+-- registers
351+reg : process(clk)
352+begin
353+ if rising_edge(clk) then
354+ r <= rin;
355+ end if;
356+end process;
357+
358+end rtl;
359+
--- a/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/mjpeg.vhd
+++ b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/mjpeg.vhd
@@ -120,15 +120,14 @@ component huffmemcont is
120120 kstrobe2 : out std_logic;
121121 kdata2 : out std_logic_vector(11 downto 0);
122122 error : out std_logic;
123-
124123 samp_fact : in std_logic;
125124 kstrobeq1 : in std_logic;
126125 kdataq1 : in std_logic_vector(7 downto 0);
127- kdataq2 : out std_logic_vector(7 downto 0);
128-
126+ kdataq2 : out std_logic_vector(7 downto 0);
129127 kaddq : in std_logic_vector(7 downto 0);
130128 krdq : in std_logic;
131- krddataq : out std_logic_vector(7 downto 0)
129+ krddataq : out std_logic_vector(7 downto 0);
130+ startgen : in std_logic
132131 );
133132 end component;
134133
@@ -164,7 +163,8 @@ component dctmem2cont is
164163 kready2 : in std_logic;
165164 kstrobe2 : out std_logic;
166165 kdata2 : out std_logic_vector(15 downto 0);
167- error : out std_logic
166+ error : out std_logic;
167+ startgen : in std_logic
168168 );
169169 end component;
170170
@@ -177,7 +177,8 @@ component idct1 is
177177 quantin : in std_logic_vector (7 downto 0);
178178 outdata : out std_logic_vector (15 downto 0);
179179 ready2 : in std_logic;
180- strobe2 : out std_logic
180+ strobe2 : out std_logic;
181+ startgen : in std_logic
181182 );
182183 end component;
183184
@@ -189,7 +190,8 @@ component idct2 is
189190 coeffin : in std_logic_vector (15 downto 0);
190191 outdata : out std_logic_vector (7 downto 0);
191192 ready2 : in std_logic;
192- strobe2 : out std_logic
193+ strobe2 : out std_logic;
194+ startgen : in std_logic
193195 );
194196 end component;
195197
@@ -240,7 +242,8 @@ component yccmemcont
240242 kstrobe2 : out std_logic;
241243 kdata2 : out std_logic_vector(23 downto 0);
242244 samp_fact : in std_logic;
243- error : out std_logic
245+ error : out std_logic;
246+ startgen : in std_logic
244247 );
245248 end component;
246249
--- /dev/null
+++ b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/mjpeg.vhd.bak
@@ -0,0 +1,275 @@
1+------------------------------------------------------------------------------
2+-- Copyright (C) 20011 , Kenichi Kurimoto
3+--
4+-- This program is free software; you can redistribute it and/or modify
5+-- it under the terms of the GNU General Public License as published by
6+-- the Free Software Foundation; either version 2 of the License, or
7+-- (at your option) any later version.
8+--
9+-- This program is distributed in the hope that it will be useful,
10+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12+-- GNU General Public License for more details.
13+--
14+-- You should have received a copy of the GNU General Public License
15+-- along with this program; if not, write to the Free Software
16+-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17+-----------------------------------------------------------------------------
18+-- Entity: mjpeg package
19+-- File: mjpeg.vhd
20+-- Author: Kenichi Kurimoto
21+-- Description: motion JPEG package
22+------------------------------------------------------------------------------
23+
24+
25+
26+library ieee;
27+use ieee.std_logic_1164.all;
28+use ieee.numeric_std.all;
29+
30+library grlib;
31+use grlib.stdlib.all;
32+use grlib.amba.all;
33+use grlib.devices.all;
34+
35+library techmap;
36+use techmap.gencomp.all;
37+
38+package mjpeg is
39+
40+type jpg_set_type is record
41+ samp_fact : std_logic;
42+ xmcumax : std_logic_vector(5 downto 0);
43+ ymcumax : std_logic_vector(4 downto 0);
44+ incaddy : std_logic_vector(15 downto 0);
45+ incaddmcux : std_logic_vector(15 downto 0);
46+ incaddmcuy : std_logic_vector(10 downto 0);
47+ fbstartadd : std_logic_vector(31 downto 0);
48+end record;
49+
50+component huffdctycc is
51+ generic (
52+ memtech : integer := DEFMEMTECH;
53+ shindex : integer := 0;
54+ haddr : integer := 0;
55+ hmask : integer := 16#fff#;
56+ hirq : integer := 0;
57+ pindex : integer := 0;
58+ paddr : integer := 0;
59+ pmask : integer := 16#fff#;
60+ mhindex : integer := 0;
61+ chprot : integer := 3);
62+
63+ port (
64+ rst : in std_ulogic;
65+ clk : in std_ulogic;
66+ ahbmi : in ahb_mst_in_type;
67+ ahbmo : out ahb_mst_out_type;
68+ ahbsi : in ahb_slv_in_type;
69+ ahbso : out ahb_slv_out_type;
70+ apbi : in apb_slv_in_type;
71+ apbo : out apb_slv_out_type;
72+ logan_sig : out std_logic_vector(31 downto 0)
73+ );
74+end component;
75+
76+component huff is
77+ generic (
78+ memtech : integer := DEFMEMTECH;
79+ shindex : integer := 0;
80+ haddr : integer := 0;
81+ hmask : integer := 16#fff#;
82+ hirq : integer := 0;
83+ pindex : integer := 0;
84+ paddr : integer := 0;
85+ pmask : integer := 16#fff#;
86+ mhindex : integer := 0;
87+ chprot : integer := 3);
88+ port (
89+ rst : in std_ulogic;
90+ clk : in std_ulogic;
91+ ahbsi : in ahb_slv_in_type;
92+ ahbso : out ahb_slv_out_type;
93+ apbi : in apb_slv_in_type;
94+ apbo : out apb_slv_out_type;
95+ kready : in std_logic;
96+ kstrobe : out std_logic;
97+ kdata : out std_logic_vector(11 downto 0);
98+ kaddress : out std_logic_vector(5 downto 0);
99+ jpg_setting : out jpg_set_type;
100+ error : in std_logic_vector(2 downto 0);
101+ startgen : out std_logic;
102+ kstrobeq : out std_logic;
103+ kdataq : out std_logic_vector(7 downto 0);
104+ kaddq : out std_logic_vector(7 downto 0);
105+ krddataq : in std_logic_vector(7 downto 0);
106+ krdq : out std_logic
107+ );
108+end component;
109+
110+component huffmemcont is
111+ generic (
112+ memtech : integer := DEFMEMTECH);
113+ port (
114+ rst : in std_ulogic;
115+ clk : in std_ulogic;
116+ kready1 : out std_logic;
117+ kstrobe1 : in std_logic;
118+ kaddress1 : in std_logic_vector(5 downto 0);
119+ kdata1 : in std_logic_vector(11 downto 0);
120+ kready2 : in std_logic;
121+ kstrobe2 : out std_logic;
122+ kdata2 : out std_logic_vector(11 downto 0);
123+ error : out std_logic;
124+ samp_fact : in std_logic;
125+ kstrobeq1 : in std_logic;
126+ kdataq1 : in std_logic_vector(7 downto 0);
127+ kdataq2 : out std_logic_vector(7 downto 0);
128+ kaddq : in std_logic_vector(7 downto 0);
129+ krdq : in std_logic;
130+ krddataq : out std_logic_vector(7 downto 0);
131+ startgen : in std_logic
132+ );
133+end component;
134+
135+component dctmem1cont is
136+ generic (
137+ memtech : integer := DEFMEMTECH);
138+ port (
139+ rst : in std_ulogic;
140+ clk : in std_ulogic;
141+ kready1 : out std_logic;
142+ kstrobe1 : in std_logic;
143+ kdata1 : in std_logic_vector(11 downto 0);
144+ kready2 : in std_logic;
145+ kstrobe2 : out std_logic;
146+ kdata2 : out std_logic_vector(11 downto 0);
147+ error : out std_logic;
148+ samp_fact : in std_logic;
149+ kstrobeq1 : in std_logic;
150+ kdataq1 : in std_logic_vector(7 downto 0);
151+ kdataq2 : out std_logic_vector(7 downto 0)
152+ );
153+end component;
154+
155+component dctmem2cont is
156+ generic (
157+ memtech : integer := DEFMEMTECH);
158+ port (
159+ rst : in std_ulogic;
160+ clk : in std_ulogic;
161+ kready1 : out std_logic;
162+ kstrobe1 : in std_logic;
163+ kdata1 : in std_logic_vector(15 downto 0);
164+ kready2 : in std_logic;
165+ kstrobe2 : out std_logic;
166+ kdata2 : out std_logic_vector(15 downto 0);
167+ error : out std_logic;
168+ startgen : in std_logic
169+ );
170+end component;
171+
172+component idct1 is
173+ port ( rst : in std_ulogic;
174+ clk : in std_ulogic;
175+ ready1 : out std_logic;
176+ strobe1 : in std_logic;
177+ coeffin : in std_logic_vector (11 downto 0);
178+ quantin : in std_logic_vector (7 downto 0);
179+ outdata : out std_logic_vector (15 downto 0);
180+ ready2 : in std_logic;
181+ strobe2 : out std_logic;
182+ startgen : in std_logic
183+ );
184+end component;
185+
186+component idct2 is
187+ port ( rst : in std_ulogic;
188+ clk : in std_ulogic;
189+ ready1 : out std_logic;
190+ strobe1 : in std_logic;
191+ coeffin : in std_logic_vector (15 downto 0);
192+ outdata : out std_logic_vector (7 downto 0);
193+ ready2 : in std_logic;
194+ strobe2 : out std_logic;
195+ startgen : in std_logic
196+ );
197+end component;
198+
199+component yccambaif
200+ generic (
201+ memtech : integer := DEFMEMTECH;
202+ shindex : integer := 0;
203+ haddr : integer := 0;
204+ hmask : integer := 16#fff#;
205+ hirq : integer := 0;
206+ pindex : integer := 0;
207+ paddr : integer := 0;
208+ pmask : integer := 16#fff#);
209+ port (
210+ rst : in std_ulogic;
211+ clk : in std_ulogic;
212+ ahbsi : in ahb_slv_in_type;
213+ ahbso : out ahb_slv_out_type;
214+ apbi : in apb_slv_in_type;
215+ apbo : out apb_slv_out_type;
216+ kready : in std_logic;
217+ kstrobe : out std_logic;
218+ kdata : out std_logic_vector(11 downto 0);
219+ samp_fact : out std_logic;
220+ error : in std_logic_vector(2 downto 0);
221+ xmcumax : out std_logic_vector(5 downto 0);
222+ ymcumax : out std_logic_vector(4 downto 0);
223+ incaddy : out std_logic_vector(15 downto 0);
224+ incaddmcux : out std_logic_vector(15 downto 0);
225+ incaddmcuy : out std_logic_vector(10 downto 0);
226+ fbstartadd : out std_logic_vector(31 downto 0);
227+ startgen : out std_logic;
228+ kstrobeq : out std_logic;
229+ kdataq : out std_logic_vector(7 downto 0)
230+ );
231+end component;
232+
233+component yccmemcont
234+ generic (
235+ memtech : integer := DEFMEMTECH);
236+ port (
237+ rst : in std_ulogic;
238+ clk : in std_ulogic;
239+ kready1 : out std_logic;
240+ kstrobe1 : in std_logic;
241+ kdata1 : in std_logic_vector(7 downto 0);
242+ kready2 : in std_logic;
243+ kstrobe2 : out std_logic;
244+ kdata2 : out std_logic_vector(23 downto 0);
245+ samp_fact : in std_logic;
246+ error : out std_logic;
247+ startgen : in std_logic
248+ );
249+end component;
250+
251+component yccrgb
252+ generic (
253+ memtech : integer := DEFMEMTECH;
254+ hirq : integer := 0;
255+ mhindex : integer := 0;
256+ chprot : integer := 3);
257+ port (
258+ rst : in std_ulogic;
259+ clk : in std_ulogic;
260+ ahbmi : in ahb_mst_in_type;
261+ ahbmo : out ahb_mst_out_type;
262+ kready : out std_logic;
263+ kstrobe : in std_logic;
264+ kdata : in std_logic_vector(23 downto 0);
265+ xmcumax : in std_logic_vector(5 downto 0);
266+ ymcumax : in std_logic_vector(4 downto 0);
267+ incaddy : in std_logic_vector(15 downto 0);
268+ incaddmcux : in std_logic_vector(15 downto 0);
269+ incaddmcuy : in std_logic_vector(10 downto 0);
270+ fbstartadd : in std_logic_vector(31 downto 0);
271+ startgen : in std_logic
272+ );
273+end component;
274+
275+end;
--- a/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/yccmemcont.vhd
+++ b/grlib-gpl-1.0.22-b4095/lib/kuri/mjpeg/yccmemcont.vhd
@@ -46,7 +46,8 @@ entity yccmemcont is
4646 kstrobe2 : out std_logic;
4747 kdata2 : out std_logic_vector(23 downto 0);
4848 samp_fact : in std_logic;
49- error : out std_logic
49+ error : out std_logic;
50+ startgen : in std_logic
5051 );
5152 end;
5253 -- samp_fact = 0 -> 4:1:1
@@ -92,7 +93,7 @@ crram1 : syncram generic map(tech => memtech, abits => 7, dbits => 8)
9293
9394
9495 comb : process (r, rst, kstrobe1, kdata1, kready2, samp_fact, y0dataout, y1dataout,
95- cb0dataout, cb1dataout, cr0dataout, cr1dataout)
96+ cb0dataout, cb1dataout, cr0dataout, cr1dataout, startgen)
9697 variable v : control_reg;
9798 variable vkready1 : std_logic;
9899 variable verror : std_logic;
@@ -306,7 +307,7 @@ comb : process (r, rst, kstrobe1, kdata1, kready2, samp_fact, y0dataout, y1datao
306307 end if;
307308
308309 -- reset part
309- if rst = '0' then
310+ if rst = '0' or startgen = '1' then
310311 v.swf := mem0;
311312 v.swb := mem0;
312313 v.mem0state := empty;
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