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mdr: Commit


Commit MetaInfo

Revision106 (tree)
Time2023-10-17 20:35:38
Authormateuszviste

Log Message

fixed OPL timer initialization

Change Summary

Incremental Difference

--- trunk/inc/mdr/opl.h (revision 105)
+++ trunk/inc/mdr/opl.h (revision 106)
@@ -227,7 +227,7 @@
227227 * You may use only one timer at a time.
228228 *
229229 * EXAMPLE: setting up MDR_OPL_TIMER_80US with a count of 25 would make the
230- * timer tick exactly every 2ms (25 * 80us). */
230+ * timer tick every 2ms (25 * 80us). */
231231 void mdr_opl_timer_set(enum MDR_OPL_TIMER timertype, unsigned char count);
232232
233233 /* returns 1 if timer tick occured, 0 otherwise. After a tick has been
--- trunk/opl/opltimer.c (revision 105)
+++ trunk/opl/opltimer.c (revision 106)
@@ -42,8 +42,8 @@
4242 * Resetting the "timer overflow" flag in the status register is done by
4343 * writing 0x80 to register 04. This resets both Timer 1 and Timer 2.
4444 *
45- * To initialize (start) Timer 1, write 0x41 to register 04.
46- * To initialize (start) Timer 2, write 0x22 to register 04.
45+ * To initialize (start) Timer 1, write 0x01 to register 04.
46+ * To initialize (start) Timer 2, write 0x02 to register 04.
4747 *
4848 * Because the timer overflow reset flag is shared by the two timers, it is
4949 * highly impractical to use both timers at the same time.
@@ -63,7 +63,7 @@
6363 * You may use only one timer at a time.
6464 *
6565 * EXAMPLE: setting up MDR_OPL_TIMER_80US with a count of 25 would make the
66- * timer tick exactly every 2ms (25 * 80us). */
66+ * timer tick every 2ms (25 * 80us). */
6767 void mdr_opl_timer_set(enum MDR_OPL_TIMER timertype, unsigned char count) {
6868 /* stop the timers */
6969 mdr_opl_regwr(4, 0);
@@ -73,10 +73,10 @@
7373
7474 if (timertype == MDR_OPL_TIMER_80US) {
7575 mdr_opl_regwr(2, 256 - count); /* preset val into reg 02 (timer1) */
76- mdr_opl_regwr(4, 0x41); /* start the timer */
76+ mdr_opl_regwr(4, 0x01); /* start the timer */
7777 } else {
7878 mdr_opl_regwr(3, 256 - count); /* preset val into reg 03 (timer2) */
79- mdr_opl_regwr(4, 0x22); /* start the timer */
79+ mdr_opl_regwr(4, 0x02); /* start the timer */
8080 }
8181 }
8282
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