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Motonesfpga is a NES FPGA clone. It reproduce the NES run-time environment on the FPGA. Source code is written in VHDL, it runs on Terasic DE0-CV evaluation board. It consists of state machine and microcode (decoder ROM), ALU. All 6502 register and CPU cycle are official document compliant. Picture processing and rendering, VGA output, RAM, Char/Prog ROM, clock generation supported. Simple timing constraints and logic simuration code included.
This project is a text book for those who study hardware and CPU. VHDL code size is totally less than 10,000 lines. Readers can easily capture entire CPU structures with the realistic environment.
Motonesfpga has a brother project, called Motonesemu, which aims at reproducing the NES environment on the software emulator. This emurator is used for ROM simuration and debugging.
With those two brother NES project, FPGA and emulator, what trick between "software" and "hardware" is revealed. It will encourage more people to create their own CPU architecture or unique platform.
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[Git] commits were pushed to 'motonesfpga' (current: a226f5b4970a804e063ac04a945827d7ba310cf2)
pof generate memo added.
[Git] commits were pushed to 'motonesfpga' (current: c05814ac3a5c9a35126fed1599c4ce0ae99d3f81)
update output generate file.
[File Release] Release 'motonesfpga-de0_cv_nes-53e7463' has been deleted
[File Release] New release '' has been created