| Revision | 6eaf702ca9bb0dbc459979253b8c522710cbc984 (tree) |
|---|---|
| Time | 2013-09-07 14:29:56 |
| Author | astoria-d <astoria-d@mail...> |
| Commiter | astoria-d |
- bug fix for vram write timing incorrect.
simulation/address_decoder.vhd (diff)| @@ -220,7 +220,7 @@ begin | ||
| 220 | 220 | nt1_ce_n <= '1'; |
| 221 | 221 | if (wr_n = '0') then |
| 222 | 222 | --write |
| 223 | - nt0_ce_n <= not clk; | |
| 223 | + nt0_ce_n <= clk; | |
| 224 | 224 | elsif (rd_n = '0') then |
| 225 | 225 | --read |
| 226 | 226 | nt0_ce_n <= '0'; |
| @@ -232,7 +232,7 @@ begin | ||
| 232 | 232 | nt0_ce_n <= '1'; |
| 233 | 233 | if (wr_n = '0') then |
| 234 | 234 | --write |
| 235 | - nt1_ce_n <= not clk; | |
| 235 | + nt1_ce_n <= clk; | |
| 236 | 236 | elsif (rd_n = '0') then |
| 237 | 237 | --read |
| 238 | 238 | nt1_ce_n <= '0'; |
| @@ -248,7 +248,7 @@ begin | ||
| 248 | 248 | nt1_ce_n <= '1'; |
| 249 | 249 | if (wr_n = '0') then |
| 250 | 250 | --write |
| 251 | - nt0_ce_n <= not clk; | |
| 251 | + nt0_ce_n <= clk; | |
| 252 | 252 | elsif (rd_n = '0') then |
| 253 | 253 | --read |
| 254 | 254 | nt0_ce_n <= '0'; |
| @@ -260,7 +260,7 @@ begin | ||
| 260 | 260 | nt0_ce_n <= '1'; |
| 261 | 261 | if (wr_n = '0') then |
| 262 | 262 | --write |
| 263 | - nt1_ce_n <= not clk; | |
| 263 | + nt1_ce_n <= clk; | |
| 264 | 264 | elsif (rd_n = '0') then |
| 265 | 265 | --read |
| 266 | 266 | nt1_ce_n <= '0'; |
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