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motonesfpga: Commit

Moto NES FPGA main repository

Commit MetaInfo

Revision	813eda2710dd3ba2150f8dce26a10163a7b893c7 (tree)
Time	2016-05-02 20:43:50
Author	astoria-d <astoria-d@mail...>
Commiter	astoria-d

Log Message

apu address set bug fixex!!!

Change Summary

modified: de1_nes/apu/apu.vhd (diff)
modified: de1_nes/de1_nes.vhd (diff)
modified: de1_nes/ppu/ppu.vhd (diff)
modified: de1_nes/sample1-prg.hex (diff)
modified: de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do (diff)
modified: de1_nes/simulation/modelsim/rom-file.nes (diff)
modified: tools/regression-test/regression.asm (diff)

Incremental Difference

--- a/de1_nes/apu/apu.vhd

+++ b/de1_nes/apu/apu.vhd

		@@ -149,7 +149,7 @@ begin
149	149	r_nw <= 'Z';
150	150	elsif (dma_status = DMA_ST_SETUP) then
151	151	cpu_addr <= OAMADDR;
152		- cpu_d <= dma_addr(dsize * 2 - 1 downto dsize);
	152	+ cpu_d <= (others => '0');
153	153	r_nw <= '0';
154	154	dma_next_status <= DMA_ST_PROCESS;
155	155	elsif (dma_status = DMA_ST_PROCESS) then

--- a/de1_nes/de1_nes.vhd

+++ b/de1_nes/de1_nes.vhd

		@@ -379,8 +379,8 @@ begin
379	379	dbg_ppu_scrl_x(7) <= addr(15);
380	380	dbg_ppu_scrl_y(2 downto 0) <= dbg_p_oam_ce_rn_wn(2 downto 0);
381	381	dbg_ppu_scrl_y(5 downto 3) <= dbg_plt_ce_rn_wn(2 downto 0);
382		--- dbg_disp_ptn_l (7 downto 0) <= dbg_p_oam_addr;
383		--- dbg_disp_ptn_l (15 downto 8) <= dbg_p_oam_data;
	382	+ dbg_disp_ptn_l (7 downto 0) <= dbg_p_oam_addr;
	383	+ dbg_disp_ptn_l (15 downto 8) <= dbg_p_oam_data;
384	384
385	385	dbg_cpu_clk <= cpu_clk;
386	386	dbg_mem_clk <= mem_clk;

		@@ -412,7 +412,7 @@ begin
412	412	dbg_nes_y ,
413	413	dbg_vga_y ,
414	414	dbg_disp_nt, dbg_disp_attr ,
415		- dbg_disp_ptn_h, dbg_disp_ptn_l ,
	415	+ dbg_disp_ptn_h, dbg_disp_ptn_l_dummy ,
416	416	dbg_plt_ce_rn_wn ,
417	417	dbg_plt_addr ,
418	418	dbg_plt_data ,

--- a/de1_nes/ppu/ppu.vhd

+++ b/de1_nes/ppu/ppu.vhd

		@@ -405,7 +405,7 @@ begin
405	405	end process;
406	406
407	407	--cpu and ppu clock timing adjustment...
408		- clk_cnt_set_p : process (rst_n, ce_n, r_nw, cpu_addr, ppu_clk)
	408	+ clk_cnt_set_p : process (rst_n, ce_n, r_nw, cpu_addr, ppu_clk, cpu_d, ppu_clk_cnt, ppu_addr_cnt)
409	409	begin
410	410	if (rst_n = '0') then
411	411	ppu_latch_rst_n <= '0';

--- a/de1_nes/sample1-prg.hex

+++ b/de1_nes/sample1-prg.hex

		@@ -1,13 +1,13 @@
1		-:2000000078A2FF9A20588E200E8EAD868E8500AD878E850120AE8D20AE8D20AE8D20AE8D71
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8		-:2000E000A9038D0E04A9648D0F04A95A8D1004A9648D1104A9038D1204A9328D1304A964DA
9		-:200100008D2004A9658D2104A9038D2204A9C88D2304A91E8D3004A9448D3104A9038D3248
10		-:2001200004A9C88D3304A9048D14406020068EAD458F8500AD468F850120AE8D209C80201F
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	10	+:2001200002A9C88D3302A9028D14406020128EAD518F8500AD528F850120BA8D209C8020F5
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13	13	:2001800003205480A9558D2204A922850AA904850BA9C301F8C9D7F003205480A9558D9E0B

		@@ -22,109 +22,109 @@
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104		-:200CE00080C8C04FF003205480E8E080F003205480A901184AF003205480B0032054804AA3
105		-:200D0000F0032054809003205480A95A4AC92DF003205480A9A5386AC9D2F0032054806A5F
106		-:200D20009003205480C9E9F003205480182A2AC9A5F003205480B00320548008A90048280A
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108		-:200D6000A901AA1003205480D003205480E001F003205480CA8A1003205480F00320548047
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112		-:200DE0006D01038D0103AAAD000390061869018D0003C923D00F8AC9C0D00AA9208D0003DE
113		-:200E0000A9008D010360AD3D9FD00268686020068EA9008D00208D04038D01208D0503A923
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115		-:200E40000F0818280F0C1C2C0F0010200F0616260F0818280F0A1A2AAD3D9FF028A9208D9D
116		-:200E60000003A9018D0103A9008D0203A9008D0303A9008D0403A9008D0503A9008D060303
117		-:200E8000A9008D070360888E72656772657373696F6E20746573742073746172742E2E2EA3
118		-:200EA00000A38E74657374207375636365656465642E2E2E00B78E74657374206661696C31
119		-:200EC000656421212100C88E6164647265737320746573742E2E2E00DA8E73746174757334
120		-:200EE00020746573742E2E2E00EB8E7061676520626F726465722063726F7373696E67202C
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125		-:200F800020696E737420746573742E2E2E00908F613220696E737420746573742E2E2E000F
126		-:200FA000A28F73696E676C65206279746520696E737420746573742E2E2E00000000000062
127		-:200FC000000000000000000000000000000000000000000000000000000000000000000011
	74	+:20092000EAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAEAE8E001F08018A2
	75	+:20094000A964204C89C9C8F00E205480205089602054896069646038A9C84C678969324C63
	76	+:200960006C894C5D8969324C62896932C9FBF00320548038A9C36C79898B89818986899069
	77	+:20098000896C7D8969E669E66C7F896C7B8969E6C9AAF003205480A92348A94648A96E4887
	78	+:2009A000380878081808A9FF08A90008A9FF28F00320548028300320548028900320548041
	79	+:2009C0002828B0032054805868C96EF00320548068C946F00320548068C923F003205480A9
	80	+:2009E00060AD768F8500AD778F850120BA8DA939856BA9A18DCC04A99F85FFA2FD066BA5C6
	81	+:200A00006BC972F003205480CECC04ADCC04C9A0F0032054805ECF03ADCC04C950F0032005
	82	+:200A20005480F602A5FFC9A0F0032054801836023602A5FFC981F003205480387602760271
	83	+:200A4000A5FFC9E0F00320548060AD888F8500AD898F850120BA8DA97885A1A90585A2A942
	84	+:200A6000B7A2E1A08A85A98E990A9D800D941F91A1C5A9F003205480EC990AF003205480D9
	85	+:200A8000CD610EF003205480C400F003205480CD0206F003205480A9F185B0A90585B1A277
	86	+:200AA0007CA9618134ADF105C961F003205480A9AA8520A9048521A0EC8CAA04A21BA105D3
	87	+:200AC000C9ECF00320548060AD9A8F8500AD9B8F850120BA8D18A90D69FAC907F003205493
	88	+:200AE00080A937855EA9C98571A9B6255E2471F003205480A93B8D2104A9D78D1B05A9EB96
	89	+:200B00008DCC06AE2104E88A4D1B05A8CCCC06F003205480A217A0A1A92F8D5903A990990A
	90	+:200B200090018A19900138FD4203A8C068F003205480A2CDA9F18535A9AC85BCA98D356893
	91	+:200B4000A09A592200AAE02DF003205480A9388590A9088591A9D98D0209A90AA0CA1871C5
	92	+:200B600090C9E3F003205480A93385C0A90485C1A9D08D3304A26BA922386155C9F3F0038C
	93	+:200B8000205480A93485C1A90485C2A9F58D3404E8A91F2155C915F003205480A93585C2D7
	94	+:200BA000A90485C3A0758C3504E8A975C155F003205480A93685C3A90485C4A9888D36044E
	95	+:200BC000E8A9C14155C949F003205480A93785C4A90485C5A92E8D3704E8A9910155C9BF75
	96	+:200BE000F003205480A93885C5A90485C6A97F8D3804E8A96A18E155C9EAF00320548060B7
	97	+:200C0000ADAC8F8500ADAD8F850120BA8DA980180AF003205480B0032054801003205480B1
	98	+:200C20000AF00320548090032054801003205480A9400AD0032054809003205480300320A1
	99	+:200C40005480C980F003205480A9A50AC94AF0032054800AC994F003205480A901084828CE
	100	+:200C6000B00320548018900320548028A9400848287003205480B8500320548028A203CAA8
	101	+:200C8000D003205480E002F0032054801003205480CAD003205480E001F003205480100351
	102	+:200CA000205480CAF003205480E000F0032054801003205480CAD003205480300320548009
	103	+:200CC000E0FFF003205480A2803003205480CA1003205480E07FF003205480A05088C04F67
	104	+:200CE000F00320548088C04EF003205480C8C04FF003205480E8E080F003205480A90118E1
	105	+:200D00004AF003205480B0032054804AF0032054809003205480A95A4AC92DF00320548019
	106	+:200D2000A9A5386AC9D2F0032054806A9003205480C9E9F003205480182A2AC9A5F00320CA
	107	+:200D40005480B00320548008A9004828900320548038B0032054807808682904D003205435
	108	+:200D6000805808682904F00320548028A901AA1003205480D003205480E001F00320548005
	109	+:200D8000CA8A1003205480F003205480A901A8C8C898C003F003205480BA8600A2309AA998
	110	+:200DA000DD48BAE02FF003205480A6009AA9EEAD3001C9DDF0032054806020128EAD00034C
	111	+:200DC0008D0620AD01038D0620A000B1008D0720F004C84CCB8D98291FC91FF009A9008DA0
	112	+:200DE0000720C84CD68DAD01038C01036D01038D0103AAAD000390061869018D0003C92324
	113	+:200E0000D00F8AC9C0D00AA9208D0003A9008D010360AD3D9FD00268686020128EA9008D92
	114	+:200E200000208D04038D01208D0503A93F8D0620A9008D0620A200A020BD448E8D0720E837
	115	+:200E400088D0F6600F0010200F0414240F0818280F0C1C2C0F0010200F0616260F081828B9
	116	+:200E60000F0A1A2AAD3D9FF028A9208D0003A9018D0103A9008D0203A9008D0303A9008D33
	117	+:200E80000403A9008D0503A9008D0603A9008D070360948E72656772657373696F6E207437
	118	+:200EA0006573742073746172742E2E2E00AF8E74657374207375636365656465642E2E2EC2
	119	+:200EC00000C38E74657374206661696C656421212100D48E616464726573732074657374F1
	120	+:200EE0002E2E2E00E68E73746174757320746573742E2E2E00F78E7061676520626F7264FD
	121	+:200F000065722063726F7373696E6720746573742E2E2E00168F646D6120746573742E2EF5
	122	+:200F20002E00248F73707269746520746573742E2E2E00358F73696D706C652073707269A3
	123	+:200F4000746520746573742028646D61292E2E2E00538F70707520696E73742074657374B6
	124	+:200F60002E2E2E00668F613520696E737420746573742E2E2E00788F613420696E7374207A
	125	+:200F8000746573742E2E2E008A8F613320696E737420746573742E2E2E009C8F61322069CB
	126	+:200FA0006E737420746573742E2E2E00AE8F73696E676C65206279746520696E737420746D
	127	+:200FC0006573742E2E2E00000000000000000000000000000000000000000000000000003B
128	128	:200FE0000000000000000000000000000000000000000000000000000000000000000000F1
129	129	:201000000000000000000000000000000000000000000000000000000000000000000000D0
130	130	:201020000000000000000000000000000000000000000000000000000000000000000000B0

		@@ -247,11 +247,11 @@
247	247	:201EC0002A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2AC2
248	248	:201EE0002A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2A2C9FEA6C29
249	249	:201F0000FC9E4C2F9F4CFE944CFD954CFC964CFC974CFF984CFC994CFB9A4CF49B4CFC9C30
250		-:201F20004C009D4CFD9D4C019E4CFE9E4C029FADC68E8500ADC78E850120AE8D6001000048
	250	+:201F20004C009D4CFD9D4C019E4CFE9E4C029FADD28E8500ADD38E850120BA8D6001010023
251	251	:201F4000000000000000000000000000000000000000000000000000000000000000000081
252	252	:201F6000000000000000000000000000000000000000000000000000000000000000000061
253	253	:201F8000000000000000000000000000000000000000000000000000000000000000000041
254	254	:201FA000000000000000000000000000000000000000000000000000000000000000000021
255	255	:201FC000000000000000000000000000000000000000000000000000000000000000000001
256		-:201FE00000000000000000000000000000000000000000000000000000007383008000006B
	256	+:201FE00000000000000000000000000000000000000000000000000000007F83008000005F
257	257	:00000001FF

--- a/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do

+++ b/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do

		@@ -40,59 +40,64 @@ add wave -label ea_carry -radix decimal -unsigned sim:/testbench_motones_sim/
40	40
41	41
42	42
43		-add wave -divider regs
44		-
	43	+#add wave -divider regs
	44	+#
45	45	#add wave -label pcl -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_ctrl
46	46	#add wave -label pch -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_mask
47		-
48		-add wave -label acc -radix hex sim:/testbench_motones_sim/sim_board/dbg_acc
49		-add wave -label sp -radix hex sim:/testbench_motones_sim/sim_board/dbg_sp
50		-add wave -label x -radix hex sim:/testbench_motones_sim/sim_board/dbg_x
51		-add wave -label y -radix hex sim:/testbench_motones_sim/sim_board/dbg_y
52		-add wave -label status -radix hex sim:/testbench_motones_sim/sim_board/dbg_status
53		-
54		-
55		-#add wave -divider ppu
56		-#add wave -label ppu_clk sim:/testbench_motones_sim/sim_board/dbg_ppu_clk
57		-#add wave -label ppu_ce_n sim:/testbench_motones_sim/sim_board/dbg_ppu_ce_n
58		-#add wave -label ppu_ctrl -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_ctrl
59		-#add wave -label ppu_mask -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_mask
60		-##add wave -label ppu_status -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_status
61		-#add wave -label ppu_addr -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_addr
62		-#add wave -label ppu_data -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_data
63		-
64		-
65		-###add wave -divider vga_pos
66		-####add wave -label nes_x -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/dbg_ppu_addr
67		-###add wave -label dbg_disp_nt -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_nt
68		-###add wave -label dbg_disp_attr -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_attr
69		-####add wave -label dbg_disp_ptn_h -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_h
70		-####add wave -label dbg_disp_ptn_l -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_l
71		-###
72		-###add wave -divider vram
73		-###add wave -label ale sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x(0)
74		-###add wave -label rd_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x(1)
75		-###add wave -label wr_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x(2)
76		-###add wave -label nt0_ce_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x(3)
77		-###
78		-###add wave -radix hex -label v_addr sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_l
79		-###add wave -radix hex -label vram_ad sim:/testbench_motones_sim/sim_board/dbg_vram_ad
80		-###
81		-###
82		-###add wave -label plt_ce_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(5)
83		-###add wave -label plt_r_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(4)
84		-###add wave -label plt_w_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(3)
85		-###add wave -radix hex -label plt_addr {sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_h(12 downto 8)}
86		-###add wave -radix hex -label plt_data {sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_h(7 downto 0)}
87		-###
88		-###
89		-###
90		-###add wave -divider vga_out
91		-###add wave -label h_sync_n sim:/testbench_motones_sim/sim_board/v_sync_n
92		-###add wave -label v_sync_n sim:/testbench_motones_sim/sim_board/h_sync_n
93		-###add wave -label r -radix hex sim:/testbench_motones_sim/sim_board/r
94		-###add wave -label g -radix hex sim:/testbench_motones_sim/sim_board/g
95		-###add wave -label b -radix hex sim:/testbench_motones_sim/sim_board/b
	47	+#
	48	+#add wave -label acc -radix hex sim:/testbench_motones_sim/sim_board/dbg_acc
	49	+#add wave -label sp -radix hex sim:/testbench_motones_sim/sim_board/dbg_sp
	50	+#add wave -label x -radix hex sim:/testbench_motones_sim/sim_board/dbg_x
	51	+#add wave -label y -radix hex sim:/testbench_motones_sim/sim_board/dbg_y
	52	+#add wave -label status -radix hex sim:/testbench_motones_sim/sim_board/dbg_status
	53	+
	54	+
	55	+add wave -divider ppu
	56	+add wave -label ppu_clk sim:/testbench_motones_sim/sim_board/dbg_ppu_clk
	57	+add wave -label ppu_ce_n sim:/testbench_motones_sim/sim_board/dbg_ppu_ce_n
	58	+add wave -label ppu_ctrl -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_ctrl
	59	+add wave -label ppu_mask -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_mask
	60	+add wave -label ppu_status -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_status
	61	+add wave -label ppu_addr -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_addr
	62	+add wave -label ppu_data -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_data
	63	+
	64	+
	65	+#add wave -divider vga_pos
	66	+##add wave -label nes_x -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/dbg_ppu_addr
	67	+#add wave -label dbg_disp_nt -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_nt
	68	+#add wave -label dbg_disp_attr -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_attr
	69	+##add wave -label dbg_disp_ptn_h -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_h
	70	+##add wave -label dbg_disp_ptn_l -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_l
	71	+#
	72	+add wave -divider vram
	73	+#add wave -label ale sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x(0)
	74	+#add wave -label rd_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x(1)
	75	+#add wave -label wr_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x(2)
	76	+#add wave -label nt0_ce_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x(3)
	77	+
	78	+add wave -radix hex -label v_addr {sim:/testbench_motones_sim/sim_board/dbg_sp(5 downto 0)}
	79	+add wave -radix hex -label vram_ad sim:/testbench_motones_sim/sim_board/dbg_vram_ad
	80	+
	81	+#add wave -label plt_ce_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(5)
	82	+#add wave -label plt_r_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(4)
	83	+#add wave -label plt_w_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(3)
	84	+add wave -label oam_ce_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(2)
	85	+add wave -label oam_r_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(1)
	86	+add wave -label oam_w_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y(0)
	87	+#add wave -radix hex -label plt_addr {sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_h(12 downto 8)}
	88	+#add wave -radix hex -label plt_data {sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_h(7 downto 0)}
	89	+
	90	+
	91	+add wave -divider oam
	92	+add wave -radix hex -label p_oam_addr {sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_l (7 downto 0)}
	93	+add wave -radix hex -label p_oam_data {sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_l (15 downto 8)}
	94	+
	95	+#add wave -divider vga_out
	96	+#add wave -label h_sync_n sim:/testbench_motones_sim/sim_board/v_sync_n
	97	+#add wave -label v_sync_n sim:/testbench_motones_sim/sim_board/h_sync_n
	98	+#add wave -label r -radix hex sim:/testbench_motones_sim/sim_board/r
	99	+#add wave -label g -radix hex sim:/testbench_motones_sim/sim_board/g
	100	+#add wave -label b -radix hex sim:/testbench_motones_sim/sim_board/b
96	101
97	102
98	103	view structure

Binary files a/de1_nes/simulation/modelsim/rom-file.nes and b/de1_nes/simulation/modelsim/rom-file.nes differ

--- a/tools/regression-test/regression.asm

+++ b/tools/regression-test/regression.asm

		@@ -159,47 +159,47 @@ mainloop:
159	159	;;set sprite addr=0C (forth sprite)
160	160	;;set sprite data: y=80
161	161	lda #80
162		- sta $040C
	162	+ sta $020C
163	163	;;tile=0x4d (ascii 'd')
164	164	lda #$64
165		- sta $040D
	165	+ sta $020D
166	166	;;set sprite attr=03 (palette 03)
167	167	lda #$03
168		- sta $040E
	168	+ sta $020E
169	169	;;set sprite data: x=100
170	170	lda #$64
171		- sta $040F
	171	+ sta $020F
172	172
173	173	;;more sprite...
174	174	lda #90
175		- sta $0410
	175	+ sta $0210
176	176	lda #$64
177		- sta $0411
	177	+ sta $0211
178	178	lda #$03
179		- sta $0412
	179	+ sta $0212
180	180	lda #50
181		- sta $0413
	181	+ sta $0213
182	182
183	183	lda #100
184		- sta $0420
	184	+ sta $0220
185	185	lda #$65
186		- sta $0421
	186	+ sta $0221
187	187	lda #$03
188		- sta $0422
	188	+ sta $0222
189	189	lda #200
190		- sta $0423
	190	+ sta $0223
191	191
192	192	lda #30
193		- sta $0430
	193	+ sta $0230
194	194	lda #$44
195		- sta $0431
	195	+ sta $0231
196	196	lda #$03
197		- sta $0432
	197	+ sta $0232
198	198	lda #200
199		- sta $0433
	199	+ sta $0233
200	200
201	201	;;dma start.
202		- lda #$04
	202	+ lda #$02
203	203	sta $4014
204	204
205	205	rts

		@@ -528,6 +528,11 @@ mainloop:
528	528	.endproc
529	529
530	530	.proc dma_test
	531	+ lda full_dma_test
	532	+ bne :+
	533	+ rts
	534	+:
	535	+
531	536	;;dma test data.
532	537	ldy #$00
533	538	ldx #$41

		@@ -536,7 +541,7 @@ mainloop:
536	541	dma_set:
537	542	;;y pos
538	543	txa
539		- sta $0400, y
	544	+ sta $0200, y
540	545	iny
541	546	;;tile index
542	547	lda $00

		@@ -546,23 +551,23 @@ dma_set:
546	551	sta $00
547	552	inc_tile:
548	553	inc $00
549		- sta $0400, y
	554	+ sta $0200, y
550	555	iny
551	556	;;attribute
552	557	lda #$01
553		- sta $0400, y
	558	+ sta $0200, y
554	559	iny
555	560	;;x pos
556	561	txa
557	562	adc #$03
558	563	tax
559	564	rol
560		- sta $0400, y
	565	+ sta $0200, y
561	566	iny
562	567	bne dma_set
563	568
564	569	;;dma start.
565		- lda #$04
	570	+ lda #$02
566	571	sta $4014
567	572
568	573	jsr check_ppu

		@@ -576,15 +581,20 @@ inc_tile:
576	581	.endproc
577	582
578	583
579		-.proc set_dma
	584	+.proc update_dma
	585	+ lda full_dma_test
	586	+ bne :+
	587	+ rts
	588	+:
	589	+
580	590	ldy #0
581	591
582	592	y_loop:
583		- lda $0400, y
	593	+ lda $0200, y
584	594
585	595	clc
586	596	adc #$1
587		- sta $0400, y
	597	+ sta $0200, y
588	598
589	599	iny
590	600	iny

		@@ -594,7 +604,7 @@ y_loop:
594	604	bne y_loop
595	605
596	606	;;dma start.
597		- lda #$04
	607	+ lda #$02
598	608	sta $4014
599	609
600	610	rts

		@@ -603,7 +613,7 @@ y_loop:
603	613	nmi_test:
604	614	jsr update_counter
605	615	jsr update_scroll
606		- jsr set_dma
	616	+ jsr update_dma
607	617
608	618	rti
609	619

		@@ -3214,6 +3224,9 @@ ad_single_test:
3214	3224	use_ppu:
3215	3225	.byte $01
3216	3226
	3227	+full_dma_test:
	3228	+ .byte $01
	3229	+
3217	3230	;;;;r/w global variables.
3218	3231	.segment "BSS"
3219	3232	vram_current:

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