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/[naniya]/trunk/Toriya/clockgen.v

Contents of /trunk/Toriya/clockgen.v

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Revision 118 - (show annotations) (download)
Wed Apr 11 04:55:06 2007 UTC (17 years, 1 month ago) by chapuni
File size: 12525 byte(s) 
「本物の鳥屋」ついに公開です。
たぶん 2005/09 頃のものです。
もしかするとあと一度ほど、改良するかもね。
1 // megafunction wizard: %ALTPLL%
2 // GENERATION: STANDARD
3 // VERSION: WM1.0
4 // MODULE: altpll
5
6 // ============================================================
7 // File Name: clockgen.v
8 // Megafunction Name(s):
9 // altpll
10 // ============================================================
11 // ************************************************************
12 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
13 //
14 // 5.0 Build 148 04/26/2005 SJ Web Edition
15 // ************************************************************
16
17
18 //Copyright (C) 1991-2005 Altera Corporation
19 //Your use of Altera Corporation's design tools, logic functions
20 //and other software and tools, and its AMPP partner logic
21 //functions, and any output files any of the foregoing
22 //(including device programming or simulation files), and any
23 //associated documentation or information are expressly subject
24 //to the terms and conditions of the Altera Program License
25 //Subscription Agreement, Altera MegaCore Function License
26 //Agreement, or other applicable license agreement, including,
27 //without limitation, that your use is for the sole purpose of
28 //programming logic devices manufactured by Altera and sold by
29 //Altera or its authorized distributors. Please refer to the
30 //applicable agreement for further details.
31
32
33 // synopsys translate_off
34 `timescale 1 ps / 1 ps
35 // synopsys translate_on
36 module clockgen (
37 inclk0,
38 c0,
39 c1,
40 c2,
41 locked);
42
43 input inclk0;
44 output c0;
45 output c1;
46 output c2;
47 output locked;
48
49 wire [5:0] sub_wire0;
50 wire sub_wire4;
51 wire [0:0] sub_wire5 = 1'h1;
52 wire [0:0] sub_wire7 = 1'h0;
53 wire [2:2] sub_wire3 = sub_wire0[2:2];
54 wire [1:1] sub_wire2 = sub_wire0[1:1];
55 wire [0:0] sub_wire1 = sub_wire0[0:0];
56 wire c0 = sub_wire1;
57 wire c1 = sub_wire2;
58 wire c2 = sub_wire3;
59 wire locked = sub_wire4;
60 wire [5:0] sub_wire6 = {sub_wire7, sub_wire7, sub_wire7, sub_wire5, sub_wire5, sub_wire5};
61 wire sub_wire8 = inclk0;
62 wire [1:0] sub_wire9 = {sub_wire7, sub_wire8};
63 wire [3:0] sub_wire10 = {sub_wire7, sub_wire7, sub_wire7, sub_wire7};
64
65 altpll altpll_component (
66 .clkena (sub_wire6),
67 .inclk (sub_wire9),
68 .extclkena (sub_wire10),
69 .clk (sub_wire0),
70 .locked (sub_wire4)
71 // synopsys translate_off
72 ,
73 .activeclock (),
74 .areset (),
75 .clkbad (),
76 .clkloss (),
77 .clkswitch (),
78 .enable0 (),
79 .enable1 (),
80 .extclk (),
81 .fbin (),
82 .pfdena (),
83 .pllena (),
84 .scanaclr (),
85 .scanclk (),
86 .scandata (),
87 .scandataout (),
88 .scandone (),
89 .scanread (),
90 .scanwrite (),
91 .sclkout0 (),
92 .sclkout1 ()
93 // synopsys translate_on
94 );
95 defparam
96 altpll_component.clk1_divide_by = 1,
97 altpll_component.bandwidth_type = "AUTO",
98 altpll_component.clk1_phase_shift = "0",
99 altpll_component.clk0_duty_cycle = 50,
100 altpll_component.lpm_type = "altpll",
101 altpll_component.clk0_multiply_by = 5,
102 altpll_component.invalid_lock_multiplier = 5,
103 altpll_component.inclk0_input_frequency = 30000,
104 altpll_component.clk0_divide_by = 1,
105 altpll_component.clk1_duty_cycle = 50,
106 altpll_component.pll_type = "AUTO",
107 altpll_component.clk2_phase_shift = "-6000",
108 altpll_component.valid_lock_multiplier = 1,
109 altpll_component.clk1_multiply_by = 1,
110 altpll_component.spread_frequency = 0,
111 altpll_component.intended_device_family = "Stratix",
112 altpll_component.clk2_divide_by = 1,
113 altpll_component.operation_mode = "NORMAL",
114 altpll_component.clk2_duty_cycle = 20,
115 altpll_component.compensate_clock = "CLK0",
116 altpll_component.clk0_phase_shift = "0",
117 altpll_component.clk2_multiply_by = 1;
118
119
120 endmodule
121
122 // ============================================================
123 // CNX file retrieval info
124 // ============================================================
125 // Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
126 // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
127 // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
128 // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
129 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
130 // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
131 // Retrieval info: PRIVATE: SPREAD_USE STRING "0"
132 // Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "1"
133 // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
134 // Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "10000"
135 // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
136 // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
137 // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
138 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
139 // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
140 // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
141 // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "5"
142 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
143 // Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
144 // Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
145 // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
146 // Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
147 // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
148 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
149 // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
150 // Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
151 // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "5"
152 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
153 // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
154 // Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
155 // Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
156 // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
157 // Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "20.00000000"
158 // Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-72.00000000"
159 // Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "5"
160 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
161 // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
162 // Retrieval info: PRIVATE: SPREAD_FREQ STRING "300.000"
163 // Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
164 // Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
165 // Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
166 // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
167 // Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
168 // Retrieval info: PRIVATE: USE_CLK0 STRING "1"
169 // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
170 // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
171 // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
172 // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
173 // Retrieval info: PRIVATE: USE_CLK1 STRING "1"
174 // Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
175 // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "32.000"
176 // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
177 // Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
178 // Retrieval info: PRIVATE: USE_CLK2 STRING "1"
179 // Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
180 // Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
181 // Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "ns"
182 // Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
183 // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
184 // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e1"
185 // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
186 // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
187 // Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
188 // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
189 // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
190 // Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "5"
191 // Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
192 // Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
193 // Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
194 // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "300.000"
195 // Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "5"
196 // Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
197 // Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
198 // Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
199 // Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "30.000"
200 // Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
201 // Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
202 // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
203 // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
204 // Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
205 // Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
206 // Retrieval info: PRIVATE: DEV_FAMILY STRING "Stratix"
207 // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.000"
208 // Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
209 // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
210 // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
211 // Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
212 // Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
213 // Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.000"
214 // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
215 // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps"
216 // Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
217 // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
218 // Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
219 // Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
220 // Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
221 // Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "9"
222 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
223 // Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
224 // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
225 // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
226 // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
227 // Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
228 // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5"
229 // Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
230 // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30000"
231 // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
232 // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
233 // Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
234 // Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-6000"
235 // Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
236 // Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
237 // Retrieval info: CONSTANT: SPREAD_FREQUENCY NUMERIC "0"
238 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix"
239 // Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
240 // Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
241 // Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "20"
242 // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
243 // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
244 // Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
245 // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
246 // Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
247 // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT VCC "c1"
248 // Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT VCC "c2"
249 // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
250 // Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
251 // Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
252 // Retrieval info: CONNECT: @clkena 0 0 1 1 VCC 0 0 0 0
253 // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
254 // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
255 // Retrieval info: CONNECT: @extclkena 0 0 1 1 GND 0 0 0 0
256 // Retrieval info: CONNECT: @clkena 0 0 1 4 GND 0 0 0 0
257 // Retrieval info: CONNECT: @clkena 0 0 1 2 VCC 0 0 0 0
258 // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
259 // Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
260 // Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
261 // Retrieval info: CONNECT: @extclkena 0 0 1 2 GND 0 0 0 0
262 // Retrieval info: CONNECT: @clkena 0 0 1 5 GND 0 0 0 0
263 // Retrieval info: CONNECT: @clkena 0 0 1 0 VCC 0 0 0 0
264 // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
265 // Retrieval info: CONNECT: @extclkena 0 0 1 3 GND 0 0 0 0
266 // Retrieval info: CONNECT: @extclkena 0 0 1 0 GND 0 0 0 0
267 // Retrieval info: CONNECT: @clkena 0 0 1 3 GND 0 0 0 0
268 // Retrieval info: GEN_FILE: TYPE_NORMAL clockgen.v TRUE FALSE
269 // Retrieval info: GEN_FILE: TYPE_NORMAL clockgen.inc FALSE FALSE
270 // Retrieval info: GEN_FILE: TYPE_NORMAL clockgen.cmp FALSE FALSE
271 // Retrieval info: GEN_FILE: TYPE_NORMAL clockgen.bsf FALSE FALSE
272 // Retrieval info: GEN_FILE: TYPE_NORMAL clockgen_inst.v FALSE FALSE
273 // Retrieval info: GEN_FILE: TYPE_NORMAL clockgen_bb.v TRUE FALSE

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