trunk/Toriya/cmp9.v

/**********************************************************-*-verilog-*-
 *
 *      9AČăđTľoˇComparator
 *
 *      $Id$
 *
 */

module cmp9(input [0:65]        blk,
                        output                  matched);

        wire [5:0]              c0, c1, c2, c3, c4, c5, c6, c7, c8, c9;
        wire                    m7;

        assign                  {c0, c1, c2, c3, c4,
                                         c5, c6, c7, c8, c9} = blk[6:65];

        assign                  m7 = (c1 == c2
                                                  && c2 == c3
                                                  && c3 == c4
                                                  && c4 == c5
                                                  && c5 == c6
                                                  && c6 == c7
                                                  && c7 == c8);

        assign                  matched = ((c0 == c1 && m7)
                                                           || (m7 && c8 == c9));
endmodule

/*
 *  Local variables:
 *  tab-width: 4
 *  End:
 */