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Contents of /trunk/Toriya/s11x4.v

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Revision 118 - (show annotations) (download)
Wed Apr 11 04:55:06 2007 UTC (17 years, 1 month ago) by chapuni
File size: 9274 byte(s) 
「本物の鳥屋」ついに公開です。
たぶん 2005/09 頃のものです。
もしかするとあと一度ほど、改良するかもね。
1 // megafunction wizard: %RAM: 2-PORT%
2 // GENERATION: STANDARD
3 // VERSION: WM1.0
4 // MODULE: altsyncram
5
6 // ============================================================
7 // File Name: s11x4.v
8 // Megafunction Name(s):
9 // altsyncram
10 // ============================================================
11 // ************************************************************
12 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
13 // ************************************************************
14
15
16 //Copyright (C) 1991-2003 Altera Corporation
17 //Any megafunction design, and related netlist (encrypted or decrypted),
18 //support information, device programming or simulation file, and any other
19 //associated documentation or information provided by Altera or a partner
20 //under Altera's Megafunction Partnership Program may be used only
21 //to program PLD devices (but not masked PLD devices) from Altera. Any
22 //other use of such megafunction design, netlist, support information,
23 //device programming or simulation file, or any other related documentation
24 //or information is prohibited for any other purpose, including, but not
25 //limited to modification, reverse engineering, de-compiling, or use with
26 //any other silicon devices, unless such use is explicitly licensed under
27 //a separate agreement with Altera or a megafunction partner. Title to the
28 //intellectual property, including patents, copyrights, trademarks, trade
29 //secrets, or maskworks, embodied in any such megafunction design, netlist,
30 //support information, device programming or simulation file, or any other
31 //related documentation or information provided by Altera or a megafunction
32 //partner, remains with Altera, the megafunction partner, or their respective
33 //licensors. No other licenses, including any licenses needed under any third
34 //party's intellectual property, are provided herein.
35
36
37 module s11x4 (
38 data_a,
39 wren_a,
40 address_a,
41 data_b,
42 address_b,
43 wren_b,
44 clock,
45 q_a,
46 q_b);
47
48 input [3:0] data_a;
49 input wren_a;
50 input [9:0] address_a;
51 input [3:0] data_b;
52 input [9:0] address_b;
53 input wren_b;
54 input clock;
55 output [3:0] q_a;
56 output [3:0] q_b;
57
58 wire [3:0] sub_wire0;
59 wire [3:0] sub_wire1;
60 wire [3:0] q_a = sub_wire0[3:0];
61 wire [3:0] q_b = sub_wire1[3:0];
62
63 altsyncram altsyncram_component (
64 .wren_a (wren_a),
65 .clock0 (clock),
66 .wren_b (wren_b),
67 .address_a (address_a),
68 .address_b (address_b),
69 .data_a (data_a),
70 .data_b (data_b),
71 .q_a (sub_wire0),
72 .q_b (sub_wire1));
73 defparam
74 altsyncram_component.intended_device_family = "Stratix",
75 altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
76 altsyncram_component.width_a = 4,
77 altsyncram_component.widthad_a = 10,
78 altsyncram_component.numwords_a = 1024,
79 altsyncram_component.width_b = 4,
80 altsyncram_component.widthad_b = 10,
81 altsyncram_component.numwords_b = 1024,
82 altsyncram_component.lpm_type = "altsyncram",
83 altsyncram_component.width_byteena_a = 1,
84 altsyncram_component.width_byteena_b = 1,
85 altsyncram_component.outdata_reg_a = "CLOCK0",
86 altsyncram_component.outdata_aclr_a = "NONE",
87 altsyncram_component.outdata_reg_b = "CLOCK0",
88 altsyncram_component.indata_aclr_a = "NONE",
89 altsyncram_component.wrcontrol_aclr_a = "NONE",
90 altsyncram_component.address_aclr_a = "NONE",
91 altsyncram_component.indata_reg_b = "CLOCK0",
92 altsyncram_component.address_reg_b = "CLOCK0",
93 altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0",
94 altsyncram_component.indata_aclr_b = "NONE",
95 altsyncram_component.wrcontrol_aclr_b = "NONE",
96 altsyncram_component.address_aclr_b = "NONE",
97 altsyncram_component.outdata_aclr_b = "NONE",
98 altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
99 altsyncram_component.ram_block_type = "M4K",
100 altsyncram_component.init_file = "s1x4.mif";
101
102
103 endmodule
104
105 // ============================================================
106 // CNX file retrieval info
107 // ============================================================
108 // Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
109 // Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
110 // Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
111 // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix"
112 // Retrieval info: PRIVATE: VarWidth NUMERIC "0"
113 // Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "4"
114 // Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "4"
115 // Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "4"
116 // Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "4"
117 // Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
118 // Retrieval info: PRIVATE: Clock NUMERIC "0"
119 // Retrieval info: PRIVATE: rden NUMERIC "0"
120 // Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
121 // Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
122 // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
123 // Retrieval info: PRIVATE: Clock_A NUMERIC "0"
124 // Retrieval info: PRIVATE: Clock_B NUMERIC "0"
125 // Retrieval info: PRIVATE: REGdata NUMERIC "1"
126 // Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
127 // Retrieval info: PRIVATE: REGwren NUMERIC "1"
128 // Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
129 // Retrieval info: PRIVATE: REGrren NUMERIC "0"
130 // Retrieval info: PRIVATE: REGq NUMERIC "1"
131 // Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
132 // Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
133 // Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
134 // Retrieval info: PRIVATE: CLRdata NUMERIC "0"
135 // Retrieval info: PRIVATE: CLRwren NUMERIC "0"
136 // Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
137 // Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
138 // Retrieval info: PRIVATE: CLRrren NUMERIC "0"
139 // Retrieval info: PRIVATE: CLRq NUMERIC "0"
140 // Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
141 // Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
142 // Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
143 // Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
144 // Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
145 // Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
146 // Retrieval info: PRIVATE: enable NUMERIC "0"
147 // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
148 // Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
149 // Retrieval info: PRIVATE: MIFfilename STRING "C:/usr/chapuni/trip/exp/trip_ram/s1x4.mif"
150 // Retrieval info: PRIVATE: UseLCs NUMERIC "0"
151 // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
152 // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "256"
153 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix"
154 // Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
155 // Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
156 // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
157 // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
158 // Retrieval info: CONSTANT: WIDTH_B NUMERIC "4"
159 // Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
160 // Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
161 // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
162 // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
163 // Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
164 // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
165 // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
166 // Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
167 // Retrieval info: CONSTANT: INDATA_ACLR_A STRING "NONE"
168 // Retrieval info: CONSTANT: WRCONTROL_ACLR_A STRING "NONE"
169 // Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
170 // Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
171 // Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
172 // Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
173 // Retrieval info: CONSTANT: INDATA_ACLR_B STRING "NONE"
174 // Retrieval info: CONSTANT: WRCONTROL_ACLR_B STRING "NONE"
175 // Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
176 // Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
177 // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
178 // Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M4K"
179 // Retrieval info: CONSTANT: INIT_FILE STRING "C:/usr/chapuni/trip/exp/trip_ram/s1x4.mif"
180 // Retrieval info: USED_PORT: data_a 0 0 4 0 INPUT NODEFVAL data_a[3..0]
181 // Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
182 // Retrieval info: USED_PORT: q_a 0 0 4 0 OUTPUT NODEFVAL q_a[3..0]
183 // Retrieval info: USED_PORT: q_b 0 0 4 0 OUTPUT NODEFVAL q_b[3..0]
184 // Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL address_a[9..0]
185 // Retrieval info: USED_PORT: data_b 0 0 4 0 INPUT NODEFVAL data_b[3..0]
186 // Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL address_b[9..0]
187 // Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
188 // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
189 // Retrieval info: CONNECT: @data_a 0 0 4 0 data_a 0 0 4 0
190 // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
191 // Retrieval info: CONNECT: q_a 0 0 4 0 @q_a 0 0 4 0
192 // Retrieval info: CONNECT: q_b 0 0 4 0 @q_b 0 0 4 0
193 // Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0
194 // Retrieval info: CONNECT: @data_b 0 0 4 0 data_b 0 0 4 0
195 // Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0
196 // Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
197 // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
198 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all

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