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// megafunction wizard: %ROM% |
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// GENERATION: STANDARD |
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// VERSION: WM1.0 |
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// MODULE: altsyncram |
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|
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// ============================================================ |
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// File Name: srom7x1.v |
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// Megafunction Name(s): |
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// altsyncram |
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// ============================================================ |
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// ************************************************************ |
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! |
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// ************************************************************ |
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|
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|
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//Copyright (C) 1991-2003 Altera Corporation |
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//Any megafunction design, and related netlist (encrypted or decrypted), |
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//support information, device programming or simulation file, and any other |
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//associated documentation or information provided by Altera or a partner |
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//under Altera's Megafunction Partnership Program may be used only |
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//to program PLD devices (but not masked PLD devices) from Altera. Any |
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//other use of such megafunction design, netlist, support information, |
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//device programming or simulation file, or any other related documentation |
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//or information is prohibited for any other purpose, including, but not |
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//limited to modification, reverse engineering, de-compiling, or use with |
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//any other silicon devices, unless such use is explicitly licensed under |
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//a separate agreement with Altera or a megafunction partner. Title to the |
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//intellectual property, including patents, copyrights, trademarks, trade |
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//secrets, or maskworks, embodied in any such megafunction design, netlist, |
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//support information, device programming or simulation file, or any other |
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//related documentation or information provided by Altera or a megafunction |
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//partner, remains with Altera, the megafunction partner, or their respective |
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//licensors. No other licenses, including any licenses needed under any third |
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//party's intellectual property, are provided herein. |
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|
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|
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module srom7x1 ( |
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address, |
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clock, |
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q); |
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|
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input [6:0] address; |
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input clock; |
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output [3:0] q; |
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|
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wire [3:0] sub_wire0; |
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wire [3:0] q = sub_wire0[3:0]; |
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|
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altsyncram altsyncram_component ( |
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.clock0 (clock), |
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.address_a (address), |
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.q_a (sub_wire0)); |
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defparam |
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altsyncram_component.intended_device_family = "Stratix", |
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altsyncram_component.width_a = 4, |
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altsyncram_component.widthad_a = 7, |
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altsyncram_component.numwords_a = 128, |
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altsyncram_component.operation_mode = "ROM", |
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altsyncram_component.outdata_reg_a = "UNREGISTERED", |
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altsyncram_component.address_aclr_a = "NONE", |
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altsyncram_component.outdata_aclr_a = "NONE", |
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altsyncram_component.width_byteena_a = 1, |
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altsyncram_component.init_file = "s7x1.mif", |
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altsyncram_component.lpm_type = "altsyncram"; |
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|
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|
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endmodule |
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|
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// ============================================================ |
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// CNX file retrieval info |
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// ============================================================ |
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// Retrieval info: PRIVATE: WidthData NUMERIC "4" |
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// Retrieval info: PRIVATE: WidthAddr NUMERIC "7" |
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix" |
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// Retrieval info: PRIVATE: SingleClock NUMERIC "1" |
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// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" |
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// Retrieval info: PRIVATE: RegAddr NUMERIC "1" |
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// Retrieval info: PRIVATE: RegOutput NUMERIC "0" |
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// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" |
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// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" |
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// Retrieval info: PRIVATE: AclrByte NUMERIC "0" |
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// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" |
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// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" |
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// Retrieval info: PRIVATE: Clken NUMERIC "0" |
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// Retrieval info: PRIVATE: MIFfilename STRING "C:/usr/chapuni/altera/exp/trip_ram/s7x1.mif" |
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix" |
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// Retrieval info: CONSTANT: WIDTH_A NUMERIC "4" |
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// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "7" |
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// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "128" |
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// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" |
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// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" |
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// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" |
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// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" |
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// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" |
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// Retrieval info: CONSTANT: INIT_FILE STRING "C:/usr/chapuni/altera/exp/trip_ram/s7x1.mif" |
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// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" |
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// Retrieval info: USED_PORT: address 0 0 7 0 INPUT NODEFVAL address[6..0] |
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// Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL q[3..0] |
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// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock |
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// Retrieval info: CONNECT: @address_a 0 0 7 0 address 0 0 7 0 |
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// Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0 |
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// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 |
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// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all |