| 1 |
/**********************************************************-*-verilog-*- |
| 2 |
* |
| 3 |
* Project: TORIYA -鳥屋- |
| 4 |
* THE TOP MODULE of TRIP for the Legacy Serial |
| 5 |
* $Id$ |
| 6 |
* |
| 7 |
*/ |
| 8 |
|
| 9 |
module top_ser(CLK1P, CLK4P, CLK14P, |
| 10 |
TxD1, RTS1, RxD1, CTS1, |
| 11 |
SWIN, |
| 12 |
LEDDB, LEDOEN); |
| 13 |
|
| 14 |
input CLK1P; // on-board clock generator |
| 15 |
input CLK4P; // same as CLK1P |
| 16 |
input CLK14P; // same as CLK1P |
| 17 |
output TxD1; |
| 18 |
output RTS1; |
| 19 |
input RxD1; |
| 20 |
input CTS1; |
| 21 |
input [1:5] SWIN; // functional switch |
| 22 |
output [7:0] LEDDB; |
| 23 |
output [4:0] LEDOEN; |
| 24 |
|
| 25 |
`include "func_des.v" |
| 26 |
`include "func_salt.v" |
| 27 |
`include "func_util.v" |
| 28 |
|
| 29 |
// この回路で使用する比較器の個数!!! |
| 30 |
parameter NCAP = 54; // これでもキツい |
| 31 |
parameter NCTH = 0; |
| 32 |
|
| 33 |
// Salt固定で、鳥屋トリップをひねり出すかどうか |
| 34 |
parameter SALT_MSB = 1'b0; |
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|
| 36 |
// リセットは、回路内にて正論理で使用する。 |
| 37 |
wire clk_locked; |
| 38 |
wire serclk_locked; |
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wire rst = !SWIN[5] || !clk_locked || !serclk_locked; |
| 40 |
reg trip_rstgo; |
| 41 |
wire trip_rst = rst || trip_rstgo; |
| 42 |
|
| 43 |
// x5 PLL |
| 44 |
wire clk, clk5, st_gate; |
| 45 |
clockgen pllx5(CLK4P, clk5, clk, st_gate, clk_locked); |
| 46 |
|
| 47 |
// Serial clock |
| 48 |
wire txclk, rxclk, hostclk, ledclk; |
| 49 |
wire serclk16; |
| 50 |
serclockgen serclkx16(CLK14P, serclk16, serclk_locked); |
| 51 |
reg [12:0] serclk_div; |
| 52 |
assign hostclk = serclk_div[1]; // 1/4 |
| 53 |
assign rxclk = serclk_div[1]; // 1/4 |
| 54 |
assign txclk = serclk_div[3]; // 1/16 |
| 55 |
assign ledclk = serclk_div[12]; // たぶん225Hz |
| 56 |
|
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// FIFO |
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wire [55:0] fifo_data; |
| 59 |
reg fifo_rdreq; |
| 60 |
wire fifo_wrreq; |
| 61 |
wire [55:0] fifo_q; |
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wire fifo_rdempty; |
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wire [12:0] fifo_usedw; |
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wire fifo_wrfull; |
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kfifo fifo1(fifo_data, fifo_wrreq, fifo_rdreq, |
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hostclk, clk, rst, |
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fifo_q, fifo_rdempty, fifo_usedw, |
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fifo_wrfull); |
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|
| 70 |
// LED driver |
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wire [7:0] led_d8; |
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wire [15:0] led_h8b; |
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wire [3:0] led_d4; |
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leddrv4 led7sg(ledclk, rst, |
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LEDDB, LEDOEN, |
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led_h8b[15:12], |
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led_h8b[11: 8], |
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led_h8b[ 7: 4], |
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led_h8b[ 3: 0], |
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led_d4[3], |
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led_d4[2], |
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led_d4[1], |
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led_d4[0]); |
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|
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// Serial clock generator(serclk16 = 32MHz * 36 / 625) |
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always @(posedge serclk16) |
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serclk_div <= serclk_div + 1; |
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|
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// Serial Rx driver |
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wire [7:0] rxdata; |
| 91 |
wire rxrdy; |
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reg rxack; |
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rxdriver rxdrv1(rxclk, rst, RxD1, RTS1, rxrdy, rxdata, rxack); |
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|
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// Serial Tx Driver |
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reg [7:0] txdata; |
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reg txwe; |
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wire txrdy; |
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txdriver txdrv1(txclk, rst, TxD1, CTS1, txwe, txdata, txrdy); |
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|
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// TRIP ENGINE |
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reg tripper_ken; |
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reg tripper_wait; |
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reg [11:0] salt; |
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reg [27:0] kl, kr; |
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wire [27:0] kli, kri; |
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wire tripper_bsy; |
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wire tripper_oen; |
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wire [55:0] o_k; |
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wire [1:64] o_h; |
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|
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parameter krstep = 28'b0000_0001_0000_0000_000_000_000_000; |
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parameter krmask = 28'b0000_0000_1111_1111_111_111_111_111; |
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assign {kli, kri} = {kl, kr} + {28'b0, krstep}; |
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|
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crypt22 #(krmask) |
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tripper(rst, |
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clk, clk5, st_gate, |
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tripper_ken, salt, {kr, kl}, |
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tripper_bsy, |
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tripper_oen, o_k, o_h); |
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|
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// まずはタイミング的に厳しい o_h を取り出してしまう |
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reg men0; |
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reg [55:0] fk0; |
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reg [1:66] fh0; |
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always @(posedge clk) |
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begin |
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men0 <= tripper_oen; |
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fk0 <= kmux({krmask, 28'b0}, |
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{kr, kl}, |
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o_k); |
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fh0 <= {o_h, 2'b0}; |
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end |
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|
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// 比較器マシーン(組み合わせ回路) |
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wire matched; |
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reg c_we; // pulse |
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reg [55:0] fk1; |
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reg [7:0] c_wu; |
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reg [7:0] c_txd; |
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comparators #(NCAP, NCTH) |
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cmps(rst, |
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clk, |
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men0, |
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fk0, fh0, // 区別ありキー |
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fk1, matched, // ヒット結果 |
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hostclk, |
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c_we, c_wu, c_txd); |
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|
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assign fifo_wrreq = matched; |
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assign fifo_data = pc1(fk1); |
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|
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// FIFO は、rdreq から１サイクル遅れで出てくる! |
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reg fifo_rdrdy; |
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|
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// コマンド一覧 |
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parameter CMD_READY = 8'b0000_0001; |
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parameter CMD_RESET = 8'b0000_0011; |
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parameter CMD_GETCAP = 8'b0000_0111; |
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parameter CMD_TEXT = 8'b0000_1101; |
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parameter CMD_STANDBY = 8'b0000_1111; |
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parameter CMD_SETCOND = 2'b01; |
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parameter CMD_SETKEY = 8'b1000_0000; |
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|
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// コマンドのステートなど |
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reg [3:0] st_cmd; |
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parameter ST_CMD_STANDBY = 4'b0000; |
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parameter ST_CMD_READY = 4'b0001; |
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parameter ST_CMD_TEXT = 4'b0010; |
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parameter ST_CMD_GETTING_CAP = 4'b1000; |
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parameter ST_CMD_SENDING = 4'b1001; |
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parameter ST_CMD_TEXT_SENDING = 4'b1010; |
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parameter ST_CMD_SETTING_COND = 4'b1011; |
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parameter ST_CMD_SETTING_KEY1 = 4'b1101; |
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parameter ST_CMD_SETTING_KEY2 = 4'b1110; |
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parameter ST_CMD_SETTING_KEY3 = 4'b1111; |
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|
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// 送信するための一時レジスタ |
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reg [4:0] st_send; // 0..16 |
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reg [63:0] found_key; |
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|
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wire rdy_led; |
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assign rdy_led = !fifo_rdempty || st_cmd == ST_CMD_READY; |
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|
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// 状態のレポートLED |
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assign led_d8 = {1'b0, |
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1'b0, |
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1'b0, |
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1'b0, |
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1'b0, |
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1'b0, |
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1'b0, |
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1'b0}; |
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assign led_h8b = (SWIN[1] ? kl[27:12] |
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: SWIN[4] ? kr[23: 8] |
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: SWIN[2] ? {3'b0, fifo_usedw} |
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: {kl[11:0], kr[27:24]}); |
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assign led_d4 = {1'b0, |
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rdy_led, |
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~CTS1 & ~kr[23], |
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fifo_wrfull}; |
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|
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/* |
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* ホストインタフェイス。なんとなくserclk基準で回してみる |
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*/ |
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always @(posedge hostclk or posedge rst) |
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if (rst) |
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begin |
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// reset |
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fifo_rdreq <= 0; |
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fifo_rdrdy <= 0; |
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txwe <= 0; |
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rxack <= 0; |
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trip_rstgo <= 0; |
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st_cmd <= ST_CMD_STANDBY; |
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tripper_ken <= 0; |
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tripper_wait <= 0; |
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kl <= 28'b0; |
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kr <= 28'b0; |
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c_we <= 0; |
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c_wu <= 0; |
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found_key <= 0; |
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end |
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else |
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begin |
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/* |
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* キーまわし |
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*/ |
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if (!tripper_ken && !tripper_bsy && !tripper_wait) |
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begin |
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tripper_ken <= 1; |
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end |
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else if (tripper_ken && tripper_bsy && !tripper_wait) |
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begin |
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tripper_wait <= 1; |
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end |
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else if (tripper_ken && !tripper_bsy && tripper_wait) |
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begin |
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tripper_wait <= 0; |
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tripper_ken <= 0; |
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{kl, kr} <= {kli, kri}; |
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salt <= {mksalt({SALT_MSB, kli[24:22], kri[23:20]}), |
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mksalt({SALT_MSB, kli[27:25], kri[27:24]})}; |
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end |
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|
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/* |
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* コマンド受信 |
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*/ |
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if (st_cmd == ST_CMD_STANDBY |
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//|| st_cmd == ST_CMD_TEXT |
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|| st_cmd == ST_CMD_READY) |
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begin |
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if (!c_we && rxrdy && !rxack) |
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case (rxdata) |
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CMD_RESET: |
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begin |
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rxack <= 1; |
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trip_rstgo <= 1; |
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st_cmd <= ST_CMD_STANDBY; |
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end |
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CMD_READY: |
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begin |
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rxack <= 1; |
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st_cmd <= ST_CMD_READY; |
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end |
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CMD_STANDBY: |
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begin |
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// キーを報告してスタンバイへ |
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rxack <= 1; |
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st_cmd <= ST_CMD_STANDBY; |
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end |
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/* |
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CMD_TEXT: |
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begin |
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rxack <= 1; |
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st_cmd <= ST_CMD_TEXT; |
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end |
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*/ |
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CMD_GETCAP: |
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if (txrdy && !txwe) |
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begin |
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rxack <= 1; |
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st_cmd <= ST_CMD_GETTING_CAP; |
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|
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// コンパレータの総数を送る |
| 287 |
// まずはこれを送ってしまう |
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txdata[5:0] <= NCAP; |
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txdata[7:6] <= 2'b0; |
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txwe <= 1; |
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c_wu <= 0; |
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end |
| 293 |
CMD_SETKEY: |
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begin |
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st_cmd <= ST_CMD_SETTING_KEY1; |
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rxack <= 1; |
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end |
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default: |
| 299 |
case (rxdata[7:6]) |
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CMD_SETCOND: |
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begin |
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// スロット#を受け取る |
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c_wu <= {2'b0, rxdata[5:0]}; |
| 304 |
st_cmd <= ST_CMD_SETTING_COND; |
| 305 |
rxack <= 1; |
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end |
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default: |
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rxack <= 1; // 読み捨て |
| 309 |
endcase |
| 310 |
endcase |
| 311 |
end |
| 312 |
/* |
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* コマンド処理 |
| 314 |
*/ |
| 315 |
case (st_cmd) |
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ST_CMD_GETTING_CAP: |
| 317 |
if (txrdy && !txwe) |
| 318 |
begin |
| 319 |
st_cmd <= ST_CMD_STANDBY; |
| 320 |
/* |
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// 後続に、能力を、知らせた分だけ送る |
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txdata <= c_cap; |
| 323 |
txwe <= 1; |
| 324 |
if (c_wu == NCAP - 1) |
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st_cmd <= ST_CMD_STANDBY; |
| 326 |
c_wu <= c_wu + 1; |
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*/ |
| 328 |
end |
| 329 |
ST_CMD_SETTING_KEY1: |
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// KEY は、NETWORK ORDERの逆(shit!) |
| 331 |
if (rxrdy && !rxack) |
| 332 |
begin |
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kl[11: 4] <= rxdata; |
| 334 |
rxack <= 1; |
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st_cmd <= ST_CMD_SETTING_KEY2; |
| 336 |
end |
| 337 |
ST_CMD_SETTING_KEY2: |
| 338 |
if (rxrdy && !rxack) |
| 339 |
begin |
| 340 |
kl[19:12] <= rxdata; |
| 341 |
rxack <= 1; |
| 342 |
st_cmd <= ST_CMD_SETTING_KEY3; |
| 343 |
end |
| 344 |
ST_CMD_SETTING_KEY3: |
| 345 |
if (rxrdy && !rxack) |
| 346 |
begin |
| 347 |
kl[27:20] <= rxdata; |
| 348 |
rxack <= 1; |
| 349 |
tripper_ken <= 0; |
| 350 |
tripper_wait <= 0; |
| 351 |
st_cmd <= ST_CMD_STANDBY; |
| 352 |
end |
| 353 |
ST_CMD_SETTING_COND: |
| 354 |
if (rxrdy && !rxack && !c_we) |
| 355 |
begin |
| 356 |
// キーを受け取り、ケツから詰めていく |
| 357 |
c_txd <= rxdata; |
| 358 |
c_we <= 1; |
| 359 |
rxack <= 1; |
| 360 |
st_cmd <= ST_CMD_STANDBY; |
| 361 |
end |
| 362 |
ST_CMD_READY: |
| 363 |
begin |
| 364 |
/* キーを発見したらホストに送り返すモード */ |
| 365 |
if (CTS1) |
| 366 |
begin |
| 367 |
fifo_rdreq <= 0; |
| 368 |
fifo_rdrdy <= 0; |
| 369 |
st_cmd <= ST_CMD_STANDBY; |
| 370 |
end |
| 371 |
else if (!fifo_rdempty && !fifo_rdreq && !fifo_rdrdy) |
| 372 |
begin |
| 373 |
// FIFOへのデータ要求 |
| 374 |
fifo_rdreq <= 1; |
| 375 |
fifo_rdrdy <= 0; |
| 376 |
end |
| 377 |
else if (fifo_rdreq && !fifo_rdrdy) |
| 378 |
begin |
| 379 |
fifo_rdreq <= 0; |
| 380 |
fifo_rdrdy <= 1; |
| 381 |
end |
| 382 |
else if (!fifo_rdreq && fifo_rdrdy) |
| 383 |
begin |
| 384 |
// FIFOからの取り込み |
| 385 |
// 送るデータは、LITTLE ENDIANだ(糞 |
| 386 |
found_key <= i_pc1(fifo_q, SALT_MSB); |
| 387 |
fifo_rdreq <= 0; |
| 388 |
st_send <= 0; |
| 389 |
fifo_rdrdy <= 0; |
| 390 |
st_cmd <= ST_CMD_SENDING; |
| 391 |
end |
| 392 |
end |
| 393 |
ST_CMD_SENDING: |
| 394 |
if (txrdy && !txwe) |
| 395 |
begin |
| 396 |
/* |
| 397 |
* 一致キーをバイナリにて送信するモード |
| 398 |
*/ |
| 399 |
// 順繰りに(pos, data)を送り出していく |
| 400 |
// というのは古い仕様。 |
| 401 |
// いまは、data のみひたすら送出している。 |
| 402 |
txdata <= found_key[63:56]; |
| 403 |
txwe <= 1; |
| 404 |
found_key <= {found_key[55:0], 8'b0000_0000}; |
| 405 |
st_send <= st_send + 1; |
| 406 |
if (st_send == 8 - 1) |
| 407 |
st_cmd <= CTS1 ? ST_CMD_STANDBY : ST_CMD_READY; |
| 408 |
end |
| 409 |
endcase |
| 410 |
|
| 411 |
/* |
| 412 |
* 送受信のACKを戻す |
| 413 |
*/ |
| 414 |
if (!txrdy && txwe) |
| 415 |
txwe <= 0; |
| 416 |
if (!rxrdy && rxack) |
| 417 |
rxack <= 0; |
| 418 |
|
| 419 |
/* |
| 420 |
* レジスタ we (パルス) を戻す |
| 421 |
*/ |
| 422 |
if (c_we) |
| 423 |
c_we <= 0; |
| 424 |
|
| 425 |
/* |
| 426 |
* エンジンリセットをアサートしていたら |
| 427 |
* やがてネゲートするようにしてみたり |
| 428 |
*/ |
| 429 |
if (trip_rstgo) |
| 430 |
trip_rstgo <= 0; |
| 431 |
end |
| 432 |
|
| 433 |
endmodule // top_ser |
| 434 |
|
| 435 |
/*-------------------------------------------------------------------------------------------+ |
| 436 |
; Fitter Resource Usage Summary ; |
| 437 |
+---------------------------------------------+----------------------------------------------+ |
| 438 |
; Resource ; Usage ; |
| 439 |
+---------------------------------------------+----------------------------------------------+ |
| 440 |
; Total logic elements ; 10,307 / 10,570 ( 98 % ) ; |
| 441 |
; -- Combinational with no register ; 1086 ; |
| 442 |
; -- Register only ; 3862 ; |
| 443 |
; -- Combinational with a register ; 5359 ; |
| 444 |
; ; ; |
| 445 |
; Logic element usage by number of LUT inputs ; ; |
| 446 |
; -- 4 input functions ; 4530 ; |
| 447 |
; -- 3 input functions ; 565 ; |
| 448 |
; -- 2 input functions ; 1306 ; |
| 449 |
; -- 1 input functions ; 1858 ; |
| 450 |
; -- 0 input functions ; 2048 ; |
| 451 |
; ; ; |
| 452 |
; Logic elements by mode ; ; |
| 453 |
; -- normal mode ; 10123 ; |
| 454 |
; -- arithmetic mode ; 184 ; |
| 455 |
; -- qfbk mode ; 2735 ; |
| 456 |
; -- register cascade mode ; 499 ; |
| 457 |
; -- synchronous clear/load mode ; 5526 ; |
| 458 |
; -- asynchronous clear/load mode ; 4198 ; |
| 459 |
; ; ; |
| 460 |
; Total registers ; 9,221 / 13,052 ( 71 % ) ; |
| 461 |
; Total LABs ; 1,048 / 1,057 ( 99 % ) ; |
| 462 |
; Logic elements in carry chains ; 200 ; |
| 463 |
; User inserted logic elements ; 0 ; |
| 464 |
; Virtual pins ; 0 ; |
| 465 |
; I/O pins ; 25 / 427 ( 6 % ) ; |
| 466 |
; -- Clock pins ; 3 / 16 ( 19 % ) ; |
| 467 |
; Global signals ; 8 ; |
| 468 |
; M512s ; 94 / 94 ( 100 % ) ; |
| 469 |
; M4Ks ; 60 / 60 ( 100 % ) ; |
| 470 |
; M-RAMs ; 1 / 1 ( 100 % ) ; |
| 471 |
; Total memory bits ; 752,640 / 920,448 ( 82 % ) ; |
| 472 |
; Total RAM block bits ; 920,448 / 920,448 ( 100 % ) ; |
| 473 |
; DSP block 9-bit elements ; 0 / 48 ( 0 % ) ; |
| 474 |
; PLLs ; 2 / 6 ( 33 % ) ; |
| 475 |
; Global clocks ; 8 / 16 ( 50 % ) ; |
| 476 |
; Regional clocks ; 0 / 16 ( 0 % ) ; |
| 477 |
; Fast regional clocks ; 0 / 8 ( 0 % ) ; |
| 478 |
; SERDES transmitters ; 0 / 44 ( 0 % ) ; |
| 479 |
; SERDES receivers ; 0 / 44 ( 0 % ) ; |
| 480 |
; Average interconnect usage ; 28% ; |
| 481 |
; Peak interconnect usage ; 45% ; |
| 482 |
; Maximum fan-out node ; clockgen:pllx5|altpll:altpll_component|_clk0 ; |
| 483 |
; Maximum fan-out ; 5274 ; |
| 484 |
; Highest non-global fan-out signal ; ~GND ; |
| 485 |
; Highest non-global fan-out ; 240 ; |
| 486 |
; Total fan-out ; 46320 ; |
| 487 |
; Average fan-out ; 4.42 ; |
| 488 |
+---------------------------------------------+---------------------------------------------*/ |
| 489 |
|
| 490 |
/* |
| 491 |
* Local variables: |
| 492 |
* tab-width: 4 |
| 493 |
* End: |
| 494 |
*/ |
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