Verilog HDLに移植する

• Reporter: molelord
• Owner: molelord
• Type: Feature Requests
• Status: Closed
• Component: (None)
• MileStone: (None)
• Priority: 5 - Medium
• Severity: 5 - Medium
• Resolution: None
• File: None

Details Reply

VHDLで書かれたソースをVerilog HDLに移植する。

Ticket History (1/1 Histories)

2008-11-08 23:36 Updated by: molelord

• Status Update from Open to Closed
• Ticket Close date is changed to 2008-11-08 23:36

Comment Reply

rev44で移植作業を完了した。