PuzzleBox - Processor for functional languages

Fork

GC bugs are fixed that PuzzleBox GC module is not check car reg and cdr reg,
and the bitmap controller in GC module does not mark 'USED' bit while GC.

All mark-and-sweep GC functions are implemented in the PuzzleBox, but
not verified completely.

Now free pointer manager can control evaluation stack for GC, but
not implemented yet.

PuzzleBox Free Pointer module is modified using an allocation bitmap memory.
This modification is for mark-and-sweep GC, but it is not implemented yet.

PuzzleBox VM is updated to get input data before ISBSY becomes low.

PuzzleBox evaluation stack is modified to reduce area and complexity.

Loader supports binary transfer to external memory via serial port.

Some timing bugs in RTL is fixed.
PSEQ now supports binary tranfar of write data with term "w", not "W".
PSEQ and loader now supports address increments when accessing memory to
reduce transfer band width via serial port.

The name of loader changes to zload.
Loader supports detecting error abortion of puzzlebox.

Serial device definition is moved to the Makefile.
README now includes descriptions for configuration and run with FPGA.

PSEQ bug that EOF in output stream does not dequeued is fixed.
In the loader, asynchronous input/output stream transfer is
totaly supported to use pthread.

Program Loader for PuzzleBox is implemented.
Note that this loader does not support input/output stream completely.
It only works with fact.l because no input and one output is only supported.

Memory instances are modified for FPGA TOP synthesis.

EOS of Input/Output stream is supported to use term 'S' in UART.
Configurations in verification is moved to simulation directory.
An ISBSY timing bug is fixed.
Now all vectors in fpga top sim is passed.

Read/Write command via Main BUS is implemented to control SPRAM and
PuzzleBox core.
Main BUS module is added to route access from PSEQ and PuzzleBox to
SPRAM and PuzzleBox slave.

Note that EOF of Input/Output Stream on FPGA TOP module is not implemented yet,
so some testbench on FPGA TOP is aborted abnormally.
Those bugs are fixed later.

TOP Sequencer PSEQ command R, W, M is added for accessing an external memory.
Scratch Pad SRAM is also added as an external memory.

UART_TXD bugs in reset is fixed.

Reset signal becomes synchronus for FPGA.

RTL search path for synthesis is added.

PuzzleBox configuration file is moved to conf/ dir.
Configuration of PuzzleBox default is changed to 16bit CAF
because of limited size of SRAM on FPGA.

Synthesis and Program scripts for Altera Cyclone III EP3C25F324C6 is added in
the directory syn/altera.
These scripts supports only Nios II Embedded Evaluation Kit,
Cyclone III Edition and windows environment.
Don't run this scripts for Other FPGAs and boards.

UART bugs that low level signals mean 1 and high level signals means 0 is fixed.

PUZZLE BOX IS RDY & BSY direction is inversed due to symmetric interface.

FPGA top sequencer controled by UART is added.

FPGA TOP and UART is added for FPGA Implementation.
Verification environment for FPGA TOP is implemented.

README is modified to fix some directory changes and show add7 sample program.

Some syntax errors in rtl is fixed, and a macro with parameter is eliminated,
because iverilog seems not to support it.

Some directories are moved for restructuring.

PB_ESTK is modified to be almost synthesizable.

External address space is expanded to 30bit. Profiler for PuzzleBox is added.
Now compiler accepts LazyRead term "L".
Note that if you use LazyRead, solo use of "L" is prohibited due to CAF
modification: use "(I L)" instead.
License format is refined.