A verilog language compiler written using Java and JavaCC. It produces a netlist, an ascii text file, of all the cell connections. It can compile very large circuits comprised of many modules.
Latest 4 files |
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|---|---|---|---|
| Name | Size | Date | Download count |
| verilogx.jar | 471.2 KB | 2009-08-30 05:19 | 51 |
| README_FIRST.TXT | 2.4 KB | 2009-08-24 05:20 | 59 |
| Compiler Manual.pdf | 617.5 KB | 2009-08-23 04:07 | 106 |
| Verilog Parser Rights.pdf | 63.2 KB | 2009-08-22 05:52 | 228 |
All Files |
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| Binaries | |||
| verilogx.jar | 471.2 KB | 2009-08-30 05:19 | 51 |
| README | |||
| README_FIRST.TXT | 2.4 KB | 2009-08-24 05:20 | 59 |
| Compiler Manual.pdf | 617.5 KB | 2009-08-23 04:07 | 106 |
| Verilog Parser Rights.pdf | 63.2 KB | 2009-08-22 05:52 | 228 |
