Commit MetaInfo

Revision0889c1fadbd8b3000a2980ec453bcc98a741b1e2 (tree)
Time2016-04-14 17:05:55
AuthorYoshinori Sato <ysato@user...>
CommiterYoshinori Sato

Log Message

sh: IO-DATA HDL-U (aka. landisk) dts.

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>

Change Summary

Incremental Difference

--- /dev/null
+++ b/arch/sh/boot/dts/landisk.dts
@@ -0,0 +1,121 @@
1+#include <dt-bindings/interrupt-controller/sh_intc.h>
2+
3+/dts-v1/;
4+/ {
5+ model = "I/O DATA HDL-U";
6+ compatible = "iodata,hdl-u";
7+ #address-cells = <1>;
8+ #size-cells = <1>;
9+ interrupt-parent = <&shintc>;
10+ chosen {
11+ stdout-path = &sci1;
12+ };
13+ aliases {
14+ serial1 = &sci1;
15+ };
16+
17+ oclk: oscillator {
18+ #clock-cells = <0>;
19+ compatible = "fixed-clock";
20+ clock-frequency = <22222222>;
21+ };
22+ pllclk: pllclk {
23+ compatible = "renesas,sh7750-pll-clock";
24+ clocks = <&oclk>;
25+ #clock-cells = <0>;
26+ renesas,mult = <12>;
27+ reg = <0xffc00000 2>, <0xffc00008 4>;
28+ };
29+ iclk: iclk {
30+ compatible = "renesas,sh7750-div-clock";
31+ clocks = <&pllclk>;
32+ #clock-cells = <0>;
33+ reg = <0xffc00000 2>;
34+ renesas,offset = <6>;
35+ clock-output-names = "ick";
36+ };
37+ bclk: bclk {
38+ compatible = "renesas,sh7750-div-clock";
39+ clocks = <&pllclk>;
40+ #clock-cells = <0>;
41+ reg = <0xffc00000 2>;
42+ renesas,offset = <3>;
43+ clock-output-names = "bck";
44+ };
45+ fclk: fclk {
46+ compatible = "renesas,sh7750-div-clock";
47+ clocks = <&pllclk>;
48+ #clock-cells = <0>;
49+ reg = <0xffc00000 2>;
50+ renesas,offset = <0>;
51+ clock-output-names = "fck";
52+ };
53+ cpus {
54+ #address-cells = <1>;
55+ #size-cells = <0>;
56+ cpu@0 {
57+ compatible = "renesas,sh4", "renesas,sh";
58+ clock-frequency = <266666666>;
59+ };
60+ };
61+ memory@0c000000 {
62+ device_type = "memory";
63+ reg = <0x0c000000 0x4000000>;
64+ };
65+ shintc: interrupt-controller@ffd00000 {
66+ compatible = "renesas,sh7751-intc";
67+ #interrupt-cells = <2>;
68+ #address-cells = <1>;
69+ #size-cells = <1>;
70+ interrupt-controller;
71+ reg = <0xffd00000 14>, <0xfe080000 128>;
72+
73+ };
74+ cpldintc: cpld@b0000000 {
75+ compatible = "iodata,landisk-intc";
76+ #interrupt-cells = <2>;
77+ interrupt-controller;
78+ reg = <0xb0000000 8>;
79+ interrupt-map=<0 &shintc 0 0>, <1 &shintc 1 0>,
80+ <2 &shintc 2 0>, <3 &shintc 3 0>,
81+ <4 &shintc 4 0>, <5 &shintc 5 0>,
82+ <6 &shintc 6 0>, <7 &shintc 7 0>;
83+ };
84+
85+ sci1: serial@ffe80000 {
86+ compatible = "renesas,scif";
87+ reg = <0xffe80000 0x100>;
88+ interrupts = <evt2irq(0x700) 0
89+ evt2irq(0x720) 0
90+ evt2irq(0x740) 0
91+ evt2irq(0x760) 0>;
92+ clocks = <&fclk>;
93+ clock-names = "fck";
94+ };
95+ tmu: timer@ffd80008 {
96+ compatible = "renesas,tmu";
97+ reg = <0xffd80000 12>;
98+ interrupts = <evt2irq(0x400) 0
99+ evt2irq(0x420) 0
100+ evt2irq(0x440) 0>;
101+ clocks = <&fclk>;
102+ clock-names = "fck";
103+ renesas,channels-mask = <0x03>;
104+ };
105+
106+ pci: pci-controller@fe200000 {
107+ compatible = "renesas,sh7751-pci";
108+ device_type = "pci";
109+ ranges = <0x02000000 0x00000000 0xfd000000 0x01000000>,
110+ <0x01000000 0x00000000 0xfe240000 0x00400000>;
111+ reg = <0xfe200000 0x400>;
112+ renesas,pcimem = <0xfd000000>;
113+ renesas,pciio = <0xfe240000>;
114+ interrupts = <evt2irq(0x2a0) 0
115+ evt2irq(0x2c0) 0
116+ evt2irq(0x2e0) 0
117+ evt2irq(0x300) 0
118+ evt2irq(0x320) 0
119+ evt2irq(0x340) 0>;
120+ };
121+};
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