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Aarch64 SVE: Support changing vector lengths in gdbserver

There are two parts to this patch - gdbserver and GDB.

In gdbserver, there needs to be an equivalent of the thread_architecture
method used in GDB. In regcache, validate the tdesc with the
use target_validate_tdesc target function. If this fails then re-obtain
the target descriptor via general setup.
The aarch64 validation step simply checks the value of the VG register to
see if it matches the current kernel value.

In GDB, we have a similar check when receiving a stop reply. Validate the
tdesc using gdbarch_target_description_changed_p. If this fails re-obtain
the target descriptor via general setup - which is done by setting up an
tdep info structure containing the vector length.
The aarch64 validation step checks the value of VG (which is marked as
an expediated register, so is in the stop reply).

2018-11-07 Alan Hayward <alan.hayward@arm.com>

gdb/
* aarch64-tdep.c
(aarch64_target_description_changed_p): Check vector length.
(aarch64_target_get_tdep_info): Store vector length.
* remote.c (remote_target::process_stop_reply): Validate tdesc.
* target-descriptions.c (target_find_description): Pass through info.
* target-descriptions.h (target_find_description): Add arg.

gdbserver/
* linux-aarch64-low.c (aarch64_validate_tdesc): Check vector length.
* regcache.c (get_thread_regcache): Validate tdesc.

Add gdbserver target methods target_validate_tdesc and arch_setup

target_validate_tdesc () is added as a new target function.
This function checks current target description is still valid for the
current inferior, returning false if not. On SVE, we need to check if the
vector length has changed - if it has then the current target descriptor
will need to be switched to a valid one.

The existing arch_setup () is extended to be a target function.
This will later allow it to be called from get_thread_regcache () in
gdbserver/regcache.c. This call is required to generate a new target
descriptor if we have decided the current one is no longer valid.

2018-11-07 Alan Hayward <alan.hayward@arm.com>

gdbserver/
* linux-aarch64-low.c (int aarch64_validate_tdesc): New function.
(struct linux_target_ops): Add aarch64_validate_tdesc.
* linux-low.c (linux_validate_tdesc): New function.
(linux_target_ops): Add linux_arch_setup and linux_validate_tdesc.
* linux-low.h (linux_target_ops): Add validate_tdesc.
* target.h (struct target_ops): Likewise.
(target_arch_setup) New macro.
(target_validate_tdesc) New macro.

Add target_description_changed_p and target_get_tdep_info methods

target_description_changed_p () is added as a new gdbarch function.
Given a list of register values received from the inferior, it will check if
the current target descriptor is no longer valid for the inferior. This is
required because on SVE the register sizes can change whilst the inferior is
running.

target_get_tdep_info () is added as a new gdbarch function.
Given a list of registers, it will return a tdep info which then can be used
when creating/finding a valid target descriptor for that inferior.

Include stubbed aarch64 versions.

2018-11-07 Alan Hayward <alan.hayward@arm.com>

gdb/
* aarch64-tdep.c (aarch64_target_description_changed_p): New function.
(aarch64_target_get_tdep_info): New function.
(aarch64_gdbarch_init): Add in the new functions
* arch-utils.c (default_target_description_changed_p): New function.
(default_target_get_tdep_info): New function.
* arch-utils.h: (default_target_description_changed_p): New
declaration.
(default_target_get_tdep_info): New declaration.
* gdbarch.c: Regenerate.
* gdbarch.h: Regenerate.
* gdbarch.sh: (target_description_changed_p): New function.
(target_get_tdep_info): New function.

Name and seperate the union in gdbarch_info

Add gdbarch_target_info as a new union. This will allow it to be
used directly as a parameter to functions in later patches.

2018-11-07 Alan Hayward <alan.hayward@arm.com>

* aarch64-linux-nat.c
(aarch64_linux_nat_target::thread_architecture): Use target_info.
* aarch64-tdep.c (aarch64_gdbarch_init): Likewise.
* amd64-linux-tdep.c (amd64_linux_init_abi): Likewise.
(amd64_x32_linux_init_abi): Likewise.
* amd64-tdep.c (amd64_init_abi): Likewise.
* gdbarch.c: Regenerate.
* gdbarch.h: Likewise.
* gdbarch.sh (gdbarch_target_info): Add union
(gdbarch_info): Use gdbarch_target_info.
* i386-linux-tdep.c (i386_linux_init_abi): Use target_info.
* i386-tdep.c (i386_gdbarch_init): Likewise.
* mips-linux-tdep.c (mips_linux_init_abi): Likewise.
* mips-tdep.c (mips_gdbarch_init): Likewise.
* nds32-tdep.c (nds32_gdbarch_init): Likewise.
* ppc-linux-tdep.c (ppu2spu_sniffer): Likewise.
(ppc_linux_init_abi): Likewise.
* rs6000-tdep.c (rs6000_gdbarch_init): Likewise.
* s390-tdep.c (s390_gdbarch_init): Likewise.
* sparc-tdep.c (sparc32_gdbarch_init): Likewise.
* spu-multiarch.c (spu_gdbarch): Likewise.
* spu-tdep.c (spu_gdbarch_init): Likewise.

Aarch64 SVE: Support changing vector lengths in GDB

Override the thread_architecture method to place the vector length in the
tdep_info and then find using info. Do not set this as a pointer as
this will cause issues in later patches.

2018-11-07 Alan Hayward <alan.hayward@arm.com>

gdb/
* aarch64-linux-nat.c
(aarch64_linux_nat_target::thread_architecture): Add override.
* aarch64-tdep.c (aarch64_get_tdesc_vq): Check for nullptr.
(aarch64_gdbarch_init): Ensure differemt tdesc for each VQ.

Aarch64 SVE: Support changing vector lengths for ptrace

When writing registers to the kernel, check if regcache VG has been changed. If
so then update the thread's vector length. If required, resize the registers
in the kernel dump before writing it back.

When reading registers from the kernel, ensure regcache VG register is updated.
The regcache registers should already be of the correct length.

2018-11-07 Alan Hayward <alan.hayward@arm.com>

gdb/
* aarch64-linux-nat.c (fetch_sveregs_from_thread): Pass regcache.
(store_sveregs_to_thread): Likewise.
* nat/aarch64-sve-linux-ptrace.c (aarch64_sve_get_sveregs): Check
vector length.
(aarch64_sve_regs_copy_to_reg_buf): Likewise.
(aarch64_sve_regs_copy_from_reg_buf): Likewise.
* nat/aarch64-sve-linux-ptrace.h (aarch64_sve_get_sveregs): Add
reg_buf arg.

gdb: Guard against NULL dereference in dwarf2_init_integer_type

In this commit:

commit eb77c9df9f6d2f7aa644a170280fe31ce080f887
Date: Thu Oct 18 14:04:27 2018 +0100

gdb: Handle ICC's unexpected void return type

A potential dereference of a NULL pointer was introduced if a
DW_TAG_base_type is missing a DW_AT_name attribute.

I have taken this opportunity to fix a slight confusion that existed
in the test also added in the above commit, the test had two C
variables, declared like this:

int var_a = 5;

void *var_ptr = &var_a;

However, the fake DWARF in the test script declared them like this:

void var_a = 5;

void *var_ptr = &var_a;

This wasn't a problem as the test never uses 'var_a' directly, this
only exists so 'var_ptr' can be initialised. However, it seemed worth
fixing.

I've also added a test for a DW_TAG_base_type with a missing
DW_AT_name, as clearly there's not test currently that covers this
(the original patch tested cleanly). I can confirm that the new test
causes GDB to crash before this patch, and passes with this patch.

gdb/ChangeLog:

* dwarf2read.c (dwarf2_init_integer_type): Check for name being
NULL before dereferencing it.

gdb/testsuite/ChangeLog:

* gdb.dwarf2/void-type.exp: Rename types, and make var_a an 'int'.
* gdb.dwarf2/missing-type-name.exp: New file.

Regen bfd/configure

* configure: Regenerate.

rx: Add target rx-*-linux.

Automatic date update in version.in

[gdb] Fix gdb crash when reading core file

Consider the test-case from this patch, compiled with O0.

The executable segfaults, and generates a core dump:
...
$ ./a.out
Segmentation fault (core dumped)
...

When loading the core file, limiting stack size to 4MB, gdb crashes:
...
$ ulimit -s 4096
$ gdb -batch ./a.out core.saved
[New LWP 19379]
Segmentation fault (core dumped)
...

The crash originates here in linux_vsyscall_range_raw, where we call alloca
with phdrs_size == 4194112 (roughly 4MB):
...
phdrs = (Elf_Internal_Phdr *) alloca (phdrs_size);
...

While for this test-case gdb runs fine with the system default stack limit of
8MB, there are cases reported of 12MB phdrs_size where gdb also crashes with
the system default stack limit.

Fix this by using xmalloc instead of alloca, which prevents the crash provided
the stack limit is at least 112kb.

Build and reg-tested on x86_64-linux.

2018-11-06 Tom de Vries <tdevries@suse.de>

* linux-tdep.c (linux_vsyscall_range_raw): Use xmalloc to allocate
program headers.

* gdb.base/many-headers.c: New test.
* gdb.base/many-headers.exp: New file.

RISC-V: Force variables to .data for code_elim.

RISC-V puts a global variable in .sdata by default, which causes the
add-symbol-file commands with -s .data to fail as there is no .data section.
This fixes 3 testsuite failures.

gdb/testsuite/
* gdb.base/code_elim.exp: For riscv, set additional_flags
to include -msmall-data-limit=0.

gdb: xtensa: use linux ABI code for uclinux

gdb/
2018-11-06 Max Filippov <jcmvbkbc@gmail.com>

* configure.tgt (xtensa*-*-linux*): Change to xtensa*-*-*linux*
so that it applies to uclinux as well.

ARM: Do not use FP reg when on AAPCS

GDB tries to dereference the frame pointer in arm_scan_prologue as a
last resort to create frame information.
However, the more recent AAPCS ABI does not make use of a frame pointer.

This patch checks whether the specified arm_abi is AAPCS before
dereferencing the "frame pointer". If so, just return as efforts to use
it for restoring frame information won't work.

gdb/ChangeLog
2018-11-06 Marius Muench <marius.muench@eurecom.fr>

* arm-tdep.c (arm_scan_prologue): Don't dereference FP reg
when on AAPCS.

Note that PT_GETREGS supplies SSTATUS for FreeBSD/riscv.

This permits reading the value of the SSTATUS CSR returned by ptrace()
for live FreeBSD/riscv processes.

* riscv-fbsd-nat.c (getregs_supplies): Return true for
RISCV_CSR_SSTATUS_REGNUM.

elfedit: Add --enable-x86-feature/--disable-x86-feature

Add --enable-x86-feature and --disable-x86-feature options to elfedit
to set and clear the IBT and SHSTK bits in program property in ELF
executables and shared objects.

binutils/

* doc/binutils.texi: Document --enable-x86-feature and
--disable-x86-feature options for elfedit.
* elfedit.c: Include "config.h" and <sys/mman.h>.
(enable_x86_features): New.
(disable_x86_features): Likewise.
(update_gnu_property): Likewise.
(elf_x86_feature): Likewise.
(process_file): Call update_gnu_property on ET_EXEC or ET_DYN
file.
(command_line_switch): Add OPTION_ENABLE_X86_FEATURE and
OPTION_DISABLE_X86_FEATURE.
(options): Add--enable-x86-feature and --disable-x86-feature.
(usage): Likewise.
(main): Handle OPTION_ENABLE_X86_FEATURE and
OPTION_DISABLE_X86_FEATURE.

ld/

* testsuite/config/default.exp (ELFEDIT): New.
* testsuite/ld-elf/linux-x86.exp (elfedit_test): New proc.
Run elfedit tests.
* testsuite/ld-elf/x86-feature-1a.rd: New file.
* testsuite/ld-elf/x86-feature-1b.rd: Likewise.
* testsuite/ld-elf/x86-feature-1c.rd: Likewise.
* testsuite/ld-elf/x86-feature-1d.rd: Likewise.
* testsuite/ld-elf/x86-feature-1e.rd: Likewise.

Add support for a couple of new Mach-O commands.

PR 23742
* mach-o.c (bfd_mach_o_read_command): Accept and ignore
BFD_MACH_O_LC_LINKER_OPTIONS and BFD_MACH_O_LC_BUILD_VERSION
commands.

* mach-o/loader.h: Add BFD_MACH_O_LC_BUILD_VERSION.

[arm] fix testsuite breakage on pe-coff

The PE target can insert NOP's for padding to 4 byte alignment.
This was causing a testcase failure, this commit fixes the testcase.

This commit also escapes some full-stops in the testcase regexp.

2018-11-06 Matthew Malcomson <matthew.malcomson@arm.com>

* testsuite/gas/arm/neon-cond-bad_t2.d: Fix testcase for PE
target.

[arm] Check for neon and condition in vcvt.f16.f32

VCVT between f16 and f32 is an Advanced SIMD instruction.
Not all the VCVT alternatives need neon, hence the check for neon is in
the encode function.

The check on neon for VCVT.f16.f32 (and vice versa) is missing.

vshcmd: > echo 'vcvt.f16.f32 d1, q1' | gas/as-new -mfpu=vfpxd -march=armv8.5-a -
testdir [15:59:10] $

Also, the handling of the condition code behaves differently to other
SIMD instructions -- no error message is produced when assembling an
instruction with a condition code suffix despite the arm encoding not
allowing a condition code. (n.b. the actual binary produced is
independent of the suffix).

The instruction should be treated similarly to VSUBL that has the same
caveat of "must be unconditional" describing the {<c>} symbol. vcvt
half-precision to single precision found in F6.1.58 in the ARM
Architecture Reference Manual issue C.a, vsubl found in F6.1.240 in
the ARM Architecture Reference Manual issue C.a

2018-11-06 Matthew Malcomson <matthew.malcomson@arm.com>

* config/tc-arm.c (do_neon_cvt_1): Add check for neon and condition
codes to half-precision conversion.
* testsuite/gas/arm/neon-cond-bad-inc.s: Check vcvteq disallowed.
* testsuite/gas/arm/neon-cond-bad.l: Likewise.
* testsuite/gas/arm/neon-cond-bad_t2.d: Check vcvteq allowed in IT
block.
* testsuite/gas/arm/vfp-bad.l: Ensure vcvt doesn't work without neon.
* testsuite/gas/arm/vfp-bad.s: Likewise.

[BINUTILS, ARM] Add Armv8.5-A to select_arm_features and update macros.

This patch addresses the following
1) Adding ARMv8.5-A in select_arm_features.
2) Updating the feature macro so that the new ARM_EXT2_* features for
Armv8.5-A are moved to ARM_AEXT2_V8_5A.

*** opcodes/ChangeLog ***

2018-11-06 Sudakshina Das <sudi.das@arm.com>

* arm-dis.c (select_arm_features): Update bfd_mach_arm_8
with Armv8.5-A. Remove reduntant ARM_EXT2_FP16_FML.

*** include/ChangeLog ***

2018-11-06 Sudakshina Das <sudi.das@arm.com>

* opcode/arm.h (ARM_ARCH_V8_5A): Move ARM_EXT2_PREDRES and
ARM_EXT2_SB to ...
(ARM_AEXT2_V8_5A): Here.

PowerPC instruction mask checks

The instruction mask bits should never overlap any of the operands,
nor should operand bits overlap, but some operands weren't checked.
This patch arranges to check the omitted operands, using a mask
returned by the operand->insert function. Some tweaking of various
insert functions is needed to support this: The error case must set
field bits.

Since I was looking at the insert functions, I tidied some dead code
and simplified some of the powerpc_operands entries.

gas/
* config/tc-ppc.c (insn_validate): Don't ignore mask in
PPC_OPSHIFT_INV case. Call the insert function to calculate
a mask.
opcodes/
* ppc-opc.c (insert_arx, insert_ary, insert_rx, insert_ry, insert_ls),
(insert_evuimm1_ex0, insert_evuimm2_ex0, insert_evuimm4_ex0),
(insert_evuimm8_ex0, insert_evuimm_lt8, insert_evuimm_lt16),
(insert_rD_rS_even, insert_off_lsp, insert_off_spe2, insert_Ddd):
Don't return zero on error, insert mask bits instead.
(insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w): Delete.
(insert_sh6, extract_sh6): Delete dead code.
(insert_sprbat, insert_sprg): Use unsigned comparisions.
(powerpc_operands <OIMM>): Set shift count rather than using
PPC_OPSHIFT_INV.
<SE_SDH, SE_SDW>: Likewise. Don't use insert/extract functions.

PowerPC instruction operand flag validation

This adds another check that might have saved me a little time
recently if it had been present.

* config/tc-ppc.c (insn_validate): Check that optional operands
are not followed by non-optional operands.

x86: correctly handle VPBROADCASTD with EVEX.W set outside of 64-bit mode

For the flavor having a GPR operand EVEX.W is ignored outside of 64-bit
mode. The mnemonic should therefore not be VPBROADCASTQ.

x86: correctly handle VMOVD with EVEX.W set outside of 64-bit mode

For the flavors having a GPR operand EVEX.W is ignored outside of 64-bit
mode. The mnemonic should therefore not be KMOVQ, the GPR operand should
not name a non-existing 64-bit register, just like is already the case
for the AVX counterparts, and the Disp8 scaling factor should be 4
rather than 8.

x86: correctly handle KMOVD with VEX.W set outside of 64-bit mode

For the flavors having a GPR operand VEX.W is ignored outside of 64-bit
mode. The mnemonic should therefore not be KMOVQ.

x86: adjust {,E}VEX.W handling for PEXTR* / PINSR*

PEXTR{B,W} and PINSR{B,W}, just like for AVX512BW, are WIG, no matter
that the SDM uses a nonstandard description of that fact.

PEXTRD, even with EVEX.W set, ignores that bit outside of 64-bit mode,
just like its AVX counterpart.

x86: adjust {,E}VEX.W handling outside of 64-bit mode

Many VEX-/EVEX-encoded instructions accessing GPRs become WIG outside of
64-bit mode. The respective templates should specify neither VexWIG nor
VexW0, but instead the setting of the bit should be determined from
- REX.W in 64-bit mode,
- the setting established through -mvexwig= / -mevexwig= otherwise.
This implies that the evex-wig2 testcase needs to go away, as being
wrong altogether.

A few test additions desirable here will only happen in later patches,
as the disassembler needs adjustments first.

Once again SSE2AVX templates are left alone, for it being unclear what
the behavior there should be.

x86: fix various non-LIG templates

Quite a few templates were marked LIG while really the insns aren't.
Introduce descriptive shorthands once again, instead of continuing to
use the less legible original forms.

x86: allow {store} to select alternative {,}PEXTRW encoding

The 0F C5 encoding is indeed a load type one (just that memory operands
are not permitted), while the 0F 3A 15 encoding is obviously a store.
Allow the pseudo prefixes to be used to select between them.

Also move (without any change) the secondary AVX512BW templates next to
the primary one.

x86: add more VexWIG

Commits 6865c0435a ("x86: Support VEX/EVEX WIG encoding") and 6fa52824c3
("x86: Replace VexW=3 with VexWIG") omitted quite a few templates, oddly
enough in some cases despite testcases getting added (which then were
recorded with wrong expected output).

Also adjust VPMAXUB's attributes in the AVX512BW case to match ordering
of that of neighboring templates.

For the moment SSE2AVX templates are left alone, as it isn't clear
whether they were intentionally left untouched by the original commits
(the descriptions don't say either way).

In this context I question the decision in commit 0375113302 ("x86: Add
-mvexwig=[0|1] option to assembler") to move the logic to determine the
value of the W bit ahead of the decision whether to use 2-byte VEX:
While I can see this as one possible interpretation of -mvexwig=, the
other alternative (setting the value of the bit only if it actually
exists in the encoding) looks as reasonable to me, and perhaps even more
in line with us generally trying to pick the shortest encoding.