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Automatic date update in version.in

MIPS/GAS: Fix an ISA override not lifting ABI restrictions

Correct a regression introduced with commit 919731affbef ("Add MIPS
.module directive") causing code like:

.set mips3
dli $2, 0x9000000080000000

to fail assembly with the following error message produced:

Error: number (0x9000000080000000) larger than 32 bits

if built with `mips3' selected as the global ISA (e.g. `-march=mips3').
This is because a `.set' directive doing an ISA override does not lift
the ABI restriction on register sizes if the ISA remains unchanged.
Previously the directive always set register sizes from the ISA chosen,
which is what some code expects. Restore the old semantics then.

gas/
* config/tc-mips.c (code_option_type): New enum.
(parse_code_option): Return status indicating option type.
(s_mipsset): Update `parse_code_option' call site accordingly.
Always set register sizes from the ISA with ISA overrides.
(s_module): Update `parse_code_option' call site.
* testsuite/gas/mips/isa-override-1.d: New test.
* testsuite/gas/mips/micromips@isa-override-1.d: New test.
* testsuite/gas/mips/mips1@isa-override-1.d: New test.
* testsuite/gas/mips/mips2@isa-override-1.d: New test.
* testsuite/gas/mips/mips32@isa-override-1.d: New test.
* testsuite/gas/mips/mips32r2@isa-override-1.d: New test.
* testsuite/gas/mips/mips32r3@isa-override-1.d: New test.
* testsuite/gas/mips/mips32r5@isa-override-1.d: New test.
* testsuite/gas/mips/mips32r6@isa-override-1.d: New test.
* testsuite/gas/mips/mips64r2@isa-override-1.d: New test.
* testsuite/gas/mips/mips64r3@isa-override-1.d: New test.
* testsuite/gas/mips/mips64r5@isa-override-1.d: New test.
* testsuite/gas/mips/mips64r6@isa-override-1.d: New test.
* testsuite/gas/mips/r3000@isa-override-1.d: New test.
* testsuite/gas/mips/r3900@isa-override-1.d: New test.
* testsuite/gas/mips/r5900@isa-override-1.d: New test.
* testsuite/gas/mips/octeon@isa-override-1.d: New test.
* testsuite/gas/mips/octeon3@isa-override-1.d: New test.
* testsuite/gas/mips/isa-override-2.l: New list test.
* testsuite/gas/mips/mips1@isa-override-2.l: New list test.
* testsuite/gas/mips/mips2@isa-override-2.l: New list test.
* testsuite/gas/mips/mips32@isa-override-2.l: New list test.
* testsuite/gas/mips/mips32r2@isa-override-2.l: New list test.
* testsuite/gas/mips/mips32r3@isa-override-2.l: New list test.
* testsuite/gas/mips/mips32r5@isa-override-2.l: New list test.
* testsuite/gas/mips/mips32r6@isa-override-2.l: New list test.
* testsuite/gas/mips/r3000@isa-override-2.l: New list test.
* testsuite/gas/mips/r3900@isa-override-2.l: New list test.
* testsuite/gas/mips/octeon3@isa-override-2.l: New list test.
* testsuite/gas/mips/octeon3@isa-override-1.l: New stderr
output.
* testsuite/gas/mips/isa-override-1.s: New test source.
* testsuite/gas/mips/r5900@isa-override-1.s: New test source.
* testsuite/gas/mips/isa-override-2.s: New test source.
* testsuite/gas/mips/mips1@isa-override-2.s: New test source.
* testsuite/gas/mips/mips2@isa-override-2.s: New test source.
* testsuite/gas/mips/mips32@isa-override-2.s: New test source.
* testsuite/gas/mips/mips32r2@isa-override-2.s: New test source.
* testsuite/gas/mips/mips32r3@isa-override-2.s: New test source.
* testsuite/gas/mips/mips32r5@isa-override-2.s: New test source.
* testsuite/gas/mips/mips32r6@isa-override-2.s: New test source.
* testsuite/gas/mips/r3000@isa-override-2.s: New test source.
* testsuite/gas/mips/r3900@isa-override-2.s: New test source.
* testsuite/gas/mips/octeon3@isa-override-2.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.

(cherry picked from commit 5475e3249a6ab15afa0fe00456ada988d940a302)

[Testsuite] treate -specs as both cflags & ldflags

Backport from master
2014-11-11 Jiong Wang <jiong.wang@arm.com>

ld/testsuite/

* lib/ld-lib.exp (run_ld_link_exec_tests): Append board_cflags if gcc
driver used as link tool.
(run_cc_link_exec_tests): Likewise.

[Testsuite] Fix running unique tests on ARM

Backport from master:
2014-10-30 Will Newton <will.newton@linaro.org>

ld/testsuite/ChangeLog:
* ld-unique/unique.exp: Use a wider glob for matching ARM
targets.
* ld-unique/unique.s: Use % instead of @ in .type directive.
* ld-unique/unique_shared.s: Likewise.

PR gold/17473: Fix gold build with system C++ headers that use <ctype.h>.

gold/
PR gold/17473
* binary.cc: Move #include "safe-ctype.h" to be last #include.

(cherry picked from commit 95c29a83ebadd0038fd304539a83c5e90798c1b9)

Remove one unnecessary iteration in insertion sort

PR 18867
* elflink.c (elf_link_adjust_relocs): Correct start of insertion
sort main loop.

Fix slowdown in ld -r for most common case of out-of-order relocs

I chose insertion sort since relocs are mostly sorted, but there is a
common case we can handle better; A run of relocs put out of order
due to not linking input files in order.

PR 18867
* elflink.c (elf_link_adjust_relocs): Modify insertion sort to
insert a run. Return status in case of malloc failure.
Adjust callers.

Don't sort ld -r output relocs on alpha

LITERAL/LITUSE relocs must be kept together.

PR 18867
* elf64-alpha.c (elf64_alpha_sort_relocs_p): New function.
(elf_backend_sort_relocs_p): Define.

Use stable sort for ld -r relocs

A number of targets emit multiple relocs at a given r_offset, and
depend on those relocs staying in their original order.

PR 18867
* elflink.c (cmp_ext32l_r_offset, cmp_ext32b_r_offset): Delete.
(cmp_ext64l_r_offset, cmp_ext64b_r_offset): Delete.
(ext32l_r_offset, ext32b_r_offset, ext64l_r_offset, ext64b_r_offset):
New functions.
(elf_link_adjust_relocs): Use an insertion sort to sort relocs.

Make arm_unaligned_reloc test less sensitive to disassembler output format.

Bump version to 2.25.2

bfd/
2015-07-21 Tristan Gingold <gingold@adacore.com>

* version.m4: Bump version to 2.25.2
* configure: Regenerate.

binutils/
2015-07-21 Tristan Gingold <gingold@adacore.com>

* configure: Regenerate.

gas/
2015-07-21 Tristan Gingold <gingold@adacore.com>

* configure: Regenerate.

gprof/
2015-07-21 Tristan Gingold <gingold@adacore.com>

* configure: Regenerate.

ld/
2015-07-21 Tristan Gingold <gingold@adacore.com>

* configure: Regenerate.

opcodes/
2015-07-21 Tristan Gingold <gingold@adacore.com>

* configure: Regenerate.

Release 2.25.1, add generated files

Automatic date update in version.in

Automatic date update in version.in

Automatic date update in version.in

Automatic date update in version.in

Automatic date update in version.in

Correct readelf dynamic section buffer overlow test

PR binutils/18672
* readelf.c (get_32bit_dynamic_section): Correct buffer limit test.
(get_64bit_dynamic_section): Likewise.

Automatic date update in version.in

Automatic date update in version.in

Automatic date update in version.in

Automatic date update in version.in

Automatic date update in version.in

Automatic date update in version.in

Fix an opd->adjust index in elf64-ppc.c

bfd/
* elf64-ppc.c (toc_adjusting_stub_needed): Use the symbol value
plus addend rather than the original st_value when looking up
entries in opd->adjust.

ld/testsuite/
* ld-powerpc/tocopt6-inc.s, ld-powerpc/tocopt6a.s,
ld-powerpc/tocopt6b.s, ld-powerpc/tocopt6c.s,
ld-powerpc/tocopt6.d: New test.
* ld-powerpc/powerpc.exp (ppc64elftests): Add it.

Remove ppc860, ppc750cl, ppc7450 insns from common ppc.

Back in the day support for these processors was added, we probably
didn't want to waste PPC_OPCODE bits on minor variations. I've had a
complaint that disassembly of mfspr/mtspr was wrong for power8. This
patch fixes that problem.

Note that since -m860/-m850/-m821 are new gas options enabling the
mpc8xx specific mfspr/mtspr variants it is possible that this change
will break some mpc8xx assembly code. ie. you might need to modify
makefiles to pass -m860 to gas.

include/opcode/
* ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
opcodes/
* ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
* ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
gas/
* config/tc-ppc.c (md_show_usage): Add -m821, -m850, -m860.
* doc/c-ppc.texi (PowerPC-Opts): Likewise.
gas/testsuite/
* gas/ppc/titan.d: Correct mfmcsrr0 disassembly.

PPC sync instruction accepts invalid and incompatible operands

ISA 2.07 added a new category called Elemental Memory Barriers that modifies
the sync instruction to accept an additional operand ESYNC. Edmar added
support for this insruction varient here:

https://sourceware.org/ml/binutils/2012-02/msg00221.html

Looking at this closer, I see that the insert_ls() function is misnamed
(since it's attached to the ESYNC operand, not the LS operand) but more
importantly, it is silently modifying the LS operand value behind the
users back when the LS operand is either invalid or is incompatible with
the new ESYNC operand. The ISA 2.07 doc has an Assembler Note that clearly
states that assemblers that support the ESYNC operand should report all
invalid uses of LS and ESYNC. This patch changes the assembler to
error out on invalid and incompatible operand usage.

opcodes/
* ppc-opc.c (insert_ls): Test for invalid LS operands.
(insert_esync): New function.
(LS, WC): Use insert_ls.
(ESYNC): Use insert_esync.

gas/testsuite/
* gas/ppc/e6500.s <sync>: Fix invalid test.
* gas/ppc/e6500.d: Likewise.

Allow for optional operands with non-zero default values.

ISA 2.07 (ie, POWER8) added the rfebb instruction which takes one operand
with the value of either a 0 or 1. It also defines an extended mnemonic
with no operands (ie, "rfebb") that is supposed to be equivalent to "rfebb 1".
I implemented rfebb's lone operand with PPC_OPERAND_OPTIONAL, but the
problem is, optional operands that are ommitted always default to the
value 0, which is wrong in this case. I have added support for allowing
non-zero default values by adding an additional flag PPC_OPERAND_OPTIONAL_VALUE
that specifies that the default operand value to be used is stored in the
SHIFT field of the operand field immediately following this one.

This fixes the rfebb issue. I also fixed the mftb and mfcr instructions
so they use the same mechanism. This allows us to flag invalid uses of
mfcr where we explicitly pass in a zero FXM value, like the use in a2.[sd].

include/opcode/

* ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
(ppc_optional_operand_value): New inline function.

opcodes/
* ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
* ppc-opc.c (FXM4): Add non-zero optional value.
(TBR): Likewise.
(SXL): Likewise.
(insert_fxm): Handle new default operand value.
(extract_fxm): Likewise.
(insert_tbr): Likewise.
(extract_tbr): Likewise.

gas/
* config/tc-ppc.c (md_assemble): Use ppc_optional_operand_value.
Allow for optional operands without insert functions.

gas/testsuite/
* gas/ppc/power8.d: Fixup rfebb test results.
* gas/ppc/a2.s: Fix invalid mfcr test.
* gas/ppc/a2.d: Likewise.

ppc476 linker workaround shared lib fixes again

Huh, I can't even write a binary search properly.

bfd/
* elf32-ppc.c (ppc_elf_relocate_section): Correct binary search of
dynamic relocs.
ld/testsuite/
* ld-powerpc/ppc476-shared.s: Repeat dynamic reloc generating insns.
* ld-powerpc/ppc476-shared.d: Update.
* ld-powerpc/ppc476-shared2.d: Update.

Remove unused MTMSRD_L macro and re-add accidentally deleted comment.

In the commit that added PowerPC Pair Singles, Ben accidentally removed
a comment and re-added an unused MTMSRD_L macro Alan had recently deleted.
This was probably just an oversite when he was refreshing his patch to
trunk.

opcodes/
* ppc-opc.c: Add comment accidentally removed by old commit.
(MTMSRD_L): Delete.