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Correct disassembly of dot product instructions.

Dot products deviate from the normal disassembly rules for lane indexed
instruction. Their canonical representation is in the form of:

v0.2s, v0.8b, v0.4b[0] instead of v0.2s, v0.8b, v0.b[0] to try to denote
that these instructions select 4x 1 byte elements instead of a single 1 byte
element.

Previously we were disassembling them following the normal rules, this patch
corrects the disassembly.

gas/

PR gas/22559
* config/tc-aarch64.c (vectype_to_qualifier): Support AARCH64_OPND_QLF_S_4B.
* gas/testsuite/gas/aarch64/dotproduct.d: Update disassembly.

include/

PR gas/22559
* aarch64.h (aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_S_4B.

opcodes/

PR gas/22559
* aarch64-asm.c (aarch64_ins_reglane): Change AARCH64_OPND_QLF_S_B to
AARCH64_OPND_QLF_S_4B
* aarch64-dis.c (aarch64_ext_reglane): Change AARCH64_OPND_QLF_S_B to
AARCH64_OPND_QLF_S_4B
* aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant.
* aarch64-tbl.h (QL_V2DOT): Change S_B to S_4B.

Change-Id: Ie80d878ceaeaca281f85583e77e4e367e2a909ea

Add support for V_4B so we can properly reject it.

Previously parse_vector_type_for_operand was changed to allow the use of 4b
register size for indexed lane instructions. However this had the unintended
side effect of also allowing 4b for normal vector registers.

Because this support was only partial the rest of the tool silently treated
4b as 8b and continued. This patch adds full support for 4b so it can be
properly distinguished from 8b and the correct errors are generated.

With this patch you still can't encode any instruction which actually requires
v<num>.4b but such instructions don't exist so to prevent needing a workaround
in get_vreg_qualifier_from_value this was just omitted.

gas/

PR gas/22529
* config/tc-aarch64.c (vectype_to_qualifier): Support AARCH64_OPND_QLF_V_4B.
* gas/testsuite/gas/aarch64/pr22529.s: New.
* gas/testsuite/gas/aarch64/pr22529.d: New.
* gas/testsuite/gas/aarch64/pr22529.l: New.

include/

PR gas/22529
* opcode/aarch64.h (aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_V_4B.

opcodes/

PR gas/22529
* aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant.

Merge with binutils-2_28-branch rev 1e4d2a179d0

2018-01-12 Eric Christopher <echristo@gmail.com>

Apply from master:
2018-01-12 Sterling Augustine <saugustine@google.com>

* cref.cc (Cref_inputs::Cref_table_compare::operator): Add
conditionals and calls to is_forwarder.

Fix typo in ChangeLog entry.

Fix DWARF reader to use correct size for DW_FORM_ref_addr.

2017-11-19 Ian Lance Taylor <iant@google.com>
Cary Coutant <ccoutant@gmail.com>

gold/
* gold/dwarf_reader.h (class Dwarf_info_reader): Add ref_addr_size
method.
* gold/dwarf_reader.cc (Dwarf_die::read_attributes): Use ref_addr_size
for DW_FORM_ref_addr_size.
(Dwarf_die::skip_attributes): Likewise.

Apply from mainline:

[GOLD] Fix powerpc64 optimization of TOC accesses

Fixes a thinko. Given code that puts variables into the TOC (a bad
idea, but some see the TOC as a small data section) this bug could
result in an attempt to optimize a sequence that should not be
optimized.

* powerpc.cc (Target_powerpc::Scan::local): Correct dst_off
calculation for TOC16 relocs.
(Target_powerpc::Scan::global): Likewise.

2017-11-08 Kyle Butt <iteratee@google.com>

* object.cc (do_find_special_sections): Fix a thinko with memmem return
values and check for != NULL rather than == 0.

PR22220, BFD linker wrongly marks symbols as PREVAILING_DEF_IRONLY

non_ir_ref_dynamic wasn't being set in the case where we have a
versioned dynamic symbol definition with a non-versioned matching IR
symbol.

bfd/
PR 22220
* elflink.c (_bfd_elf_merge_symbol): Set non_ir_ref_dynamic in
a case where plugin_notice isn't called.
ld/
* testsuite/ld-plugin/pr22220.h,
* testsuite/ld-plugin/pr22220lib.cc,
* testsuite/ld-plugin/pr22220lib.ver,
* testsuite/ld-plugin/pr22220main.cc: New test.
* testsuite/ld-plugin/lto.exp: Run it.

(cherry picked from commit 1a3b5c34fe371f618402f811a981839c9191ff9f)

Rename non_ir_ref to non_ir_ref_regular

Since the flag is now set only for regular object refs.

include/
* bfdlink.h (struct bfd_link_hash_entry <non_ir_ref>): Rename to
non_ir_ref_regular.
bfd/
* elf-m10300.c: Rename occurrences of non_ir_ref.
* elf32-arm.c: Likewise.
* elf32-bfin.c: Likewise.
* elf32-cr16.c: Likewise.
* elf32-cris.c: Likewise.
* elf32-d10v.c: Likewise.
* elf32-dlx.c: Likewise.
* elf32-fr30.c: Likewise.
* elf32-frv.c: Likewise.
* elf32-hppa.c: Likewise.
* elf32-i370.c: Likewise.
* elf32-i386.c: Likewise.
* elf32-iq2000.c: Likewise.
* elf32-lm32.c: Likewise.
* elf32-m32c.c: Likewise.
* elf32-m32r.c: Likewise.
* elf32-m68hc1x.c: Likewise.
* elf32-m68k.c: Likewise.
* elf32-mcore.c: Likewise.
* elf32-metag.c: Likewise.
* elf32-microblaze.c: Likewise.
* elf32-moxie.c: Likewise.
* elf32-msp430.c: Likewise.
* elf32-mt.c: Likewise.
* elf32-nios2.c: Likewise.
* elf32-or1k.c: Likewise.
* elf32-ppc.c: Likewise.
* elf32-rl78.c: Likewise.
* elf32-s390.c: Likewise.
* elf32-score.c: Likewise.
* elf32-score7.c: Likewise.
* elf32-sh.c: Likewise.
* elf32-tic6x.c: Likewise.
* elf32-tilepro.c: Likewise.
* elf32-v850.c: Likewise.
* elf32-vax.c: Likewise.
* elf32-xstormy16.c: Likewise.
* elf32-xtensa.c: Likewise.
* elf64-alpha.c: Likewise.
* elf64-hppa.c: Likewise.
* elf64-ia64-vms.c: Likewise.
* elf64-mmix.c: Likewise.
* elf64-ppc.c: Likewise.
* elf64-s390.c: Likewise.
* elf64-sh64.c: Likewise.
* elf64-x86-64.c: Likewise.
* elflink.c: Likewise.
* elfnn-aarch64.c: Likewise.
* elfnn-ia64.c: Likewise.
* elfnn-riscv.c: Likewise.
* elfxx-mips.c: Likewise.
* elfxx-sparc.c: Likewise.
* elfxx-tilegx.c: Likewise.
* linker.c: Likewise.
ld/
* plugin.c: Rename occurrences of non_ir_ref.

(cherry picked from commit bc4e12ded1d4c8d589d82b2a10ade6b47f219db3)

non_ir_ref_dynamic

dynamic_ref_after_ir_def is a little odd compared to other symbol
flags in that as the name suggests, it is set only for certain
references after a definition. It turns out that setting a flag for
any non-ir reference from a dynamic object can be used to solve the
problem for which this flag was invented, which I think is a cleaner.
This patch does that, and sets non_ir_ref only for regular object
references.

include/
* bfdlink.h (struct bfd_link_hash_entry): Update non_ir_ref
comment. Rename dynamic_ref_after_ir_def to non_ir_ref_dynamic.
ld/
* plugin.c (is_visible_from_outside): Use non_ir_ref_dynamic.
(plugin_notice): Set non_ir_ref for references from regular
objects, non_ir_ref_dynamic for references from dynamic objects.
bfd/
* elf64-ppc.c (add_symbol_adjust): Transfer non_ir_ref_dynamic.
* elflink.c (elf_link_add_object_symbols): Update to use
non_ir_ref_dynamic.
(elf_link_input_bfd): Test non_ir_ref_dynamic in addition to
non_ir_ref.
* linker.c (_bfd_generic_link_add_one_symbol): Likewise.

(cherry picked from commit 4070765b1a1640ff8f43483cd9ee06727f658dfe)

Handle symbol defined in IR and referenced in DSO

We need to make an IR symbol visible if it is defined in an IR object
and referenced in a dynamic object. When --as-needed is used, since
linker removes the IR symbol reference of the dynamic object if the
dynamic object isn't needed in the first pass, the IR definition isn't
visible to the dynamic object even if the dynamic object becomes needed
in the second pass. Add dynamic_ref_after_ir_def to bfd_link_hash_entry
to track IR symbol which is defined in an IR object and later referenced
in a dynamic object. dynamic_ref_after_ir_def is preserved when restoring
the symbol table for unneeded dynamic object.

bfd/

PR ld/21382
* elflink.c (elf_link_add_object_symbols): Preserve
dynamic_ref_after_ir_def when restoring the symbol table for
unneeded dynamic object.

include/

PR ld/21382
* bfdlink.h (bfd_link_hash_entry): Add dynamic_ref_after_ir_def.

ld/

PR ld/21382
* plugin.c (is_visible_from_outside): Symbol may be visible
from outside if dynamic_ref_after_ir_def is set.
(plugin_notice): Set dynamic_ref_after_ir_def if the symbol is
defined in an IR object and referenced in a dynamic object.
* testsuite/ld-plugin/lto.exp: Run PR ld/21382 tests.
* testsuite/ld-plugin/pr21382a.c: New file.
* testsuite/ld-plugin/pr21382b.c: Likewise.

(cherry picked from commit 59fa66c53823dc695f78669f40ec2eebab3aec42)

[ld, testsuite] Always assemble those intermediate .o files used later

ld/
* testsuite/ld-plugin/lto.exp (lto_link_elf_tests): Move "Compile 7",
"Compile 8a", "Compile 8b"...
(lto_compile_elf_tests): ...to here. Always run these tests.
(lto_run_elf_tests): Move "LTO 7"...
(lto_run_elf_shared_tests): ...to here. Restrict these tests on
environment where share library is supported.

(cherry picked from commit 077c11e8679ea7fb4fae977327786fea8353132f)

MIPS/BFD: Correct microMIPS cross-mode BAL to JALX relaxation

Fix a bug in commit a6ebf6169a1b ("MIPS: Convert cross-mode BAL to
JALX") and in BFD linker relaxation correct the microMIPS interpretation
of the branch offset, which is supposed to be shifted by 1 bit, rather
than 2 as in the regular MIPS case.

bfd/
* elfxx-mips.c (mips_elf_perform_relocation): Correct microMIPS
branch offset interpretation.

gas/
* testsuite/gas/mips/branch-addend-micromips.d: New test.
* testsuite/gas/mips/branch-addend-micromips-n32.d: New test.
* testsuite/gas/mips/branch-addend-micromips-n64.d: New test.
* testsuite/gas/mips/branch-addend-micromips.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.

ld/
* testsuite/ld-mips-elf/bal-jalx-addend-micromips.d: New test.
* testsuite/ld-mips-elf/bal-jalx-addend-micromips-n32.d: New
test.
* testsuite/ld-mips-elf/bal-jalx-addend-micromips-n64.d: New
test.
* testsuite/ld-mips-elf/bal-jalx-local-micromips.d: New test.
* testsuite/ld-mips-elf/bal-jalx-local-micromips-n32.d: New
test.
* testsuite/ld-mips-elf/bal-jalx-local-micromips-n64.d: New
test.
* testsuite/ld-mips-elf/bal-jalx-pic-micromips.d: New test.
* testsuite/ld-mips-elf/bal-jalx-pic-micromips-n32.d: New test.
* testsuite/ld-mips-elf/bal-jalx-pic-micromips-n64.d: New test.
* testsuite/ld-mips-elf/bal-jalx-pic-ignore-micromips.d: New
test.
* testsuite/ld-mips-elf/bal-jalx-pic-ignore-micromips-n32.d: New
test.
* testsuite/ld-mips-elf/bal-jalx-pic-ignore-micromips-n64.d: New
test.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.

(cherry picked from commit 70e65ca8e5d1fc984d58f6137c290e807fe772a5)

MIPS/GAS: Also respect `-mignore-branch-isa' with MIPS16 code

Fix a bug in commit 8b10b0b3e100 ("MIPS: Add options to control branch
ISA checks") and with the `-mignore-branch-isa' command-line option also
lift a GAS check for invalid MIPS16 branches between ISA modes, which is
made separately from regular MIPS and microMIPS checks.

gas/
* config/tc-mips.c (md_convert_frag): Respect
`mips_ignore_branch_isa'.
* testsuite/gas/mips/branch-local-5.d: New test.
* testsuite/gas/mips/branch-local-n32-5.d: New test.
* testsuite/gas/mips/branch-local-n64-5.d: New test.
* testsuite/gas/mips/branch-local-6.d: New test.
* testsuite/gas/mips/branch-local-n32-6.d: New test.
* testsuite/gas/mips/branch-local-n64-6.d: New test.
* testsuite/gas/mips/branch-local-7.d: New test.
* testsuite/gas/mips/branch-local-n32-7.d: New test.
* testsuite/gas/mips/branch-local-n64-7.d: New test.
* testsuite/gas/mips/branch-local-ignore-5.d: New test.
* testsuite/gas/mips/branch-local-ignore-n32-5.d: New test.
* testsuite/gas/mips/branch-local-ignore-n64-5.d: New test.
* testsuite/gas/mips/branch-local-ignore-6.d: New test.
* testsuite/gas/mips/branch-local-ignore-n32-6.d: New test.
* testsuite/gas/mips/branch-local-ignore-n64-6.d: New test.
* testsuite/gas/mips/branch-local-5.l: New stderr output.
* testsuite/gas/mips/branch-local-6.l: New stderr output.
* testsuite/gas/mips/branch-local-5.s: New test source.
* testsuite/gas/mips/branch-local-6.s: New test source.
* testsuite/gas/mips/branch-local-7.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.

(cherry picked from commit 37b2d327512baf2f39020e44958fd1f11db46a91)

Merge with binutils-2_28-branch rev a595e022494

Change-Id: Id5cdd9fca875884f6e31a9a0847aa098d956bf23

[AArch64] Add dot product support for AArch64 to binutils

gas/
* config/tc-aarch64.c (aarch64_reg_parse_32_64): Accept 4B.
(aarch64_features): Added dotprod.
* doc/c-aarch64.texi: Added dotprod.
* testsuite/gas/aarch64/dotproduct.d: New.
* testsuite/gas/aarch64/dotproduct.s: New.

opcodes/
* aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
* aarch64-dis.c (aarch64_ext_reglane): Likewise.
* aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
(aarch64_feature_dotprod, DOT_INSN): New.
(udot, sdot): New.
* aarch64-dis-2.c: Regenerated.

include/
* opcode/aarch64.h: (AARCH64_FEATURE_DOTPROD): New.
(aarch64_insn_class): Added dotprod.

Cherry-pick of 65a55fbbd949868f7df3c65d39eb8d4455515132.

Change-Id: I712657d13a2fdb43f14536aa0388dbbb2d13ee43

[ARM] Assembler and disassembler support Dot Product Extension

This patch add assembler and disassembler support for new Dot Product
Extension.

The support can be enabled through the new "+dotprod" extension.

include/
* opcode/arm.h (FPU_NEON_EXT_DOTPROD): New macro.
(FPU_ARCH_DOTPROD_NEON_VFP_ARMV8): New macro.

gas/
* config/tc-arm.c (fpu_neon_ext_dotprod): New variable.
(neon_scalar_for_mul): Improve comments.
(do_neon_dotproduct): New function to encode Dot Product instructions.
(do_neon_dotproduct_s): Wrapper function for signed Dot Product
instructions.
(do_neon_dotproduct_u): Wrapper function for unsigned Dot Product
instructions.
(insns): New entries for vsdot and vudot.
(arm_extensions): New entry for "dotprod".
* doc/c-arm.texi: Document new "dotprod" extension.
* testsuite/gas/arm/dotprod.s: New test source.
* testsuite/gas/arm/dotprod-illegal.s: New test source.
* testsuite/gas/arm/dotprod.d: New test.
* testsuite/gas/arm/dotprod-thumb2.d: New test.
* testsuite/gas/arm/dotprod-illegal.d: New test.
* testsuite/gas/arm/dotprod-legacy-arch.d: New test.
* testsuite/gas/arm/dotprod-illegal.l: New error file.
* testsuite/gas/arm/dotprod-legacy-arch.l: New error file.

opcodes/
* arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.

Cherry-pick of c604a79ad4d47070bbcc0bc082188fb16892ceef.

Change-Id: I5521f218ba3627c1f8b3a9ef20277aa02298e2ae

gold: Add put_ch_reserved to 64-bit Chdr_write

The 64-bit ELF compression header has a reserved field. It should be
cleared to avoid random bits in it.

elfcpp/

PR gold/21857
* elfcpp.h (Chdr_write): Add put_ch_reserved.
(Chdr_write<64, true>::put_ch_reserved): New.
(Chdr_write<64, false>::put_ch_reserved): Likewise.

gold/

PR gold/21857
* compressed_output.cc (Output_compressed_section::set_final_data_size):
Call put_ch_reserved to clear the reserved field for 64-bit ELF.

(cherry picked from commit 49ba15a23a9d3d8a109ce2fd5053822eee7f1fdf)

S/390: Fix segfault when linking -shared -nostartfiles

Regression-tested on s390x.

bfd/ChangeLog:

2017-07-28 Andreas Krebbel <krebbel@linux.vnet.ibm.com>

Backport from mainline
2017-07-28 Andreas Krebbel <krebbel@linux.vnet.ibm.com>

* elf32-s390.c (elf_s390_finish_dynamic_sections): Add NULL
pointer check for htab->elf.irelplt.
* elf64-s390.c (elf_s390_finish_dynamic_sections): Likewise.

S/390: Support z14 as CPU name.

With IBM z14 officially announced I can add z14 as CPU name.

No regressions with that patch on s390x.

gas/ChangeLog:

2017-07-26 Andreas Krebbel <krebbel@linux.vnet.ibm.com>

Backport from mainline
2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>

* config/tc-s390.c (s390_parse_cpu): Add z14 as alternate CPU
name.
* doc/as.texinfo: Add z14 to CPU string list.
* doc/c-s390.texi: Likewise.

opcodes/ChangeLog:

2017-07-26 Andreas Krebbel <krebbel@linux.vnet.ibm.com>

Backport from mainline
2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>

* s390-mkopc.c (main): Enable z14 as CPU string in the opcode
table.

Bump version.

bfd/
2017-07-25 Tristan Gingold <gingold@adacore.com>

* version.m4: Bump version to 2.28.2
* configure: Regenerate.

binutils/
2017-07-25 Tristan Gingold <gingold@adacore.com>

* configure: Regenerate.

gas/
2017-07-25 Tristan Gingold <gingold@adacore.com>

* configure: Regenerate.

gprof/
2017-07-25 Tristan Gingold <gingold@adacore.com>

* configure: Regenerate.

ld/
2017-07-25 Tristan Gingold <gingold@adacore.com>

* configure: Regenerate.

opcodes/
2017-07-25 Tristan Gingold <gingold@adacore.com>

* configure: Regenerate.

Version 2.28.1

bfd/
2017-07-25 Tristan Gingold <gingold@adacore.com>

* version.m4: Bump version to 2.28.1
* configure: Regenerate.

binutils/
2017-07-25 Tristan Gingold <gingold@adacore.com>

* configure: Regenerate.

gas/
2017-07-25 Tristan Gingold <gingold@adacore.com>

* configure: Regenerate.

gprof/
2017-07-25 Tristan Gingold <gingold@adacore.com>

* configure: Regenerate.

ld/
2017-07-25 Tristan Gingold <gingold@adacore.com>

* configure: Regenerate.

opcodes/
2017-07-25 Tristan Gingold <gingold@adacore.com>

* configure: Regenerate.

[Patch, ARM] Relax the restrictions on REG_SP under Thumb mode on ARMv8-A

Backport from mainline
2017-06-06 Jiong Wang <jiong.wang@arm.com>
* config/tc-arm.c (reject_bad_reg): Allow REG_SP on ARMv8-A.
(parse_operands): Allow REG_SP for OP_oRRnpcsp and OP_RRnpcsp on
ARMv8-A.
(do_co_reg): Allow REG_SP for Rd on ARMv8-A.
(do_t_add_sub): Likewise.
(do_t_mov_cmp): Likewise.
(do_t_tb): Likewise.
* testsuite/gas/arm/ld-sp-warn.l: Delete the warning on REG_SP as Rt for
ldrsb.
* testsuite/gas/arm/sp-pc-validations-bad-t-v8a.d: New test.
* testsuite/gas/arm/sp-pc-validations-bad-t-v8a.l: New test.
* testsuite/gas/arm/sp-pc-validations-bad-t.d: Specifies -march=armv7-a.
* testsuite/gas/arm/sp-pc-validations-bad-t.s: Remove ".arch armv7-a".
* testsuite/gas/arm/sp-usage-thumb2-relax-on-v7.d: New test.
* testsuite/gas/arm/sp-usage-thumb2-relax-on-v7.l: New test.
* testsuite/gas/arm/sp-usage-thumb2-relax-on-v8.d: New test.
* testsuite/gas/arm/sp-usage-thumb2-relax.s: New test.
* testsuite/gas/arm/strex-bad-t.d: Specifies -march=armv7-a.

Fixing for PR gold/21491 - Errata workaround can produce broken images.

The problem is caused by the fact that gold is relocating the stubs
for an entire output section when it processes the relocations for a
particular input section that happened to be designated as the stub
table "owner". The Relocate_task for that input section may or may not
run before the Relocate_task for another input section that contains
the code that needs the erratum fix, but doesn't "own" the stub
table. If it runs before (or might even race with) that other task, it
ends up with a copy of the unrelocated original instruction.

In other words - when calling fix_errata() from
do_relocate_sections(), gold is going through the list of errata stubs
that are associated only with that object. This routine updates the
stored original instruction and replaces it in the output view with a
branch to the stub. Later, as gold is going through the object file's
input sections, it then checks for stub tables "owned" by each input
section, and writes out all the stubs from that stub table, regardless
of what object file each stub is associated with.

Fixed by relocating the erratum stub only after the corresponding
errata spot is fixed. That is to have fix_errata() call
Stub_table::relocate_erratum_stub() for each stub.

gold/ChangeLog
2017-07-06 Han Shen <shenhan@google.com>

PR gold/21491

* aarch64.cc (Erratum_stub::invalidate_erratum_stub): New method.
(Erratum_stub::is_invalidated_erratum_stub): New method.
(Stub_table::relocate_reloc_stub): Renamed from "relocate_stub".
(Stub_table::relocate_reloc_stubs): Renamed from "relocate_stubs".
(Stub_table::relocate_erratum_stub): New method.
(AArch64_relobj::fix_errata_and_relocate_erratum_stubs): Renamed from
"fix_errata".
(Target_aarch64::relocate_reloc_stub): Renamed from "relocate_stub".

Automatic date update in version.in

[Patch ARM] Support MVFR2 VFP Coprocessor register for ARMv8-A

This patch adds support mvfr2 control registers for armv8-a as
this was missed from the original port to armv8-a (documented
at G6.2.109 in (Issue B.a) of the ARM-ARM. This was discovered
by an internal user of the GNU toolchain.

I'd like to backport this to the binutils 2.28 and binutils 2.29
release branch if possible (with suitable testing and basically
checking removing the armv8-r parts).

regards Ramana

2017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>

* gas/config/tc-arm.c (arm_regs): Add MVFR2.
(do_vmrs): Constraint for MVFR2 and armv8.
(do_vmsr): Likewise.
* gas/testsuite/gas/arm/armv8-a+fp.d: Update.
* gas/testsuite/gas/arm/armv8-a+fp.s: Likewise.
* gas/testsuite/gas/arm/vfp-bad.s: Likewise.
* gas/testsuite/gas/arm/vfp-bad.l: Likewise.
* opcodes/arm-dis.c: Support MVFR2 in disassembly
with vmrs and vmsr.

Automatic date update in version.in

Fix ChangeLog entry

Backport of 046734ff424bc5a4c1b6a69630d5bb31aa67165c in
01106f569a3acb935447a2a7b3ee7f6866c7ea6c added the ld ChangeLog entry
to the gas ChangeLog file. This commit fixes it.

Automatic date update in version.in

Automatic date update in version.in