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Rev. Time Author
501593e renesas_hw_202105 2021-05-27 14:10:44 Yoshinori Sato

hw/rx: rx-gdbsim Add bootstrup for linux

linux kernel require initializing some peripherals.

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>

3254665 2021-05-27 14:10:44 Yoshinori Sato

hw/sh4: sh7750 use new hw modules.

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>

47faad9 2021-05-27 14:10:44 Yoshinori Sato

hw/sh4: sh7750 Add CPG.

CPG required new hw modules.

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>

416102e 2021-05-27 14:10:44 Yoshinori Sato

hw/rx: rx62n use new hw modules.

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>

45790cb 2021-05-27 14:10:39 Yoshinori Sato

hw/timer: Renesas 8bit timer.

Rewrite timer api.

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>

41ef8d4 2021-05-27 14:10:38 Yoshinori Sato

hw/rx: Add RX62N Clock generator

This module generated core and peripheral clock.

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>

cf75304 2021-05-27 14:10:38 Yoshinori Sato

hw/timer: Remove renesas_cmt.

Migrate to renesas_timer.

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>

efc7690 2021-05-27 14:10:38 Yoshinori Sato

hw/timer: Remove sh_timer.

Migrate to renesas_timer.

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>

dc983cc 2021-05-27 14:10:32 Yoshinori Sato

hw/timer: Renesas TMU/CMT module.

TMU - SH4 Timer module.
CMT - Compare and match timer used by some Renesas MCUs.

The two modules have similar interfaces and have been merged.

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>

b67abdd 2021-05-27 14:10:32 Yoshinori Sato

hw/char: remove sh_serial.

Migrate to renesas_sci.

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>

f28e129 2021-05-27 14:10:23 Yoshinori Sato

hw/char: Renesas SCI module.

This module supported SCI / SCIa / SCIF.

Hardware manual.
SCI / SCIF
https://www.renesas.com/us/en/doc/products/mpumcu/001/r01uh0457ej0401_sh7751.pdf
SCIa
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>

92f8c6f 2021-05-26 00:17:06 Peter Maydell

target-arm queue:
* Implement SVE2 emulation
* Implement integer matrix multiply accumulate
* Implement FEAT_TLBIOS
* Implement FEAT_TLBRANGE
* disas/libvixl: Protect C system header for C++ compiler
* Use correct SP in M-profile exception return
* AN524, AN547: Correct modelling of internal SRAMs
* hw/intc/arm_gicv3_cpuif: Fix EOIR write access check logic
* hw/arm/smmuv3: Another range invalidation fix
-----BEGIN PGP SIGNATURE-----

iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmCtEYEZHHBldGVyLm1h
eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3mTGD/9udRUbfe6gfYGakZQL69t4
iDGxREE6dlEwma0WxP00CGNWQTleh+TwEHxv02ITk4Ni8L62yJGrTvAUcsTrTtSa
OQN1p6IxS2bVNo0nAH+VT+Ry3Ttg0OEKZo3tzT0ICERWwmz0sxnq5CBp1s5mFJp1
OIxGaHLdjrkPt4OHKbMekoU7IJomsxHPb0D7+LyNVFq4wxxg03NfscfyfacYtAVI
kfhO9/fniH4YZbEhQ6YUSnRjFpQBiuH/8AgOSki2VD+vaIZnXXMkrVhUU4V6qIfU
SVg1cy0XWxxNTNVXsqPzQlwK/eBgYe9dpmnOndAfAls7v3+BHUa9kKq/wOx11WVu
kehjrLss5c5y2Vev3CqopC/htXAWDDAPUgGDDNpoqT6rvRnRUDQEfA+jTL3Srsyq
PEShmATq36hoE1mDMAtkv98JAtfj/Uzy2bBlJ34DXdAE+/erZax9HF57TmxN2NYn
2y1Xp7JTJVz8xK13Nz/dlsXSuaUH7WI/WG/zzEJE8Kain+RBKfm0OmXIjM3cJVTk
T45nMTZCXejSXliIThKhNc3abC2xsF/X2R1bZKH/kRQ2/eNPVIPjMN4oO/iRXQ1Q
fGB68wA80XM5EOGiuqpE2GZnCpvh3iMRwa+4Ps7HjfetTfM068jV5HX5+nYIgE8H
VpA02UbPU0RzsHW/E3/blQ==
=BwQN
-----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210525' into staging

target-arm queue:
* Implement SVE2 emulation
* Implement integer matrix multiply accumulate
* Implement FEAT_TLBIOS
* Implement FEAT_TLBRANGE
* disas/libvixl: Protect C system header for C++ compiler
* Use correct SP in M-profile exception return
* AN524, AN547: Correct modelling of internal SRAMs
* hw/intc/arm_gicv3_cpuif: Fix EOIR write access check logic
* hw/arm/smmuv3: Another range invalidation fix

# gpg: Signature made Tue 25 May 2021 16:02:25 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20210525: (114 commits)
target/arm: Enable SVE2 and related extensions
linux-user/aarch64: Enable hwcap bits for sve2 and related extensions
target/arm: Implement integer matrix multiply accumulate
target/arm: Implement aarch32 VSUDOT, VUSDOT
target/arm: Split decode of VSDOT and VUDOT
target/arm: Split out do_neon_ddda
target/arm: Fix decode for VDOT (indexed)
target/arm: Remove unused fpst from VDOT_scalar
target/arm: Split out do_neon_ddda_fpst
target/arm: Implement aarch64 SUDOT, USDOT
target/arm: Implement SVE2 fp multiply-add long
target/arm: Move endian adjustment macros to vec_internal.h
target/arm: Implement SVE2 bitwise shift immediate
target/arm: Implement 128-bit ZIP, UZP, TRN
target/arm: Implement SVE2 LD1RO
target/arm: Tidy do_ldrq
target/arm: Share table of sve load functions
target/arm: Implement SVE2 FLOGB
target/arm: Implement SVE2 FCVTXNT, FCVTX
target/arm: Implement SVE2 FCVTLT
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

f8680aa 2021-05-26 00:01:44 Richard Henderson

target/arm: Enable SVE2 and related extensions

Disable I8MM again for !have_neon during realize.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-93-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

cdc8d8b 2021-05-26 00:01:44 Richard Henderson

linux-user/aarch64: Enable hwcap bits for sve2 and related extensions

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-92-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

2323c5f 2021-05-26 00:01:44 Richard Henderson

target/arm: Implement integer matrix multiply accumulate

This is {S,U,US}MMLA for both AArch64 AdvSIMD and SVE,
and V{S,U,US}MMLA.S8 for AArch32 NEON.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-91-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

51879c6 2021-05-26 00:01:44 Richard Henderson

target/arm: Implement aarch32 VSUDOT, VUSDOT

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-90-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

f0ad96c 2021-05-26 00:01:44 Richard Henderson

target/arm: Split decode of VSDOT and VUDOT

Now that we have a common helper, sharing decode does not
save much. Also, this will solve an upcoming naming problem.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-89-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

5a46304 2021-05-26 00:01:44 Richard Henderson

target/arm: Split out do_neon_ddda

Split out a helper that can handle the 4-register
format for helpers shared with SVE.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-88-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

64ea608 2021-05-26 00:01:44 Richard Henderson

target/arm: Fix decode for VDOT (indexed)

We were extracting the M register twice, once incorrectly
as M:vm and once correctly as rm. Remove the incorrect
name and remove the incorrect decode.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-87-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

25fa6f8 2021-05-26 00:01:44 Richard Henderson

target/arm: Remove unused fpst from VDOT_scalar

Cut and paste error from another pattern.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-86-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

505fce5 2021-05-26 00:01:44 Richard Henderson

target/arm: Split out do_neon_ddda_fpst

Split out a helper that can handle the 4-register
format for helpers shared with SVE.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-85-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

f7da051 2021-05-26 00:01:44 Richard Henderson

target/arm: Implement aarch64 SUDOT, USDOT

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-84-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

50d102b 2021-05-26 00:01:44 Stephen Long

target/arm: Implement SVE2 fp multiply-add long

Implements both vectored and indexed FMLALB, FMLALT, FMLSLB, FMLSLT

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-83-richard.henderson@linaro.org
Message-Id: <20200504171240.11220-1-steplong@quicinc.com>
[rth: Rearrange to use float16_to_float32_by_bits.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

93966af 2021-05-26 00:01:44 Richard Henderson

target/arm: Move endian adjustment macros to vec_internal.h

We have two copies of these, one set of which is not complete.
Move them to a common header.

Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-82-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

a5421b5 2021-05-26 00:01:44 Stephen Long

target/arm: Implement SVE2 bitwise shift immediate

Implements SQSHL/UQSHL, SRSHR/URSHR, and SQSHLU

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-81-richard.henderson@linaro.org
Message-Id: <20200430194159.24064-1-steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

74b64b2 2021-05-26 00:01:44 Richard Henderson

target/arm: Implement 128-bit ZIP, UZP, TRN

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-80-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

12c563f 2021-05-26 00:01:44 Richard Henderson

target/arm: Implement SVE2 LD1RO

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-79-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

7924d23 2021-05-26 00:01:44 Richard Henderson

target/arm: Tidy do_ldrq

Use tcg_constant_i32 for passing the simd descriptor,
as this hashed value does not need to be freed.
Rename dofs to doff to match poff.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-78-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

c182c6d 2021-05-26 00:01:44 Richard Henderson

target/arm: Share table of sve load functions

The table used by do_ldrq is a subset of the table used by do_ld_zpa;
we can share them by passing dtype instead of msz to do_ldrq.

The lack of MTE handling in do_ldrq was a bug, fixed by this change.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-77-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

631be02 2021-05-26 00:01:44 Stephen Long

target/arm: Implement SVE2 FLOGB

Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-76-richard.henderson@linaro.org
Message-Id: <20200430191405.21641-1-steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>