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Revisiona17daafd315e33b50e098c91e2924916c9e952dd (tree)
Time2019-01-20 16:44:39
AuthorYoshinori Sato <ysato@user...>
CommiterYoshinori Sato

Log Message

cleanup PSW handling

Change Summary

Incremental Difference

--- a/target/rx/cpu.h
+++ b/target/rx/cpu.h
@@ -74,19 +74,20 @@
7474 #define NB_MMU_MODES 1
7575 #define MMU_MODE0_SUFFIX _all
7676
77-#define RX_PSW_OP_SUB 0
78-#define RX_PSW_OP_ADD 1
79-#define RX_PSW_OP_ABS 2
80-#define RX_PSW_OP_DIV 3
81-#define RX_PSW_OP_STRING 4
82-#define RX_PSW_OP_BTST 5
83-#define RX_PSW_OP_LOGIC 6
84-#define RX_PSW_OP_ROT 7
85-#define RX_PSW_OP_SHLL 8
86-#define RX_PSW_OP_SHAR 9
87-#define RX_PSW_OP_SHLR 10
88-#define RX_PSW_OP_FLOAT 11
89-#define RX_PSW_OP_FCMP 12
77+#define RX_PSW_OP_NONE 0
78+#define RX_PSW_OP_SUB 1
79+#define RX_PSW_OP_ADD 2
80+#define RX_PSW_OP_ABS 3
81+#define RX_PSW_OP_DIV 4
82+#define RX_PSW_OP_STRING 5
83+#define RX_PSW_OP_BTST 6
84+#define RX_PSW_OP_LOGIC 7
85+#define RX_PSW_OP_ROT 8
86+#define RX_PSW_OP_SHLL 9
87+#define RX_PSW_OP_SHAR 10
88+#define RX_PSW_OP_SHLR 11
89+#define RX_PSW_OP_FLOAT 12
90+#define RX_PSW_OP_FCMP 13
9091
9192 typedef struct memory_content {
9293 uint32_t address;
@@ -129,7 +130,7 @@ typedef struct CPURXState {
129130 uint32_t op_a1[12];
130131 uint32_t op_a2[12];
131132 uint32_t op_r[12];
132- uint32_t op_mode[4];
133+ uint32_t op_mode;
133134 /* Fields up to this point are cleared by a CPU reset */
134135 struct {} end_reset_fields;
135136
--- a/target/rx/helper.c
+++ b/target/rx/helper.c
@@ -29,28 +29,37 @@
2929
3030 static uint32_t psw_c(CPURXState *env)
3131 {
32- int m = env->op_mode[PSW_C];
33- if (env->psw_c != -1)
34- return env->psw_c;
32+ int m = env->op_mode & 0x000f;
33+ int c;
3534 switch (m) {
35+ case RX_PSW_OP_NONE:
36+ return env->psw_c;
3637 case RX_PSW_OP_ADD:
37- return (env->op_r[m] < env->op_a1[m]);
38+ c = (env->op_r[m - 1] < env->op_a1[m - 1]);
39+ break;
3840 case RX_PSW_OP_SUB:
3941 case RX_PSW_OP_STRING:
40- return (env->op_r[m] <= env->op_a1[m]);
42+ c = (env->op_r[m - 1] <= env->op_a1[m - 1]);
43+ break;
4144 case RX_PSW_OP_BTST:
4245 case RX_PSW_OP_ROT:
43- return (env->op_r[m] != 0);
46+ c = (env->op_r[m - 1] != 0);
47+ break;
4448 case RX_PSW_OP_SHLL:
4549 case RX_PSW_OP_SHAR:
4650 case RX_PSW_OP_SHLR:
47- return (env->op_a1[m] != 0);
51+ c = (env->op_a1[m - 1] != 0);
52+ break;
4853 case RX_PSW_OP_ABS:
49- return (env->op_r[m] == 0);
54+ c = (env->op_r[m - 1] == 0);
55+ break;
5056 default:
5157 g_assert_not_reached();
5258 return -1;
5359 }
60+ env->psw_c = c;
61+ env->op_mode &= ~0x000f;
62+ return c;
5463 }
5564
5665 uint32_t helper_psw_c(CPURXState *env)
@@ -60,21 +69,33 @@ uint32_t helper_psw_c(CPURXState *env)
6069
6170 static uint32_t psw_z(CPURXState *env)
6271 {
63- if (env->psw_z != -1)
72+ int m = (env->op_mode >> 4) & 0x000f;
73+ if (m == RX_PSW_OP_NONE)
6474 return env->psw_z;
65- else
66- return (env->op_r[env->op_mode[PSW_Z]] == 0);
75+ else {
76+ env->psw_z = (env->op_r[m - 1] == 0);
77+ env->op_mode &= ~0x00f0;
78+ return env->psw_z;
79+ }
6780 }
6881
6982 static uint32_t psw_s(CPURXState *env)
7083 {
71- int m = env->op_mode[PSW_S];
72- if (env->psw_s != -1)
84+ int m = (env->op_mode >> 8) & 0x000f;
85+ int s;
86+ switch (m) {
87+ case RX_PSW_OP_NONE:
7388 return env->psw_s;
74- if (m == RX_PSW_OP_FCMP)
75- return (env->op_r[m] == 2);
76- else
77- return ((env->op_r[m] & 0x80000000UL) != 0);
89+ case RX_PSW_OP_FCMP:
90+ s = (env->op_r[m - 1] == 2);
91+ break;
92+ default:
93+ s = ((env->op_r[m - 1] & 0x80000000UL) != 0);
94+ break;
95+ }
96+ env->psw_s = s;
97+ env->op_mode &= ~0x0f00;
98+ return s;
7899 }
79100
80101 uint32_t helper_psw_s(CPURXState *env)
@@ -84,38 +105,50 @@ uint32_t helper_psw_s(CPURXState *env)
84105
85106 static uint32_t psw_o(CPURXState *env)
86107 {
87- int m = env->op_mode[PSW_O];
88- if (env->psw_o != -1)
89- return env->psw_o;
108+ int m = (env->op_mode >> 12) & 0x000f;
109+ int o;
110+
90111 switch(m) {
112+ case RX_PSW_OP_NONE:
113+ return env->psw_o;
91114 case RX_PSW_OP_ABS:
92- return (env->op_a1[m] == 0x80000000UL);
115+ o = (env->op_a1[m - 1] == 0x80000000UL);
116+ break;
93117 case RX_PSW_OP_ADD:
94118 do {
95119 uint32_t r1, r2;
96- r1 = ~(env->op_a1[m] ^ env->op_a2[m]);
97- r2 = (env->op_a1[m] ^ env->op_r[m]);
98- return (r1 & r2) >> 31;
120+ r1 = ~(env->op_a1[m - 1] ^ env->op_a2[m - 1]);
121+ r2 = (env->op_a1[m - 1] ^ env->op_r[m - 1]);
122+ o = (r1 & r2) >> 31;
99123 } while(0);
124+ break;
100125 case RX_PSW_OP_SUB:
101126 do {
102127 uint32_t r1, r2;
103- r1 = (env->op_a1[m] ^ env->op_a2[m]);
104- r2 = (env->op_a1[m] ^ env->op_r[m]);
105- return (r1 & r2) >> 31;
128+ r1 = (env->op_a1[m - 1] ^ env->op_a2[m - 1]);
129+ r2 = (env->op_a1[m - 1] ^ env->op_r[m - 1]);
130+ o = (r1 & r2) >> 31;
106131 } while(0);
132+ break;
107133 case RX_PSW_OP_DIV:
108- return (env->op_a1[m] == 0) ||
109- ((env->op_a1[m] == -1) && (env->op_a2[m] == 0x80000000UL));
134+ o = (env->op_a1[m - 1] == 0) ||
135+ ((env->op_a1[m - 1] == -1) &&
136+ (env->op_a2[m - 1] == 0x80000000UL));
137+ break;
110138 case RX_PSW_OP_SHLL:
111- return ((env->op_a2[m] & 0x80000000UL) ^
112- (env->op_r[m] & 0x80000000UL)) != 0;
139+ o = ((env->op_a2[m - 1] & 0x80000000UL) ^
140+ (env->op_r[m - 1] & 0x80000000UL)) != 0;
141+ break;
113142 case RX_PSW_OP_SHAR:
114- return 0;
143+ o = 0;
144+ break;
115145 default:
116146 g_assert_not_reached();
117147 return -1;
118148 }
149+ env->psw_o = o;
150+ env->op_mode &= ~0xf000;
151+ return o;
119152 }
120153
121154 uint32_t helper_psw_o(CPURXState *env)
@@ -209,8 +242,7 @@ void helper_update_psw(CPURXState *env)
209242
210243 for (i = 0; i < 4; i++)
211244 *(update_proc[i].p) = update_proc[i].fn(env);
212- g_assert(env->psw_c != -1 && env->psw_z != -1 &&
213- env->psw_s != -1 && env->psw_o != -1);
245+ g_assert((env->op_mode & 0xffff) == 0);
214246 }
215247
216248 void rx_cpu_do_interrupt(CPUState *cs)
@@ -551,6 +583,7 @@ void rx_cpu_unpack_psw(CPURXState *env, int all)
551583 env->psw_s = (env->psw >> 2) & 1;
552584 env->psw_z = (env->psw >> 1) & 1;
553585 env->psw_c = (env->psw >> 0) & 1;
586+ env->op_mode = 0;
554587 }
555588
556589 uint32_t helper_mvfc(CPURXState *env, uint32_t cr)
--- a/target/rx/translate.c
+++ b/target/rx/translate.c
@@ -38,14 +38,10 @@ typedef struct DisasContext {
3838 } DisasContext;
3939
4040 typedef struct {
41- TCGv op_mode[4];
42- TCGv op_a1[12];
43- TCGv op_a2[12];
44- TCGv op_r[12];
45- TCGv_i32 override;
46- TCGCond cond;
47- TCGv arg1;
48- TCGv arg2;
41+ TCGv op_mode;
42+ TCGv op_a1[13];
43+ TCGv op_a2[13];
44+ TCGv op_r[13];
4945 } CCOP;
5046 CCOP ccop;
5147
@@ -64,7 +60,6 @@ static TCGv cpu_pc, cpu_acc_m, cpu_acc_l;
6460
6561 #include "exec/gen-icount.h"
6662
67-
6863 void rx_cpu_dump_state(CPUState *cs, FILE *f,
6964 fprintf_function cpu_fprintf, int flags)
7065 {
@@ -142,58 +137,45 @@ static uint32_t rx_load_simm(CPURXState *env, uint32_t addr, int sz, uint32_t *r
142137 }
143138 }
144139
145-#define SET_MODE_O(mode) \
146- do { \
147- tcg_gen_movi_i32(ccop.op_mode[PSW_O], mode); \
148- tcg_gen_movi_i32(cpu_psw_o, 0xffffffff); \
140+#define SET_MODE_O(mode) \
141+ do { \
142+ tcg_gen_andi_i32(ccop.op_mode, ccop.op_mode, ~0xf000); \
143+ tcg_gen_ori_i32(ccop.op_mode, ccop.op_mode, mode << 12); \
149144 } while(0)
150145
151-#define SET_MODE_ZS(mode) \
152- do { \
153- tcg_gen_movi_i32(ccop.op_mode[PSW_Z], mode); \
154- tcg_gen_movi_i32(ccop.op_mode[PSW_S], mode); \
155- tcg_gen_movi_i32(cpu_psw_z, 0xffffffff); \
156- tcg_gen_movi_i32(cpu_psw_s, 0xffffffff); \
146+#define SET_MODE_ZS(mode) \
147+ do { \
148+ tcg_gen_andi_i32(ccop.op_mode, ccop.op_mode, ~0x0ff0); \
149+ tcg_gen_ori_i32(ccop.op_mode, ccop.op_mode, \
150+ (mode << 8) | (mode << 4)); \
157151 } while(0)
158152
159-#define SET_MODE_ZSO(mode) \
160- do { \
161- tcg_gen_movi_i32(ccop.op_mode[PSW_Z], mode); \
162- tcg_gen_movi_i32(ccop.op_mode[PSW_S], mode); \
163- tcg_gen_movi_i32(ccop.op_mode[PSW_O], mode); \
164- tcg_gen_movi_i32(cpu_psw_z, 0xffffffff); \
165- tcg_gen_movi_i32(cpu_psw_s, 0xffffffff); \
166- tcg_gen_movi_i32(cpu_psw_o, 0xffffffff); \
153+#define SET_MODE_ZSO(mode) \
154+ do { \
155+ tcg_gen_andi_i32(ccop.op_mode, ccop.op_mode, ~0xfff0); \
156+ tcg_gen_ori_i32(ccop.op_mode, ccop.op_mode, \
157+ (mode << 12) | (mode << 8) | (mode << 4)); \
167158 } while(0)
168159
169-#define SET_MODE_CZ(mode) \
170- do { \
171- tcg_gen_movi_i32(ccop.op_mode[PSW_C], mode); \
172- tcg_gen_movi_i32(ccop.op_mode[PSW_Z], mode); \
173- tcg_gen_movi_i32(cpu_psw_c, 0xffffffff); \
174- tcg_gen_movi_i32(cpu_psw_z, 0xffffffff); \
160+#define SET_MODE_CZ(mode) \
161+ do { \
162+ tcg_gen_andi_i32(ccop.op_mode, ccop.op_mode, ~0x00ff); \
163+ tcg_gen_ori_i32(ccop.op_mode, ccop.op_mode, \
164+ (mode << 4) | mode); \
175165 } while(0)
176166
177-#define SET_MODE_CZSO(mode) \
178- do { \
179- tcg_gen_movi_i32(ccop.op_mode[PSW_C], mode); \
180- tcg_gen_movi_i32(ccop.op_mode[PSW_Z], mode); \
181- tcg_gen_movi_i32(ccop.op_mode[PSW_S], mode); \
182- tcg_gen_movi_i32(ccop.op_mode[PSW_O], mode); \
183- tcg_gen_movi_i32(cpu_psw_c, 0xffffffff); \
184- tcg_gen_movi_i32(cpu_psw_z, 0xffffffff); \
185- tcg_gen_movi_i32(cpu_psw_s, 0xffffffff); \
186- tcg_gen_movi_i32(cpu_psw_o, 0xffffffff); \
167+#define SET_MODE_CZSO(mode) \
168+ do { \
169+ tcg_gen_movi_i32(ccop.op_mode, \
170+ (mode << 12) | (mode << 8) | \
171+ (mode << 4) | mode); \
187172 } while(0)
188173
189-#define SET_MODE_CZS(mode) \
190- do { \
191- tcg_gen_movi_i32(ccop.op_mode[PSW_C], mode); \
192- tcg_gen_movi_i32(ccop.op_mode[PSW_Z], mode); \
193- tcg_gen_movi_i32(ccop.op_mode[PSW_S], mode); \
194- tcg_gen_movi_i32(cpu_psw_c, 0xffffffff); \
195- tcg_gen_movi_i32(cpu_psw_z, 0xffffffff); \
196- tcg_gen_movi_i32(cpu_psw_s, 0xffffffff); \
174+#define SET_MODE_CZS(mode) \
175+ do { \
176+ tcg_gen_andi_i32(ccop.op_mode, ccop.op_mode, ~0x0fff); \
177+ tcg_gen_ori_i32(ccop.op_mode, ccop.op_mode, \
178+ (mode << 8) | (mode << 4) | mode); \
197179 } while(0)
198180
199181 #define DEFINE_INSN(name) \
@@ -1762,6 +1744,7 @@ DEFINE_INSN(rmpa)
17621744 tcg_gen_ext16s_i32(cpu_regs[6], cpu_regs[6]);
17631745 tcg_gen_shri_i32(cpu_psw_s, cpu_regs[6], 31);
17641746 tcg_gen_movi_i32(cpu_psw_o, 0);
1747+ tcg_gen_andi_i32(ccop.op_mode, ccop.op_mode, 0x00ff);
17651748 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_regs[6], 0, l3);
17661749 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_regs[6], -1, l3);
17671750 tcg_gen_movi_i32(cpu_psw_o, 1);
@@ -2298,10 +2281,13 @@ DEFINE_INSN(clrsetpsw)
22982281 cpu_psw_i, cpu_psw_u, NULL, NULL,
22992282 NULL, NULL, NULL,NULL
23002283 };
2284+ static const uint32_t opmask[] = {~0x000f, ~0x00f0, ~0x0f00, ~0xf000};
23012285 int mode,dst;
23022286 mode = (insn >> 20 & 1);
23032287 dst = (insn >> 16) & 15;
23042288 tcg_gen_movi_i32(psw[dst], (mode?0:1));
2289+ if (dst < 4)
2290+ tcg_gen_andi_i32(ccop.op_mode, ccop.op_mode, opmask[dst]);
23052291 dc->pc += 2;
23062292 }
23072293
@@ -2699,7 +2685,7 @@ struct op {
26992685 OPTABLE(0x4400, 0xfc00, cmp4)
27002686 OPTABLE(0x0604, 0xff3c, cmp5)
27012687
2702- OPTABLE(0xfc00, 0xfff8, adc2sbb1)
2688+ OPTABLE(0xfc00, 0xfff4, adc2sbb1)
27032689
27042690 OPTABLE(0x7e00, 0xffc0, absnegnot1)
27052691 OPTABLE(0xfc03, 0xffc3, absnegnot2)
@@ -2947,22 +2933,19 @@ void rx_translate_init(void)
29472933 regnames[i]);
29482934 }
29492935 for (i = 0; i < 12; i++) {
2950- ccop.op_a1[i] = tcg_global_mem_new_i32(cpu_env,
2936+ ccop.op_a1[i + 1] = tcg_global_mem_new_i32(cpu_env,
29512937 offsetof(CPURXState, op_a1[i]),
29522938 "");
2953- ccop.op_a2[i] = tcg_global_mem_new_i32(cpu_env,
2939+ ccop.op_a2[i + 1] = tcg_global_mem_new_i32(cpu_env,
29542940 offsetof(CPURXState, op_a2[i]),
29552941 "");
2956- ccop.op_r[i] = tcg_global_mem_new_i32(cpu_env,
2942+ ccop.op_r[i + 1] = tcg_global_mem_new_i32(cpu_env,
29572943 offsetof(CPURXState, op_r[i]),
29582944 "");
29592945 }
2960- for (i = 0; i < 4; i++) {
2961- ccop.op_mode[i] = tcg_global_mem_new_i32(cpu_env,
2962- offsetof(CPURXState, op_mode[i]),
2963- "");
2964- }
2965-
2946+ ccop.op_mode = tcg_global_mem_new_i32(cpu_env,
2947+ offsetof(CPURXState, op_mode),
2948+ "");
29662949 ALLOC_REGISTER(pc, "PC");
29672950 ALLOC_REGISTER(psw, "PSW");
29682951 ALLOC_REGISTER(psw_o, "PSW(O)");