uclibc-ng

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RX: fix build error

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>

RX: header update.

argv fix

update __uClibc_main arguments

RX support

RISC-V 32-bit support

Added 32-bit RISC-V support. I have managed to get 32-bit RISC-V No-MMU
Linux running based on mainstream buildroot. It's nice to have uclibc
support this 32-bit No-MMU target.

There's no substantial code change except definations and config
options.

Signed-off-by: Yimin Gu <ustcymgu@gmail.com>

Static pie support for ppc

Modified config files and crt1.S to support static pie elf generation.

Signed-off-by: linted <linted@users.noreply.github.com>

arc: add optimized string functions for ARCv3

Add ability to use optimized versions of string functions for ARCv3 32-bit
CPUs with UCLIBC_HAS_STRING_ARCH_OPT option. Add optimized
memcpy/memset/memcmp code for ARCv3 CPUs based on the code from newlib
and adapt for ARCv3 existed optimized strchr/strcmp/strcpy/strlen.

Link to the Synopsys newlib repo with code for ARCv3 on GitHub:
https://github.com/foss-for-synopsys-dwc-arc-processors/newlib

Signed-off-by: Pavel Kozlov <pavel.kozlov@synopsys.com>

arc: add support for ARCv3 32-bit processors

New ARCv3 ISA includes both 64-bit and 32-bit CPU family.
This patch adds support for 32-bit ARCv3 HS5x processors.

Signed-off-by: Sergey Matyukevich <sergey.matyukevich@synopsys.com>
Signed-off-by: Pavel Kozlov <pavel.kozlov@synopsys.com>

arc: add asm macros

Add a header file with assembler macros to be able to handle in one
place the differences between ARCv2 and ARCv3 ISAs. It is a preparatory
step before the introduction of support for ARCv3 CPUs.

Signed-off-by: Sergey Matyukevich <sergey.matyukevich@synopsys.com>
Signed-off-by: Pavel Kozlov <pavel.kozlov@synopsys.com>

ldso: arc: add compiler option check

Option '-mno-long-calls' is not supported by all arc gcc compilers.
For instance, this option is not supported by GCC for ARCv3 processors.
Check if this option is supported before applying it.

Signed-off-by: Sergey Matyukevich <sergey.matyukevich@synopsys.com>
Signed-off-by: Pavel Kozlov <pavel.kozlov@synopsys.com>

arc: minor cleanup for ARCv2

Add missing ARCv2 check in MATCH_MACHINE macro.
Update comment for EM_ARCV2 define.

Signed-off-by: Sergey Matyukevich <sergey.matyukevich@synopsys.com>
Signed-off-by: Pavel Kozlov <pavel.kozlov@synopsys.com>

Added some documentation on how to add static-pie support to the porting guide

Signed-off-by: linted <linted@users.noreply.github.com>

xtensa: add static pie support

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

xtensa: drop ARCH_NEEDS_BOOTSTRAP_RELOCS

Xtensa does not define PERFORM_BOOTSTRAP_RELOC so it doesn't need
ARCH_NEEDS_BOOTSTRAP_RELOCS definition. Remove it.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

xtensa: ldso: make GOT protection adjustment conditional

Xtensa PERFORM_BOOTSTRAP_GOT macro uses mprotect to make bits of GOT
writable, but noMMU linux kernel returns ENOSYS to mprotect syscalls,
and syscall wrapper tries to update errno with the error code. This
happens well before the relocations are done and results in writes to
unrelated locations, memory corruption or protection violations.

Only define PERFORM_BOOTSTRAP_GOT when building xtensa configuration
with MMU support.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

ldso: clean up PERFORM_BOOTSTRAP_GOT ifdeferry

3 architectures currently define PERFORM_BOOTSTRAP_GOT: avr32, mips and
xtensa. A block of code that applies relative relocations in the
DL_START is disabled when PERFORM_BOOTSTRAP_GOT is defined, unless it's
avr32 or mips, effectively disabling it only for xtensa.
This may be simplified by removing the call to elf_machine_relative from
the xtensa PERFORM_BOOTSTRAP_GOT and always using common code.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

static pie: fix building static PDE

When uclibc is built with static PIE support the _dl_load_base variable
shared between the libc-tls.c and reloc_static_pie.c creates the
dependency that requires linking reloc_static_pie.o into static
position-dependent executables resulting in the following build errors:
gcc -static test.c -o test
...ld:
...usr/lib/libc.a(reloc_static_pie.os):(.text+0x0):
undefined reference to `_DYNAMIC'

Move _dl_load_base definition to libc-tls.c to resolve this dependency
and fix static PDE build.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

nptl: use mmap to allocate initial TLS data for static PIE on noMMU

Static PIE ELFs may be loaded on noMMU linux platforms with FDPIC
support, but they don't have adjustable brk, and thus cannot allocate
memory for the TLS. Use mmap instead of sbrk to allocate initial TLS
memory when building with static PIE support for noMMU.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

Added support for creation of Static Position-Independent Executables (PIE) on mips

Updated config to allow compilation of rcrt1.o for mips and modified it's crt1.S to perform relocates in __start.

The mips architecture performs relocations differently then most other architectures. reloc_static_pie was rewritten, taking code from dl-startup.c, in order to perfrom the additional relocations. Modifications were made to mips' dl-startup.h to allow for the use of contained macros without including _start definition.

Signed-off-by: linted <linted@users.noreply.github.com>

bump version for 1.0.42 release

fix ARCH_NATIVE_BIT for aarch64

Patch suggested by Thomas Petazzoni and tested by me.

Reported-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>

Added support for creation of Static Position-Independent Executables (PIE) on aarch64

Updated config to allow compilation of rcrt1.o for aarch64 and modified it's crt1.S to relocate dynamic section prior to __uClibc_main.

Disabled stack protector when compiling reloc_static_pie.c to avoid TLS access prior to it being setup.

Signed-off-by: linted <linted@users.noreply.github.com>

resource.h: add missing RUSAGE_THREAD

There is a real-world usage of RUSAGE_THREAD by the pistache project,
https://github.com/oktal/pistache.

Reported-By: Thomas Petazzoni <thomas.petazzoni@bootlin.com>

Added support for creation of Static Position-Independent Executables (PIE) on i386, x86_64, and arm.

This patch adds the generation of rcrt1.o which is used by gcc when compiling with the --static-pie flag.

rcrt1.o differs from crt1.o and Scrt1.o in that it the executable has a dynamic section but no relocations have been performed prior to _start being called.
crt1.o assumes there to be no dynamic relocations, and Scrt1.o has all relocations performed prior to execution by lsdo.

The new reloc_static_pie function handles parsing the dynamic section, and performing the relocations in a architecture agnostic method.
It also sets _dl_load_base which is used when initalizing TLS to ensure loading from the proper location.
This allows for easier porting of static-pie support to additional architectures as only modifications to crt1.S to find the load address are required.

Signed-off-by: linted <linted@users.noreply.github.com>

linuxthread/arm: Unlock ldrex/strex varsion of testandset for __ARM_ARCH >= 7

Thomas has repored failure building ARM 32-bit systems for ARMv8 cores

CC libpthread/linuxthreads/mutex.os
/tmp/ccn8SFKU.s: Assembler messages:
/tmp/ccn8SFKU.s:162: Error: swp{b} use is obsoleted for ARMv8 and later
/tmp/ccn8SFKU.s:186: Error: swp{b} use is obsoleted for ARMv8 and later
/tmp/ccn8SFKU.s:203: Error: swp{b} use is obsoleted for ARMv8 and later
/tmp/ccn8SFKU.s:224: Error: swp{b} use is obsoleted for ARMv8 and later
make[1]: *** [Makerules:369: libpthread/linuxthreads/mutex.os] Error 1

This is due to libpthread/linuxthreads/sysdeps/arm/pt-machine.h which
uses the swp instruction that is not allowed on ARMv8.

All __ARM_ARCH >= 7 support ldrex/strex instructions, so unlock
testandset() varaint for them.

Reported-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>

linuxthreads/arm: fix ldrex/strex loop when built with O0

O0 build result in the following codegen

00000000 <ldrex>:
0: b480 push {r7}
2: b085 sub sp, #20
4: af00 add r7, sp, #0
6: 6078 str r0, [r7, #4]
8: 687b ldr r3, [r7, #4]
a: e853 3f00 ldrex r3, [r3]
e: 60fb str r3, [r7, #12]
10: 68fb ldr r3, [r7, #12]
12: 4618 mov r0, r3
14: 3714 adds r7, #20
16: 46bd mov sp, r7
18: f85d 7b04 ldr.w r7, [sp], #4
1c: 4770 bx lr

0000001e <strex>:
1e: b480 push {r7}
20: b085 sub sp, #20
22: af00 add r7, sp, #0
24: 6078 str r0, [r7, #4]
26: 6039 str r1, [r7, #0]
28: 687b ldr r3, [r7, #4]
2a: 683a ldr r2, [r7, #0]
2c: e842 3300 strex r3, r3, [r2]
30: 60fb str r3, [r7, #12]
32: 68fb ldr r3, [r7, #12]
34: 4618 mov r0, r3
36: 3714 adds r7, #20
38: 46bd mov sp, r7
3a: f85d 7b04 ldr.w r7, [sp], #4
3e: 4770 bx lr

00000040 <testandset>:
40: b590 push {r4, r7, lr}
42: b083 sub sp, #12
44: af00 add r7, sp, #0
46: 6078 str r0, [r7, #4]
48: 6878 ldr r0, [r7, #4]
4a: f7ff fffe bl 0 <ldrex>
4e: 4603 mov r3, r0
50: 461c mov r4, r3
52: 6879 ldr r1, [r7, #4]
54: 2001 movs r0, #1
56: f7ff fffe bl 1e <strex>
5a: 4603 mov r3, r0
5c: 2b00 cmp r3, #0
5e: d1f3 bne.n 48 <testandset+0x8>
60: 4623 mov r3, r4
62: 4618 mov r0, r3
64: 370c adds r7, #12
66: 46bd mov sp, r7
68: bd90 pop {r4, r7, pc}

ARM ARM suggests that LoadExcl/StoreExcl loops are guaranteed to make
forward progress only if, for any LoadExcl/StoreExcl loop within a
single thread of execution, the software meets all of the following
conditions:

1 Between the Load-Exclusive and the Store-Exclusive, there are no
explicit memory accesses, preloads, direct or indirect System
register writes, address translation instructions, cache or TLB
maintenance instructions, exception generating instructions,
exception returns, or indirect branches.

...

Obviously condition is not met for O0 builds.

O2 build (which is highly likely the most common setting) able to do
the right thing resulting in

00000000 <ldrex>:
0: e850 0f00 ldrex r0, [r0]
4: 4770 bx lr
6: bf00 nop

00000008 <strex>:
8: e841 0000 strex r0, r0, [r1]
c: 4770 bx lr
e: bf00 nop

00000010 <testandset>:
10: 2101 movs r1, #1
12: 4603 mov r3, r0
14: e853 0f00 ldrex r0, [r3]
18: e843 1200 strex r2, r1, [r3]
1c: 2a00 cmp r2, #0
1e: d1f9 bne.n 14 <testandset+0x4>
20: 4770 bx lr
22: bf00 nop

Rather than depending on level of optimisation implement whole
ldrex/strex loop in inline assembly.

Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>

assert: Add static_assert macro

See the C11 standard 7.2 §3

The definition is copied from glibc.

Signed-off-by: Nicolas Cavallari <nicolas.cavallari@green-communications.fr>

xtensa: implement user context manipulation functions

Implement getcontext, makecontext, setcontext and swapcontext.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

inet: gethostid: only accept v4 addresses

getaddrinfo() returns addresses from, at least, ip(7) and ipv6(7),
but _addr() always uses sin_addr from struct sockaddr_in;
we're saved from wild unsoundness (or incompatibility)
by virtue of struct sockaddr_in6 having an always-0 u32 sin6_flowinfo
at the same offset, so we end up returning 0 anyway,
but in a round-about and definitely unintended way

Instead, limit the request to AF_INET, and fall through to the end
early, returning the default id=0

Signed-off-by: Ahelenia Ziemiańska <nabijaczleweli@nabijaczleweli.xyz>