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hardware/intel/intel-driver


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Revision9f4d9a929f1be68035e2db5dad6e978c2f82db32 (tree)
Time2015-06-24 07:38:53
AuthorZhao Yakui <yakui.zhao@inte...>
CommiterZhao, Yakui

Log Message

VPP: Configure SURFACE_STATE based on HW requirement to fix out-of-bound access issue

Otherwise some pixles will be regarded as out-of-bound and the
access will be dropped.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Xiang haihao <haihao.xiang@intel.com>
(cherry picked from commit d5cd551887c8f4e5408327aba993e9927dd7d297)

Change Summary

Incremental Difference

--- a/src/gen8_post_processing.c
+++ b/src/gen8_post_processing.c
@@ -529,25 +529,25 @@ gen8_pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_proc
529529 if (is_target) {
530530 gen8_pp_set_surface_state(ctx, pp_context,
531531 bo, 0,
532- width[0] / 4, height[0], pitch[0],
532+ ALIGN(width[0], 4) / 4, height[0], pitch[0],
533533 I965_SURFACEFORMAT_R8_UINT,
534534 base_index, 1);
535535
536536 if (fourcc_info->num_planes == 2) {
537537 gen8_pp_set_surface_state(ctx, pp_context,
538538 bo, offset[1],
539- width[1] / 2, height[1], pitch[1],
539+ ALIGN(width[1], 2) / 2, height[1], pitch[1],
540540 I965_SURFACEFORMAT_R8G8_SINT,
541541 base_index + 1, 1);
542542 } else if (fourcc_info->num_planes == 3) {
543543 gen8_pp_set_surface_state(ctx, pp_context,
544544 bo, offset[1],
545- width[1] / 4, height[1], pitch[1],
545+ ALIGN(width[1], 4) / 4, height[1], pitch[1],
546546 I965_SURFACEFORMAT_R8_SINT,
547547 base_index + 1, 1);
548548 gen8_pp_set_surface_state(ctx, pp_context,
549549 bo, offset[2],
550- width[2] / 4, height[2], pitch[2],
550+ ALIGN(width[2], 4) / 4, height[2], pitch[2],
551551 I965_SURFACEFORMAT_R8_SINT,
552552 base_index + 2, 1);
553553 }
--- a/src/i965_post_processing.c
+++ b/src/i965_post_processing.c
@@ -2051,26 +2051,26 @@ pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_processin
20512051 /* Y surface */
20522052 i965_pp_set_surface_state(ctx, pp_context,
20532053 bo, offset[Y],
2054- width[Y] *scale_factor_of_1st_plane_width_in_byte / 4, height[Y], pitch[Y], I965_SURFACEFORMAT_R8_UNORM,
2054+ ALIGN(width[Y] *scale_factor_of_1st_plane_width_in_byte, 4) / 4, height[Y], pitch[Y], I965_SURFACEFORMAT_R8_UNORM,
20552055 base_index, is_target);
20562056
20572057 if (!packed_yuv && !full_packed_format) {
20582058 if (interleaved_uv) {
20592059 i965_pp_set_surface_state(ctx, pp_context,
20602060 bo, offset[UV],
2061- width[UV] / 4, height[UV], pitch[UV], I965_SURFACEFORMAT_R8_UNORM,
2061+ ALIGN(width[UV], 4) / 4, height[UV], pitch[UV], I965_SURFACEFORMAT_R8_UNORM,
20622062 base_index + 1, is_target);
20632063 } else {
20642064 /* U surface */
20652065 i965_pp_set_surface_state(ctx, pp_context,
20662066 bo, offset[U],
2067- width[U] / 4, height[U], pitch[U], I965_SURFACEFORMAT_R8_UNORM,
2067+ ALIGN(width[U], 4) / 4, height[U], pitch[U], I965_SURFACEFORMAT_R8_UNORM,
20682068 base_index + 1, is_target);
20692069
20702070 /* V surface */
20712071 i965_pp_set_surface_state(ctx, pp_context,
20722072 bo, offset[V],
2073- width[V] / 4, height[V], pitch[V], I965_SURFACEFORMAT_R8_UNORM,
2073+ ALIGN(width[V], 4) / 4, height[V], pitch[V], I965_SURFACEFORMAT_R8_UNORM,
20742074 base_index + 2, is_target);
20752075 }
20762076 }
@@ -2153,25 +2153,25 @@ gen7_pp_set_media_rw_message_surface(VADriverContextP ctx, struct i965_post_proc
21532153 if (is_target) {
21542154 gen7_pp_set_surface_state(ctx, pp_context,
21552155 bo, 0,
2156- width[0] / 4, height[0], pitch[0],
2156+ ALIGN(width[0], 4) / 4, height[0], pitch[0],
21572157 I965_SURFACEFORMAT_R8_UINT,
21582158 base_index, 1);
21592159
21602160 if (fourcc_info->num_planes == 2) {
21612161 gen7_pp_set_surface_state(ctx, pp_context,
21622162 bo, offset[1],
2163- width[1] / 2, height[1], pitch[1],
2163+ ALIGN(width[1], 2) / 2, height[1], pitch[1],
21642164 I965_SURFACEFORMAT_R8G8_SINT,
21652165 base_index + 1, 1);
21662166 } else if (fourcc_info->num_planes == 3) {
21672167 gen7_pp_set_surface_state(ctx, pp_context,
21682168 bo, offset[1],
2169- width[1] / 4, height[1], pitch[1],
2169+ ALIGN(width[1], 4) / 4, height[1], pitch[1],
21702170 I965_SURFACEFORMAT_R8_SINT,
21712171 base_index + 1, 1);
21722172 gen7_pp_set_surface_state(ctx, pp_context,
21732173 bo, offset[2],
2174- width[2] / 4, height[2], pitch[2],
2174+ ALIGN(width[2], 4) / 4, height[2], pitch[2],
21752175 I965_SURFACEFORMAT_R8_SINT,
21762176 base_index + 2, 1);
21772177 }
@@ -2451,7 +2451,7 @@ pp_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_con
24512451 /* source UV surface index 2 */
24522452 i965_pp_set_surface_state(ctx, pp_context,
24532453 obj_surface->bo, in_wpitch * in_hpitch,
2454- in_w / 2, in_h / 2, in_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
2454+ ALIGN(in_w, 2) / 2, in_h / 2, in_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
24552455 2, 0);
24562456
24572457 /* destination surface */
@@ -2464,13 +2464,13 @@ pp_nv12_scaling_initialize(VADriverContextP ctx, struct i965_post_processing_con
24642464 /* destination Y surface index 7 */
24652465 i965_pp_set_surface_state(ctx, pp_context,
24662466 obj_surface->bo, 0,
2467- out_w / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_UNORM,
2467+ ALIGN(out_w, 4) / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_UNORM,
24682468 7, 1);
24692469
24702470 /* destination UV surface index 8 */
24712471 i965_pp_set_surface_state(ctx, pp_context,
24722472 obj_surface->bo, out_wpitch * out_hpitch,
2473- out_w / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
2473+ ALIGN(out_w, 4) / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
24742474 8, 1);
24752475
24762476 /* sampler state */
@@ -2739,13 +2739,13 @@ pp_nv12_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context
27392739 /* destination Y surface index 7 */
27402740 i965_pp_set_surface_state(ctx, pp_context,
27412741 obj_surface->bo, 0,
2742- out_w / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_UNORM,
2742+ ALIGN(out_w, 4) / 4, out_h, out_wpitch, I965_SURFACEFORMAT_R8_UNORM,
27432743 7, 1);
27442744
27452745 /* destination UV surface index 8 */
27462746 i965_pp_set_surface_state(ctx, pp_context,
27472747 obj_surface->bo, out_wpitch * out_hpitch,
2748- out_w / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
2748+ ALIGN(out_w, 4) / 4, out_h / 2, out_wpitch, I965_SURFACEFORMAT_R8G8_UNORM,
27492749 8, 1);
27502750
27512751 /* sampler 8x8 state */
@@ -3401,9 +3401,9 @@ pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_contex
34013401 orig_h = obj_surface->orig_height;
34023402
34033403 i965_pp_set_surface_state(ctx, pp_context, obj_surface->bo, 0,
3404- orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM, 7, 1);
3404+ ALIGN(orig_w, 4) / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM, 7, 1);
34053405 i965_pp_set_surface_state(ctx, pp_context, obj_surface->bo, w * h,
3406- orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM, 8, 1);
3406+ ALIGN(orig_w, 4) / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM, 8, 1);
34073407
34083408 /* Current output surfaces (index = { 10, 11 }) */
34093409 obj_surface = dndi_ctx->frame_store[DNDI_FRAME_OUT_CURRENT].obj_surface;
@@ -3413,9 +3413,9 @@ pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_contex
34133413 orig_h = obj_surface->orig_height;
34143414
34153415 i965_pp_set_surface_state(ctx, pp_context, obj_surface->bo, 0,
3416- orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM, 10, 1);
3416+ ALIGN(orig_w, 4) / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM, 10, 1);
34173417 i965_pp_set_surface_state(ctx, pp_context, obj_surface->bo, w * h,
3418- orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM, 11, 1);
3418+ ALIGN(orig_w, 4) / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM, 11, 1);
34193419
34203420 /* STMM output surface (index = 20) */
34213421 obj_surface = dndi_ctx->frame_store[DNDI_FRAME_OUT_STMM].obj_surface;
@@ -3596,7 +3596,7 @@ pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context
35963596 /* source UV surface index 2 */
35973597 i965_pp_set_surface_state(ctx, pp_context,
35983598 obj_surface->bo, w * h,
3599- orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3599+ ALIGN(orig_w, 4) / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
36003600 2, 0);
36013601
36023602 /* source YUV surface index 4 */
@@ -3623,13 +3623,13 @@ pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_context
36233623 /* destination Y surface index 7 */
36243624 i965_pp_set_surface_state(ctx, pp_context,
36253625 obj_surface->bo, 0,
3626- orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
3626+ ALIGN(orig_w, 4) / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
36273627 7, 1);
36283628
36293629 /* destination UV surface index 8 */
36303630 i965_pp_set_surface_state(ctx, pp_context,
36313631 obj_surface->bo, w * h,
3632- orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
3632+ ALIGN(orig_w, 4) / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
36333633 8, 1);
36343634 /* sampler dn */
36353635 dri_bo_map(pp_context->sampler_state_table.bo, True);
@@ -3807,9 +3807,9 @@ gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_c
38073807 orig_h = obj_surface->orig_height;
38083808
38093809 gen7_pp_set_surface_state(ctx, pp_context, obj_surface->bo, 0,
3810- orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM, 27, 1);
3810+ ALIGN(orig_w, 4) / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM, 27, 1);
38113811 gen7_pp_set_surface_state(ctx, pp_context, obj_surface->bo, w * h,
3812- orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM, 28, 1);
3812+ ALIGN(orig_w, 4) / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM, 28, 1);
38133813
38143814 /* Current output surfaces (index = { 30, 31 }) */
38153815 obj_surface = dndi_ctx->frame_store[DNDI_FRAME_OUT_CURRENT].obj_surface;
@@ -3819,9 +3819,9 @@ gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_c
38193819 orig_h = obj_surface->orig_height;
38203820
38213821 gen7_pp_set_surface_state(ctx, pp_context, obj_surface->bo, 0,
3822- orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM, 30, 1);
3822+ ALIGN(orig_w, 4) / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM, 30, 1);
38233823 gen7_pp_set_surface_state(ctx, pp_context, obj_surface->bo, w * h,
3824- orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM, 31, 1);
3824+ ALIGN(orig_w, 4) / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM, 31, 1);
38253825
38263826 /* STMM output surface (index = 33) */
38273827 obj_surface = dndi_ctx->frame_store[DNDI_FRAME_OUT_STMM].obj_surface;
@@ -4015,7 +4015,7 @@ gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_con
40154015 /* source UV surface index 1 */
40164016 gen7_pp_set_surface_state(ctx, pp_context,
40174017 obj_surface->bo, w * h,
4018- orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
4018+ ALIGN(orig_w, 4) / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
40194019 1, 0);
40204020
40214021 /* source YUV surface index 3 */
@@ -4050,13 +4050,13 @@ gen7_pp_nv12_dn_initialize(VADriverContextP ctx, struct i965_post_processing_con
40504050 /* destination Y surface index 24 */
40514051 gen7_pp_set_surface_state(ctx, pp_context,
40524052 obj_surface->bo, 0,
4053- orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
4053+ ALIGN(orig_w, 4) / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
40544054 24, 1);
40554055
40564056 /* destination UV surface index 25 */
40574057 gen7_pp_set_surface_state(ctx, pp_context,
40584058 obj_surface->bo, w * h,
4059- orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
4059+ ALIGN(orig_w, 4) / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
40604060 25, 1);
40614061
40624062 /* sampler dn */