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hardware/intel/intel-driver


Commit MetaInfo

Revisionfc6d9e94d867928aaf9bd40e76244a91cadee24f (tree)
Time2015-07-08 10:20:34
AuthorXiang, Haihao <haihao.xiang@inte...>
CommiterXiang, Haihao

Log Message

Merge branch 'v1.6-branch' into master

Change Summary

Incremental Difference

--- a/Makefile.am
+++ b/Makefile.am
@@ -21,3 +21,5 @@ deb.upstream: dist
2121 tar zxvf ../$(PACKAGE)-$(VERSION).tar.gz && \
2222 cd $(PACKAGE)-$(VERSION) && \
2323 $(MAKE) deb -f Makefile.am
24+
25+EXTRA_DIST = Android.mk
--- a/NEWS
+++ b/NEWS
@@ -1,5 +1,32 @@
1-libva-intel-driver NEWS -- summary of changes. 2014-12-28
2-Copyright (C) 2009-2014 Intel Corporation
1+libva-intel-driver NEWS -- summary of changes. 2015-07-01
2+Copyright (C) 2009-2015 Intel Corporation
3+
4+Version 1.6.0 - 01.Jul.2015
5+* Add support for VP8 encoding (CQP, CBR) on BSW/SKL
6+* Add support for HEVC decoding on BSW
7+* Add support for HEVC encoding (CQP) on SKL
8+* Add support for low-power mode (VA_PROC_PIPELINE_FAST) in VPP to discard
9+ any complex operation that would consume too many HW resources
10+* Fix memory leak issue for JPEG decoding
11+* Fix HEVC decoding issue on BSW/SKL
12+* Fix GPU hang issue caused by VP8 decoding on BDW/BSW
13+* Fix MADI/MCDI issues on SNB/IVB
14+* Improve the JPEG encoding quality
15+* Optimize MPEG-2 start code search on IVB
16+
17+Version 1.5.1 - DD.03.2015
18+* Fix forward reference requirement for Bob deinterlacing
19+* Fix a lot of potential rendering issues on GEN8+
20+* Fix scaling of NV12 surfaces when no output_region is set
21+* Fix the broken attribute setting of i965_GetConfigAttrib
22+* Fix the GetConfigAttributes() for JPEGBaseline profile
23+* Fix the wrong overlap setting for VC-1 decoding on GEN6+
24+* Fix VP8 decoding issue on GEN8+, HW needs 1 extra byte for each partition
25+* Fix JPEG encoding issue.
26+* Add support for aub dump
27+* Enhance STD on GEN8+
28+* Implement max width and height in QuerySurfaceAttributes
29+* Add new SKL PCI ids
330
431 Version 1.5.0 - 28.Dec.2014
532 * Add support for Skylake
--- a/configure.ac
+++ b/configure.ac
@@ -2,7 +2,7 @@
22 m4_define([intel_driver_major_version], [1])
33 m4_define([intel_driver_minor_version], [6])
44 m4_define([intel_driver_micro_version], [0])
5-m4_define([intel_driver_pre_version], [1])
5+m4_define([intel_driver_pre_version], [0])
66 m4_define([intel_driver_version],
77 [intel_driver_major_version.intel_driver_minor_version.intel_driver_micro_version])
88 m4_if(intel_driver_pre_version, [0], [], [
@@ -10,8 +10,8 @@ m4_append([intel_driver_version], intel_driver_pre_version, [.pre])
1010 ])
1111
1212 # libva minimum version requirement
13-m4_define([va_api_version], [0.37])
14-m4_define([libva_package_version], [1.5.0])
13+m4_define([va_api_version], [0.38])
14+m4_define([libva_package_version], [1.6.0])
1515
1616 # libdrm minimum version requirement
1717 m4_define([libdrm_version], [2.4.45])
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -190,7 +190,7 @@ $(PKG_VERSION_FILE): $(NEW_VERSION_FILE)
190190 @cp -f $< $@
191191
192192 BUILT_SOURCES += intel_version.h
193-EXTRA_DIST += intel_version.h.in $(PKG_VERSION_FILE)
193+EXTRA_DIST += Android.mk intel_version.h.in $(PKG_VERSION_FILE)
194194
195195 # Wayland protocol
196196 protocol_source_h = wayland-drm-client-protocol.h
--- a/src/shaders/render/Makefile.am
+++ b/src/shaders/render/Makefile.am
@@ -195,6 +195,7 @@ EXTRA_DIST = \
195195 $(INTEL_G7A) \
196196 $(INTEL_G7B) \
197197 $(INTEL_G7B_HASWELL) \
198+ $(INTEL_G7I) \
198199 $(INTEL_G8A) \
199200 $(INTEL_G8B) \
200201 $(INTEL_G9A) \
--- a/src/shaders/vme/Makefile.am
+++ b/src/shaders/vme/Makefile.am
@@ -1,8 +1,8 @@
11 VME_CORE = batchbuffer.asm intra_frame.asm inter_frame.asm
22 VME7_CORE = batchbuffer.asm intra_frame_ivb.asm inter_frame_ivb.asm inter_bframe_ivb.asm mpeg2_inter_ivb.asm
33 VME75_CORE = batchbuffer.asm intra_frame_haswell.asm inter_frame_haswell.asm inter_bframe_haswell.asm mpeg2_inter_haswell.asm
4-VME8_CORE = intra_frame_gen8.asm inter_frame_gen8.asm inter_bframe_gen8.asm mpeg2_inter_gen8.asm
5-VME9_CORE = $(VME8_CORE) vp8_intra_frame_gen9.asm vp8_inter_frame_gen9.asm
4+VME8_CORE = intra_frame_gen8.asm inter_frame_gen8.asm inter_bframe_gen8.asm mpeg2_inter_gen8.asm vp8_intra_frame_gen8.asm vp8_inter_frame_gen8.asm
5+VME9_CORE = $(VME8_CORE)
66
77 INTEL_G6B = batchbuffer.g6b intra_frame.g6b inter_frame.g6b
88 INTEL_G6A = batchbuffer.g6a intra_frame.g6a inter_frame.g6a
--- a/src/shaders/vme/vp8_inter_frame_gen9.asm
+++ /dev/null
@@ -1,739 +0,0 @@
1-/*
2- * Copyright © 2014 Intel Corporation
3- *
4- * Permission is hereby granted, free of charge, to any person obtaining a
5- * copy of this software and associated documentation files (the
6- * "Software"), to deal in the Software without restriction, including
7- * without limitation the rights to use, copy, modify, merge, publish,
8- * distribute, sub license, and/or sell copies of the Software, and to
9- * permit persons to whom the Software is furnished to do so, subject to
10- * the following conditions:
11- *
12- * The above copyright notice and this permission notice (including the
13- * next paragraph) shall be included in all copies or substantial portions
14- * of the Software.
15- *
16- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19- * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23- *
24- * Authors:
25- * Zhao Yakui <yakui.zhao@intel.com>
26- * Xiang Haihao <haihao.xiang@intel.com>
27- * Li Zhong <zhong.li@intel.com>
28- *
29- */
30-
31-#define SAVE_RET add (1) RETURN_REG<1>:ud ip:ud 32:ud
32-#define RETURN mov (1) ip:ud RETURN_REG<0,1,0>:ud
33-
34-/*
35- * __START
36- */
37-__INTER_START:
38-mov (16) tmp_reg0.0<1>:UD 0x0:UD {align1};
39-mov (16) tmp_reg2.0<1>:UD 0x0:UD {align1};
40-mov (16) tmp_reg4.0<1>:UD 0x0:UD {align1} ;
41-mov (16) tmp_reg6.0<1>:UD 0x0:UD {align1} ;
42-
43-shl (2) read0_header.0<1>:D orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */
44-add (1) read0_header.0<1>:D read0_header.0<0,1,0>:D -8:W {align1}; /* X offset */
45-add (1) read0_header.4<1>:D read0_header.4<0,1,0>:D -1:W {align1}; /* Y offset */
46-mov (1) read0_header.8<1>:UD BLOCK_32X1 {align1};
47-mov (1) read0_header.20<1>:UB thread_id_ub {align1}; /* dispatch id */
48-
49-shl (2) read1_header.0<1>:D orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */
50-add (1) read1_header.0<1>:D read1_header.0<0,1,0>:D -4:W {align1}; /* X offset */
51-mov (1) read1_header.8<1>:UD BLOCK_4X16 {align1};
52-mov (1) read1_header.20<1>:UB thread_id_ub {align1}; /* dispatch id */
53-
54-shl (2) vme_m0.8<1>:UW orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */
55-mov (1) vme_m0.20<1>:UB thread_id_ub {align1}; /* dispatch id */
56-
57-mul (1) obw_m0.8<1>:UD w_in_mb_uw<0,1,0>:UW orig_y_ub<0,1,0>:UB {align1};
58-add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD orig_x_ub<0,1,0>:UB {align1};
59-mul (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 24:UD {align1};
60-mov (1) obw_m0.20<1>:UB thread_id_ub {align1}; /* dispatch id */
61-
62-/*
63- * Media Read Message -- fetch Luma neighbor edge pixels
64- */
65-/* ROW */
66-mov (8) msg_reg0.0<1>:UD read0_header.0<8,8,1>:UD {align1};
67-send (8) msg_ind INEP_ROW<1>:UB null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 1 {align1};
68-
69-/* COL */
70-mov (8) msg_reg0.0<1>:UD read1_header.0<8,8,1>:UD {align1};
71-send (8) msg_ind INEP_COL0<1>:UB null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 2 {align1};
72-
73-/*
74- * Media Read Message -- fetch Chroma neighbor edge pixels
75- */
76-/* ROW */
77-shl (2) read0_header.0<1>:D orig_xy_ub<2,2,1>:UB 3:UW {align1}; /* x * 16 , y * 8 */
78-mul (1) read0_header.0<1>:D read0_header.0<0,1,0>:D 2:W {align1};
79-add (1) read0_header.0<1>:D read0_header.0<0,1,0>:D -8:W {align1}; /* X offset */
80-add (1) read0_header.4<1>:D read0_header.4<0,1,0>:D -1:W {align1}; /* Y offset */
81-mov (8) msg_reg0.0<1>:UD read0_header.0<8,8,1>:UD {align1};
82-send (8) msg_ind CHROMA_ROW<1>:UB null read(BIND_IDX_CBCR, 0, 0, 4) mlen 1 rlen 1 {align1};
83-
84-/* COL */
85-shl (2) read1_header.0<1>:D orig_xy_ub<2,2,1>:UB 3:UW {align1}; /* x * 16, y * 8 */
86-mul (1) read1_header.0<1>:D read1_header.0<0,1,0>:D 2:W {align1};
87-add (1) read1_header.0<1>:D read1_header.0<0,1,0>:D -4:W {align1}; /* X offset */
88-mov (1) read1_header.8<1>:UD BLOCK_8X4 {align1};
89-mov (8) msg_reg0.0<1>:UD read1_header.0<8,8,1>:UD {align1};
90-send (8) msg_ind CHROMA_COL<1>:UB null read(BIND_IDX_CBCR, 0, 0, 4) mlen 1 rlen 1 {align1};
91-
92-mov (8) mb_mvp_ref.0<1>:ud 0:ud {align1};
93-mov (8) mb_ref_win.0<1>:ud 0:ud {align1};
94-and.z.f0.0 (1) null:uw mb_hwdep<0,1,0>:uw 0x04:uw {align1};
95-(f0.0) jmpi (1) __mb_hwdep_end;
96-/* read back the data for MB A */
97-/* the layout of MB result is: rx.0(Available). rx.4(MVa), rX.8(MVb), rX.16(Pred_L0 flag),
98-* rX.18 (Pred_L1 flag), rX.20(Forward reference ID), rX.22(Backwared reference ID)
99-*/
100-mov (8) mba_result.0<1>:ud 0x0:ud {align1};
101-mov (8) mbb_result.0<1>:ud 0x0:ud {align1};
102-mov (8) mbc_result.0<1>:ud 0x0:ud {align1};
103-mba_start:
104-mov (8) mb_msg0.0<1>:ud 0:ud {align1};
105-and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_AE:uw {align1};
106-/* MB A doesn't exist. Zero MV. mba_flag is zero and ref ID = -1 */
107-(f0.0) mov (2) mba_result.20<1>:w -1:w {align1};
108-(f0.0) jmpi (1) mbb_start;
109-mov (1) mba_result.0<1>:d MB_AVAIL {align1};
110-mov (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB {align1};
111-add (1) tmp_reg0.0<1>:w tmp_reg0.0<0,1,0>:w -1:w {align1};
112-mul (1) mb_msg0.8<1>:UD w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1};
113-add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD tmp_reg0.0<0,1,0>:uw {align1};
114-mul (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD 24:UD {align1};
115-mov (1) mb_msg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */
116-
117-/* bind index 3, read 4 oword (64bytes), msg type: 0(OWord Block Read) */
118-send (16)
119- mb_ind
120- mb_wb.0<1>:ud
121- NULL
122- data_port(
123- OBR_CACHE_TYPE,
124- OBR_MESSAGE_TYPE,
125- OBR_CONTROL_4,
126- OBR_BIND_IDX,
127- OBR_WRITE_COMMIT_CATEGORY,
128- OBR_HEADER_PRESENT
129- )
130- mlen 1
131- rlen 2
132- {align1};
133-
134-/* TODO: RefID is required after multi-references are added */
135-cmp.l.f0.0 (1) null:w mb_intra_wb.16<0,1,0>:uw mb_inter_wb.8<0,1,0>:uw {align1};
136-(f0.0) mov (2) mba_result.20<1>:w -1:w {align1};
137-(f0.0) jmpi (1) mbb_start;
138-
139-add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:ud 3:ud {align1};
140-/* Read MV for MB A */
141-/* bind index 3, read 8 oword (128bytes), msg type: 0(OWord Block Read) */
142-send (16)
143- mb_ind
144- mb_mv0.0<1>:ud
145- NULL
146- data_port(
147- OBR_CACHE_TYPE,
148- OBR_MESSAGE_TYPE,
149- OBR_CONTROL_8,
150- OBR_BIND_IDX,
151- OBR_WRITE_COMMIT_CATEGORY,
152- OBR_HEADER_PRESENT
153- )
154- mlen 1
155- rlen 4
156- {align1};
157-/* TODO: RefID is required after multi-references are added */
158-/* MV */
159-mov (2) mba_result.4<1>:ud mb_mv1.8<2,2,1>:ud {align1};
160-mov (1) mba_result.16<1>:w MB_PRED_FLAG {align1};
161-
162-mbb_start:
163-mov (8) mb_msg0.0<1>:ud 0:ud {align1};
164-and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_B:uw {align1};
165-/* MB B doesn't exist. Zero MV. mba_flag is zero */
166-/* If MB B doesn't exist, neither MB C nor D exists */
167-(f0.0) mov (2) mbb_result.20<1>:w -1:w {align1};
168-(f0.0) mov (2) mbc_result.20<1>:w -1:w {align1};
169-(f0.0) jmpi (1) mb_mvp_start;
170-mov (1) mbb_result.0<1>:d MB_AVAIL {align1};
171-mov (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB {align1};
172-add (1) tmp_reg0.2<1>:w tmp_reg0.2<0,1,0>:w -1:w {align1};
173-mul (1) mb_msg0.8<1>:UD w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1};
174-add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD tmp_reg0.0<0,1,0>:uw {align1};
175-mul (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD 24:UD {align1};
176-mov (1) mb_msg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */
177-
178-/* bind index 3, read 4 oword (64bytes), msg type: 0(OWord Block Read) */
179-send (16)
180- mb_ind
181- mb_wb.0<1>:ud
182- NULL
183- data_port(
184- OBR_CACHE_TYPE,
185- OBR_MESSAGE_TYPE,
186- OBR_CONTROL_4,
187- OBR_BIND_IDX,
188- OBR_WRITE_COMMIT_CATEGORY,
189- OBR_HEADER_PRESENT
190- )
191- mlen 1
192- rlen 2
193- {align1};
194-
195-/* TODO: RefID is required after multi-references are added */
196-cmp.l.f0.0 (1) null:w mb_intra_wb.16<0,1,0>:uw mb_inter_wb.8<0,1,0>:uw {align1};
197-(f0.0) mov (2) mbb_result.20<1>:w -1:w {align1};
198-(f0.0) jmpi (1) mbc_start;
199-add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:ud 3:ud {align1};
200-/* Read MV for MB B */
201-/* bind index 3, read 8 oword (128bytes), msg type: 0(OWord Block Read) */
202-send (16)
203- mb_ind
204- mb_mv0.0<1>:ud
205- NULL
206- data_port(
207- OBR_CACHE_TYPE,
208- OBR_MESSAGE_TYPE,
209- OBR_CONTROL_8,
210- OBR_BIND_IDX,
211- OBR_WRITE_COMMIT_CATEGORY,
212- OBR_HEADER_PRESENT
213- )
214- mlen 1
215- rlen 4
216- {align1};
217-/* TODO: RefID is required after multi-references are added */
218-mov (2) mbb_result.4<1>:ud mb_mv2.16<2,2,1>:ud {align1};
219-mov (1) mbb_result.16<1>:w MB_PRED_FLAG {align1};
220-
221-mbc_start:
222-mov (8) mb_msg0.0<1>:ud 0:ud {align1};
223-and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_C:uw {align1};
224-/* MB C doesn't exist. Zero MV. mba_flag is zero */
225-/* Based on h264 spec the MB D will be replaced if MB C doesn't exist */
226-(f0.0) jmpi (1) mbd_start;
227-mov (1) mbc_result.0<1>:d MB_AVAIL {align1};
228-mov (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB {align1};
229-add (1) tmp_reg0.2<1>:w tmp_reg0.2<0,1,0>:w -1:w {align1};
230-add (1) tmp_reg0.0<1>:w tmp_reg0.0<0,1,0>:w 1:w {align1};
231-mul (1) mb_msg0.8<1>:UD w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1};
232-add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD tmp_reg0.0<0,1,0>:uw {align1};
233-mul (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD 24:UD {align1};
234-mov (1) mb_msg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */
235-
236-/* bind index 3, read 4 oword (64bytes), msg type: 0(OWord Block Read) */
237-send (16)
238- mb_ind
239- mb_wb.0<1>:ud
240- NULL
241- data_port(
242- OBR_CACHE_TYPE,
243- OBR_MESSAGE_TYPE,
244- OBR_CONTROL_4,
245- OBR_BIND_IDX,
246- OBR_WRITE_COMMIT_CATEGORY,
247- OBR_HEADER_PRESENT
248- )
249- mlen 1
250- rlen 2
251- {align1};
252-
253-/* TODO: RefID is required after multi-references are added */
254-cmp.l.f0.0 (1) null:w mb_intra_wb.16<0,1,0>:uw mb_inter_wb.8<0,1,0>:uw {align1};
255-(f0.0) mov (2) mbc_result.20<1>:w -1:w {align1};
256-(f0.0) jmpi (1) mb_mvp_start;
257-add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:ud 3:ud {align1};
258-/* Read MV for MB C */
259-/* bind index 3, read 8 oword (128bytes), msg type: 0(OWord Block Read) */
260-send (16)
261- mb_ind
262- mb_mv0.0<1>:ud
263- NULL
264- data_port(
265- OBR_CACHE_TYPE,
266- OBR_MESSAGE_TYPE,
267- OBR_CONTROL_8,
268- OBR_BIND_IDX,
269- OBR_WRITE_COMMIT_CATEGORY,
270- OBR_HEADER_PRESENT
271- )
272- mlen 1
273- rlen 4
274- {align1};
275-/* TODO: RefID is required after multi-references are added */
276-/* Forward MV */
277-mov (2) mbc_result.4<1>:ud mb_mv2.16<2,2,1>:ud {align1};
278-mov (1) mbc_result.16<1>:w MB_PRED_FLAG {align1};
279-
280-jmpi (1) mb_mvp_start;
281-mbd_start:
282-mov (8) mb_msg0.0<1>:ud 0:ud {align1};
283-and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_D:uw {align1};
284-(f0.0) mov (2) mbc_result.20<1>:w -1:w {align1};
285-(f0.0) jmpi (1) mb_mvp_start;
286-mov (1) mbc_result.0<1>:d MB_AVAIL {align1};
287-mov (2) tmp_reg0.0<1>:UW orig_xy_ub<2,2,1>:UB {align1};
288-add (2) tmp_reg0.0<1>:w tmp_reg0.0<2,2,1>:w -1:w {align1};
289-mul (1) mb_msg0.8<1>:UD w_in_mb_uw<0,1,0>:UW tmp_reg0.2<0,1,0>:UW {align1};
290-add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD tmp_reg0.0<0,1,0>:uw {align1};
291-mul (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:UD 24:UD {align1};
292-mov (1) mb_msg0.20<1>:UB thread_id_ub {align1}; /* dispatch id */
293-
294-/* bind index 3, read 4 oword (64bytes), msg type: 0(OWord Block Read) */
295-send (16)
296- mb_ind
297- mb_wb.0<1>:ud
298- NULL
299- data_port(
300- OBR_CACHE_TYPE,
301- OBR_MESSAGE_TYPE,
302- OBR_CONTROL_4,
303- OBR_BIND_IDX,
304- OBR_WRITE_COMMIT_CATEGORY,
305- OBR_HEADER_PRESENT
306- )
307- mlen 1
308- rlen 2
309- {align1};
310-
311-cmp.l.f0.0 (1) null:w mb_intra_wb.16<0,1,0>:uw mb_inter_wb.8<0,1,0>:uw {align1};
312-(f0.0) mov (2) mbc_result.20<1>:w -1:w {align1};
313-(f0.0) jmpi (1) mb_mvp_start;
314-
315-add (1) mb_msg0.8<1>:UD mb_msg0.8<0,1,0>:ud 3:ud {align1};
316-/* Read MV for MB D */
317-/* bind index 3, read 8 oword (128bytes), msg type: 0(OWord Block Read) */
318-send (16)
319- mb_ind
320- mb_mv0.0<1>:ub
321- NULL
322- data_port(
323- OBR_CACHE_TYPE,
324- OBR_MESSAGE_TYPE,
325- OBR_CONTROL_8,
326- OBR_BIND_IDX,
327- OBR_WRITE_COMMIT_CATEGORY,
328- OBR_HEADER_PRESENT
329- )
330- mlen 1
331- rlen 4
332- {align1};
333-
334-/* TODO: RefID is required after multi-references are added */
335-
336-/* Forward MV */
337-mov (2) mbc_result.4<1>:ud mb_mv3.24<2,2,1>:ud {align1};
338-mov (1) mbc_result.16<1>:w MB_PRED_FLAG {align1};
339-
340-mb_mvp_start:
341-/*TODO: Add the skip prediction */
342-/* Check whether both MB B and C are inavailable */
343-add (1) tmp_reg0.0<1>:d mbb_result.0<0,1,0>:d mbc_result.0<0,1,0>:d {align1};
344-cmp.z.f0.0 (1) null:d tmp_reg0.0<0,1,0>:d 0:d {align1};
345-(-f0.0) jmpi (1) mb_median_start;
346-cmp.nz.f0.0 (1) null:d mba_result.0<0,1,0>:d 0:d {align1};
347-(f0.0) mov (1) mbb_result.4<1>:ud mba_result.4<0,1,0>:ud {align1};
348-(f0.0) mov (1) mbc_result.4<1>:ud mba_result.4<0,1,0>:ud {align1};
349-(f0.0) mov (1) mbb_result.20<1>:uw mba_result.20<0,1,0>:uw {align1};
350-(f0.0) mov (1) mbc_result.20<1>:uw mba_result.20<0,1,0>:uw {align1};
351-(f0.0) mov (1) mb_mvp_ref.0<1>:ud mba_result.4<0,1,0>:ud {align1};
352-(-f0.0) mov (1) mb_mvp_ref.0<1>:ud 0:ud {align1};
353-jmpi (1) __mb_hwdep_end;
354-
355-mb_median_start:
356-/* check whether only one neighbour MB has the same ref ID with the current MB */
357-mov (8) tmp_reg0.0<1>:ud 0:ud {align1};
358-cmp.z.f0.0 (1) null:d mba_result.20<0,1,0>:w 0:w {align1};
359-(f0.0) add (1) tmp_reg0.0<1>:w tmp_reg0.0<0,1,0>:w 1:w {align1};
360-(f0.0) mov (1) tmp_reg0.4<1>:ud mba_result.4<0,1,0>:ud {align1};
361-cmp.z.f0.0 (1) null:d mbb_result.20<0,1,0>:w 0:w {align1};
362-(f0.0) add (1) tmp_reg0.0<1>:w tmp_reg0.0<0,1,0>:w 1:w {align1};
363-(f0.0) mov (1) tmp_reg0.4<1>:ud mbb_result.4<0,1,0>:ud {align1};
364-cmp.z.f0.0 (1) null:d mbc_result.20<0,1,0>:w 0:w {align1};
365-(f0.0) add (1) tmp_reg0.0<1>:w tmp_reg0.0<0,1,0>:w 1:w {align1};
366-(f0.0) mov (1) tmp_reg0.4<1>:ud mbc_result.4<0,1,0>:ud {align1};
367-cmp.e.f0.0 (1) null:d tmp_reg0.0<0,1,0>:w 1:w {align1};
368-(f0.0) mov (1) mb_mvp_ref.0<1>:ud tmp_reg0.4<0,1,0>:ud {align1};
369-(f0.0) jmpi (1) __mb_hwdep_end;
370-
371-mov (1) INPUT_ARG0.0<1>:w mba_result.4<0,1,0>:w {align1};
372-mov (1) INPUT_ARG0.4<1>:w mbb_result.4<0,1,0>:w {align1};
373-mov (1) INPUT_ARG0.8<1>:w mbc_result.4<0,1,0>:w {align1};
374-SAVE_RET {align1};
375- jmpi (1) word_imedian;
376-mov (1) mb_mvp_ref.0<1>:w RET_ARG<0,1,0>:w {align1};
377-mov (1) INPUT_ARG0.0<1>:w mba_result.6<0,1,0>:w {align1};
378-mov (1) INPUT_ARG0.4<1>:w mbb_result.6<0,1,0>:w {align1};
379-mov (1) INPUT_ARG0.8<1>:w mbc_result.6<0,1,0>:w {align1};
380-SAVE_RET {align1};
381-jmpi (1) word_imedian;
382-mov (1) mb_mvp_ref.2<1>:w RET_ARG<0,1,0>:w {align1};
383-
384-__mb_hwdep_end:
385-asr (2) mb_ref_win.0<1>:w mb_mvp_ref.0<2,2,1>:w 2:w {align1};
386-add (2) mb_ref_win.8<1>:w mb_ref_win.0<2,2,1>:w 3:w {align1};
387-and (2) mb_ref_win.16<1>:uw mb_ref_win.8<2,2,1>:uw 0xFFFC:uw {align1};
388-/* m2, get the MV/Mb cost passed from constant buffer when
389-spawning thread by MEDIA_OBJECT */
390-mov (8) vme_m2<1>:UD r1.0<8,8,1>:UD {align1};
391-
392-mov (8) vme_msg_2<1>:UD vme_m2.0<8,8,1>:UD {align1};
393-
394-/* m3 FWD/BWD cost center*/
395-mov (8) vme_msg_3<1>:UD 0x0:UD {align1};
396-
397-/* m4 skip center*/
398-mov (8) vme_msg_4<1>:UD 0x0:UD {align1};
399-
400-/* m5 */
401-mov (1) INEP_ROW.0<1>:UD 0x0:UD {align1};
402-and (1) INEP_ROW.4<1>:UD INEP_ROW.4<0,1,0>:UD 0xFF000000:UD {align1};
403-mov (8) vme_msg_5<1>:UD INEP_ROW.0<8,8,1>:UD {align1};
404-
405-
406-/* Use the Luma mode */
407-mov (1) tmp_reg0.0<1>:UW LUMA_INTRA_MODE:UW {align1};
408-mov (1) vme_msg_5.5<1>:UB tmp_reg0.0<0,1,0>:UB {align1};
409-
410-/* m6 */
411-mov (8) vme_msg_6<1>:UD 0x0:UD {align1};
412-mov (16) vme_msg_6.0<1>:UB INEP_COL0.3<32,8,4>:UB {align1};
413-mov (1) vme_msg_6.16<1>:UD INTRA_PREDICTORE_MODE {align1};
414-
415-/* the penalty for Intra mode */
416-mov (1) vme_msg_6.28<1>:UD 0x010101:UD {align1};
417-mov (1) vme_msg_6.20<1>:UW CHROMA_ROW.6<0,1,0>:UW {align1};
418-
419-
420-/* m7 */
421-
422-mov (4) vme_msg_7.16<1>:UD CHROMA_ROW.8<4,4,1>:UD {align1};
423-mov (8) vme_msg_7.0<1>:UW CHROMA_COL.2<16,8,2>:UW {align1};
424-
425-/*
426- * SIC VME message
427- */
428-
429-/* m1 */
430-mov (1) intra_flag<1>:UW 0x0:UW {align1};
431-mov (1) intra_part_mask_ub<1>:UB LUMA_INTRA_8x8_DISABLE {align1}; /* vp8 don't support intra_8x8 mode*/
432-
433-/* assign MB intra struct from the thread payload*/
434-mov (1) mb_intra_struct_ub<1>:UB input_mb_intra_ub<0,1,0>:UB {align1};
435-
436-/* Disable DC HAAR component when calculating HARR SATD block */
437-mov (1) tmp_reg0.0<1>:UW DC_HARR_DISABLE:UW {align1};
438-mov (1) vme_m1.30<1>:UB tmp_reg0.0<0,1,0>:UB {align1};
439-mov (8) vme_msg_1<1>:UD vme_m1.0<8,8,1>:UD {align1};
440-
441-/* m0 */
442-mov (1) vme_m0.12<1>:UD INTRA_SAD_HAAR:UD {align1}; /* 16x16 Source, Intra_harr */
443-mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1};
444-
445-/* after verification it will be passed by using payload */
446-send (8)
447- vme_msg_ind
448- vme_wb<1>:UD
449- null
450- cre(
451- BIND_IDX_VME,
452- VME_SIC_MESSAGE_TYPE
453- )
454- mlen sic_vme_msg_length
455- rlen vme_wb_length
456- {align1};
457-/*
458- * Oword Block Write message
459- */
460-mov (8) msg_reg0.0<1>:UD obw_m0<8,8,1>:UD {align1};
461-
462-mov (1) msg_reg1.0<1>:UD vme_wb.0<0,1,0>:UD {align1};
463-mov (1) msg_reg1.4<1>:UD vme_wb.16<0,1,0>:UD {align1};
464-mov (1) msg_reg1.8<1>:UD vme_wb.20<0,1,0>:UD {align1};
465-mov (1) msg_reg1.12<1>:UD vme_wb.24<0,1,0>:UD {align1};
466-
467-/* Distortion, Intra (17-16), */
468-mov (1) msg_reg1.16<1>:UW vme_wb.12<0,1,0>:UW {align1};
469-
470-mov (1) msg_reg1.20<1>:UD vme_wb.8<0,1,0>:UD {align1};
471-/* VME clock counts */
472-mov (1) msg_reg1.24<1>:UD vme_wb.28<0,1,0>:UD {align1};
473-
474-mov (1) msg_reg1.28<1>:UD obw_m0.8<0,1,0>:UD {align1};
475-
476-/* bind index 3, write 2 oword (32bytes), msg type: 8(OWord Block Write) */
477-send (16)
478- msg_ind
479- obw_wb
480- null
481- data_port(
482- OBW_CACHE_TYPE,
483- OBW_MESSAGE_TYPE,
484- OBW_CONTROL_2,
485- OBW_BIND_IDX,
486- OBW_WRITE_COMMIT_CATEGORY,
487- OBW_HEADER_PRESENT
488- )
489- mlen 2
490- rlen obw_wb_length
491- {align1};
492-
493-/* IME search */
494-mov (1) vme_m0.12<1>:UD SEARCH_CTRL_SINGLE + VP8_INTER_PART_MASK + INTER_SAD_HAAR:UD {align1}; /* 16x16 Source, harr */
495-mov (1) vme_m0.22<1>:UW REF_REGION_SIZE {align1}; /* Reference Width&Height, 48x40 */
496-
497-mov (1) vme_m0.0<1>:UD vme_m0.8<0,1,0>:UD {align1};
498-
499-add (1) vme_m0.0<1>:W vme_m0.0<0,1,0>:W -16:W {align1}; /* Reference = (x-16,y-12)-(x+32,y+28) */
500-add (1) vme_m0.2<1>:W vme_m0.2<0,1,0>:W -12:W {align1};
501-
502-mov (1) vme_m0.0<1>:W -16:W {align1};
503-mov (1) vme_m0.2<1>:W -12:W {align1};
504-
505-mov (1) vme_m0.4<1>:UD vme_m0.0<0,1,0>:UD {align1};
506-
507-and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_AE:uw {align1};
508-(f0.0) add (1) vme_m0.0<1>:w vme_m0.0<0,1,0>:w 12:w {align1};
509-and.z.f0.0 (1) null:uw input_mb_intra_ub<0,1,0>:ub INTRA_PRED_AVAIL_FLAG_B:uw {align1};
510-(f0.0) add (1) vme_m0.2<1>:w vme_m0.2<0,1,0>:w 8:w {align1};
511-
512-add (2) vme_m0.0<1>:w vme_m0.0<2,2,1>:w mb_ref_win.16<2,2,1>:w {align1};
513-add (2) vme_m0.4<1>:w vme_m0.4<2,2,1>:w mb_ref_win.16<2,2,1>:w {align1};
514-mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1};
515-
516-mov (1) vme_m1.0<1>:UD ADAPTIVE_SEARCH_ENABLE:ud {align1} ;
517-/* the Max MV number is passed by constant buffer */
518-mov (1) vme_m1.4<1>:UB r4.28<0,1,0>:UB {align1};
519-mov (1) vme_m1.8<1>:UD START_CENTER + SEARCH_PATH_LEN:UD {align1};
520-mov (8) vme_msg_1.0<1>:UD vme_m1.0<8,8,1>:UD {align1};
521-
522-/* Setup the Cost center */
523-/* currently four 8x8 share the same cost center */
524-mov (4) vme_m3.0<2>:ud mb_mvp_ref.0<0,1,0>:ud {align1};
525-mov (4) vme_m3.4<2>:ud mb_mvp_ref.0<0,1,0>:ud {align1};
526-
527-mov (8) vme_msg_3<1>:UD vme_m3.0<8,8,1>:UD {align1};
528-mov (8) vme_msg_2<1>:UD vme_m2.0<8,8,1>:UD {align1};
529-
530-/* M4/M5 search path */
531-mov (1) vme_msg_4.0<1>:UD 0x01010101:UD {align1};
532-mov (1) vme_msg_4.4<1>:UD 0x10010101:UD {align1};
533-mov (1) vme_msg_4.8<1>:UD 0x0F0F0F0F:UD {align1};
534-mov (1) vme_msg_4.12<1>:UD 0x100F0F0F:UD {align1};
535-mov (1) vme_msg_4.16<1>:UD 0x01010101:UD {align1};
536-mov (1) vme_msg_4.20<1>:UD 0x10010101:UD {align1};
537-mov (1) vme_msg_4.24<1>:UD 0x0F0F0F0F:UD {align1};
538-mov (1) vme_msg_4.28<1>:UD 0x100F0F0F:UD {align1};
539-
540-mov (1) vme_msg_5.0<1>:UD 0x01010101:UD {align1};
541-mov (1) vme_msg_5.4<1>:UD 0x10010101:UD {align1};
542-mov (1) vme_msg_5.8<1>:UD 0x0F0F0F0F:UD {align1};
543-mov (1) vme_msg_5.12<1>:UD 0x000F0F0F:UD {align1};
544-
545-mov (4) vme_msg_5.16<1>:UD 0x0:UD {align1};
546-
547-send (8)
548- vme_msg_ind
549- vme_wb<1>:UD
550- null
551- vme(
552- BIND_IDX_VME,
553- 0,
554- 0,
555- VME_IME_MESSAGE_TYPE
556- )
557- mlen ime_vme_msg_length
558- rlen vme_wb_length {align1};
559-
560-/* Set Macroblock-shape/mode for FBR */
561-
562-mov (1) vme_m2.20<1>:UD 0x0:UD {align1};
563-mov (1) vme_m2.21<1>:UB vme_wb.25<0,1,0>:UB {align1};
564-mov (1) vme_m2.22<1>:UB vme_wb.26<0,1,0>:UB {align1};
565-
566-and (1) tmp_reg0.0<1>:UW vme_wb.0<0,1,0>:UW 0x03:UW {align1};
567-mov (1) vme_m2.20<1>:UB tmp_reg0.0<0,1,0>:UB {align1};
568-
569-/* Send FBR message into CRE */
570-
571-mov (8) vme_msg_4.0<1>:UD vme_wb1.0<8,8,1>:UD {align1};
572-mov (8) vme_msg_5.0<1>:ud vme_wb2.0<8,8,1>:ud {align1};
573-mov (8) vme_msg_6.0<1>:ud vme_wb3.0<8,8,1>:ud {align1};
574-mov (8) vme_msg_7.0<1>:ud vme_wb4.0<8,8,1>:ud {align1};
575-
576-mov (1) vme_m0.12<1>:UD INTER_SAD_HAAR + SUB_PEL_MODE_QUARTER + FBR_BME_DISABLE:UD {align1}; /* 16x16 Source, 1/4 pixel, harr, BME disable */
577-mov (8) vme_msg_0.0<1>:UD vme_m0.0<8,8,1>:UD {align1};
578-mov (8) vme_msg_1.0<1>:UD vme_m1.0<8,8,1>:UD {align1};
579-
580-mov (8) vme_msg_2.0<1>:UD vme_m2.0<8,8,1>:UD {align1};
581-mov (8) vme_msg_3.0<1>:UD vme_m3.0<8,8,1>:UD {align1};
582-
583-/* after verification it will be passed by using payload */
584-send (8)
585- vme_msg_ind
586- vme_wb<1>:UD
587- null
588- cre(
589- BIND_IDX_VME,
590- VME_FBR_MESSAGE_TYPE
591- )
592- mlen fbr_vme_msg_length
593- rlen vme_wb_length
594- {align1};
595-
596-add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 0x02:UD {align1};
597-mov (8) msg_reg0.0<1>:UD obw_m0<8,8,1>:UD {align1};
598-/* write FME info */
599-mov (1) msg_reg1.0<1>:UD vme_wb.0<0,1,0>:UD {align1};
600-
601-mov (1) msg_reg1.4<1>:UD vme_wb.24<0,1,0>:UD {align1};
602-/* Inter distortion of FME */
603-mov (1) msg_reg1.8<1>:UD vme_wb.8<0,1,0>:UD {align1};
604-
605-mov (1) msg_reg1.12<1>:UD vme_m2.20<0,1,0>:UD {align1};
606-
607-/* bind index 3, write oword (16bytes), msg type: 8(OWord Block Write) */
608-send (16)
609- msg_ind
610- obw_wb
611- null
612- data_port(
613- OBW_CACHE_TYPE,
614- OBW_MESSAGE_TYPE,
615- OBW_CONTROL_0,
616- OBW_BIND_IDX,
617- OBW_WRITE_COMMIT_CATEGORY,
618- OBW_HEADER_PRESENT
619- )
620- mlen 2
621- rlen obw_wb_length
622- {align1};
623-
624-/* Write FME/BME MV */
625-add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 0x01:UD {align1};
626-mov (8) msg_reg0.0<1>:UD obw_m0.0<8,8,1>:UD {align1};
627-
628-
629-mov (8) msg_reg1.0<1>:UD vme_wb1.0<8,8,1>:UD {align1};
630-mov (8) msg_reg2.0<1>:ud vme_wb2.0<8,8,1>:ud {align1};
631-mov (8) msg_reg3.0<1>:ud vme_wb3.0<8,8,1>:ud {align1};
632-mov (8) msg_reg4.0<1>:ud vme_wb4.0<8,8,1>:ud {align1};
633-/* bind index 3, write 8 oword (128 bytes), msg type: 8(OWord Block Write) */
634-send (16)
635- msg_ind
636- obw_wb
637- null
638- data_port(
639- OBW_CACHE_TYPE,
640- OBW_MESSAGE_TYPE,
641- OBW_CONTROL_8,
642- OBW_BIND_IDX,
643- OBW_WRITE_COMMIT_CATEGORY,
644- OBW_HEADER_PRESENT
645- )
646- mlen 5
647- rlen obw_wb_length
648- {align1};
649-
650-/* Write FME/BME RefID */
651-add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 0x08:UD {align1};
652-mov (8) msg_reg0.0<1>:UD obw_m0<8,8,1>:UD {align1};
653-
654-mov (8) msg_reg1.0<1>:UD vme_wb6.0<8,8,1>:UD {align1};
655-
656-/* bind index 3, write 2 oword (32bytes), msg type: 8(OWord Block Write) */
657-send (16)
658- msg_ind
659- obw_wb
660- null
661- data_port(
662- OBW_CACHE_TYPE,
663- OBW_MESSAGE_TYPE,
664- OBW_CONTROL_2,
665- OBW_BIND_IDX,
666- OBW_WRITE_COMMIT_CATEGORY,
667- OBW_HEADER_PRESENT
668- )
669- mlen 2
670- rlen obw_wb_length
671- {align1};
672-
673-/* Issue message fence so that the previous write message is committed */
674-send (16)
675- mb_ind
676- mb_wb.0<1>:ud
677- NULL
678- data_port(
679- OBR_CACHE_TYPE,
680- OBR_MESSAGE_FENCE,
681- OBR_MF_COMMIT,
682- OBR_BIND_IDX,
683- OBR_WRITE_COMMIT_CATEGORY,
684- OBR_HEADER_PRESENT
685- )
686- mlen 1
687- rlen 1
688- {align1};
689-
690-__EXIT:
691-/*
692- * kill thread
693- */
694-mov (8) ts_msg_reg0<1>:UD r0<8,8,1>:UD {align1};
695-send (16) ts_msg_ind acc0<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT};
696-
697-
698- nop ;
699- nop ;
700-/* Compare three word data to get the min value */
701-word_imin:
702- cmp.le.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.4<0,1,0>:w {align1};
703- (f0.0) mov (1) TEMP_VAR0.0<1>:w INPUT_ARG0.0<0,1,0>:w {align1};
704- (-f0.0) mov (1) TEMP_VAR0.0<1>:w INPUT_ARG0.4<0,1,0>:w {align1};
705- cmp.le.f0.0 (1) null:w TEMP_VAR0.0<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1};
706- (f0.0) mov (1) RET_ARG<1>:w TEMP_VAR0.0<0,1,0>:w {align1};
707- (-f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.8<0,1,0>:w {align1};
708- RETURN {align1};
709-
710-/* Compare three word data to get the max value */
711-word_imax:
712- cmp.ge.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.4<0,1,0>:w {align1};
713- (f0.0) mov (1) TEMP_VAR0.0<1>:w INPUT_ARG0.0<0,1,0>:w {align1};
714- (-f0.0) mov (1) TEMP_VAR0.0<1>:w INPUT_ARG0.4<0,1,0>:w {align1};
715- cmp.ge.f0.0 (1) null:w TEMP_VAR0.0<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1};
716- (f0.0) mov (1) RET_ARG<1>:w TEMP_VAR0.0<0,1,0>:w {align1};
717- (-f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.8<0,1,0>:w {align1};
718- RETURN {align1};
719-
720-word_imedian:
721- cmp.ge.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.4<0,1,0>:w {align1};
722- (f0.0) jmpi (1) cmp_a_ge_b;
723- cmp.ge.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1};
724- (f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.0<0,1,0>:w {align1};
725- (f0.0) jmpi (1) cmp_end;
726- cmp.ge.f0.0 (1) null:w INPUT_ARG0.4<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1};
727- (f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.8<0,1,0>:w {align1};
728- (-f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.4<0,1,0>:w {align1};
729- jmpi (1) cmp_end;
730-cmp_a_ge_b:
731- cmp.ge.f0.0 (1) null:w INPUT_ARG0.4<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1};
732- (f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.4<0,1,0>:w {align1};
733- (f0.0) jmpi (1) cmp_end;
734- cmp.ge.f0.0 (1) null:w INPUT_ARG0.0<0,1,0>:w INPUT_ARG0.8<0,1,0>:w {align1};
735- (f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.8<0,1,0>:w {align1};
736- (-f0.0) mov (1) RET_ARG<1>:w INPUT_ARG0.0<0,1,0>:w {align1};
737-cmp_end:
738- RETURN {align1};
739-
--- a/src/shaders/vme/vp8_inter_frame_gen9.g9a
+++ b/src/shaders/vme/vp8_inter_frame_gen9.g9a
@@ -1,2 +1,2 @@
11 #include "vme8.inc"
2-#include "vp8_inter_frame_gen9.asm"
2+#include "vp8_inter_frame_gen8.asm"
--- a/src/shaders/vme/vp8_intra_frame_gen9.asm
+++ /dev/null
@@ -1,200 +0,0 @@
1-/*
2- * Copyright © 2014 Intel Corporation
3- *
4- * Permission is hereby granted, free of charge, to any person obtaining a
5- * copy of this software and associated documentation files (the
6- * "Software"), to deal in the Software without restriction, including
7- * without limitation the rights to use, copy, modify, merge, publish,
8- * distribute, sub license, and/or sell copies of the Software, and to
9- * permit persons to whom the Software is furnished to do so, subject to
10- * the following conditions:
11- *
12- * The above copyright notice and this permission notice (including the
13- * next paragraph) shall be included in all copies or substantial portions
14- * of the Software.
15- *
16- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19- * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23- *
24- * Authors:
25- * Zhao Yakui <yakui.zhao@intel.com>
26- * Xiang Haihao <haihao.xiang@intel.com>
27- * Li Zhong <zhong.li@intel.com>
28- *
29- */
30-
31-/*
32- * __START
33- */
34-__INTRA_START:
35-mov (16) tmp_reg0.0<1>:UD 0x0:UD {align1};
36-mov (16) tmp_reg2.0<1>:UD 0x0:UD {align1};
37-mov (16) tmp_reg4.0<1>:UD 0x0:UD {align1} ;
38-mov (16) tmp_reg6.0<1>:UD 0x0:UD {align1} ;
39-
40-shl (2) read0_header.0<1>:D orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */
41-add (1) read0_header.0<1>:D read0_header.0<0,1,0>:D -8:W {align1}; /* X offset */
42-add (1) read0_header.4<1>:D read0_header.4<0,1,0>:D -1:W {align1}; /* Y offset */
43-mov (1) read0_header.8<1>:UD BLOCK_32X1 {align1};
44-mov (1) read0_header.20<1>:UB thread_id_ub {align1}; /* dispatch id */
45-
46-shl (2) read1_header.0<1>:D orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */
47-add (1) read1_header.0<1>:D read1_header.0<0,1,0>:D -4:W {align1}; /* X offset */
48-mov (1) read1_header.8<1>:UD BLOCK_4X16 {align1};
49-mov (1) read1_header.20<1>:UB thread_id_ub {align1}; /* dispatch id */
50-
51-shl (2) vme_m0.8<1>:UW orig_xy_ub<2,2,1>:UB 4:UW {align1}; /* (x, y) * 16 */
52-mov (1) vme_m0.20<1>:UB thread_id_ub {align1}; /* dispatch id */
53-
54-mul (1) obw_m0.8<1>:UD w_in_mb_uw<0,1,0>:UW orig_y_ub<0,1,0>:UB {align1};
55-add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD orig_x_ub<0,1,0>:UB {align1};
56-mul (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 0x02:UD {align1};
57-mov (1) obw_m0.20<1>:UB thread_id_ub {align1}; /* dispatch id */
58-
59-/*
60- * Media Read Message -- fetch Luma neighbor edge pixels
61- */
62-/* ROW */
63-mov (8) msg_reg0.0<1>:UD read0_header.0<8,8,1>:UD {align1};
64-send (8) msg_ind INEP_ROW<1>:UB null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 1 {align1};
65-
66-/* COL */
67-mov (8) msg_reg0.0<1>:UD read1_header.0<8,8,1>:UD {align1};
68-send (8) msg_ind INEP_COL0<1>:UB null read(BIND_IDX_INEP, 0, 0, 4) mlen 1 rlen 2 {align1};
69-
70-/*
71- * Media Read Message -- fetch Chroma neighbor edge pixels
72- */
73-/* ROW */
74-shl (2) read0_header.0<1>:D orig_xy_ub<2,2,1>:UB 3:UW {align1}; /* x * 16 , y * 8 */
75-mul (1) read0_header.0<1>:D read0_header.0<0,1,0>:D 2:W {align1};
76-add (1) read0_header.0<1>:D read0_header.0<0,1,0>:D -8:W {align1}; /* X offset */
77-add (1) read0_header.4<1>:D read0_header.4<0,1,0>:D -1:W {align1}; /* Y offset */
78-mov (8) msg_reg0.0<1>:UD read0_header.0<8,8,1>:UD {align1};
79-send (8) msg_ind CHROMA_ROW<1>:UB null read(BIND_IDX_CBCR, 0, 0, 4) mlen 1 rlen 1 {align1};
80-
81-/* COL */
82-shl (2) read1_header.0<1>:D orig_xy_ub<2,2,1>:UB 3:UW {align1}; /* x * 16, y * 8 */
83-mul (1) read1_header.0<1>:D read1_header.0<0,1,0>:D 2:W {align1};
84-add (1) read1_header.0<1>:D read1_header.0<0,1,0>:D -4:W {align1}; /* X offset */
85-mov (1) read1_header.8<1>:UD BLOCK_8X4 {align1};
86-mov (8) msg_reg0.0<1>:UD read1_header.0<8,8,1>:UD {align1};
87-send (8) msg_ind CHROMA_COL<1>:UB null read(BIND_IDX_CBCR, 0, 0, 4) mlen 1 rlen 1 {align1};
88-
89-/* m2, get the MV/Mb cost passed by constant buffer
90-when creating EU thread by MEDIA_OBJECT */
91-mov (8) vme_msg_2<1>:UD r1.0<8,8,1>:UD {align1};
92-
93-/* m3. This is changed for FWD/BWD cost center */
94-mov (8) vme_msg_3<1>:UD 0x0:UD {align1};
95-
96-/* m4.*/
97-mov (8) vme_msg_4<1>:ud 0x0:ud {align1};
98-
99-/* m5 */
100-mov (1) INEP_ROW.0<1>:UD 0x0:UD {align1};
101-and (1) INEP_ROW.4<1>:UD INEP_ROW.4<0,1,0>:UD 0xFF000000:UD {align1};
102-mov (8) vme_msg_5<1>:UD INEP_ROW.0<8,8,1>:UD {align1};
103-
104-mov (1) tmp_reg0.0<1>:UB INTRA_PLANAR_MODE_MASK {align1}; /* vp8 don't support planar intra mode */
105-mov (1) tmp_reg0.1<1>:UB LUMA_CHROMA_MODE {align1}; /* Intra type: Luma + Chroma */
106-
107-/* Intra mode mask && Intra compute type */
108-mov (1) vme_msg_5.4<1>:UW tmp_reg0.0<0,1,0>:UW {align1};
109-
110-/* m6 */
111-mov (8) vme_msg_6<1>:UD 0x0:UD {align1};
112-mov (16) vme_msg_6.0<1>:UB INEP_COL0.3<32,8,4>:UB {align1};
113-mov (1) vme_msg_6.16<1>:UD INTRA_PREDICTORE_MODE {align1};
114-
115-/* the penalty for Intra mode */
116-mov (1) vme_msg_6.28<1>:UD 0x010101:UD {align1};
117-mov (1) vme_msg_6.20<1>:UW CHROMA_ROW.6<0,1,0>:UW {align1};
118-
119-
120-/* m7 */
121-
122-mov (4) vme_msg_7.16<1>:UD CHROMA_ROW.8<4,4,1>:UD {align1};
123-mov (8) vme_msg_7.0<1>:UW CHROMA_COL.2<16,8,2>:UW {align1};
124-
125-/*
126- * VME message
127- */
128-
129-/* m1 */
130-mov (1) intra_flag<1>:UW 0x0:UW {align1};
131-mov (1) intra_part_mask_ub<1>:UB LUMA_INTRA_8x8_DISABLE {align1}; /* vp8 don't support intra_8x8 mode*/
132-
133-/* assign MB intra struct from the thread payload*/
134-mov (1) mb_intra_struct_ub<1>:UB input_mb_intra_ub<0,1,0>:UB {align1};
135-
136-/* Disable DC HAAR component when calculating HARR SATD block */
137-mov (1) tmp_reg0.0<1>:UW DC_HARR_DISABLE:UW {align1};
138-mov (1) vme_m1.30<1>:UB tmp_reg0.0<0,1,0>:UB {align1};
139-
140-mov (8) vme_msg_1<1>:UD vme_m1.0<8,8,1>:UD {align1};
141-
142-/* m0 */
143-add (1) vme_m0.12<1>:UD vme_m0.12<0,1,0>:ud INTRA_SAD_HAAR:UD {align1};/* 16x16 Source, Intra_harr */
144-mov (1) vme_m0.15<1>:UB SUB_PART_8x4_DISABLE + SUB_PART_4x8_DISABLE {align1}; /* vp8 don't support 8x4 and 4x8 partion */
145-mov (8) vme_msg_0<1>:UD vme_m0.0<8,8,1>:UD {align1};
146-
147-/* after verification it will be passed by using payload */
148-send (8)
149- vme_msg_ind
150- vme_wb<1>:UD
151- null
152- cre(
153- BIND_IDX_VME,
154- VME_SIC_MESSAGE_TYPE
155- )
156- mlen sic_vme_msg_length
157- rlen vme_wb_length
158- {align1};
159-/*
160- * Oword Block Write message
161- */
162-mov (8) msg_reg0.0<1>:UD obw_m0<8,8,1>:UD {align1};
163-
164-mov (1) msg_reg1.0<1>:UD vme_wb.0<0,1,0>:UD {align1};
165-mov (1) msg_reg1.4<1>:UD vme_wb.16<0,1,0>:UD {align1};
166-mov (1) msg_reg1.8<1>:UD vme_wb.20<0,1,0>:UD {align1};
167-mov (1) msg_reg1.12<1>:UD vme_wb.24<0,1,0>:UD {align1};
168-
169-/* Distortion, Intra (17-16), */
170-mov (1) msg_reg1.16<1>:UW vme_wb.12<0,1,0>:UW {align1};
171-
172-mov (1) msg_reg1.20<1>:UD vme_wb.8<0,1,0>:UD {align1};
173-/* VME clock counts */
174-mov (1) msg_reg1.24<1>:UD vme_wb.28<0,1,0>:UD {align1};
175-
176-mov (1) msg_reg1.28<1>:UD obw_m0.8<0,1,0>:UD {align1};
177-
178-/* bind index 3, write 2 oword (32bytes), msg type: 8(OWord Block Write) */
179-send (16)
180- msg_ind
181- obw_wb
182- null
183- data_port(
184- OBW_CACHE_TYPE,
185- OBW_MESSAGE_TYPE,
186- OBW_CONTROL_2,
187- OBW_BIND_IDX,
188- OBW_WRITE_COMMIT_CATEGORY,
189- OBW_HEADER_PRESENT
190- )
191- mlen 2
192- rlen obw_wb_length
193- {align1};
194-
195-__EXIT:
196-/*
197- * kill thread
198- */
199-mov (8) ts_msg_reg0<1>:UD r0<8,8,1>:UD {align1};
200-send (16) ts_msg_ind acc0<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT};
--- a/src/shaders/vme/vp8_intra_frame_gen9.g9a
+++ b/src/shaders/vme/vp8_intra_frame_gen9.g9a
@@ -1,2 +1,2 @@
11 #include "vme8.inc"
2-#include "vp8_intra_frame_gen9.asm"
2+#include "vp8_intra_frame_gen8.asm"