Fork| Rev. | Time | Author |
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| 472daf5 | 2016-10-15 16:08:08 |  suikan |
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sincos_sub.vhd sra_rounded has been refactored. Now, no warning at compile time |
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| f0b10ec | 2016-10-15 09:12:14 | suikan |
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Refactored cordic_sincos_testgen. round_shift of main.c is now deleted. filanames are changed to const char[] |
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| 8ab32de | 2016-10-14 23:42:38 | suikan |
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eclipse status update |
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| 680285b | 2016-10-14 23:42:03 | suikan |
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the sin/cos value is scalled down to [-0.5,0.5) |
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| d8f75e6 | 2016-10-13 12:46:57 | suikan |
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Range compensation flag test is added. Test passed |
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| 07989d1 | 2016-10-13 10:28:18 | suikan |
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CORDIC SINCOS Test refactoring is done. model and SINCOS SUB now have range compensatin flag. The SINCOS CORDIC module need to work to use it |
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| f365c2e | 2016-10-13 09:44:28 | suikan |
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At the middle of work. Test bench is under refactoring |
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| 34ac3b3 | 2016-10-12 19:16:04 | suikan |
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Build command is splited to build# copy test vector and reference data |
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| 61e697a | 2016-10-12 19:13:07 | suikan |
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build command is renamed |
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| cdf96bc | 2016-10-12 19:11:28 | suikan |
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Test refactoring is done. SINCOS CORDIC passed all test |
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| 95e69d2 | 2016-10-12 11:42:37 | suikan |
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Debug undergoing. Some problem in pipeline |
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| 8ead774 | 2016-10-12 08:59:22 | suikan |
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Refactored directory |
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| 5a41f28 | 2016-10-12 00:46:33 | suikan |
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Still small bug on the clocking model |
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| 3621a2f | 2016-10-11 16:42:37 | suikan |
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sincos sub is under debugging. The rounding algorithm is wrong |
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| a4dbaa0 | 2016-10-11 09:56:30 | suikan |
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Debugged mistake of shift value in cordic_sincos.cpp |
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| c98a994 | 2016-10-10 22:04:40 | suikan |
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class sincos_cordic is under development |
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| 9ee67e9 | 2016-10-10 16:52:12 | suikan |
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refactoring the comment |
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| dc825f7 | 2016-10-10 13:43:43 | suikan |
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Refactoring the SINCOS model |
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| f989739 | 2016-10-10 11:22:14 | suikan |
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refactoring the test vector generator |
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| 292e3b1 | 2016-10-09 22:08:23 | suikan |
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Simulation cause warning, because the test vector doesn't reset at first. Test program doesn't represent the pipeline |
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| 6a3e9a1 | 2016-10-09 16:52:41 | suikan |
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Now, adding cordic design to vhdl. Need to convert the p_signal and q_signal to p and q, respectively |
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| 0de1869 | 2016-10-09 16:05:34 | suikan |
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The SINCOS test routine started to work for sin&cos routine |
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| 23bc3fc | 2016-10-08 22:54:37 | suikan |
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buidling test of the sincos |
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| ff426c0 | 2016-10-08 18:21:50 | suikan |
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tested coff initializaiton by file |
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| 289b294 | 2016-10-08 14:25:32 | suikan |
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Started to write sincos_cordic |
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| 760eb3f | 2016-10-07 22:32:07 | suikan |
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update comment |
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| 593c3e7 | 2016-10-06 21:09:39 | suikan |
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trial vhdl doxygen comment |
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| bcc4ada | 2016-10-06 18:00:47 | suikan |
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Added vhdl comment |
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| 1683fa4 | 2016-10-05 18:12:55 | suikan |
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Added management project for this directory |
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| 82e5035 | 2016-10-05 12:42:30 | suikan |
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sincos sub is working now. Async reset is OK |
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