Revision | 3628adf1cb50a27e3d90a75cc30314e458034dc9 (tree) |
---|---|
Time | 2019-06-16 22:31:41 |
Author | Yoshinori Sato <ysato@user...> |
Commiter | Yoshinori Sato |
hw/rx: RX Target hardware definition
rx62n - RX62N cpu.
rx-virt - RX QEMU virtual target.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20190607091116.49044-9-ysato@users.sourceforge.jp>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
[PMD: Use TYPE_RX62N_CPU, use #define for RX62N_NR_TMR/CMT/SCI,
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
v19: Fixed typo (Peter Maydell)
@@ -0,0 +1,14 @@ | ||
1 | +config RX | |
2 | + bool | |
3 | + | |
4 | +config RX62N | |
5 | + bool | |
6 | + select RX | |
7 | + select RX_ICU | |
8 | + select RENESAS_TMR8 | |
9 | + select RENESAS_CMT | |
10 | + select RENESAS_SCI | |
11 | + | |
12 | +config RX_VIRT | |
13 | + bool | |
14 | + select RX62N |
@@ -0,0 +1,2 @@ | ||
1 | +obj-$(CONFIG_RX62N) += rx62n.o | |
2 | +obj-$(CONFIG_RX_VIRT) += rx-virt.o |
@@ -0,0 +1,105 @@ | ||
1 | +/* | |
2 | + * RX QEMU virtual platform | |
3 | + * | |
4 | + * Copyright (c) 2019 Yoshinori Sato | |
5 | + * | |
6 | + * This program is free software; you can redistribute it and/or modify it | |
7 | + * under the terms and conditions of the GNU General Public License, | |
8 | + * version 2 or later, as published by the Free Software Foundation. | |
9 | + * | |
10 | + * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | + * more details. | |
14 | + * | |
15 | + * You should have received a copy of the GNU General Public License along with | |
16 | + * this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | + */ | |
18 | + | |
19 | +#include "qemu/osdep.h" | |
20 | +#include "qapi/error.h" | |
21 | +#include "qemu-common.h" | |
22 | +#include "cpu.h" | |
23 | +#include "hw/hw.h" | |
24 | +#include "hw/sysbus.h" | |
25 | +#include "hw/loader.h" | |
26 | +#include "hw/rx/rx62n.h" | |
27 | +#include "sysemu/sysemu.h" | |
28 | +#include "sysemu/qtest.h" | |
29 | +#include "sysemu/device_tree.h" | |
30 | +#include "hw/boards.h" | |
31 | + | |
32 | +/* Same address of GDB integrated simulator */ | |
33 | +#define SDRAM_BASE 0x01000000 | |
34 | + | |
35 | +static void rxvirt_init(MachineState *machine) | |
36 | +{ | |
37 | + RX62NState *s = g_new(RX62NState, 1); | |
38 | + MemoryRegion *sysmem = get_system_memory(); | |
39 | + MemoryRegion *sdram = g_new(MemoryRegion, 1); | |
40 | + const char *kernel_filename = machine->kernel_filename; | |
41 | + const char *dtb_filename = machine->dtb; | |
42 | + void *dtb = NULL; | |
43 | + int dtb_size; | |
44 | + | |
45 | + /* Allocate memory space */ | |
46 | + memory_region_init_ram(sdram, NULL, "sdram", 16 * MiB, | |
47 | + &error_fatal); | |
48 | + memory_region_add_subregion(sysmem, SDRAM_BASE, sdram); | |
49 | + | |
50 | + /* Initialize MCU */ | |
51 | + object_initialize_child(OBJECT(machine), "mcu", s, | |
52 | + sizeof(RX62NState), TYPE_RX62N, | |
53 | + &error_fatal, NULL); | |
54 | + object_property_set_link(OBJECT(s), OBJECT(get_system_memory()), | |
55 | + "memory", &error_abort); | |
56 | + object_property_set_bool(OBJECT(s), kernel_filename != NULL, | |
57 | + "load-kernel", &error_abort); | |
58 | + object_property_set_bool(OBJECT(s), true, "realized", &error_abort); | |
59 | + | |
60 | + /* Load kernel and dtb */ | |
61 | + if (kernel_filename) { | |
62 | + rx_load_image(RXCPU(first_cpu), kernel_filename, | |
63 | + SDRAM_BASE + 8 * MiB, 8 * MiB); | |
64 | + if (dtb_filename) { | |
65 | + dtb = load_device_tree(dtb_filename, &dtb_size); | |
66 | + if (dtb == NULL) { | |
67 | + fprintf(stderr, "Couldn't open dtb file %s\n", dtb_filename); | |
68 | + exit(1); | |
69 | + } | |
70 | + if (machine->kernel_cmdline && | |
71 | + qemu_fdt_setprop_string(dtb, "/chosen", "bootargs", | |
72 | + machine->kernel_cmdline) < 0) { | |
73 | + fprintf(stderr, "couldn't set /chosen/bootargs\n"); | |
74 | + exit(1); | |
75 | + } | |
76 | + rom_add_blob_fixed("dtb", dtb, dtb_size, | |
77 | + SDRAM_BASE + 16 * MiB - dtb_size); | |
78 | + /* Set dtb address to R1 */ | |
79 | + RXCPU(first_cpu)->env.regs[1] = 0x02000000 - dtb_size; | |
80 | + } | |
81 | + } | |
82 | +} | |
83 | + | |
84 | +static void rxvirt_class_init(ObjectClass *oc, void *data) | |
85 | +{ | |
86 | + MachineClass *mc = MACHINE_CLASS(oc); | |
87 | + | |
88 | + mc->desc = "RX QEMU Virtual Target"; | |
89 | + mc->init = rxvirt_init; | |
90 | + mc->is_default = 1; | |
91 | + mc->default_cpu_type = TYPE_RX62N_CPU; | |
92 | +} | |
93 | + | |
94 | +static const TypeInfo rxvirt_type = { | |
95 | + .name = MACHINE_TYPE_NAME("rx-virt"), | |
96 | + .parent = TYPE_MACHINE, | |
97 | + .class_init = rxvirt_class_init, | |
98 | +}; | |
99 | + | |
100 | +static void rxvirt_machine_init(void) | |
101 | +{ | |
102 | + type_register_static(&rxvirt_type); | |
103 | +} | |
104 | + | |
105 | +type_init(rxvirt_machine_init) |
@@ -0,0 +1,238 @@ | ||
1 | +/* | |
2 | + * RX62N Microcontroller | |
3 | + * | |
4 | + * Datasheet: RX62N Group, RX621 Group User's Manual: Hardware | |
5 | + * (Rev.1.40 R01UH0033EJ0140) | |
6 | + * | |
7 | + * Copyright (c) 2019 Yoshinori Sato | |
8 | + * | |
9 | + * This program is free software; you can redistribute it and/or modify it | |
10 | + * under the terms and conditions of the GNU General Public License, | |
11 | + * version 2 or later, as published by the Free Software Foundation. | |
12 | + * | |
13 | + * This program is distributed in the hope it will be useful, but WITHOUT | |
14 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | + * more details. | |
17 | + * | |
18 | + * You should have received a copy of the GNU General Public License along with | |
19 | + * this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | + */ | |
21 | + | |
22 | +#include "qemu/osdep.h" | |
23 | +#include "qapi/error.h" | |
24 | +#include "hw/hw.h" | |
25 | +#include "hw/rx/rx62n.h" | |
26 | +#include "hw/loader.h" | |
27 | +#include "hw/sysbus.h" | |
28 | +#include "sysemu/sysemu.h" | |
29 | +#include "cpu.h" | |
30 | + | |
31 | +/* | |
32 | + * IRQ -> IPR mapping table | |
33 | + * 0x00 - 0x91: IPR no (IPR00 to IPR91) | |
34 | + * 0xff: IPR not assigned | |
35 | + * See "11.3.1 Interrupt Vector Table" in hardware manual. | |
36 | + */ | |
37 | +static const int ipr_table[NR_IRQS] = { | |
38 | + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
39 | + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 15 */ | |
40 | + 0x00, 0xff, 0xff, 0xff, 0xff, 0x01, 0xff, 0x02, | |
41 | + 0xff, 0xff, 0xff, 0x03, 0x04, 0x05, 0x06, 0x07, /* 31 */ | |
42 | + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, | |
43 | + 0x10, 0x11, 0x12, 0x13, 0x14, 0x14, 0x14, 0x14, /* 47 */ | |
44 | + 0x15, 0x15, 0x15, 0x15, 0xff, 0xff, 0xff, 0xff, | |
45 | + 0x18, 0x18, 0x18, 0x18, 0x18, 0x1d, 0x1e, 0x1f, /* 63 */ | |
46 | + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, | |
47 | + 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, /* 79 */ | |
48 | + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
49 | + 0xff, 0xff, 0x3a, 0x3b, 0x3c, 0xff, 0xff, 0xff, /* 95 */ | |
50 | + 0x40, 0xff, 0x44, 0x45, 0xff, 0xff, 0x48, 0xff, | |
51 | + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 111 */ | |
52 | + 0xff, 0xff, 0x51, 0x51, 0x51, 0x51, 0x52, 0x52, | |
53 | + 0x52, 0x53, 0x53, 0x54, 0x54, 0x55, 0x55, 0x56, /* 127 */ | |
54 | + 0x56, 0x57, 0x57, 0x57, 0x57, 0x58, 0x59, 0x59, | |
55 | + 0x59, 0x59, 0x5a, 0x5b, 0x5b, 0x5b, 0x5c, 0x5c, /* 143 */ | |
56 | + 0x5c, 0x5c, 0x5d, 0x5d, 0x5d, 0x5e, 0x5e, 0x5f, | |
57 | + 0x5f, 0x60, 0x60, 0x61, 0x61, 0x62, 0x62, 0x62, /* 159 */ | |
58 | + 0x62, 0x63, 0x64, 0x64, 0x64, 0x64, 0x65, 0x66, | |
59 | + 0x66, 0x66, 0x67, 0x67, 0x67, 0x67, 0x68, 0x68, /* 175 */ | |
60 | + 0x68, 0x69, 0x69, 0x69, 0x6a, 0x6a, 0x6a, 0x6b, | |
61 | + 0x6b, 0x6b, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 191 */ | |
62 | + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x70, 0x71, | |
63 | + 0x72, 0x73, 0x74, 0x75, 0xff, 0xff, 0xff, 0xff, /* 207 */ | |
64 | + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80, 0x80, | |
65 | + 0x80, 0x80, 0x81, 0x81, 0x81, 0x81, 0x82, 0x82, /* 223 */ | |
66 | + 0x82, 0x82, 0x83, 0x83, 0x83, 0x83, 0xff, 0xff, | |
67 | + 0xff, 0xff, 0x85, 0x85, 0x85, 0x85, 0x86, 0x86, /* 239 */ | |
68 | + 0x86, 0x86, 0xff, 0xff, 0xff, 0xff, 0x88, 0x89, | |
69 | + 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, 0x90, 0x91, /* 255 */ | |
70 | +}; | |
71 | + | |
72 | +/* | |
73 | + * Level triggerd IRQ list | |
74 | + * Not listed IRQ is Edge trigger. | |
75 | + * See "11.3.1 Interrupt Vector Table" in hardware manual. | |
76 | + */ | |
77 | +static const uint32_t levelirq[] = { | |
78 | + 16, 21, 32, 44, 47, 48, 51, 64, 65, 66, | |
79 | + 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, | |
80 | + 77, 78, 79, 90, 91, 170, 171, 172, 173, 214, | |
81 | + 217, 218, 221, 222, 225, 226, 229, 234, 237, 238, | |
82 | + 241, 246, 249, 250, 253, | |
83 | +}; | |
84 | + | |
85 | +static void register_icu(RX62NState *s) | |
86 | +{ | |
87 | + int i; | |
88 | + SysBusDevice *icu; | |
89 | + | |
90 | + object_initialize_child(OBJECT(s), "icu", &s->icu, sizeof(RXICUState), | |
91 | + TYPE_RXICU, &error_abort, NULL); | |
92 | + | |
93 | + icu = SYS_BUS_DEVICE(&s->icu); | |
94 | + sysbus_mmio_map(SYS_BUS_DEVICE(icu), 0, RX62N_ICUBASE); | |
95 | + qdev_prop_set_uint32(DEVICE(icu), "len-ipr-map", NR_IRQS); | |
96 | + for (i = 0; i < NR_IRQS; i++) { | |
97 | + char propname[32]; | |
98 | + snprintf(propname, sizeof(propname), "ipr-map[%d]", i); | |
99 | + qdev_prop_set_uint32(DEVICE(icu), propname, ipr_table[i]); | |
100 | + } | |
101 | + qdev_prop_set_uint32(DEVICE(icu), "len-trigger-level", | |
102 | + ARRAY_SIZE(levelirq)); | |
103 | + for (i = 0; i < ARRAY_SIZE(levelirq); i++) { | |
104 | + char propname[32]; | |
105 | + snprintf(propname, sizeof(propname), "trigger-level[%d]", i); | |
106 | + qdev_prop_set_uint32(DEVICE(icu), propname, levelirq[i]); | |
107 | + } | |
108 | + | |
109 | + for (i = 0; i < NR_IRQS; i++) { | |
110 | + s->irq[i] = qdev_get_gpio_in(DEVICE(icu), i); | |
111 | + } | |
112 | + | |
113 | + qdev_init_nofail(DEVICE(icu)); | |
114 | + sysbus_connect_irq(icu, 0, qdev_get_gpio_in(DEVICE(&s->cpu), RX_CPU_IRQ)); | |
115 | + sysbus_connect_irq(icu, 1, qdev_get_gpio_in(DEVICE(&s->cpu), RX_CPU_FIR)); | |
116 | + sysbus_connect_irq(icu, 2, s->irq[SWI]); | |
117 | + | |
118 | +} | |
119 | + | |
120 | +static void register_tmr(RX62NState *s, int unit) | |
121 | +{ | |
122 | + SysBusDevice *tmr; | |
123 | + int i, irqbase; | |
124 | + | |
125 | + object_initialize_child(OBJECT(s), "tmr[*]", &s->tmr[unit], | |
126 | + sizeof(RTMRState), TYPE_RENESAS_TMR, | |
127 | + &error_abort, NULL); | |
128 | + | |
129 | + tmr = SYS_BUS_DEVICE(&s->tmr[unit]); | |
130 | + sysbus_mmio_map(tmr, 0, RX62N_TMRBASE + unit * 0x10); | |
131 | + qdev_prop_set_uint64(DEVICE(tmr), "input-freq", RX62N_PCLK); | |
132 | + | |
133 | + qdev_init_nofail(DEVICE(tmr)); | |
134 | + irqbase = RX62N_TMR_IRQBASE + TMR_NR_IRQ * unit; | |
135 | + for (i = 0; i < TMR_NR_IRQ; i++) { | |
136 | + sysbus_connect_irq(tmr, i, s->irq[irqbase + i]); | |
137 | + } | |
138 | +} | |
139 | + | |
140 | +static void register_cmt(RX62NState *s, int unit) | |
141 | +{ | |
142 | + SysBusDevice *cmt; | |
143 | + int i, irqbase; | |
144 | + | |
145 | + object_initialize_child(OBJECT(s), "cmt[*]", &s->cmt[unit], | |
146 | + sizeof(RCMTState), TYPE_RENESAS_CMT, | |
147 | + &error_abort, NULL); | |
148 | + | |
149 | + cmt = SYS_BUS_DEVICE(&s->cmt[unit]); | |
150 | + sysbus_mmio_map(cmt, 0, RX62N_CMTBASE + unit * 0x10); | |
151 | + qdev_prop_set_uint64(DEVICE(cmt), "input-freq", RX62N_PCLK); | |
152 | + | |
153 | + qdev_init_nofail(DEVICE(cmt)); | |
154 | + irqbase = RX62N_CMT_IRQBASE + CMT_NR_IRQ * unit; | |
155 | + for (i = 0; i < CMT_NR_IRQ; i++) { | |
156 | + sysbus_connect_irq(cmt, i, s->irq[irqbase + i]); | |
157 | + } | |
158 | +} | |
159 | + | |
160 | +static void register_sci(RX62NState *s, int unit) | |
161 | +{ | |
162 | + SysBusDevice *sci; | |
163 | + int i, irqbase; | |
164 | + | |
165 | + object_initialize_child(OBJECT(s), "sci[*]", &s->sci[unit], | |
166 | + sizeof(RSCIState), TYPE_RENESAS_SCI, | |
167 | + &error_abort, NULL); | |
168 | + | |
169 | + sci = SYS_BUS_DEVICE(&s->sci[unit]); | |
170 | + sysbus_mmio_map(sci, 0, RX62N_SCIBASE + unit * 0x08); | |
171 | + qdev_prop_set_chr(DEVICE(sci), "chardev", serial_hd(unit)); | |
172 | + qdev_prop_set_uint64(DEVICE(sci), "input-freq", RX62N_PCLK); | |
173 | + | |
174 | + qdev_init_nofail(DEVICE(sci)); | |
175 | + irqbase = RX62N_SCI_IRQBASE + SCI_NR_IRQ * unit; | |
176 | + for (i = 0; i < SCI_NR_IRQ; i++) { | |
177 | + sysbus_connect_irq(sci, i, s->irq[irqbase + i]); | |
178 | + } | |
179 | +} | |
180 | + | |
181 | +static void rx62n_realize(DeviceState *dev, Error **errp) | |
182 | +{ | |
183 | + RX62NState *s = RX62N(dev); | |
184 | + | |
185 | + memory_region_init_ram(&s->iram, NULL, "iram", RX62N_IRAM_SIZE, errp); | |
186 | + memory_region_add_subregion(s->sysmem, RX62N_IRAM_BASE, &s->iram); | |
187 | + memory_region_init_rom(&s->d_flash, NULL, "dataflash", | |
188 | + RX62N_DFLASH_SIZE, errp); | |
189 | + memory_region_add_subregion(s->sysmem, RX62N_DFLASH_BASE, &s->d_flash); | |
190 | + memory_region_init_rom(&s->c_flash, NULL, "codeflash", | |
191 | + RX62N_CFLASH_SIZE, errp); | |
192 | + memory_region_add_subregion(s->sysmem, RX62N_CFLASH_BASE, &s->c_flash); | |
193 | + if (!s->kernel) { | |
194 | + rom_add_file_fixed(bios_name, RX62N_CFLASH_BASE, 0); | |
195 | + } | |
196 | + | |
197 | + /* Initialize CPU */ | |
198 | + object_initialize_child(OBJECT(s), "cpu", &s->cpu, sizeof(RXCPU), | |
199 | + TYPE_RX62N_CPU, errp, NULL); | |
200 | + object_property_set_bool(OBJECT(&s->cpu), true, "realized", errp); | |
201 | + | |
202 | + register_icu(s); | |
203 | + s->cpu.env.ack = qdev_get_gpio_in_named(DEVICE(&s->icu), "ack", 0); | |
204 | + register_tmr(s, 0); | |
205 | + register_tmr(s, 1); | |
206 | + register_cmt(s, 0); | |
207 | + register_cmt(s, 1); | |
208 | + register_sci(s, 0); | |
209 | +} | |
210 | + | |
211 | +static Property rx62n_properties[] = { | |
212 | + DEFINE_PROP_LINK("memory", RX62NState, sysmem, TYPE_MEMORY_REGION, | |
213 | + MemoryRegion *), | |
214 | + DEFINE_PROP_BOOL("load-kernel", RX62NState, kernel, false), | |
215 | + DEFINE_PROP_END_OF_LIST(), | |
216 | +}; | |
217 | + | |
218 | +static void rx62n_class_init(ObjectClass *klass, void *data) | |
219 | +{ | |
220 | + DeviceClass *dc = DEVICE_CLASS(klass); | |
221 | + | |
222 | + dc->realize = rx62n_realize; | |
223 | + dc->props = rx62n_properties; | |
224 | +} | |
225 | + | |
226 | +static const TypeInfo rx62n_info = { | |
227 | + .name = TYPE_RX62N, | |
228 | + .parent = TYPE_SYS_BUS_DEVICE, | |
229 | + .instance_size = sizeof(RX62NState), | |
230 | + .class_init = rx62n_class_init, | |
231 | +}; | |
232 | + | |
233 | +static void rx62n_register_types(void) | |
234 | +{ | |
235 | + type_register_static(&rx62n_info); | |
236 | +} | |
237 | + | |
238 | +type_init(rx62n_register_types) |
@@ -0,0 +1,7 @@ | ||
1 | +#ifndef QEMU_RX_H | |
2 | +#define QEMU_RX_H | |
3 | +/* Definitions for RX board emulation. */ | |
4 | + | |
5 | +#include "target/rx/cpu-qom.h" | |
6 | + | |
7 | +#endif |
@@ -0,0 +1,91 @@ | ||
1 | +/* | |
2 | + * RX62N MCU Object | |
3 | + * | |
4 | + * Datasheet: RX62N Group, RX621 Group User's Manual: Hardware | |
5 | + * (Rev.1.40 R01UH0033EJ0140) | |
6 | + * | |
7 | + * Copyright (c) 2019 Yoshinori Sato | |
8 | + * | |
9 | + * This program is free software; you can redistribute it and/or modify it | |
10 | + * under the terms and conditions of the GNU General Public License, | |
11 | + * version 2 or later, as published by the Free Software Foundation. | |
12 | + * | |
13 | + * This program is distributed in the hope it will be useful, but WITHOUT | |
14 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | + * more details. | |
17 | + * | |
18 | + * You should have received a copy of the GNU General Public License along with | |
19 | + * this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | + */ | |
21 | + | |
22 | +#ifndef HW_RX_RX62N_H | |
23 | +#define HW_RX_RX62N_H | |
24 | + | |
25 | +#include "hw/sysbus.h" | |
26 | +#include "hw/intc/rx_icu.h" | |
27 | +#include "hw/timer/renesas_tmr.h" | |
28 | +#include "hw/timer/renesas_cmt.h" | |
29 | +#include "hw/char/renesas_sci.h" | |
30 | +#include "target/rx/cpu.h" | |
31 | +#include "qemu/units.h" | |
32 | + | |
33 | +#define TYPE_RX62N "rx62n" | |
34 | +#define RX62N(obj) OBJECT_CHECK(RX62NState, (obj), TYPE_RX62N) | |
35 | + | |
36 | +#define RX62N_NR_TMR 2 | |
37 | +#define RX62N_NR_CMT 2 | |
38 | +#define RX62N_NR_SCI 6 | |
39 | + | |
40 | +typedef struct RX62NState { | |
41 | + SysBusDevice parent_obj; | |
42 | + | |
43 | + RXCPU cpu; | |
44 | + RXICUState icu; | |
45 | + RTMRState tmr[RX62N_NR_TMR]; | |
46 | + RCMTState cmt[RX62N_NR_CMT]; | |
47 | + RSCIState sci[RX62N_NR_SCI]; | |
48 | + | |
49 | + MemoryRegion *sysmem; | |
50 | + bool kernel; | |
51 | + | |
52 | + MemoryRegion iram; | |
53 | + MemoryRegion iomem1; | |
54 | + MemoryRegion d_flash; | |
55 | + MemoryRegion iomem2; | |
56 | + MemoryRegion iomem3; | |
57 | + MemoryRegion c_flash; | |
58 | + qemu_irq irq[NR_IRQS]; | |
59 | +} RX62NState; | |
60 | + | |
61 | +/* | |
62 | + * RX62N Peripheral Address | |
63 | + * See users manual section 5 | |
64 | + */ | |
65 | +#define RX62N_ICUBASE 0x00087000 | |
66 | +#define RX62N_TMRBASE 0x00088200 | |
67 | +#define RX62N_CMTBASE 0x00088000 | |
68 | +#define RX62N_SCIBASE 0x00088240 | |
69 | + | |
70 | +/* | |
71 | + * RX62N Peripheral IRQ | |
72 | + * See users manual section 11 | |
73 | + */ | |
74 | +#define RX62N_TMR_IRQBASE 174 | |
75 | +#define RX62N_CMT_IRQBASE 28 | |
76 | +#define RX62N_SCI_IRQBASE 214 | |
77 | + | |
78 | +/* | |
79 | + * RX62N Internal Memory | |
80 | + * It is the value of R5F562N8. | |
81 | + * Please change the size for R5F562N7. | |
82 | + */ | |
83 | +#define RX62N_IRAM_BASE 0x00000000 | |
84 | +#define RX62N_IRAM_SIZE (96 * KiB) | |
85 | +#define RX62N_DFLASH_BASE 0x00100000 | |
86 | +#define RX62N_DFLASH_SIZE (32 * KiB) | |
87 | +#define RX62N_CFLASH_BASE 0xfff80000 | |
88 | +#define RX62N_CFLASH_SIZE (512 * KiB) | |
89 | + | |
90 | +#define RX62N_PCLK (48 * 1000 * 1000) | |
91 | +#endif |