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Revision50d8d6ed558c2e30158b4a7cc76ec824d497bed9 (tree)
Time2020-06-01 00:49:33
AuthorYoshinori Sato <ysato@user...>
CommiterYoshinori Sato

Log Message

hw/timer: remove sh_timer.c

SH4 TMU using new module. This file is obsolute.

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>

Change Summary

  • delete: hw/timer/sh_timer.c

Incremental Difference

--- a/hw/timer/sh_timer.c
+++ /dev/null
@@ -1,341 +0,0 @@
1-/*
2- * SuperH Timer modules.
3- *
4- * Copyright (c) 2007 Magnus Damm
5- * Based on arm_timer.c by Paul Brook
6- * Copyright (c) 2005-2006 CodeSourcery.
7- *
8- * This code is licensed under the GPL.
9- */
10-
11-#include "qemu/osdep.h"
12-#include "hw/hw.h"
13-#include "hw/irq.h"
14-#include "hw/sh4/sh.h"
15-#include "qemu/timer.h"
16-#include "hw/ptimer.h"
17-
18-//#define DEBUG_TIMER
19-
20-#define TIMER_TCR_TPSC (7 << 0)
21-#define TIMER_TCR_CKEG (3 << 3)
22-#define TIMER_TCR_UNIE (1 << 5)
23-#define TIMER_TCR_ICPE (3 << 6)
24-#define TIMER_TCR_UNF (1 << 8)
25-#define TIMER_TCR_ICPF (1 << 9)
26-#define TIMER_TCR_RESERVED (0x3f << 10)
27-
28-#define TIMER_FEAT_CAPT (1 << 0)
29-#define TIMER_FEAT_EXTCLK (1 << 1)
30-
31-#define OFFSET_TCOR 0
32-#define OFFSET_TCNT 1
33-#define OFFSET_TCR 2
34-#define OFFSET_TCPR 3
35-
36-typedef struct {
37- ptimer_state *timer;
38- uint32_t tcnt;
39- uint32_t tcor;
40- uint32_t tcr;
41- uint32_t tcpr;
42- int freq;
43- int int_level;
44- int old_level;
45- int feat;
46- int enabled;
47- qemu_irq irq;
48-} sh_timer_state;
49-
50-/* Check all active timers, and schedule the next timer interrupt. */
51-
52-static void sh_timer_update(sh_timer_state *s)
53-{
54- int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE);
55-
56- if (new_level != s->old_level)
57- qemu_set_irq (s->irq, new_level);
58-
59- s->old_level = s->int_level;
60- s->int_level = new_level;
61-}
62-
63-static uint32_t sh_timer_read(void *opaque, hwaddr offset)
64-{
65- sh_timer_state *s = (sh_timer_state *)opaque;
66-
67- switch (offset >> 2) {
68- case OFFSET_TCOR:
69- return s->tcor;
70- case OFFSET_TCNT:
71- return ptimer_get_count(s->timer);
72- case OFFSET_TCR:
73- return s->tcr | (s->int_level ? TIMER_TCR_UNF : 0);
74- case OFFSET_TCPR:
75- if (s->feat & TIMER_FEAT_CAPT)
76- return s->tcpr;
77- /* fall through */
78- default:
79- hw_error("sh_timer_read: Bad offset %x\n", (int)offset);
80- return 0;
81- }
82-}
83-
84-static void sh_timer_write(void *opaque, hwaddr offset,
85- uint32_t value)
86-{
87- sh_timer_state *s = (sh_timer_state *)opaque;
88- int freq;
89-
90- switch (offset >> 2) {
91- case OFFSET_TCOR:
92- s->tcor = value;
93- ptimer_transaction_begin(s->timer);
94- ptimer_set_limit(s->timer, s->tcor, 0);
95- ptimer_transaction_commit(s->timer);
96- break;
97- case OFFSET_TCNT:
98- s->tcnt = value;
99- ptimer_transaction_begin(s->timer);
100- ptimer_set_count(s->timer, s->tcnt);
101- ptimer_transaction_commit(s->timer);
102- break;
103- case OFFSET_TCR:
104- ptimer_transaction_begin(s->timer);
105- if (s->enabled) {
106- /* Pause the timer if it is running. This may cause some
107- inaccuracy dure to rounding, but avoids a whole lot of other
108- messyness. */
109- ptimer_stop(s->timer);
110- }
111- freq = s->freq;
112- /* ??? Need to recalculate expiry time after changing divisor. */
113- switch (value & TIMER_TCR_TPSC) {
114- case 0: freq >>= 2; break;
115- case 1: freq >>= 4; break;
116- case 2: freq >>= 6; break;
117- case 3: freq >>= 8; break;
118- case 4: freq >>= 10; break;
119- case 6:
120- case 7: if (s->feat & TIMER_FEAT_EXTCLK) break;
121- default: hw_error("sh_timer_write: Reserved TPSC value\n"); break;
122- }
123- switch ((value & TIMER_TCR_CKEG) >> 3) {
124- case 0: break;
125- case 1:
126- case 2:
127- case 3: if (s->feat & TIMER_FEAT_EXTCLK) break;
128- default: hw_error("sh_timer_write: Reserved CKEG value\n"); break;
129- }
130- switch ((value & TIMER_TCR_ICPE) >> 6) {
131- case 0: break;
132- case 2:
133- case 3: if (s->feat & TIMER_FEAT_CAPT) break;
134- default: hw_error("sh_timer_write: Reserved ICPE value\n"); break;
135- }
136- if ((value & TIMER_TCR_UNF) == 0)
137- s->int_level = 0;
138-
139- value &= ~TIMER_TCR_UNF;
140-
141- if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT)))
142- hw_error("sh_timer_write: Reserved ICPF value\n");
143-
144- value &= ~TIMER_TCR_ICPF; /* capture not supported */
145-
146- if (value & TIMER_TCR_RESERVED)
147- hw_error("sh_timer_write: Reserved TCR bits set\n");
148- s->tcr = value;
149- ptimer_set_limit(s->timer, s->tcor, 0);
150- ptimer_set_freq(s->timer, freq);
151- if (s->enabled) {
152- /* Restart the timer if still enabled. */
153- ptimer_run(s->timer, 0);
154- }
155- ptimer_transaction_commit(s->timer);
156- break;
157- case OFFSET_TCPR:
158- if (s->feat & TIMER_FEAT_CAPT) {
159- s->tcpr = value;
160- break;
161- }
162- default:
163- hw_error("sh_timer_write: Bad offset %x\n", (int)offset);
164- }
165- sh_timer_update(s);
166-}
167-
168-static void sh_timer_start_stop(void *opaque, int enable)
169-{
170- sh_timer_state *s = (sh_timer_state *)opaque;
171-
172-#ifdef DEBUG_TIMER
173- printf("sh_timer_start_stop %d (%d)\n", enable, s->enabled);
174-#endif
175-
176- ptimer_transaction_begin(s->timer);
177- if (s->enabled && !enable) {
178- ptimer_stop(s->timer);
179- }
180- if (!s->enabled && enable) {
181- ptimer_run(s->timer, 0);
182- }
183- ptimer_transaction_commit(s->timer);
184- s->enabled = !!enable;
185-
186-#ifdef DEBUG_TIMER
187- printf("sh_timer_start_stop done %d\n", s->enabled);
188-#endif
189-}
190-
191-static void sh_timer_tick(void *opaque)
192-{
193- sh_timer_state *s = (sh_timer_state *)opaque;
194- s->int_level = s->enabled;
195- sh_timer_update(s);
196-}
197-
198-static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq)
199-{
200- sh_timer_state *s;
201-
202- s = (sh_timer_state *)g_malloc0(sizeof(sh_timer_state));
203- s->freq = freq;
204- s->feat = feat;
205- s->tcor = 0xffffffff;
206- s->tcnt = 0xffffffff;
207- s->tcpr = 0xdeadbeef;
208- s->tcr = 0;
209- s->enabled = 0;
210- s->irq = irq;
211-
212- s->timer = ptimer_init(sh_timer_tick, s, PTIMER_POLICY_DEFAULT);
213-
214- sh_timer_write(s, OFFSET_TCOR >> 2, s->tcor);
215- sh_timer_write(s, OFFSET_TCNT >> 2, s->tcnt);
216- sh_timer_write(s, OFFSET_TCPR >> 2, s->tcpr);
217- sh_timer_write(s, OFFSET_TCR >> 2, s->tcpr);
218- /* ??? Save/restore. */
219- return s;
220-}
221-
222-typedef struct {
223- MemoryRegion iomem;
224- MemoryRegion iomem_p4;
225- MemoryRegion iomem_a7;
226- void *timer[3];
227- int level[3];
228- uint32_t tocr;
229- uint32_t tstr;
230- int feat;
231-} tmu012_state;
232-
233-static uint64_t tmu012_read(void *opaque, hwaddr offset,
234- unsigned size)
235-{
236- tmu012_state *s = (tmu012_state *)opaque;
237-
238-#ifdef DEBUG_TIMER
239- printf("tmu012_read 0x%lx\n", (unsigned long) offset);
240-#endif
241-
242- if (offset >= 0x20) {
243- if (!(s->feat & TMU012_FEAT_3CHAN))
244- hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
245- return sh_timer_read(s->timer[2], offset - 0x20);
246- }
247-
248- if (offset >= 0x14)
249- return sh_timer_read(s->timer[1], offset - 0x14);
250-
251- if (offset >= 0x08)
252- return sh_timer_read(s->timer[0], offset - 0x08);
253-
254- if (offset == 4)
255- return s->tstr;
256-
257- if ((s->feat & TMU012_FEAT_TOCR) && offset == 0)
258- return s->tocr;
259-
260- hw_error("tmu012_write: Bad offset %x\n", (int)offset);
261- return 0;
262-}
263-
264-static void tmu012_write(void *opaque, hwaddr offset,
265- uint64_t value, unsigned size)
266-{
267- tmu012_state *s = (tmu012_state *)opaque;
268-
269-#ifdef DEBUG_TIMER
270- printf("tmu012_write 0x%lx 0x%08x\n", (unsigned long) offset, value);
271-#endif
272-
273- if (offset >= 0x20) {
274- if (!(s->feat & TMU012_FEAT_3CHAN))
275- hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
276- sh_timer_write(s->timer[2], offset - 0x20, value);
277- return;
278- }
279-
280- if (offset >= 0x14) {
281- sh_timer_write(s->timer[1], offset - 0x14, value);
282- return;
283- }
284-
285- if (offset >= 0x08) {
286- sh_timer_write(s->timer[0], offset - 0x08, value);
287- return;
288- }
289-
290- if (offset == 4) {
291- sh_timer_start_stop(s->timer[0], value & (1 << 0));
292- sh_timer_start_stop(s->timer[1], value & (1 << 1));
293- if (s->feat & TMU012_FEAT_3CHAN)
294- sh_timer_start_stop(s->timer[2], value & (1 << 2));
295- else
296- if (value & (1 << 2))
297- hw_error("tmu012_write: Bad channel\n");
298-
299- s->tstr = value;
300- return;
301- }
302-
303- if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) {
304- s->tocr = value & (1 << 0);
305- }
306-}
307-
308-static const MemoryRegionOps tmu012_ops = {
309- .read = tmu012_read,
310- .write = tmu012_write,
311- .endianness = DEVICE_NATIVE_ENDIAN,
312-};
313-
314-void tmu012_init(MemoryRegion *sysmem, hwaddr base,
315- int feat, uint32_t freq,
316- qemu_irq ch0_irq, qemu_irq ch1_irq,
317- qemu_irq ch2_irq0, qemu_irq ch2_irq1)
318-{
319- tmu012_state *s;
320- int timer_feat = (feat & TMU012_FEAT_EXTCLK) ? TIMER_FEAT_EXTCLK : 0;
321-
322- s = (tmu012_state *)g_malloc0(sizeof(tmu012_state));
323- s->feat = feat;
324- s->timer[0] = sh_timer_init(freq, timer_feat, ch0_irq);
325- s->timer[1] = sh_timer_init(freq, timer_feat, ch1_irq);
326- if (feat & TMU012_FEAT_3CHAN)
327- s->timer[2] = sh_timer_init(freq, timer_feat | TIMER_FEAT_CAPT,
328- ch2_irq0); /* ch2_irq1 not supported */
329-
330- memory_region_init_io(&s->iomem, NULL, &tmu012_ops, s,
331- "timer", 0x100000000ULL);
332-
333- memory_region_init_alias(&s->iomem_p4, NULL, "timer-p4",
334- &s->iomem, 0, 0x1000);
335- memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4);
336-
337- memory_region_init_alias(&s->iomem_a7, NULL, "timer-a7",
338- &s->iomem, 0, 0x1000);
339- memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7);
340- /* ??? Save/restore. */
341-}