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Revision	7a290b65f23f670a3fd137e69b437ee77b780c64 (tree)
Time	2019-06-02 23:44:26
Author	Yoshinori Sato <ysato@user...>
Commiter	Yoshinori Sato

Log Message

WIP: mov

Change Summary

modified: arch_init.c (diff)
modified: hw/Kconfig (diff)
modified: include/sysemu/arch_init.h (diff)
modified: scripts/decodetree.py (diff)
modified: target/h8300/cpu.c (diff)
modified: target/h8300/cpu.h (diff)
modified: target/h8300/helper.h (diff)
modified: target/h8300/insns.decode (diff)
modified: target/h8300/op_helper.c (diff)
modified: target/h8300/translate.c (diff)
modified: target/rx/translate.c (diff)

Incremental Difference

--- a/arch_init.c

+++ b/arch_init.c

		@@ -52,6 +52,8 @@ int graphic_depth = 32;
52	52	#define QEMU_ARCH QEMU_ARCH_ARM
53	53	#elif defined(TARGET_CRIS)
54	54	#define QEMU_ARCH QEMU_ARCH_CRIS
	55	+#elif defined(TARGET_H8300)
	56	+#define QEMU_ARCH QEMU_ARCH_H8300
55	57	#elif defined(TARGET_HPPA)
56	58	#define QEMU_ARCH QEMU_ARCH_HPPA
57	59	#elif defined(TARGET_I386)

--- a/hw/Kconfig

+++ b/hw/Kconfig

		@@ -42,6 +42,7 @@ source watchdog/Kconfig
42	42	source arm/Kconfig
43	43	source alpha/Kconfig
44	44	source cris/Kconfig
	45	+source h8300/Kconfig
45	46	source hppa/Kconfig
46	47	source i386/Kconfig
47	48	source lm32/Kconfig

--- a/include/sysemu/arch_init.h

+++ b/include/sysemu/arch_init.h

		@@ -26,6 +26,7 @@ enum {
26	26	QEMU_ARCH_HPPA = (1 << 18),
27	27	QEMU_ARCH_RISCV = (1 << 19),
28	28	QEMU_ARCH_RX = (1 << 20),
	29	+ QEMU_ARCH_H8300 = (1 << 21),
29	30	};
30	31
31	32	extern const uint32_t arch_type;

--- a/scripts/decodetree.py

+++ b/scripts/decodetree.py

		@@ -177,10 +177,13 @@ class Field:
177	177	return str(self.pos) + ':' + s + str(self.len)
178	178
179	179	def str_extract(self):
180		- if self.sign:
181		- extr = 'sextract32'
	180	+ if self.pos == 0 and self.len ==0:
	181	+ extr = 'dummy'
182	182	else:
183		- extr = 'extract32'
	183	+ if self.sign:
	184	+ extr = 'sextract32'
	185	+ else:
	186	+ extr = 'extract32'
184	187	return '{0}(insn, {1}, {2})'.format(extr, self.pos, self.len)
185	188
186	189	def __eq__(self, other):

--- a/target/h8300/cpu.c

+++ b/target/h8300/cpu.c

		@@ -49,19 +49,19 @@ static void h8300_cpu_reset(CPUState *s)
49	49	{
50	50	H8300CPU *cpu = H8300CPU(s);
51	51	H8300CPUClass *rcc = H8300CPU_GET_CLASS(cpu);
52		- CPURXState *env = &cpu->env;
	52	+ CPUH8300State *env = &cpu->env;
53	53	uint32_t *resetvec;
54	54
55	55	rcc->parent_reset(s);
56	56
57		- memset(env, 0, offsetof(CPURXState, end_reset_fields));
	57	+ memset(env, 0, offsetof(CPUH8300State, end_reset_fields));
58	58
59	59	resetvec = rom_ptr(0x000000, 4);
60	60	if (resetvec) {
61	61	/* In the case of kernel, it is ignored because it is not set. */
62	62	env->pc = ldl_p(resetvec);
63	63	}
64		- h8300_cpu_unpack_psw(env, 0);
	64	+ h8300_cpu_unpack_ccr(env, 0x80);
65	65	}
66	66
67	67	static void h8300_cpu_list_entry(gpointer data, gpointer user_data)

		@@ -121,7 +121,7 @@ static void h8300_cpu_set_irq(void *opaque, int no, int request)
121	121
122	122	if (irq) {
123	123	cpu->env.req_irq = irq;
124		- cpu->env.req_ipl = (request >> 8) & 0x03;
	124	+ cpu->env.req_pri = (request >> 8) & 0x03;
125	125	cpu_interrupt(cs, CPU_INTERRUPT_HARD);
126	126	} else {
127	127	cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);

		@@ -138,7 +138,7 @@ static void h8300_cpu_init(Object *obj)
138	138	{
139	139	CPUState *cs = CPU(obj);
140	140	H8300CPU *cpu = H8300CPU(obj);
141		- CPURXState *env = &cpu->env;
	141	+ CPUH8300State *env = &cpu->env;
142	142
143	143	cs->env_ptr = env;
144	144	qdev_init_gpio_in(DEVICE(cpu), h8300_cpu_set_irq, 1);

		@@ -208,6 +208,8 @@ type_init(rxcpu_register_types)
208	208
209	209	static uint32_t extable[64];
210	210
	211	+#define IRAMTOP 0xffbf20
	212	+
211	213	void h8300_load_image(H8300CPU cpu, const char filename,
212	214	uint32_t start, uint32_t size)
213	215	{

--- a/target/h8300/cpu.h

+++ b/target/h8300/cpu.h

		@@ -24,14 +24,14 @@
24	24	#include "hw/registerfields.h"
25	25	#include "qom/cpu.h"
26	26
27		-#define TYPE_RXCPU "h8300cpu"
	27	+#define TYPE_H8300CPU "h8300cpu"
28	28
29		-#define RXCPU_CLASS(klass) \
30		- OBJECT_CLASS_CHECK(RXCPUClass, (klass), TYPE_RXCPU)
31		-#define RXCPU(obj) \
32		- OBJECT_CHECK(RXCPU, (obj), TYPE_RXCPU)
33		-#define RXCPU_GET_CLASS(obj) \
34		- OBJECT_GET_CLASS(RXCPUClass, (obj), TYPE_RXCPU)
	29	+#define H8300CPU_CLASS(klass) \
	30	+ OBJECT_CLASS_CHECK(H8300CPUClass, (klass), TYPE_H8300CPU)
	31	+#define H8300CPU(obj) \
	32	+ OBJECT_CHECK(H8300CPU, (obj), TYPE_H8300CPU)
	33	+#define H8300CPU_GET_CLASS(obj) \
	34	+ OBJECT_GET_CLASS(H8300CPUClass, (obj), TYPE_H8300CPU)
35	35
36	36	/*
37	37	* H8300CPUClass:

		@@ -62,15 +62,23 @@ typedef struct H8300CPUClass {
62	62
63	63	/* CCR define */
64	64	REG8(CCR, 0)
65		-FIELD(PSW, C, 0, 1)
66		-FIELD(PSW, V, 1, 1)
67		-FIELD(PSW, Z, 2, 1)
68		-FIELD(PSW, N, 3, 1)
69		-FIELD(PSW, U, 4, 1)
70		-FIELD(PSW, H, 5, 1)
71		-FIELD(PSW, UI, 6, 1)
72		-FIELD(PSW, I, 7, 4)
73		-
	65	+FIELD(CCR, C, 0, 1)
	66	+FIELD(CCR, V, 1, 1)
	67	+FIELD(CCR, Z, 2, 1)
	68	+FIELD(CCR, N, 3, 1)
	69	+FIELD(CCR, U, 4, 1)
	70	+FIELD(CCR, H, 5, 1)
	71	+FIELD(CCR, UI, 6, 1)
	72	+FIELD(CCR, I, 7, 1)
	73	+
	74	+/* SYSCR */
	75	+REG8(SYSCR, 0)
	76	+FIELD(SYSCR, RAME, 0, 1)
	77	+FIELD(SYSCR, SSOE, 1, 1)
	78	+FIELD(SYSCR, NMIEG, 2, 1)
	79	+FIELD(SYSCR, UE, 3, 1)
	80	+FIELD(SYSCR, STS, 4, 3)
	81	+FIELD(SYSCR, SSBY, 7, 1)
74	82
75	83	#define NB_MMU_MODES 1
76	84	#define MMU_MODE0_SUFFIX _all

		@@ -82,14 +90,14 @@ enum {
82	90	typedef struct CPUH8300State {
83	91	/* CPU registers */
84	92	uint32_t regs[NUM_REGS]; /* general registers */
85		- uint32_t psw_c; /* O bit of status register */
86		- uint32_t psw_v; /* S bit of status register */
87		- uint32_t psw_z; /* Z bit of status register */
88		- uint32_t psw_n; /* C bit of status register */
89		- uint32_t psw_u;
90		- uint32_t psw_h;
91		- uint32_t psw_ui;
92		- uint32_t psw_i;
	93	+ uint32_t ccr_c; /* C bit of status register */
	94	+ uint32_t ccr_v; /* V bit of status register */
	95	+ uint32_t ccr_z; /* Z bit of status register */
	96	+ uint32_t ccr_n; /* N bit of status register */
	97	+ uint32_t ccr_u;
	98	+ uint32_t ccr_h;
	99	+ uint32_t ccr_ui;
	100	+ uint32_t ccr_i;
93	101	uint32_t pc; /* program counter */
94	102
95	103	/* Fields up to this point are cleared by a CPU reset */

		@@ -98,9 +106,9 @@ typedef struct CPUH8300State {
98	106	/* Internal use */
99	107	uint32_t in_sleep;
100	108	uint32_t req_irq; /* Requested interrupt no (hard) */
101		- uint32_t req_ipl; /* Requested interrupt level */
102	109	uint32_t ack_irq; /* execute irq */
103		- uint32_t ack_ipl; /* execute ipl */
	110	+ uint32_t req_pri;
	111	+ uint8_t syscr;
104	112	qemu_irq ack; /* Interrupt acknowledge */
105	113
106	114	CPU_COMMON

		@@ -112,7 +120,7 @@ typedef struct CPUH8300State {
112	120	*
113	121	* A H8300 CPU
114	122	*/
115		-struct H830CPU {
	123	+struct H8300CPU {
116	124	/< private >/
117	125	CPUState parent_obj;
118	126	/< public >/

		@@ -131,8 +139,8 @@ static inline H8300CPU h8300_env_get_cpu(CPUH8300State env)
131	139
132	140	#define ENV_OFFSET offsetof(H8300CPU, env)
133	141
134		-#define RX_CPU_TYPE_SUFFIX "-" TYPE_H8300CPU
135		-#define RX_CPU_TYPE_NAME(model) model H8300_CPU_TYPE_SUFFIX
	142	+#define H8300_CPU_TYPE_SUFFIX "-" TYPE_H8300CPU
	143	+#define H8300_CPU_TYPE_NAME(model) model H8300_CPU_TYPE_SUFFIX
136	144	#define CPU_RESOLVING_TYPE TYPE_H8300CPU
137	145
138	146	void h8300_cpu_do_interrupt(CPUState *cpu);

		@@ -147,9 +155,9 @@ int cpu_h8300_signal_handler(int host_signum, void *pinfo,
147	155	void *puc);
148	156
149	157	void h8300_cpu_list(void);
150		-void h8300_load_image(RXCPU cpu, const char filename,
	158	+void h8300_load_image(H8300CPU cpu, const char filename,
151	159	uint32_t start, uint32_t size);
152		-void h8300_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte);
	160	+void h8300_cpu_unpack_ccr(CPUH8300State *env, uint32_t psw);
153	161
154	162	#define cpu_signal_handler cpu_h8300_signal_handler
155	163	#define cpu_list h8300_cpu_list

		@@ -160,7 +168,7 @@ void h8300_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte);
160	168
161	169	#define H8300_CPU_IRQ 0
162	170
163		-static inline void cpu_get_tb_cpu_state(CPURXState env, target_ulong pc,
	171	+static inline void cpu_get_tb_cpu_state(CPUH8300State env, target_ulong pc,
164	172	target_ulong cs_base, uint32_t flags)
165	173	{
166	174	*pc = env->pc;

		@@ -168,12 +176,12 @@ static inline void cpu_get_tb_cpu_state(CPURXState env, target_ulong pc,
168	176	*flags = 0;
169	177	}
170	178
171		-static inline int cpu_mmu_index(CPURXState *env, bool ifetch)
	179	+static inline int cpu_mmu_index(CPUH8300State *env, bool ifetch)
172	180	{
173	181	return 0;
174	182	}
175	183
176		-static inline uint32_t h8300_cpu_pack_ccr(CPURXState *env)
	184	+static inline uint32_t h8300_cpu_pack_ccr(CPUH8300State *env)
177	185	{
178	186	uint32_t ccr = 0;
179	187	ccr = FIELD_DP32(ccr, CCR, I, env->ccr_i);

--- a/target/h8300/helper.h

+++ b/target/h8300/helper.h

		@@ -9,3 +9,5 @@ DEF_HELPER_FLAGS_2(daa, TCG_CALL_NO_WG, i32, env, i32)
9	9	DEF_HELPER_FLAGS_2(das, TCG_CALL_NO_WG, i32, env, i32)
10	10	DEF_HELPER_1(eepmovb, void, env)
11	11	DEF_HELPER_1(eepmovw, void, env)
	12	+DEF_HELPER_1(sim_write, void, env)
	13	+DEF_HELPER_1(dump, void, i32)

--- a/target/h8300/insns.decode

+++ b/target/h8300/insns.decode

		@@ -18,10 +18,12 @@
18	18	#
19	19
20	20	&i imm
21		-&ri rd imm sz
	21	+&ri r imm sz
	22	+&rdi rd imm sz
	23	+&eri er imm
22	24	&rr rs rd sz
23	25	&ai abs imm
24		-&cd cc dsp
	26	+&cd cd dsp
25	27	&rn rd rn
26	28	&an abs rn
27	29	&r r sz

		@@ -34,47 +36,47 @@
34	36	%imm32 0:0 !function=imm32
35	37	%dsp16 0:0 !function=dsp16
36	38	%dsp24 0:0 !function=dsp24
	39	+%dsp24l 0:0 !function=dsp24l
37	40	%abs16 0:0 !function=abs16
38	41	%abs24 0:0 !function=abs24
39	42	%b10_er 0:0 !function=b10_er
40	43	%b10_ldst 0:0 !function=b10_ldst
41	44
42		-@b2_imm .... .... imm:8 &i
43		-@b2_r_imm .... rd:4 imm:8 &ri sz=0
	45	+@b2_imm .... .... imm:s8 &i
	46	+@b2_r_imm .... rd:4 imm:s8 &rdi sz=0
44	47	@b2_rs_rd .... .... rs:4 rd:4 &rr
45		-@b2_adds .... .... .... 0 rd:3 &ri sz=2
	48	+@b2_adds .... .... .... 0 rd:3 &rdi sz=2
46	49	@b2_ers_erd .... .... 1 rs:3 0 rd:3 &rr
47	50	@b2_er_r .... .... . er:3 r:4 &rrdsp
48		-@b2_bop_r .... .... . imm:3 rd:4 &ri sz=0
49		-@b2_bcc .... cc:4 dsp:s8 &cd
50		-@b2_idb .... .... .... rd:4 &ri
51		-@b2_idw .... .... .... rd:4 &ri
52		-@b2_idl .... .... .... 0 rd:3 &ri
	51	+@b2_bop_r .... .... . imm:3 r:4 &ri sz=0
	52	+@b2_bcc .... cd:4 dsp:s8 &cd
	53	+@b2_idb .... .... .... rd:4 &rdi
	54	+@b2_idw .... .... .... rd:4 &rdi
	55	+@b2_idl .... .... .... 0 rd:3 &rdi
53	56	@b2_r .... .... .... r:4 &r
54	57	@b2_rs_erd .... .... rs:4 0 rd:3 &rr
55	58	@b2_er .... .... .... 0 r:3 &r
56	59	@b2_r_abs .... r:4 abs:8 &rabs
57		-@b4_rd_imm .... .... .... rd:4 imm:16 &ri sz=1
	60	+@b4_rd_imm .... .... .... rd:4 imm:s16 &rdi sz=1
58	61	@b4_ers_erd .... .... .... .... .... .... . rs:3 0 rd:3 &rr sz=2
59	62	@b4_ers_erd_d .... .... .... .... .... .... . er:3 0 r:3 &rrdsp sz=2 dsp=0
60		-@b4_bop_m .... .... 0 rd:3 .... .... .... . imm:3 .... &ri sz=0
	63	+@b4_bop_m .... .... 0 er:3 .... .... .... . imm:3 .... &eri
61	64	@b4_bop_a .... .... abs:8 .... .... . imm:3 .... &ai
62		-@b4_bcc .... .... cc:4 .... dsp:s16 &cd
	65	+@b4_bcc .... .... cd:4 .... dsp:s16 &cd
63	66	@b4_rn_rd .... .... 0 rd:3 .... .... .... rn:4 .... &rn
64	67	@b4_rn_a .... .... abs:8 .... .... rn:4 .... &an
65	68	@b4_rs_rd .... .... .... .... .... .... rs:4 rd:4 &rr
66	69	@b4_rs_erd .... .... .... .... .... .... rs:4 0 rd:3 &rr
67	70	@b4_er .... .... .... .... .... .... . r:3 .... &rdsp dsp=0
68		-@b4_er_p .... .... .... .... .... .... .... 0 r:3 &r
69	71	@b4_r_abs .... .... .... r:4 abs:16 &rabs
70		-@b6_rd_imm .... .... .... 0 rd:3 &ri imm=%imm32 sz=2
	72	+@b6_rd_imm .... .... .... 0 rd:3 &rdi imm=%imm32 sz=2
71	73	@b6_er16 .... .... .... .... .... .... . r:3 .... &rdsp dsp=%dsp16
72	74	@b6_abs16 .... .... .... .... .... .... .... .... &abs abs=%abs16
73	75	@b6_r_abs .... .... .... r:4 &rabs abs=%abs24
74	76	@b6_er_abs .... .... .... .... .... .... .... 0 r:3 &rabs abs=%abs16
75	77	@b6_ers_erd .... .... .... .... .... .... . er:3 0 r:3 &rrdsp sz=2 dsp=%dsp16
76	78	@b10_er24 .... .... .... .... .... .... 0 r:3 .... &ldstccr ldst=%b10_ldst dsp=%dsp24
77		-@b10_ers_erd .... .... .... .... .... .... . er:3 0000 &rrdsp sz=2 r=%b10_er dsp=%dsp24
	79	+@b10_ers_erd .... .... .... .... .... .... . er:3 0000 &rrdsp sz=2 r=%b10_er dsp=%dsp24l
78	80	@b8_abs24 .... .... .... .... .... .... .... .... &abs abs=%abs24
79	81	@b8_er_r .... .... 0 er:3 .... .... .... .... r:4 &rrdsp
80	82	@b8_er_abs .... .... .... .... .... .... .... 0 r:3 &rabs abs=%abs24

		@@ -137,7 +139,7 @@ BAND_a 0111 1110 .... .... 0111 0110 0 ... 0000 @b4_bop_a
137	139	# BLT d:8
138	140	# BGT d:8
139	141	# BLE d:8
140		-Bcc_B 0100 .... .... .... @b2_bcc
	142	+Bcc 0100 .... .... .... @b2_bcc
141	143	# BRA d:16
142	144	# BRN d:16
143	145	# BHI d:16

		@@ -154,7 +156,7 @@ Bcc_B 0100 .... .... .... @b2_bcc
154	156	# BLT d:16
155	157	# BGT d:16
156	158	# BLE d:16
157		-Bcc_W 0101 1000 .... 0000 .... .... .... .... @b4_bcc
	159	+Bcc 0101 1000 .... 0000 .... .... .... .... @b4_bcc
158	160	# BCLR #xx:3,Rd
159	161	BCLR_ir 0111 0010 0... .... @b2_bop_r
160	162	# BCLR #xx:3,@ERd

		@@ -234,9 +236,9 @@ BSET_rm 0111 1101 .... 0000 0110 0000 .... 0000 @b4_rn_rd
234	236	# BSET Rn,@aa:8
235	237	BSET_ra 0111 1111 .... .... 0110 0000 .... 0000 @b4_rn_a
236	238	# BSR d:8
237		-BSR_b 0101 0101 dsp:8
	239	+BSR 0101 0101 dsp:s8
238	240	# BSR d:16
239		-BSR_w 0101 1100 0000 0000 dsp:16
	241	+BSR 0101 1100 0000 0000 dsp:s16
240	242	# BST #xx:3,Rd
241	243	BST_r 0110 0111 0 ... .... @b2_bop_r
242	244	# BST #xx:3,@ERd

		@@ -297,7 +299,7 @@ DIVXU 0101 0001 .... .... @b2_rs_rd sz=0
297	299	DIVXU 0101 0011 .... .... @b2_rs_erd sz=1
298	300	# EEPMOV.B
299	301	EEPMOV_B 0111 1011 0101 1100 0101 1001 1000 1111
300		-EEPMOV.W 0111 1011 1101 0100 0101 1001 1000 1111
	302	+EEPMOV_W 0111 1011 1101 0100 0101 1001 1000 1111
301	303	# EXTS.W Rd
302	304	EXTS 0001 0111 1101 .... @b2_r sz=1
303	305	# EXTS.L ERd

		@@ -392,7 +394,7 @@ MOV_mpr 0110 1101 0 ... .... @b2_er_r dsp=0 sz=1
392	394	# MOV.W @aa:16,Rd
393	395	MOV_ar 0110 1011 0000 .... .... .... .... .... @b4_r_abs sz=1 a=16
394	396	# MOV.W @aa:24,Rd
395		-MOV_ar 0001 1011 0010 .... @b6_r_abs sz=0 a=24
	397	+MOV_ar 0110 1011 0010 .... @b6_r_abs sz=0 a=24
396	398	# MOV.W Rs,@ERd
397	399	MOV_rm 0110 1001 1 ... .... @b2_er_r dsp=0 sz=1
398	400	# MOV.W Rs,@(d:16,ERd)

		@@ -434,7 +436,7 @@ MOV_ra 0000 0001 0000 0000 0110 1011 1000 .... @b6_er_abs sz=2 a=16
434	436	# MOV.L ERs,@aa:24
435	437	MOV_ra 0000 0001 0000 0000 0110 1011 1010 .... @b8_er_abs sz=2 a=24
436	438	# MOVFPE @aa:16,Rd
437		-MOVVPE 0110 1010 0100 .... .... .... .... .... @b4_r_abs a=16 sz=0
	439	+MOVFPE 0110 1010 0100 .... .... .... .... .... @b4_r_abs a=16 sz=0
438	440	# MOVTPE Rs,@aa:16
439	441	MOVTPE 0110 1010 1100 .... .... .... .... .... @b4_r_abs a=16 sz=0
440	442	# MULXS.B Rs,Rd

		@@ -476,55 +478,55 @@ ORC 0000 0100 .... .... @b2_imm
476	478	# ROTL.B Rd
477	479	ROTL 0001 0010 1000 .... @b2_r sz=0
478	480	# ROTL.W Rd
479		-ROTL_W 0001 0010 1001 .... @b2_r sz=1
	481	+ROTL 0001 0010 1001 .... @b2_r sz=1
480	482	# ROTL.L ERd
481		-ROTL_L 0001 0010 1011 .... @b2_er sz=2
	483	+ROTL 0001 0010 1011 .... @b2_er sz=2
482	484	# ROTR.B Rd
483		-ROTR_B 0001 0011 1000 .... @b2_r sz=0
	485	+ROTR 0001 0011 1000 .... @b2_r sz=0
484	486	# ROTR.W Rd
485		-ROTR_W 0001 0011 1001 .... @b2_r sz=1
	487	+ROTR 0001 0011 1001 .... @b2_r sz=1
486	488	# ROTR.L ERd
487		-ROTR_L 0001 0011 1011 .... @b2_er sz=2
	489	+ROTR 0001 0011 1011 .... @b2_er sz=2
488	490	# ROTXL.B Rd
489		-ROTXL_B 0001 0010 0000 .... @b2_r sz=0
	491	+ROTXL 0001 0010 0000 .... @b2_r sz=0
490	492	# ROTXL.W Rd
491		-ROTXL_W 0001 0010 0001 .... @b2_r sz=1
	493	+ROTXL 0001 0010 0001 .... @b2_r sz=1
492	494	# ROTXL.L ERd
493		-ROTXL_L 0001 0010 0011 .... @b2_er sz=2
	495	+ROTXL 0001 0010 0011 .... @b2_er sz=2
494	496	# ROTXR.B Rd
495		-ROTXR_B 0001 0011 0000 .... @b2_r sz=0
	497	+ROTXR 0001 0011 0000 .... @b2_r sz=0
496	498	# ROTXR.W Rd
497		-ROTXR_W 0001 0011 0001 .... @b2_r sz=1
	499	+ROTXR 0001 0011 0001 .... @b2_r sz=1
498	500	# ROTXR.L ERd
499		-ROTXWR_L 0001 0011 0011 .... @b2_er sz=2
	501	+ROTXR 0001 0011 0011 .... @b2_er sz=2
500	502	# RTE
501	503	RTE 0101 0110 0111 0000
502	504	# RTS
503	505	RTS 0101 0100 0111 0000
504	506	# SHAL.B Rd
505		-SHAL_B 0001 0000 1000 .... @b2_r sz=0
	507	+SHAL 0001 0000 1000 .... @b2_r sz=0
506	508	# SHAL.W Rd
507		-SHAL_W 0001 0000 1001 .... @b2_r sz=1
	509	+SHAL 0001 0000 1001 .... @b2_r sz=1
508	510	# SHAL.L ERd
509		-SHAL_L 0001 0000 1011 .... @b2_er sz=2
	511	+SHAL 0001 0000 1011 .... @b2_er sz=2
510	512	# SHAR.B Rd
511		-SHAR_B 0001 0001 1000 .... @b2_r sz=0
	513	+SHAR 0001 0001 1000 .... @b2_r sz=0
512	514	# SHAR.W Rd
513		-SHAR_W 0001 0001 1001 .... @b2_r sz=1
	515	+SHAR 0001 0001 1001 .... @b2_r sz=1
514	516	# SHAR.L ERd
515		-SHAR_L 0001 0001 1011 .... @b2_er sz=2
	517	+SHAR 0001 0001 1011 .... @b2_er sz=2
516	518	# SHLL.B Rd
517		-SHLL_B 0001 0000 0000 .... @b2_r sz=0
	519	+SHLL 0001 0000 0000 .... @b2_r sz=0
518	520	# SHLL.W Rd
519		-SHLL_W 0001 0000 0001 .... @b2_r sz=1
	521	+SHLL 0001 0000 0001 .... @b2_r sz=1
520	522	# SHLL.L ERd
521		-SHLL_L 0001 0000 0011 .... @b2_er sz=2
	523	+SHLL 0001 0000 0011 .... @b2_er sz=2
522	524	# SHLR.B Rd
523		-SHLR_B 0001 0001 0000 .... @b2_r sz=0
	525	+SHLR 0001 0001 0000 .... @b2_r sz=0
524	526	# SHLR.W Rd
525		-SHLR_W 0001 0001 0001 .... @b2_r sz=1
	527	+SHLR 0001 0001 0001 .... @b2_r sz=1
526	528	# SHLR.L ERd
527		-SHLR_L 0001 0001 0011 .... @b2_er sz=2
	529	+SHLR 0001 0001 0011 .... @b2_er sz=2
528	530	# SLEEP
529	531	SLEEP 0000 0001 1000 0000
530	532	# STC CCR,Rd

		@@ -552,9 +554,9 @@ SUB_r 0001 1010 .... .... @b2_ers_erd sz=2
552	554	# SUBS #1,ERd
553	555	SUBS 0001 1011 0000 .... @b2_adds imm=1
554	556	# SUBS #2,ERd
555		-SUBS_2 0001 1011 1000 .... @b2_adds imm=2
	557	+SUBS 0001 1011 1000 .... @b2_adds imm=2
556	558	# SUBS #4,ERd
557		-SUBS_4 0001 1011 1001 .... @b2_adds imm=4
	559	+SUBS 0001 1011 1001 .... @b2_adds imm=4
558	560	# SUBX #xx:8,Rd
559	561	SUBX_i 1011 .... .... .... @b2_r_imm
560	562	# SUBX Rs,Rd

--- a/target/h8300/op_helper.c

+++ b/target/h8300/op_helper.c

		@@ -24,9 +24,6 @@
24	24	#include "exec/cpu_ldst.h"
25	25	#include "fpu/softfloat.h"
26	26
27		-static inline void QEMU_NORETURN raise_exception(CPURXState *env, int index,
28		- uintptr_t retaddr);
29		-
30	27	void helper_set_ccr(CPUH8300State *env, uint32_t ccr)
31	28	{
32	29	h8300_cpu_unpack_ccr(env, ccr);

		@@ -34,7 +31,7 @@ void helper_set_ccr(CPUH8300State *env, uint32_t ccr)
34	31
35	32	uint32_t helper_get_ccr(CPUH8300State *env)
36	33	{
37		- return h8300_cpu_pack_psw(env);
	34	+ return h8300_cpu_pack_ccr(env);
38	35	}
39	36
40	37	/* div */

		@@ -122,11 +119,11 @@ uint32_t helper_das(CPUH8300State *env, uint32_t num)
122	119	}
123	120	}
124	121
125		-static void helper_eepmovb(CPUH8300State *env)
	122	+void helper_eepmovb(CPUH8300State *env)
126	123	{
127	124	int cnt;
128	125	uint8_t tmp;
129		- cnt = extracr32(cpu_regs[4], 0, 8);
	126	+ cnt = extract32(env->regs[4], 0, 8);
130	127	while(cnt > 0) {
131	128	tmp = cpu_ldub_data_ra(env, env->regs[5], GETPC());
132	129	cpu_stb_data_ra(env, env->regs[6], tmp, GETPC());

		@@ -134,14 +131,14 @@ static void helper_eepmovb(CPUH8300State *env)
134	131	env->regs[6]++;
135	132	cnt--;
136	133	}
137		- cpu_regs[4] = deposit32(cpu_regs[4], cnt, 0, 8);
	134	+ env->regs[4] = deposit32(env->regs[4], cnt, 0, 8);
138	135	}
139	136
140		-static void helper_eepmovw(CPUH8300State *env)
	137	+void helper_eepmovw(CPUH8300State *env)
141	138	{
142	139	int cnt;
143	140	uint8_t tmp;
144		- cnt = extracr32(cpu_regs[4], 0, 16);
	141	+ cnt = extract32(env->regs[4], 0, 16);
145	142	while(cnt > 0) {
146	143	tmp = cpu_ldub_data_ra(env, env->regs[5], GETPC());
147	144	cpu_stb_data_ra(env, env->regs[6], tmp, GETPC());

		@@ -149,7 +146,29 @@ static void helper_eepmovw(CPUH8300State *env)
149	146	env->regs[6]++;
150	147	cnt--;
151	148	}
152		- cpu_regs[4] = deposit32(cpu_regs[4], cnt, 0, 16);
	149	+ env->regs[4] = deposit32(env->regs[4], cnt, 0, 16);
	150	+}
	151	+
	152	+void helper_sim_write(CPUH8300State *env)
	153	+{
	154	+ int fd, size, i;
	155	+ char buf, p;
	156	+ uint32_t addr;
	157	+
	158	+ fd = env->regs[0];
	159	+ addr = env->regs[1];
	160	+ size = env->regs[2];
	161	+ buf = malloc(size);
	162	+ for (p = buf, i = 0; i < size; i++) {
	163	+ *p++ = cpu_ldub_data_ra(env, addr++, GETPC());
	164	+ }
	165	+ write(fd, buf, size);
	166	+ free(buf);
	167	+}
	168	+
	169	+void helper_dump(uint32_t val)
	170	+{
	171	+ printf("val: %08x\n", val);
153	172	}
154	173
155	174	/* exception */

--- a/target/h8300/translate.c

+++ b/target/h8300/translate.c

		@@ -31,7 +31,7 @@
31	31
32	32	typedef struct DisasContext {
33	33	DisasContextBase base;
34		- CPURXState *env;
	34	+ CPUH8300State *env;
35	35	uint32_t pc;
36	36	} DisasContext;
37	37

		@@ -48,8 +48,8 @@ typedef struct DisasCompare {
48	48
49	49	/* global register indexes */
50	50	static TCGv cpu_regs[8];
51		-static TCGv cpu_psw_c, cpu_psw_v, cpu_psw_z, cpu_psw_n;
52		-static TCGv cpu_psw_u, cpu_psw_h, cpu_psw_ui, cpu_psw_i;
	51	+static TCGv cpu_ccr_c, cpu_ccr_v, cpu_ccr_z, cpu_ccr_n;
	52	+static TCGv cpu_ccr_u, cpu_ccr_h, cpu_ccr_ui, cpu_ccr_i;
53	53	static TCGv cpu_pc;
54	54
55	55	#define cpu_sp cpu_regs[7]

		@@ -69,17 +69,17 @@ static uint32_t decode_load_bytes(DisasContext *ctx, uint32_t insn,
69	69
70	70	static uint32_t imm32(DisasContext *ctx, int dummy)
71	71	{
72		- CPURXState *env = ctx->env;
73		- addr = ctx->base.pc_next;
	72	+ CPUH8300State *env = ctx->env;
	73	+ uint32_t addr = ctx->base.pc_next;
74	74
75		- ctx->base.pc_next += 2;
	75	+ ctx->base.pc_next += 4;
76	76	return cpu_ldl_code(env, addr);
77	77	}
78	78
79	79	static uint32_t dsp16(DisasContext *ctx, int dummy)
80	80	{
81		- CPURXState *env = ctx->env;
82		- addr = ctx->base.pc_next;
	81	+ CPUH8300State *env = ctx->env;
	82	+ uint32_t addr = ctx->base.pc_next;
83	83
84	84	ctx->base.pc_next += 2;
85	85	return cpu_ldsw_code(env, addr);

		@@ -87,20 +87,32 @@ static uint32_t dsp16(DisasContext *ctx, int dummy)
87	87
88	88	static uint32_t dsp24(DisasContext *ctx, int dummy)
89	89	{
90		- CPURXState *env = ctx->env;
	90	+ CPUH8300State *env = ctx->env;
91	91	uint32_t dsp24;
92		- addr = ctx->pc + 6;
	92	+ uint32_t addr = ctx->pc + 4;
	93	+
	94	+ ctx->base.pc_next = ctx->pc + 8;
	95	+ dsp24 = cpu_ldl_code(env, addr);
	96	+ dsp24 = deposit32(dsp24, 16, 16, sextract32(dsp24, 16, 8));
	97	+ return dsp24;
	98	+}
	99	+
	100	+static uint32_t dsp24l(DisasContext *ctx, int dummy)
	101	+{
	102	+ CPUH8300State *env = ctx->env;
	103	+ uint32_t dsp24;
	104	+ uint32_t addr = ctx->pc + 6;
93	105
94	106	ctx->base.pc_next = ctx->pc + 10;
95	107	dsp24 = cpu_ldl_code(env, addr);
96		- dsp24 = deposit(dsp24, 16, 16, sextract32(dsp24, 16, 8));
	108	+ dsp24 = deposit32(dsp24, 16, 16, sextract32(dsp24, 16, 8));
97	109	return dsp24;
98	110	}
99	111
100	112	static uint32_t abs16(DisasContext *ctx, int dummy)
101	113	{
102		- CPURXState *env = ctx->env;
103		- addr = ctx->base.pc_next;
	114	+ CPUH8300State *env = ctx->env;
	115	+ uint32_t addr = ctx->base.pc_next;
104	116
105	117	ctx->base.pc_next += 2;
106	118	return cpu_ldsw_code(env, addr);

		@@ -108,8 +120,8 @@ static uint32_t abs16(DisasContext *ctx, int dummy)
108	120
109	121	static uint32_t abs24(DisasContext *ctx, int dummy)
110	122	{
111		- CPURXState *env = ctx->env;
112		- addr = ctx->base.pc_next;
	123	+ CPUH8300State *env = ctx->env;
	124	+ uint32_t addr = ctx->base.pc_next;
113	125
114	126	ctx->base.pc_next += 4;
115	127	return cpu_ldl_code(env, addr);

		@@ -117,20 +129,25 @@ static uint32_t abs24(DisasContext *ctx, int dummy)
117	129
118	130	static uint32_t b10_er(DisasContext *ctx, int dummy)
119	131	{
120		- CPURXState *env = ctx->env;
121		- addr = ctx->pc + 5;
	132	+ CPUH8300State *env = ctx->env;
	133	+ uint32_t addr = ctx->pc + 5;
122	134
123	135	return extract32(cpu_ldub_code(env, addr), 0, 3);
124	136	}
125	137
126	138	static uint32_t b10_ldst(DisasContext *ctx, int dummy)
127	139	{
128		- CPURXState *env = ctx->env;
129		- addr = ctx->pc + 5;
	140	+ CPUH8300State *env = ctx->env;
	141	+ uint32_t addr = ctx->pc + 5;
130	142
131	143	return extract32(cpu_ldub_code(env, addr), 4, 4);
132	144	}
133	145
	146	+static int dummy(uint32_t insn, int pos, int len)
	147	+{
	148	+ return 0;
	149	+}
	150	+
134	151	/* Include the auto-generated decoder. */
135	152	#include "decode.inc.c"
136	153

		@@ -139,11 +156,11 @@ void h8300_cpu_dump_state(CPUState cs, FILE f, int flags)
139	156	H8300CPU *cpu = H8300CPU(cs);
140	157	CPUH8300State *env = &cpu->env;
141	158	int i;
142		- uint32_t psw;
	159	+ uint32_t ccr;
143	160
144		- psw = h8300_cpu_pack_psw(env);
145		- qemu_fprintf(f, "pc=0x%08x psw=0x%02x\n",
146		- env->pc, psw);
	161	+ ccr = h8300_cpu_pack_ccr(env);
	162	+ qemu_fprintf(f, "pc=0x%08x ccr=0x%02x\n",
	163	+ env->pc, ccr);
147	164	for (i = 0; i < 8; i += 4) {
148	165	qemu_fprintf(f, "er%d=0x%08x er%d=0x%08x er%d=0x%08x er%d=0x%08x\n",
149	166	i, env->regs[i], i + 1, env->regs[i + 1],

		@@ -178,60 +195,60 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
178	195	}
179	196
180	197	/* generate QEMU condition */
181		-static void psw_cond(DisasCompare *dc, uint32_t cond)
	198	+static void ccr_cond(DisasCompare *dc, uint32_t cond)
182	199	{
183	200	tcg_debug_assert(cond < 16);
184	201	switch (cond) {
185	202	case 2: /* !(c \| z) */
186	203	case 3: /* c \| z */
187		- tcg_gen_setcondi_i32(TCG_COND_NE, dc->temp, cpu_psw_z, 0);
188		- tcg_gen_or_i32(dc->temp, dc->temp, cpu_psw_c);
	204	+ tcg_gen_setcondi_i32(TCG_COND_NE, dc->temp, cpu_ccr_z, 0);
	205	+ tcg_gen_or_i32(dc->temp, dc->temp, cpu_ccr_c);
189	206	dc->cond = (cond == 2) ? TCG_COND_EQ : TCG_COND_NE;
190	207	dc->value = dc->temp;
191	208	break;
192	209	case 4: /* !c */
193	210	dc->cond = TCG_COND_EQ;
194		- dc->value = cpu_psw_c;
	211	+ dc->value = cpu_ccr_c;
195	212	break;
196	213	case 5: /* c */
197	214	dc->cond = TCG_COND_NE;
198		- dc->value = cpu_psw_c;
	215	+ dc->value = cpu_ccr_c;
199	216	break;
200	217	case 6: /* !z */
201	218	dc->cond = TCG_COND_NE;
202		- dc->value = cpu_psw_z;
	219	+ dc->value = cpu_ccr_z;
203	220	break;
204	221	case 7: /* z */
205	222	dc->cond = TCG_COND_EQ;
206		- dc->value = cpu_psw_z;
	223	+ dc->value = cpu_ccr_z;
207	224	break;
208	225	case 8: /* !v */
209	226	dc->cond = TCG_COND_EQ;
210		- dc->value = cpu_psw_v;
	227	+ dc->value = cpu_ccr_v;
211	228	break;
212	229	case 9: /* v */
213	230	dc->cond = TCG_COND_NE;
214		- dc->value = cpu_psw_v;
	231	+ dc->value = cpu_ccr_v;
215	232	break;
216	233	case 10: /* !n */
217	234	dc->cond = TCG_COND_GE;
218		- dc->value = cpu_psw_s;
	235	+ dc->value = cpu_ccr_n;
219	236	break;
220	237	case 11: /* n */
221	238	dc->cond = TCG_COND_LT;
222		- dc->value = cpu_psw_s;
	239	+ dc->value = cpu_ccr_n;
223	240	break;
224	241	case 12: /* !(n^v) */
225	242	case 13: /* n^v */
226		- tcg_gen_xor_i32(dc->temp, cpu_psw_o, cpu_psw_s);
	243	+ tcg_gen_xor_i32(dc->temp, cpu_ccr_v, cpu_ccr_n);
227	244	dc->cond = (cond == 8) ? TCG_COND_GE : TCG_COND_LT;
228	245	dc->value = dc->temp;
229	246	break;
230	247	case 14: /* !((n^v) \| z) */
231	248	case 15: /* ((n^v) \| z) */
232		- tcg_gen_xor_i32(dc->temp, cpu_psw_v, cpu_psw_s);
	249	+ tcg_gen_xor_i32(dc->temp, cpu_ccr_v, cpu_ccr_n);
233	250	tcg_gen_sari_i32(dc->temp, dc->temp, 31);
234		- tcg_gen_andc_i32(dc->temp, cpu_psw_z, dc->temp);
	251	+ tcg_gen_andc_i32(dc->temp, cpu_ccr_z, dc->temp);
235	252	dc->cond = (cond == 10) ? TCG_COND_NE : TCG_COND_EQ;
236	253	dc->value = dc->temp;
237	254	break;

		@@ -240,41 +257,43 @@ static void psw_cond(DisasCompare *dc, uint32_t cond)
240	257
241	258	static inline void h8300_gen_reg_ldb(int rn, TCGv val)
242	259	{
243		- g_assert(a < 16);
	260	+ g_assert(rn < 16);
244	261	if (rn < 8) {
245		- tcg_gen_sextract32(val, cpu_regs[rn], 8, 8);
	262	+ tcg_gen_sextract_i32(val, cpu_regs[rn], 8, 8);
246	263	} else {
247		- tcg_gen_sextract32(val, cpu_regs[rn], 8, 8);
	264	+ tcg_gen_sextract_i32(val, cpu_regs[rn & 7], 0, 8);
248	265	}
249	266	}
250	267
251	268	static inline void h8300_gen_reg_stb(int rn, TCGv val)
252	269	{
253		- g_assert(a < 16);
	270	+ g_assert(rn < 16);
254	271	if (rn < 8) {
255		- tcg_gen_deposit32(cpu_regs[rn], 8, 8, val);
	272	+ tcg_gen_deposit_i32(cpu_regs[rn], cpu_regs[rn], val, 8, 8);
256	273	} else {
257		- tcg_gen_deposit32(cpu_regs[rn], 8, 8, val);
	274	+ rn &= 7;
	275	+ tcg_gen_deposit_i32(cpu_regs[rn], cpu_regs[rn], val, 0, 8);
258	276	}
259	277	}
260	278
261	279	static inline void h8300_gen_reg_ldw(int rn, TCGv val)
262	280	{
263		- g_assert(a < 16);
	281	+ g_assert(rn < 16);
264	282	if (rn < 8) {
265		- tcg_gen_sextract32(val, cpu_regs[rn], 0, 16);
	283	+ tcg_gen_sextract_i32(val, cpu_regs[rn], 0, 16);
266	284	} else {
267		- tcg_gen_sextract32(val, cpu_regs[rn], 16, 16);
	285	+ tcg_gen_sextract_i32(val, cpu_regs[rn & 7], 16, 16);
268	286	}
269	287	}
270	288
271	289	static inline void h8300_gen_reg_stw(int rn, TCGv val)
272	290	{
273		- g_assert(a < 16);
	291	+ g_assert(rn < 16);
274	292	if (rn < 8) {
275		- tcg_gen_deposit32(cpu_regs[rn], 0, 16, val);
	293	+ tcg_gen_deposit_i32(cpu_regs[rn], cpu_regs[rn], val, 0, 16);
276	294	} else {
277		- tcg_gen_deposit32(cpu_regs[rn], 16, 16, val);
	295	+ rn &= 7;
	296	+ tcg_gen_deposit_i32(cpu_regs[rn], cpu_regs[rn], val, 16, 16);
278	297	}
279	298	}
280	299

		@@ -287,18 +306,18 @@ static bool trans_MOV_i(DisasContext ctx, arg_MOV_i a)
287	306	TCGv imm = tcg_const_i32(a->imm);
288	307	switch(a->sz) {
289	308	case SZ_B:
290		- h8300_gen_reg_stb(a->r, imm);
	309	+ h8300_gen_reg_stb(a->rd, imm);
291	310	break;
292	311	case SZ_W:
293		- h8300_gen_reg_stw(a->r, imm);
	312	+ h8300_gen_reg_stw(a->rd, imm);
294	313	break;
295		- case SZ_W:
296		- tcg_gen_mov_i32(cpu_regs[a->r], imm);
	314	+ case SZ_L:
	315	+ tcg_gen_mov_i32(cpu_regs[a->rd], imm);
297	316	break;
298	317	}
299		- tcg_gen_mov_i32(cpu_psw_z, imm);
300		- tcg_gen_mov_i32(cpu_psw_n, imm);
301		- tcg_gen_movi_i32(cpu_psw_v, 0);
	318	+ tcg_gen_mov_i32(cpu_ccr_z, imm);
	319	+ tcg_gen_mov_i32(cpu_ccr_n, imm);
	320	+ tcg_gen_movi_i32(cpu_ccr_v, 0);
302	321	tcg_temp_free(imm);
303	322	return true;
304	323	}

		@@ -315,14 +334,14 @@ static bool trans_MOV_r(DisasContext ctx, arg_MOV_r a)
315	334	h8300_gen_reg_ldw(a->rs, temp);
316	335	h8300_gen_reg_stw(a->rd, temp);
317	336	break;
318		- case SZ_W:
	337	+ case SZ_L:
319	338	tcg_gen_mov_i32(cpu_regs[a->rd], cpu_regs[a->rs]);
320	339	tcg_gen_mov_i32(temp, cpu_regs[a->rs]);
321	340	break;
322	341	}
323		- tcg_gen_mov_i32(cpu_psw_z, temp);
324		- tcg_gen_mov_i32(cpu_psw_n, temp);
325		- tcg_gen_movi_i32(cpu_psw_v, 0);
	342	+ tcg_gen_mov_i32(cpu_ccr_z, temp);
	343	+ tcg_gen_mov_i32(cpu_ccr_n, temp);
	344	+ tcg_gen_movi_i32(cpu_ccr_v, 0);
326	345	tcg_temp_free(temp);
327	346	return true;
328	347	}

		@@ -339,15 +358,15 @@ static bool trans_MOV_mr(DisasContext ctx, arg_MOV_mr a)
339	358	h8300_gen_reg_stb(a->r, temp);
340	359	break;
341	360	case SZ_W:
342		- h8300_gen_reg_stw(a->rr, temp);
	361	+ h8300_gen_reg_stw(a->r, temp);
343	362	break;
344		- case SZ_W:
	363	+ case SZ_L:
345	364	tcg_gen_mov_i32(cpu_regs[a->r], temp);
346	365	break;
347	366	}
348		- tcg_gen_mov_i32(cpu_psw_z, temp);
349		- tcg_gen_mov_i32(cpu_psw_n, temp);
350		- tcg_gen_movi_i32(cpu_psw_v, 0);
	367	+ tcg_gen_mov_i32(cpu_ccr_z, temp);
	368	+ tcg_gen_mov_i32(cpu_ccr_n, temp);
	369	+ tcg_gen_movi_i32(cpu_ccr_v, 0);
351	370	tcg_temp_free(mem);
352	371	tcg_temp_free(temp);
353	372	return true;

		@@ -364,15 +383,15 @@ static bool trans_MOV_mpr(DisasContext ctx, arg_MOV_mr a)
364	383	h8300_gen_reg_stb(a->r, temp);
365	384	break;
366	385	case SZ_W:
367		- h8300_gen_reg_stw(a->rr, temp);
	386	+ h8300_gen_reg_stw(a->r, temp);
368	387	break;
369		- case SZ_W:
	388	+ case SZ_L:
370	389	tcg_gen_mov_i32(cpu_regs[a->r], temp);
371	390	break;
372	391	}
373		- tcg_gen_mov_i32(cpu_psw_z, temp);
374		- tcg_gen_mov_i32(cpu_psw_n, temp);
375		- tcg_gen_movi_i32(cpu_psw_v, 0);
	392	+ tcg_gen_mov_i32(cpu_ccr_z, temp);
	393	+ tcg_gen_mov_i32(cpu_ccr_n, temp);
	394	+ tcg_gen_movi_i32(cpu_ccr_v, 0);
376	395	tcg_temp_free(temp);
377	396	return true;
378	397	}

		@@ -397,15 +416,15 @@ static bool trans_MOV_ar(DisasContext ctx, arg_MOV_ar a)
397	416	h8300_gen_reg_stb(a->r, temp);
398	417	break;
399	418	case SZ_W:
400		- h8300_gen_reg_stw(a->rr, temp);
	419	+ h8300_gen_reg_stw(a->r, temp);
401	420	break;
402		- case SZ_W:
	421	+ case SZ_L:
403	422	tcg_gen_mov_i32(cpu_regs[a->r], temp);
404	423	break;
405	424	}
406		- tcg_gen_mov_i32(cpu_psw_z, temp);
407		- tcg_gen_mov_i32(cpu_psw_n, temp);
408		- tcg_gen_movi_i32(cpu_psw_v, 0);
	425	+ tcg_gen_mov_i32(cpu_ccr_z, temp);
	426	+ tcg_gen_mov_i32(cpu_ccr_n, temp);
	427	+ tcg_gen_movi_i32(cpu_ccr_v, 0);
409	428	tcg_temp_free(mem);
410	429	tcg_temp_free(temp);
411	430	return true;

		@@ -422,16 +441,16 @@ static bool trans_MOV_rm(DisasContext ctx, arg_MOV_mr a)
422	441	h8300_gen_reg_ldb(a->r, temp);
423	442	break;
424	443	case SZ_W:
425		- h8300_gen_reg_ldw(a->rr, temp);
	444	+ h8300_gen_reg_ldw(a->r, temp);
426	445	break;
427		- case SZ_W:
428		- tcg_gen_mov_i32(cpu_regs[a->r], temp);
	446	+ case SZ_L:
	447	+ tcg_gen_mov_i32(temp, cpu_regs[a->r]);
429	448	break;
430	449	}
431	450	tcg_gen_qemu_st_i32(temp, mem, 0, a->sz \| MO_SIGN \| MO_TE);
432		- tcg_gen_mov_i32(cpu_psw_z, temp);
433		- tcg_gen_mov_i32(cpu_psw_n, temp);
434		- tcg_gen_movi_i32(cpu_psw_v, 0);
	451	+ tcg_gen_mov_i32(cpu_ccr_z, temp);
	452	+ tcg_gen_mov_i32(cpu_ccr_n, temp);
	453	+ tcg_gen_movi_i32(cpu_ccr_v, 0);
435	454	tcg_temp_free(mem);
436	455	tcg_temp_free(temp);
437	456	return true;

		@@ -445,19 +464,19 @@ static bool trans_MOV_rmp(DisasContext ctx, arg_MOV_mr a)
445	464	tcg_gen_subi_i32(cpu_regs[a->er], cpu_regs[a->er], 1 << a->sz);
446	465	switch(a->sz) {
447	466	case SZ_B:
448		- h8300_gen_reg_stb(a->r, temp);
	467	+ h8300_gen_reg_ldb(a->r, temp);
449	468	break;
450	469	case SZ_W:
451		- h8300_gen_reg_stw(a->rr, temp);
	470	+ h8300_gen_reg_ldw(a->r, temp);
452	471	break;
453		- case SZ_W:
	472	+ case SZ_L:
454	473	tcg_gen_mov_i32(temp, cpu_regs[a->r]);
455	474	break;
456	475	}
457	476	tcg_gen_qemu_st_i32(temp, cpu_regs[a->er], 0, a->sz \| MO_SIGN \| MO_TE);
458		- tcg_gen_mov_i32(cpu_psw_z, temp);
459		- tcg_gen_mov_i32(cpu_psw_n, temp);
460		- tcg_gen_movi_i32(cpu_psw_v, 0);
	477	+ tcg_gen_mov_i32(cpu_ccr_z, temp);
	478	+ tcg_gen_mov_i32(cpu_ccr_n, temp);
	479	+ tcg_gen_movi_i32(cpu_ccr_v, 0);
461	480	tcg_temp_free(mem);
462	481	tcg_temp_free(temp);
463	482	return true;

		@@ -482,16 +501,16 @@ static bool trans_MOV_ra(DisasContext ctx, arg_MOV_ra a)
482	501	h8300_gen_reg_ldb(a->r, temp);
483	502	break;
484	503	case SZ_W:
485		- h8300_gen_reg_ldw(a->rr, temp);
	504	+ h8300_gen_reg_ldw(a->r, temp);
486	505	break;
487		- case SZ_W:
	506	+ case SZ_L:
488	507	tcg_gen_mov_i32(temp, cpu_regs[a->r]);
489	508	break;
490	509	}
491	510	tcg_gen_qemu_st_i32(temp, mem, 0, a->sz \| MO_SIGN \| MO_TE);
492		- tcg_gen_mov_i32(cpu_psw_z, temp);
493		- tcg_gen_mov_i32(cpu_psw_n, temp);
494		- tcg_gen_movi_i32(cpu_psw_v, 0);
	511	+ tcg_gen_mov_i32(cpu_ccr_z, temp);
	512	+ tcg_gen_mov_i32(cpu_ccr_n, temp);
	513	+ tcg_gen_movi_i32(cpu_ccr_v, 0);
495	514	tcg_temp_free(mem);
496	515	tcg_temp_free(temp);
497	516	return true;

		@@ -499,25 +518,29 @@ static bool trans_MOV_ra(DisasContext ctx, arg_MOV_ra a)
499	518
500	519	static bool trans_MOVFPE(DisasContext ctx, arg_MOVFPE a)
501	520	{
502		- TCGv mem;
	521	+ TCGv mem, temp;
503	522
504	523	a->abs = sextract32(a->abs, 0, 16) & 0x00ffffff;
505	524	mem = tcg_const_i32(a->abs);
506		- tcg_gen_qemu_ld_i32(temp, mem, 0, MO_B \| MO_SIGN \| MO_TE);
	525	+ temp = tcg_temp_new();
	526	+ tcg_gen_qemu_ld_i32(temp, mem, 0, MO_8 \| MO_SIGN \| MO_TE);
507	527	h8300_gen_reg_stb(a->r, temp);
508	528	tcg_temp_free(mem);
	529	+ tcg_temp_free(temp);
509	530	return true;
510	531	}
511	532
512	533	static bool trans_MOVTPE(DisasContext ctx, arg_MOVTPE a)
513	534	{
514		- TCGv mem;
	535	+ TCGv mem, temp;
515	536
516	537	a->abs = sextract32(a->abs, 0, 16) & 0x00ffffff;
517	538	mem = tcg_const_i32(a->abs);
	539	+ temp = tcg_temp_new();
518	540	h8300_gen_reg_ldb(a->r, temp);
519		- tcg_gen_qemu_st_i32(temp, mem, 0, MO_B \| MO_SIGN \| MO_TE);
	541	+ tcg_gen_qemu_st_i32(temp, mem, 0, MO_8 \| MO_SIGN \| MO_TE);
520	542	tcg_temp_free(mem);
	543	+ tcg_temp_free(temp);
521	544	return true;
522	545	}
523	546

		@@ -559,36 +582,36 @@ static inline void h8300_add(int sz, TCGv ret, TCGv arg1, TCGv arg2, bool c)
559	582	z = tcg_const_i32(0);
560	583
561	584	if (c) {
562		- tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, arg1, z, arg2, z);
	585	+ tcg_gen_add2_i32(cpu_ccr_n, cpu_ccr_c, arg1, z, arg2, z);
563	586	} else {
564		- tcg_gen_add_i32(cpu_psw_s, arg1, arg2);
	587	+ tcg_gen_add_i32(cpu_ccr_n, arg1, arg2);
565	588	}
566		- tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
567		- tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1);
	589	+ tcg_gen_mov_i32(cpu_ccr_z, cpu_ccr_n);
	590	+ tcg_gen_xor_i32(cpu_ccr_v, cpu_ccr_n, arg1);
568	591	switch(sz) {
569	592	case SZ_B:
570		- tcg_gen_ext8s(cpu_psw_s, cpu_psw_s);
	593	+ tcg_gen_ext8s_i32(cpu_ccr_n, cpu_ccr_n);
571	594	if (c) {
572		- tcg_gen_extract_i32(cpu_psw_c, cpu_psw_o, 8, 1);
	595	+ tcg_gen_extract_i32(cpu_ccr_c, cpu_ccr_v, 8, 1);
573	596	}
574		- tcg_gen_extract_i32(cpu_psw_h, cpu_psw_o, 4, 1);
	597	+ tcg_gen_extract_i32(cpu_ccr_h, cpu_ccr_v, 4, 1);
575	598	break;
576	599	case SZ_W:
577		- tcg_gen_ext16s(cpu_psw_s, cpu_psw_s);
	600	+ tcg_gen_ext16s_i32(cpu_ccr_n, cpu_ccr_n);
578	601	if (c) {
579		- tcg_gen_extract_i32(cpu_psw_c, cpu_psw_o, 16, 1);
	602	+ tcg_gen_extract_i32(cpu_ccr_c, cpu_ccr_v, 16, 1);
580	603	}
581		- tcg_gen_extract_i32(cpu_psw_h, cpu_psw_o, 12, 1);
	604	+ tcg_gen_extract_i32(cpu_ccr_h, cpu_ccr_v, 12, 1);
582	605	break;
583	606	case SZ_L:
584		- tcg_gen_extract_i32(cpu_psw_h, cpu_psw_o, 28, 1);
	607	+ tcg_gen_extract_i32(cpu_ccr_h, cpu_ccr_v, 28, 1);
585	608	break;
586	609	default:
587	610	g_assert_not_reached();
588	611	}
589	612	tcg_gen_xor_i32(z, arg1, arg2);
590		- tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, z);
591		- tcg_gen_mov_i32(ret, cpu_psw_s);
	613	+ tcg_gen_andc_i32(cpu_ccr_v, cpu_ccr_v, z);
	614	+ tcg_gen_mov_i32(ret, cpu_ccr_n);
592	615	tcg_temp_free(z);
593	616	}
594	617

		@@ -597,56 +620,56 @@ static inline void h8300_addx(TCGv ret, TCGv arg1, TCGv arg2)
597	620	TCGv z;
598	621	z = tcg_const_i32(0);
599	622
600		- tcg_gen_add_i32(cpu_psw_s, arg1, cpu_psw_c);
601		- tcg_gen_add_i32(cpu_psw_s, cpu_psw_s, arg2);
602		- tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
603		- tcg_gen_ext8s(cpu_psw_s, cpu_psw_s);
604		- tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1);
605		- tcg_gen_extract_i32(cpu_psw_h, cpu_psw_o, 4, 1);
606		- tcg_gen_extract_i32(cpu_psw_c, cpu_psw_o, 8, 1);
	623	+ tcg_gen_add_i32(cpu_ccr_n, arg1, cpu_ccr_c);
	624	+ tcg_gen_add_i32(cpu_ccr_n, cpu_ccr_n, arg2);
	625	+ tcg_gen_mov_i32(cpu_ccr_z, cpu_ccr_n);
	626	+ tcg_gen_ext8s_i32(cpu_ccr_n, cpu_ccr_n);
	627	+ tcg_gen_xor_i32(cpu_ccr_v, cpu_ccr_n, arg1);
	628	+ tcg_gen_extract_i32(cpu_ccr_h, cpu_ccr_v, 4, 1);
	629	+ tcg_gen_extract_i32(cpu_ccr_c, cpu_ccr_v, 8, 1);
607	630	tcg_gen_xor_i32(z, arg1, arg2);
608		- tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, z);
609		- tcg_gen_mov_i32(ret, cpu_psw_s);
	631	+ tcg_gen_andc_i32(cpu_ccr_v, cpu_ccr_v, z);
	632	+ tcg_gen_mov_i32(ret, cpu_ccr_n);
610	633	tcg_temp_free(z);
611	634	}
612	635
613	636	static void h8300_sub(int sz, TCGv ret, TCGv arg1, TCGv arg2, bool c)
614	637	{
615	638	TCGv temp;
616		- tcg_gen_sub_i32(cpu_psw_s, arg1, arg2);
617		- tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
	639	+ tcg_gen_sub_i32(cpu_ccr_n, arg1, arg2);
	640	+ tcg_gen_mov_i32(cpu_ccr_z, cpu_ccr_n);
618	641	if (c) {
619		- tcg_gen_setcond_i32(TCG_COND_GEU, cpu_psw_c, arg1, arg2);
	642	+ tcg_gen_setcond_i32(TCG_COND_GEU, cpu_ccr_c, arg1, arg2);
620	643	}
621		- tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1);
	644	+ tcg_gen_xor_i32(cpu_ccr_v, cpu_ccr_n, arg1);
622	645	switch(sz) {
623	646	case SZ_B:
624		- tcg_gen_ext8s(cpu_psw_s, cpu_psw_s);
	647	+ tcg_gen_ext8s_i32(cpu_ccr_n, cpu_ccr_n);
625	648	if (c) {
626		- tcg_gen_extract_i32(cpu_psw_c, cpu_psw_o, 8, 1);
	649	+ tcg_gen_extract_i32(cpu_ccr_c, cpu_ccr_v, 8, 1);
627	650	}
628		- tcg_gen_extract_i32(cpu_psw_h, cpu_psw_o, 4, 1);
	651	+ tcg_gen_extract_i32(cpu_ccr_h, cpu_ccr_v, 4, 1);
629	652	break;
630	653	case SZ_W:
631		- tcg_gen_ext16s(cpu_psw_s, cpu_psw_s);
	654	+ tcg_gen_ext16s_i32(cpu_ccr_n, cpu_ccr_n);
632	655	if (c) {
633		- tcg_gen_extract_i32(cpu_psw_c, cpu_psw_o, 16, 1);
	656	+ tcg_gen_extract_i32(cpu_ccr_c, cpu_ccr_v, 16, 1);
634	657	}
635		- tcg_gen_extract_i32(cpu_psw_h, cpu_psw_o, 12, 1);
	658	+ tcg_gen_extract_i32(cpu_ccr_h, cpu_ccr_v, 12, 1);
636	659	break;
637	660	case SZ_L:
638		- tcg_gen_extract_i32(cpu_psw_h, cpu_psw_o, 28, 1);
	661	+ tcg_gen_extract_i32(cpu_ccr_h, cpu_ccr_v, 28, 1);
639	662	break;
640	663	default:
641	664	g_assert_not_reached();
642	665	}
643	666	temp = tcg_temp_new_i32();
644	667	tcg_gen_xor_i32(temp, arg1, arg2);
645		- tcg_gen_and_i32(cpu_psw_o, cpu_psw_o, temp);
	668	+ tcg_gen_and_i32(cpu_ccr_v, cpu_ccr_v, temp);
646	669	tcg_temp_free_i32(temp);
647	670	/* CMP not requred return */
648	671	if (ret) {
649		- tcg_gen_mov_i32(ret, cpu_psw_s);
	672	+ tcg_gen_mov_i32(ret, cpu_ccr_n);
650	673	}
651	674	}
652	675

		@@ -654,12 +677,12 @@ static inline void h8300_ccr_adjust(int sz)
654	677	{
655	678	switch(sz) {
656	679	case SZ_B:
657		- tcg_gen_ext8s_i32(cpu_psw_s, cpu_psw_s);
658		- tcg_gen_ext8s_i32(cpu_psw_z, cpu_psw_z);
	680	+ tcg_gen_ext8s_i32(cpu_ccr_n, cpu_ccr_n);
	681	+ tcg_gen_ext8s_i32(cpu_ccr_z, cpu_ccr_z);
659	682	break;
660		- case SZ_B:
661		- tcg_gen_ext16s_i32(cpu_psw_s, cpu_psw_s);
662		- tcg_gen_ext16s_i32(cpu_psw_z, cpu_psw_z);
	683	+ case SZ_W:
	684	+ tcg_gen_ext16s_i32(cpu_ccr_n, cpu_ccr_n);
	685	+ tcg_gen_ext16s_i32(cpu_ccr_z, cpu_ccr_z);
663	686	break;
664	687	case SZ_L:
665	688	break;

		@@ -670,7 +693,7 @@ static inline void h8300_ccr_adjust(int sz)
670	693
671	694	static bool trans_ADD_i(DisasContext ctx, arg_ADD_i a)
672	695	{
673		- TCGv temp, imm;
	696	+ TCGv temp, imm, reg;
674	697	imm = tcg_const_i32(a->imm);
675	698	temp = tcg_temp_new();
676	699	reg = h8300_reg_ld(a->sz, a->rd, temp);

		@@ -681,7 +704,7 @@ static bool trans_ADD_i(DisasContext ctx, arg_ADD_i a)
681	704	return true;
682	705	}
683	706
684		-static bool trans_ADD_r(DisasContext ctx, arg_ADD_i a)
	707	+static bool trans_ADD_r(DisasContext ctx, arg_ADD_r a)
685	708	{
686	709	TCGv temp1, temp2, reg1, reg2;
687	710	temp1 = tcg_temp_new();

		@@ -698,22 +721,23 @@ static bool trans_ADD_r(DisasContext ctx, arg_ADD_i a)
698	721	static bool trans_ADDS(DisasContext ctx, arg_ADDS a)
699	722	{
700	723	tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], a->imm);
	724	+ return true;
701	725	}
702	726
703	727	static bool trans_ADDX_i(DisasContext ctx, arg_ADDX_i a)
704	728	{
705		- TCGv temp, reg, h;
	729	+ TCGv temp, reg, imm;
706	730	imm = tcg_const_i32(a->imm);
707	731	temp = tcg_temp_new();
708	732	reg = h8300_reg_ld(SZ_B, a->rd, temp);
709		- h8300_addx(a->sz, reg, reg, imm);
	733	+ h8300_addx(reg, reg, imm);
710	734	h8300_reg_st(SZ_B, a->rd, temp);
711	735	tcg_temp_free(temp);
712	736	tcg_temp_free(imm);
713	737	return true;
714	738	}
715	739
716		-static bool trans_ADDX_r(DisasContext ctx, arg_ADDX_i a)
	740	+static bool trans_ADDX_r(DisasContext ctx, arg_ADDX_r a)
717	741	{
718	742	TCGv temp1, temp2, reg1, reg2;
719	743	temp1 = tcg_temp_new();

		@@ -729,7 +753,7 @@ static bool trans_ADDX_r(DisasContext ctx, arg_ADDX_i a)
729	753
730	754	static bool trans_SUB_i(DisasContext ctx, arg_SUB_i a)
731	755	{
732		- TCGv temp, reg, h;
	756	+ TCGv temp, reg, imm;
733	757	imm = tcg_const_i32(a->imm);
734	758	temp = tcg_temp_new();
735	759	reg = h8300_reg_ld(a->sz, a->rd, temp);

		@@ -740,7 +764,7 @@ static bool trans_SUB_i(DisasContext ctx, arg_SUB_i a)
740	764	return true;
741	765	}
742	766
743		-static bool trans_SUB_r(DisasContext ctx, arg_SUB_i a)
	767	+static bool trans_SUB_r(DisasContext ctx, arg_SUB_r a)
744	768	{
745	769	TCGv temp1, temp2, reg1, reg2;
746	770	temp1 = tcg_temp_new();

		@@ -757,30 +781,32 @@ static bool trans_SUB_r(DisasContext ctx, arg_SUB_i a)
757	781	static bool trans_SUBS(DisasContext ctx, arg_SUBS a)
758	782	{
759	783	tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], a->imm);
	784	+ return true;
760	785	}
761	786
762		-static bool trans_SUBX_i(DisasContext ctx, arg_SUB_i a)
	787	+static bool trans_SUBX_i(DisasContext ctx, arg_SUBX_i a)
763	788	{
764		- TCGv temp, reg, h;
	789	+ TCGv temp, reg, imm;
765	790	temp = tcg_temp_new();
	791	+ imm = tcg_temp_new();
766	792	reg = h8300_reg_ld(SZ_B, a->rd, temp);
767		- tcg_gen_addi_i32(imm, psw_c, a->imm);
768		- h8300_sub(SZ_B, reg, reg, imm);
	793	+ tcg_gen_addi_i32(imm, cpu_ccr_c, a->imm);
	794	+ h8300_sub(SZ_B, reg, reg, imm, true);
769	795	h8300_reg_st(SZ_B, a->rd, temp);
770	796	tcg_temp_free(temp);
771	797	tcg_temp_free(imm);
772	798	return true;
773	799	}
774	800
775		-static bool trans_SUBX_r(DisasContext ctx, arg_SUB_i a)
	801	+static bool trans_SUBX_r(DisasContext ctx, arg_SUBX_r a)
776	802	{
777	803	TCGv temp1, temp2, reg1, reg2;
778	804	temp1 = tcg_temp_new();
779	805	temp2 = tcg_temp_new();
780	806	reg1 = h8300_reg_ld(SZ_B, a->rd, temp1);
781	807	reg2 = h8300_reg_ld(SZ_B, a->rs, temp2);
782		- tcg_gen_add_i32(reg2, reg2, 1);
783		- h8300_sub(SZ_B, reg1, reg1, reg2);
	808	+ tcg_gen_add_i32(reg2, reg2, cpu_ccr_c);
	809	+ h8300_sub(SZ_B, reg1, reg1, reg2, true);
784	810	h8300_reg_st(SZ_B, a->rd, reg1);
785	811	tcg_temp_free(temp1);
786	812	tcg_temp_free(temp2);

		@@ -789,7 +815,7 @@ static bool trans_SUBX_r(DisasContext ctx, arg_SUB_i a)
789	815
790	816	static bool trans_CMP_i(DisasContext ctx, arg_CMP_i a)
791	817	{
792		- TCGv temp, reg, h;
	818	+ TCGv temp, reg, imm;
793	819	imm = tcg_const_i32(a->imm);
794	820	temp = tcg_temp_new();
795	821	reg = h8300_reg_ld(a->sz, a->rd, temp);

		@@ -799,7 +825,7 @@ static bool trans_CMP_i(DisasContext ctx, arg_CMP_i a)
799	825	return true;
800	826	}
801	827
802		-static bool trans_CMP_r(DisasContext ctx, arg_CMP_i a)
	828	+static bool trans_CMP_r(DisasContext ctx, arg_CMP_r a)
803	829	{
804	830	TCGv temp1, temp2, reg1, reg2;
805	831	temp1 = tcg_temp_new();

		@@ -814,7 +840,7 @@ static bool trans_CMP_r(DisasContext ctx, arg_CMP_i a)
814	840
815	841	static bool trans_INC(DisasContext ctx, arg_INC a)
816	842	{
817		- TCGv temp, imm;
	843	+ TCGv temp, imm, reg;
818	844	imm = tcg_const_i32(a->imm);
819	845	temp = tcg_temp_new();
820	846	reg = h8300_reg_ld(a->sz, a->rd, temp);

		@@ -827,7 +853,7 @@ static bool trans_INC(DisasContext ctx, arg_INC a)
827	853
828	854	static bool trans_DEC(DisasContext ctx, arg_DEC a)
829	855	{
830		- TCGv temp, imm;
	856	+ TCGv temp, imm, reg;
831	857	imm = tcg_const_i32(a->imm);
832	858	temp = tcg_temp_new();
833	859	reg = h8300_reg_ld(a->sz, a->rd, temp);

		@@ -842,9 +868,9 @@ static bool trans_DAA(DisasContext ctx, arg_DAA a)
842	868	{
843	869	TCGv temp;
844	870	temp = tcg_temp_new();
845		- h8300_reg_ld(SZ_B, a->rd, temp);
	871	+ h8300_reg_ld(SZ_B, a->r, temp);
846	872	gen_helper_daa(temp, cpu_env, temp);
847		- h8300_reg_st(SZ_B, a->rd, temp);
	873	+ h8300_reg_st(SZ_B, a->r, temp);
848	874	return true;
849	875	}
850	876

		@@ -852,9 +878,9 @@ static bool trans_DAS(DisasContext ctx, arg_DAS a)
852	878	{
853	879	TCGv temp;
854	880	temp = tcg_temp_new();
855		- h8300_reg_ld(SZ_B, a->rd, temp);
	881	+ h8300_reg_ld(SZ_B, a->r, temp);
856	882	gen_helper_das(temp, cpu_env, temp);
857		- h8300_reg_st(SZ_B, a->rd, temp);
	883	+ h8300_reg_st(SZ_B, a->r, temp);
858	884	return true;
859	885	}
860	886

		@@ -867,18 +893,18 @@ static bool trans_MULXU(DisasContext ctx, arg_MULXU a)
867	893	reg2 = h8300_reg_ld(a->sz, a->rs, temp2);
868	894	switch(a->sz) {
869	895	case SZ_B:
870		- tcg_gen_ext8u(reg1, reg1);
871		- tcg_gen_ext8u(reg2, reg2);
	896	+ tcg_gen_ext8u_i32(reg1, reg1);
	897	+ tcg_gen_ext8u_i32(reg2, reg2);
872	898	break;
873	899	case SZ_W:
874		- tcg_gen_ext16u(reg1, reg1);
875		- tcg_gen_ext16u(reg2, reg2);
	900	+ tcg_gen_ext16u_i32(reg1, reg1);
	901	+ tcg_gen_ext16u_i32(reg2, reg2);
876	902	break;
877	903	default:
878	904	g_assert_not_reached();
879	905	}
880	906	tcg_gen_mul_i32(reg1, reg1, reg2);
881		- h8300_reg_st(a->sz + 1, reg1);
	907	+ h8300_reg_st(a->sz + 1, a->rd, reg1);
882	908	tcg_temp_free(temp1);
883	909	tcg_temp_free(temp2);
884	910	return true;

		@@ -892,7 +918,7 @@ static bool trans_MULXS(DisasContext ctx, arg_MULXU a)
892	918	reg1 = h8300_reg_ld(a->sz + 1, a->rd, temp1);
893	919	reg2 = h8300_reg_ld(a->sz, a->rs, temp2);
894	920	tcg_gen_mul_i32(reg1, reg1, reg2);
895		- h8300_reg_st(a->sz + 1, reg1);
	921	+ h8300_reg_st(a->sz + 1, a->rd, reg1);
896	922	tcg_temp_free(temp1);
897	923	tcg_temp_free(temp2);
898	924	return true;

		@@ -907,20 +933,20 @@ static bool trans_DIVXU(DisasContext ctx, arg_DIVXU a)
907	933	reg2 = h8300_reg_ld(a->sz, a->rs, temp2);
908	934	switch(a->sz) {
909	935	case SZ_B:
910		- tcg_gen_ext8u(reg1, reg1);
911		- tcg_gen_ext8u(reg2, reg2);
	936	+ tcg_gen_ext8u_i32(reg1, reg1);
	937	+ tcg_gen_ext8u_i32(reg2, reg2);
912	938	break;
913	939	case SZ_W:
914		- tcg_gen_ext16u(reg1, reg1);
915		- tcg_gen_ext16u(reg2, reg2);
	940	+ tcg_gen_ext16u_i32(reg1, reg1);
	941	+ tcg_gen_ext16u_i32(reg2, reg2);
916	942	break;
917	943	default:
918	944	g_assert_not_reached();
919	945	}
920		- gen_helper_divu(reg1, reg1, reg2);
	946	+ gen_helper_divu(reg1, cpu_env, reg1, reg2);
921	947	tcg_gen_mov_i32(cpu_ccr_z, reg1);
922	948	tcg_gen_mov_i32(cpu_ccr_n, reg1);
923		- h8300_reg_st(a->sz + 1, reg1);
	949	+ h8300_reg_st(a->sz + 1, a->rd, reg1);
924	950	tcg_temp_free(temp1);
925	951	tcg_temp_free(temp2);
926	952	return true;

		@@ -933,10 +959,10 @@ static bool trans_DIVXS(DisasContext ctx, arg_DIVXU a)
933	959	temp2 = tcg_temp_new();
934	960	reg1 = h8300_reg_ld(a->sz + 1, a->rd, temp1);
935	961	reg2 = h8300_reg_ld(a->sz, a->rs, temp2);
936		- gen_helper_divu(reg1, reg1, reg2);
	962	+ gen_helper_divu(reg1, cpu_env, reg1, reg2);
937	963	tcg_gen_mov_i32(cpu_ccr_z, reg1);
938	964	tcg_gen_mov_i32(cpu_ccr_n, reg1);
939		- h8300_reg_st(a->sz + 1, reg1);
	965	+ h8300_reg_st(a->sz + 1, a->rd, reg1);
940	966	tcg_temp_free(temp1);
941	967	tcg_temp_free(temp2);
942	968	return true;

		@@ -947,16 +973,16 @@ static bool trans_NEG(DisasContext ctx, arg_NEG a)
947	973	TCGv temp, reg;
948	974	uint32_t s;
949	975	temp = tcg_temp_new();
950		- reg = h8300_reg_ld(a->sz, a->rd, temp);
	976	+ reg = h8300_reg_ld(a->sz, a->r, temp);
951	977	s = 8 * (1 << a->sz) - 1;
952	978	s = 1 << s;
953		- tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_o, reg, s);
	979	+ tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_ccr_v, reg, s);
954	980	tcg_gen_neg_i32(reg, reg);
955		- tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_c, reg, 0);
956		- tcg_gen_mov_i32(cpu_psw_z, reg);
957		- tcg_gen_mov_i32(cpu_psw_s, reg);
958		- h8300_ccr_adjist(a->sz);
959		- h8300_reg_st(a->sz, reg);
	981	+ tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_ccr_c, reg, 0);
	982	+ tcg_gen_mov_i32(cpu_ccr_z, reg);
	983	+ tcg_gen_mov_i32(cpu_ccr_n, reg);
	984	+ h8300_ccr_adjust(a->sz);
	985	+ h8300_reg_st(a->sz, a->r, reg);
960	986	tcg_temp_free(temp);
961	987	return true;
962	988	}

		@@ -965,7 +991,7 @@ static bool trans_EXTU(DisasContext ctx, arg_EXTU a)
965	991	{
966	992	TCGv temp, reg;
967	993	temp = tcg_temp_new();
968		- reg = h8300_reg_ld(a->sz - 1, a->rd, temp);
	994	+ reg = h8300_reg_ld(a->sz - 1, a->r, temp);
969	995	switch(a->sz) {
970	996	case SZ_W:
971	997	tcg_gen_ext8u_i32(reg, reg);

		@@ -973,12 +999,12 @@ static bool trans_EXTU(DisasContext ctx, arg_EXTU a)
973	999	case SZ_L:
974	1000	tcg_gen_ext16u_i32(reg, reg);
975	1001	break;
976		- defalut:
	1002	+ default:
977	1003	g_assert_not_reached();
978	1004	}
979	1005	h8300_reg_st(a->sz, a->r, reg);
980		- tcg_gen_mov_i32(cpu_psw_z, reg);
981		- tcg_gen_mov_i32(cpu_psw_s, reg);
	1006	+ tcg_gen_mov_i32(cpu_ccr_z, reg);
	1007	+ tcg_gen_mov_i32(cpu_ccr_n, reg);
982	1008	tcg_gen_movi_i32(cpu_ccr_v, 0);
983	1009	tcg_temp_free(temp);
984	1010	return true;

		@@ -990,9 +1016,9 @@ static bool trans_EXTS(DisasContext ctx, arg_EXTU a)
990	1016	temp = tcg_temp_new();
991	1017	reg = h8300_reg_ld(a->sz - 1, a->r, temp);
992	1018	h8300_reg_st(a->sz, a->r, reg);
993		- tcg_gen_mov_i32(cpu_psw_z, reg);
994		- tcg_gen_mov_i32(cpu_psw_s, reg);
995		- h8300_ccr_adjist(a->sz);
	1019	+ tcg_gen_mov_i32(cpu_ccr_z, reg);
	1020	+ tcg_gen_mov_i32(cpu_ccr_n, reg);
	1021	+ h8300_ccr_adjust(a->sz);
996	1022	tcg_gen_movi_i32(cpu_ccr_v, 0);
997	1023	tcg_temp_free(temp);
998	1024	return true;

		@@ -1002,12 +1028,12 @@ static bool trans_AND_i(DisasContext ctx, arg_AND_i a)
1002	1028	{
1003	1029	TCGv temp, reg;
1004	1030	temp = tcg_temp_new();
1005		- reg = h8300_reg_ld(a->sz - 1, a->r, temp);
	1031	+ reg = h8300_reg_ld(a->sz - 1, a->rd, temp);
1006	1032	tcg_gen_andi_i32(reg, reg, a->imm);
1007		- h8300_reg_st(a->sz, a->r, reg);
1008		- tcg_gen_mov_i32(cpu_psw_z, reg);
1009		- tcg_gen_mov_i32(cpu_psw_s, reg);
1010		- h8300_ccr_adjist(a->sz);
	1033	+ h8300_reg_st(a->sz, a->rd, reg);
	1034	+ tcg_gen_mov_i32(cpu_ccr_z, reg);
	1035	+ tcg_gen_mov_i32(cpu_ccr_n, reg);
	1036	+ h8300_ccr_adjust(a->sz);
1011	1037	tcg_gen_movi_i32(cpu_ccr_v, 0);
1012	1038	tcg_temp_free(temp);
1013	1039	return true;

		@@ -1022,9 +1048,9 @@ static bool trans_AND_r(DisasContext ctx, arg_AND_r a)
1022	1048	reg2 = h8300_reg_ld(a->sz, a->rs, temp2);
1023	1049	tcg_gen_and_i32(reg1, reg1, reg2);
1024	1050	h8300_reg_st(a->sz, a->rd, reg1);
1025		- tcg_gen_mov_i32(cpu_psw_z, reg1);
1026		- tcg_gen_mov_i32(cpu_psw_s, reg1);
1027		- h8300_ccr_adjist(a->sz);
	1051	+ tcg_gen_mov_i32(cpu_ccr_z, reg1);
	1052	+ tcg_gen_mov_i32(cpu_ccr_n, reg1);
	1053	+ h8300_ccr_adjust(a->sz);
1028	1054	tcg_gen_movi_i32(cpu_ccr_v, 0);
1029	1055	tcg_temp_free(temp1);
1030	1056	tcg_temp_free(temp2);

		@@ -1035,12 +1061,12 @@ static bool trans_OR_i(DisasContext ctx, arg_OR_i a)
1035	1061	{
1036	1062	TCGv temp, reg;
1037	1063	temp = tcg_temp_new();
1038		- reg = h8300_reg_ld(a->sz - 1, a->r, temp);
	1064	+ reg = h8300_reg_ld(a->sz - 1, a->rd, temp);
1039	1065	tcg_gen_ori_i32(reg, reg, a->imm);
1040		- h8300_reg_st(a->sz, a->r, reg);
1041		- tcg_gen_mov_i32(cpu_psw_z, reg);
1042		- tcg_gen_mov_i32(cpu_psw_s, reg);
1043		- h8300_ccr_adjist(a->sz);
	1066	+ h8300_reg_st(a->sz, a->rd, reg);
	1067	+ tcg_gen_mov_i32(cpu_ccr_z, reg);
	1068	+ tcg_gen_mov_i32(cpu_ccr_n, reg);
	1069	+ h8300_ccr_adjust(a->sz);
1044	1070	tcg_gen_movi_i32(cpu_ccr_v, 0);
1045	1071	tcg_temp_free(temp);
1046	1072	return true;

		@@ -1055,9 +1081,9 @@ static bool trans_OR_r(DisasContext ctx, arg_OR_r a)
1055	1081	reg2 = h8300_reg_ld(a->sz, a->rs, temp2);
1056	1082	tcg_gen_or_i32(reg1, reg1, reg2);
1057	1083	h8300_reg_st(a->sz, a->rd, reg1);
1058		- tcg_gen_mov_i32(cpu_psw_z, reg1);
1059		- tcg_gen_mov_i32(cpu_psw_s, reg1);
1060		- h8300_ccr_adjist(a->sz);
	1084	+ tcg_gen_mov_i32(cpu_ccr_z, reg1);
	1085	+ tcg_gen_mov_i32(cpu_ccr_n, reg1);
	1086	+ h8300_ccr_adjust(a->sz);
1061	1087	tcg_gen_movi_i32(cpu_ccr_v, 0);
1062	1088	tcg_temp_free(temp1);
1063	1089	tcg_temp_free(temp2);

		@@ -1068,12 +1094,12 @@ static bool trans_XOR_i(DisasContext ctx, arg_XOR_i a)
1068	1094	{
1069	1095	TCGv temp, reg;
1070	1096	temp = tcg_temp_new();
1071		- reg = h8300_reg_ld(a->sz - 1, a->r, temp);
	1097	+ reg = h8300_reg_ld(a->sz - 1, a->rd, temp);
1072	1098	tcg_gen_xori_i32(reg, reg, a->imm);
1073		- h8300_reg_st(a->sz, a->r, reg);
1074		- tcg_gen_mov_i32(cpu_psw_z, reg);
1075		- tcg_gen_mov_i32(cpu_psw_s, reg);
1076		- h8300_ccr_adjist(a->sz);
	1099	+ h8300_reg_st(a->sz, a->rd, reg);
	1100	+ tcg_gen_mov_i32(cpu_ccr_z, reg);
	1101	+ tcg_gen_mov_i32(cpu_ccr_n, reg);
	1102	+ h8300_ccr_adjust(a->sz);
1077	1103	tcg_gen_movi_i32(cpu_ccr_v, 0);
1078	1104	tcg_temp_free(temp);
1079	1105	return true;

		@@ -1088,30 +1114,27 @@ static bool trans_XOR_r(DisasContext ctx, arg_XOR_r a)
1088	1114	reg2 = h8300_reg_ld(a->sz, a->rs, temp2);
1089	1115	tcg_gen_xor_i32(reg1, reg1, reg2);
1090	1116	h8300_reg_st(a->sz, a->rd, reg1);
1091		- tcg_gen_mov_i32(cpu_psw_z, reg1);
1092		- tcg_gen_mov_i32(cpu_psw_s, reg1);
1093		- h8300_ccr_adjist(a->sz);
	1117	+ tcg_gen_mov_i32(cpu_ccr_z, reg1);
	1118	+ tcg_gen_mov_i32(cpu_ccr_n, reg1);
	1119	+ h8300_ccr_adjust(a->sz);
1094	1120	tcg_gen_movi_i32(cpu_ccr_v, 0);
1095	1121	tcg_temp_free(temp1);
1096	1122	tcg_temp_free(temp2);
1097	1123	return true;
1098	1124	}
1099	1125
1100		-static bool trans_NOT_r(DisasContext ctx, arg_NOT_r a)
	1126	+static bool trans_NOT(DisasContext ctx, arg_NOT a)
1101	1127	{
1102		- TCGv temp1, temp2, reg1, reg2;
1103		- temp1 = tcg_temp_new();
1104		- temp2 = tcg_temp_new();
1105		- reg1 = h8300_reg_ld(a->sz, a->rd, temp1);
1106		- reg2 = h8300_reg_ld(a->sz, a->rs, temp2);
1107		- tcg_gen_not_i32(reg1, reg1, reg2);
1108		- h8300_reg_st(a->sz, a->rd, reg1);
1109		- tcg_gen_mov_i32(cpu_psw_z, reg1);
1110		- tcg_gen_mov_i32(cpu_psw_s, reg1);
1111		- h8300_ccr_adjist(a->sz);
	1128	+ TCGv temp, reg;
	1129	+ temp = tcg_temp_new();
	1130	+ reg = h8300_reg_ld(a->sz, a->r, temp);
	1131	+ tcg_gen_not_i32(reg, reg);
	1132	+ h8300_reg_st(a->sz, a->r, reg);
	1133	+ tcg_gen_mov_i32(cpu_ccr_z, reg);
	1134	+ tcg_gen_mov_i32(cpu_ccr_n, reg);
	1135	+ h8300_ccr_adjust(a->sz);
1112	1136	tcg_gen_movi_i32(cpu_ccr_v, 0);
1113		- tcg_temp_free(temp1);
1114		- tcg_temp_free(temp2);
	1137	+ tcg_temp_free(temp);
1115	1138	return true;
1116	1139	}
1117	1140

		@@ -1120,16 +1143,16 @@ static bool trans_SHAL(DisasContext ctx, arg_SHAL a)
1120	1143	TCGv temp, reg;
1121	1144	int s;
1122	1145	temp = tcg_temp_new();
1123		- reg = h8300_reg_ld(a->sz, a->rd, temp);
	1146	+ reg = h8300_reg_ld(a->sz, a->r, temp);
1124	1147	s = 8 * (1 << a->sz) - 1 ;
1125		- tcg_gen_extract_i32(cpu_psw_c, reg, s, 1);
1126		- tcg_gen_shli_i32(cpu_psw_v, reg, 1);
1127		- tcg_gen_xor_i32(cpu_psw_v, cpu_psw_v, reg);
1128		- tcg_gen_extract_i32(cpu_psw_v, cpu_psw_v, s, 1);
1129		- h8300_reg_st(a->sz, a->rd, reg);
1130		- tcg_gen_mov_i32(cpu_psw_z, reg);
1131		- tcg_gen_mov_i32(cpu_psw_s, reg);
1132		- h8300_ccr_adjist(a->sz);
	1148	+ tcg_gen_extract_i32(cpu_ccr_c, reg, s, 1);
	1149	+ tcg_gen_shli_i32(cpu_ccr_v, reg, 1);
	1150	+ tcg_gen_xor_i32(cpu_ccr_v, cpu_ccr_v, reg);
	1151	+ tcg_gen_extract_i32(cpu_ccr_v, cpu_ccr_v, s, 1);
	1152	+ h8300_reg_st(a->sz, a->r, reg);
	1153	+ tcg_gen_mov_i32(cpu_ccr_z, reg);
	1154	+ tcg_gen_mov_i32(cpu_ccr_n, reg);
	1155	+ h8300_ccr_adjust(a->sz);
1133	1156	tcg_temp_free(temp);
1134	1157	return true;
1135	1158	}

		@@ -1139,17 +1162,17 @@ static bool trans_SHAR(DisasContext ctx, arg_SHAR a)
1139	1162	TCGv temp, reg;
1140	1163	int s;
1141	1164	temp = tcg_temp_new();
1142		- reg = h8300_reg_ld(a->sz, a->rd, temp);
	1165	+ reg = h8300_reg_ld(a->sz, a->r, temp);
1143	1166	s = 8 * (1 << a->sz) - 1 ;
1144		- tcg_gen_extract_i32(cpu_psw_c, reg, 0, 1);
1145		- tcg_gen_andi_i32(cpu_psw_v, reg, 1 << s);
	1167	+ tcg_gen_extract_i32(cpu_ccr_c, reg, 0, 1);
	1168	+ tcg_gen_andi_i32(cpu_ccr_v, reg, 1 << s);
1146	1169	tcg_gen_shri_i32(reg, reg, 1);
1147		- tcg_gen_or_i32(reg, reg, cpu_psw_v);
1148		- h8300_reg_st(a->sz, a->rd, reg);
1149		- tcg_gen_mov_i32(cpu_psw_z, reg);
1150		- tcg_gen_mov_i32(cpu_psw_s, reg);
1151		- tcg_gen_mov_i32(cpu_psw_v, 0);
1152		- h8300_ccr_adjist(a->sz);
	1170	+ tcg_gen_or_i32(reg, reg, cpu_ccr_v);
	1171	+ h8300_reg_st(a->sz, a->r, reg);
	1172	+ tcg_gen_mov_i32(cpu_ccr_z, reg);
	1173	+ tcg_gen_mov_i32(cpu_ccr_n, reg);
	1174	+ tcg_gen_mov_i32(cpu_ccr_v, 0);
	1175	+ h8300_ccr_adjust(a->sz);
1153	1176	tcg_temp_free(temp);
1154	1177	return true;
1155	1178	}

		@@ -1159,15 +1182,15 @@ static bool trans_SHLL(DisasContext ctx, arg_SHLL a)
1159	1182	TCGv temp, reg;
1160	1183	int s;
1161	1184	temp = tcg_temp_new();
1162		- reg = h8300_reg_ld(a->sz, a->rd, temp);
	1185	+ reg = h8300_reg_ld(a->sz, a->r, temp);
1163	1186	s = 8 * (1 << a->sz) - 1 ;
1164		- tcg_gen_extract_i32(cpu_psw_c, reg, s, 1);
	1187	+ tcg_gen_extract_i32(cpu_ccr_c, reg, s, 1);
1165	1188	tcg_gen_shli_i32(reg, reg, 1);
1166		- h8300_reg_st(a->sz, a->rd, reg);
1167		- tcg_gen_mov_i32(cpu_psw_z, reg);
1168		- tcg_gen_mov_i32(cpu_psw_s, reg);
1169		- h8300_ccr_adjist(a->sz);
1170		- tcg_gen_mov_i32(cpu_psw_v, 0);
	1189	+ h8300_reg_st(a->sz, a->r, reg);
	1190	+ tcg_gen_mov_i32(cpu_ccr_z, reg);
	1191	+ tcg_gen_mov_i32(cpu_ccr_n, reg);
	1192	+ h8300_ccr_adjust(a->sz);
	1193	+ tcg_gen_mov_i32(cpu_ccr_v, 0);
1171	1194	tcg_temp_free(temp);
1172	1195	return true;
1173	1196	}

		@@ -1175,17 +1198,15 @@ static bool trans_SHLL(DisasContext ctx, arg_SHLL a)
1175	1198	static bool trans_SHLR(DisasContext ctx, arg_SHLR a)
1176	1199	{
1177	1200	TCGv temp, reg;
1178		- int s;
1179	1201	temp = tcg_temp_new();
1180		- reg = h8300_reg_ld(a->sz, a->rd, temp);
1181		- s = 8 * (1 << a->sz) - 1 ;
1182		- tcg_gen_extract_i32(cpu_psw_c, reg, 0, 1);
	1202	+ reg = h8300_reg_ld(a->sz, a->r, temp);
	1203	+ tcg_gen_extract_i32(cpu_ccr_c, reg, 0, 1);
1183	1204	tcg_gen_shri_i32(reg, reg, 1);
1184		- h8300_reg_st(a->sz, a->rd, reg);
1185		- tcg_gen_mov_i32(cpu_psw_z, reg);
1186		- tcg_gen_mov_i32(cpu_psw_s, reg);
1187		- h8300_ccr_adjist(a->sz);
1188		- tcg_gen_mov_i32(cpu_psw_v, 0);
	1205	+ h8300_reg_st(a->sz, a->r, reg);
	1206	+ tcg_gen_mov_i32(cpu_ccr_z, reg);
	1207	+ tcg_gen_mov_i32(cpu_ccr_n, reg);
	1208	+ h8300_ccr_adjust(a->sz);
	1209	+ tcg_gen_mov_i32(cpu_ccr_v, 0);
1189	1210	tcg_temp_free(temp);
1190	1211	return true;
1191	1212	}

		@@ -1195,16 +1216,16 @@ static bool trans_ROTL(DisasContext ctx, arg_ROTL a)
1195	1216	TCGv temp, reg;
1196	1217	int s;
1197	1218	temp = tcg_temp_new();
1198		- reg = h8300_reg_ld(a->sz, a->rd, temp);
	1219	+ reg = h8300_reg_ld(a->sz, a->r, temp);
1199	1220	s = 8 * (1 << a->sz) - 1 ;
1200		- tcg_gen_extract_i32(cpu_psw_c, reg, s, 1);
	1221	+ tcg_gen_extract_i32(cpu_ccr_c, reg, s, 1);
1201	1222	tcg_gen_shli_i32(reg, reg, 1);
1202		- tcg_gen_or_i32(reg, reg, cpu_psw_c);
1203		- h8300_reg_st(a->sz, a->rd, reg);
1204		- tcg_gen_mov_i32(cpu_psw_z, reg);
1205		- tcg_gen_mov_i32(cpu_psw_s, reg);
1206		- h8300_ccr_adjist(a->sz);
1207		- tcg_gen_mov_i32(cpu_psw_v, 0);
	1223	+ tcg_gen_or_i32(reg, reg, cpu_ccr_c);
	1224	+ h8300_reg_st(a->sz, a->r, reg);
	1225	+ tcg_gen_mov_i32(cpu_ccr_z, reg);
	1226	+ tcg_gen_mov_i32(cpu_ccr_n, reg);
	1227	+ h8300_ccr_adjust(a->sz);
	1228	+ tcg_gen_mov_i32(cpu_ccr_v, 0);
1208	1229	tcg_temp_free(temp);
1209	1230	return true;
1210	1231	}

		@@ -1212,20 +1233,18 @@ static bool trans_ROTL(DisasContext ctx, arg_ROTL a)
1212	1233	static bool trans_ROTR(DisasContext ctx, arg_ROTR a)
1213	1234	{
1214	1235	TCGv temp, reg, c;
1215		- int s;
1216	1236	temp = tcg_temp_new();
1217	1237	c = tcg_temp_new();
1218		- reg = h8300_reg_ld(a->sz, a->rd, temp);
1219		- s = 8 * (1 << a->sz) - 1;
1220		- tcg_gen_extract_i32(cpu_psw_c, reg, 0, 1);
	1238	+ reg = h8300_reg_ld(a->sz, a->r, temp);
	1239	+ tcg_gen_shli_i32(c, cpu_ccr_c, (1 << a->sz) - 1);
	1240	+ tcg_gen_extract_i32(cpu_ccr_c, reg, 0, 1);
1221	1241	tcg_gen_shri_i32(reg, reg, 1);
1222		- tcg_gen_shli_i32(c, cpu_psw, (1 << a->sz) - 1);
1223	1242	tcg_gen_or_i32(reg, reg, c);
1224		- h8300_reg_st(a->sz, a->rd, reg);
1225		- tcg_gen_mov_i32(cpu_psw_z, reg);
1226		- tcg_gen_mov_i32(cpu_psw_s, reg);
1227		- h8300_ccr_adjist(a->sz);
1228		- tcg_gen_mov_i32(cpu_psw_v, 0);
	1243	+ h8300_reg_st(a->sz, a->r, reg);
	1244	+ tcg_gen_mov_i32(cpu_ccr_z, reg);
	1245	+ tcg_gen_mov_i32(cpu_ccr_n, reg);
	1246	+ h8300_ccr_adjust(a->sz);
	1247	+ tcg_gen_mov_i32(cpu_ccr_v, 0);
1229	1248	tcg_temp_free(temp);
1230	1249	tcg_temp_free(c);
1231	1250	return true;

		@@ -1237,17 +1256,17 @@ static bool trans_ROTXL(DisasContext ctx, arg_ROTXL a)
1237	1256	int s;
1238	1257	temp = tcg_temp_new();
1239	1258	c = tcg_temp_new();
1240		- reg = h8300_reg_ld(a->sz, a->rd, temp);
	1259	+ reg = h8300_reg_ld(a->sz, a->r, temp);
1241	1260	s = 8 * (1 << a->sz) - 1 ;
1242	1261	tcg_gen_extract_i32(c, reg, s, 1);
1243	1262	tcg_gen_shli_i32(reg, reg, 1);
1244		- tcg_gen_or_i32(reg, reg, cpu_psw_c);
1245		- tcg_gen_mov_i32(cpu_psw_c, c);
1246		- h8300_reg_st(a->sz, a->rd, reg);
1247		- tcg_gen_mov_i32(cpu_psw_z, reg);
1248		- tcg_gen_mov_i32(cpu_psw_s, reg);
1249		- h8300_ccr_adjist(a->sz);
1250		- tcg_gen_mov_i32(cpu_psw_v, 0);
	1263	+ tcg_gen_or_i32(reg, reg, cpu_ccr_c);
	1264	+ tcg_gen_mov_i32(cpu_ccr_c, c);
	1265	+ h8300_reg_st(a->sz, a->r, reg);
	1266	+ tcg_gen_mov_i32(cpu_ccr_z, reg);
	1267	+ tcg_gen_mov_i32(cpu_ccr_n, reg);
	1268	+ h8300_ccr_adjust(a->sz);
	1269	+ tcg_gen_mov_i32(cpu_ccr_v, 0);
1251	1270	tcg_temp_free(temp);
1252	1271	tcg_temp_free(c);
1253	1272	return true;

		@@ -1256,21 +1275,19 @@ static bool trans_ROTXL(DisasContext ctx, arg_ROTXL a)
1256	1275	static bool trans_ROTXR(DisasContext ctx, arg_ROTXR a)
1257	1276	{
1258	1277	TCGv temp, reg, c;
1259		- int s;
1260	1278	temp = tcg_temp_new();
1261	1279	c = tcg_temp_new();
1262		- reg = h8300_reg_ld(a->sz, a->rd, temp);
1263		- s = 8 * (1 << a->sz) - 1;
	1280	+ reg = h8300_reg_ld(a->sz, a->r, temp);
1264	1281	tcg_gen_extract_i32(c, reg, 0, 1);
1265	1282	tcg_gen_shri_i32(reg, reg, 1);
1266		- tcg_gen_shli_i32(cpu_psw_c, cpu_psw_c, (1 << a->sz) - 1);
1267		- tcg_gen_or_i32(reg, reg, cpu_psw_c);
1268		- h8300_reg_st(a->sz, a->rd, reg);
1269		- tcg_gen_mov_i32(cpu_psw_c, c);
1270		- tcg_gen_mov_i32(cpu_psw_z, reg);
1271		- tcg_gen_mov_i32(cpu_psw_s, reg);
1272		- h8300_ccr_adjist(a->sz);
1273		- tcg_gen_mov_i32(cpu_psw_v, 0);
	1283	+ tcg_gen_shli_i32(cpu_ccr_c, cpu_ccr_c, (1 << a->sz) - 1);
	1284	+ tcg_gen_or_i32(reg, reg, cpu_ccr_c);
	1285	+ h8300_reg_st(a->sz, a->r, reg);
	1286	+ tcg_gen_mov_i32(cpu_ccr_c, c);
	1287	+ tcg_gen_mov_i32(cpu_ccr_z, reg);
	1288	+ tcg_gen_mov_i32(cpu_ccr_n, reg);
	1289	+ h8300_ccr_adjust(a->sz);
	1290	+ tcg_gen_mov_i32(cpu_ccr_v, 0);
1274	1291	tcg_temp_free(temp);
1275	1292	tcg_temp_free(c);
1276	1293	return true;

		@@ -1282,9 +1299,9 @@ static bool trans_BAND_r(DisasContext ctx, arg_BAND_r a)
1282	1299	temp = tcg_temp_new();
1283	1300	mask = tcg_temp_new();
1284	1301	h8300_gen_reg_ldb(a->r, temp);
1285		- tcg_gen_shli_i32(mask, cpu_psw_c, a->imm);
	1302	+ tcg_gen_shli_i32(mask, cpu_ccr_c, a->imm);
1286	1303	tcg_gen_and_i32(mask, temp, mask);
1287		- tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, mask, 0);
	1304	+ tcg_gen_setcondi_i32(TCG_COND_NE, cpu_ccr_c, mask, 0);
1288	1305	tcg_temp_free(temp);
1289	1306	tcg_temp_free(mask);
1290	1307	return true;

		@@ -1295,10 +1312,10 @@ static bool trans_BAND_m(DisasContext ctx, arg_BAND_m a)
1295	1312	TCGv temp, mask;
1296	1313	temp = tcg_temp_new();
1297	1314	mask = tcg_temp_new();
1298		- tcg_gen_qemu_ld_i32(temp, cpu_regs[a->er], 0, MO_B \| MO_SIGN \| MO_TE);
1299		- tcg_gen_shli_i32(mask, cpu_psw_c, a->imm);
	1315	+ tcg_gen_qemu_ld_i32(temp, cpu_regs[a->er], 0, MO_8 \| MO_SIGN \| MO_TE);
	1316	+ tcg_gen_shli_i32(mask, cpu_ccr_c, a->imm);
1300	1317	tcg_gen_and_i32(mask, temp, mask);
1301		- tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, mask, 0);
	1318	+ tcg_gen_setcondi_i32(TCG_COND_NE, cpu_ccr_c, mask, 0);
1302	1319	tcg_temp_free(temp);
1303	1320	tcg_temp_free(mask);
1304	1321	return true;

		@@ -1310,10 +1327,10 @@ static bool trans_BAND_a(DisasContext ctx, arg_BAND_a a)
1310	1327	temp = tcg_temp_new();
1311	1328	mask = tcg_temp_new();
1312	1329	mem = tcg_const_i32(0xffff00 \| a->abs);
1313		- tcg_gen_qemu_ld_i32(temp, mem, 0, MO_B \| MO_SIGN \| MO_TE);
1314		- tcg_gen_shli_i32(mask, cpu_psw_c, a->imm);
	1330	+ tcg_gen_qemu_ld_i32(temp, mem, 0, MO_8 \| MO_SIGN \| MO_TE);
	1331	+ tcg_gen_shli_i32(mask, cpu_ccr_c, a->imm);
1315	1332	tcg_gen_and_i32(mask, temp, mask);
1316		- tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, mask, 0);
	1333	+ tcg_gen_setcondi_i32(TCG_COND_NE, cpu_ccr_c, mask, 0);
1317	1334	tcg_temp_free(temp);
1318	1335	tcg_temp_free(mask);
1319	1336	tcg_temp_free(mem);

		@@ -1327,9 +1344,9 @@ static bool trans_BIAND_r(DisasContext ctx, arg_BIAND_r a)
1327	1344	mask = tcg_temp_new();
1328	1345	h8300_gen_reg_ldb(a->r, temp);
1329	1346	tcg_gen_not_i32(temp, temp);
1330		- tcg_gen_shli_i32(mask, cpu_psw_c, a->imm);
	1347	+ tcg_gen_shli_i32(mask, cpu_ccr_c, a->imm);
1331	1348	tcg_gen_and_i32(mask, temp, mask);
1332		- tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, mask, 0);
	1349	+ tcg_gen_setcondi_i32(TCG_COND_NE, cpu_ccr_c, mask, 0);
1333	1350	tcg_temp_free(temp);
1334	1351	tcg_temp_free(mask);
1335	1352	return true;

		@@ -1340,11 +1357,11 @@ static bool trans_BIAND_m(DisasContext ctx, arg_BIAND_m a)
1340	1357	TCGv temp, mask;
1341	1358	temp = tcg_temp_new();
1342	1359	mask = tcg_temp_new();
1343		- tcg_gen_qemu_ld_i32(temp, cpu_regs[a->er], 0, MO_B \| MO_SIGN \| MO_TE);
	1360	+ tcg_gen_qemu_ld_i32(temp, cpu_regs[a->er], 0, MO_8 \| MO_SIGN \| MO_TE);
1344	1361	tcg_gen_not_i32(temp, temp);
1345		- tcg_gen_shli_i32(mask, cpu_psw_c, a->imm);
	1362	+ tcg_gen_shli_i32(mask, cpu_ccr_c, a->imm);
1346	1363	tcg_gen_and_i32(mask, temp, mask);
1347		- tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, mask, 0);
	1364	+ tcg_gen_setcondi_i32(TCG_COND_NE, cpu_ccr_c, mask, 0);
1348	1365	tcg_temp_free(temp);
1349	1366	tcg_temp_free(mask);
1350	1367	return true;

		@@ -1356,11 +1373,11 @@ static bool trans_BIAND_a(DisasContext ctx, arg_BIAND_a a)
1356	1373	temp = tcg_temp_new();
1357	1374	mask = tcg_temp_new();
1358	1375	mem = tcg_const_i32(0xffff00 \| a->abs);
1359		- tcg_gen_qemu_ld_i32(temp, mem, 0, MO_B \| MO_SIGN \| MO_TE);
	1376	+ tcg_gen_qemu_ld_i32(temp, mem, 0, MO_8 \| MO_SIGN \| MO_TE);
1360	1377	tcg_gen_not_i32(temp, temp);
1361		- tcg_gen_shli_i32(mask, cpu_psw_c, a->imm);
	1378	+ tcg_gen_shli_i32(mask, cpu_ccr_c, a->imm);
1362	1379	tcg_gen_and_i32(mask, temp, mask);
1363		- tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, mask, 0);
	1380	+ tcg_gen_setcondi_i32(TCG_COND_NE, cpu_ccr_c, mask, 0);
1364	1381	tcg_temp_free(temp);
1365	1382	tcg_temp_free(mask);
1366	1383	tcg_temp_free(mem);

		@@ -1373,30 +1390,30 @@ static bool trans_BILD_r(DisasContext ctx, arg_BILD_r a)
1373	1390	temp = tcg_temp_new();
1374	1391	h8300_gen_reg_ldb(a->r, temp);
1375	1392	tcg_gen_not_i32(temp, temp);
1376		- tcg_gen_extract_i32(cpu_psw_c, temp, a->imm, 1);
	1393	+ tcg_gen_extract_i32(cpu_ccr_c, temp, a->imm, 1);
1377	1394	tcg_temp_free(temp);
1378	1395	return true;
1379	1396	}
1380	1397
1381	1398	static bool trans_BILD_m(DisasContext ctx, arg_BILD_m a)
1382	1399	{
1383		- TCGv temp, mask;
	1400	+ TCGv temp;
1384	1401	temp = tcg_temp_new();
1385		- tcg_gen_qemu_ld_i32(temp, cpu_regs[a->er], 0, MO_B \| MO_SIGN \| MO_TE);
	1402	+ tcg_gen_qemu_ld_i32(temp, cpu_regs[a->er], 0, MO_8 \| MO_SIGN \| MO_TE);
1386	1403	tcg_gen_not_i32(temp, temp);
1387		- tcg_gen_extract_i32(cpu_psw_c, temp, a->imm, 1);
	1404	+ tcg_gen_extract_i32(cpu_ccr_c, temp, a->imm, 1);
1388	1405	tcg_temp_free(temp);
1389	1406	return true;
1390	1407	}
1391	1408
1392	1409	static bool trans_BILD_a(DisasContext ctx, arg_BILD_a a)
1393	1410	{
1394		- TCGv temp, mask, mem;
	1411	+ TCGv temp, mem;
1395	1412	temp = tcg_temp_new();
1396	1413	mem = tcg_const_i32(0xffff00 \| a->abs);
1397		- tcg_gen_qemu_ld_i32(temp, mem, 0, MO_B \| MO_SIGN \| MO_TE);
	1414	+ tcg_gen_qemu_ld_i32(temp, mem, 0, MO_8 \| MO_SIGN \| MO_TE);
1398	1415	tcg_gen_not_i32(temp, temp);
1399		- tcg_gen_extract_i32(cpu_psw_c, temp, a->imm, 1);
	1416	+ tcg_gen_extract_i32(cpu_ccr_c, temp, a->imm, 1);
1400	1417	tcg_temp_free(temp);
1401	1418	tcg_temp_free(mem);
1402	1419	return true;

		@@ -1410,9 +1427,9 @@ static bool trans_BIOR_r(DisasContext ctx, arg_BIOR_r a)
1410	1427	h8300_gen_reg_ldb(a->r, temp);
1411	1428	tcg_gen_not_i32(temp, temp);
1412	1429	tcg_gen_andi_i32(temp, temp, 1 << a->imm);
1413		- tcg_gen_shli_i32(mask, cpu_psw_c, a->imm);
	1430	+ tcg_gen_shli_i32(mask, cpu_ccr_c, a->imm);
1414	1431	tcg_gen_or_i32(mask, temp, mask);
1415		- tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, mask, 0);
	1432	+ tcg_gen_setcondi_i32(TCG_COND_NE, cpu_ccr_c, mask, 0);
1416	1433	tcg_temp_free(temp);
1417	1434	tcg_temp_free(mask);
1418	1435	return true;

		@@ -1423,12 +1440,12 @@ static bool trans_BIOR_m(DisasContext ctx, arg_BIOR_m a)
1423	1440	TCGv temp, mask;
1424	1441	temp = tcg_temp_new();
1425	1442	mask = tcg_temp_new();
1426		- tcg_gen_qemu_ld_i32(temp, cpu_regs[a->er], 0, MO_B \| MO_SIGN \| MO_TE);
	1443	+ tcg_gen_qemu_ld_i32(temp, cpu_regs[a->er], 0, MO_8 \| MO_SIGN \| MO_TE);
1427	1444	tcg_gen_not_i32(temp, temp);
1428	1445	tcg_gen_andi_i32(temp, temp, 1 << a->imm);
1429		- tcg_gen_shli_i32(mask, cpu_psw_c, a->imm);
	1446	+ tcg_gen_shli_i32(mask, cpu_ccr_c, a->imm);
1430	1447	tcg_gen_or_i32(mask, temp, mask);
1431		- tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, mask, 0);
	1448	+ tcg_gen_setcondi_i32(TCG_COND_NE, cpu_ccr_c, mask, 0);
1432	1449	tcg_temp_free(temp);
1433	1450	tcg_temp_free(mask);
1434	1451	return true;

		@@ -1440,12 +1457,12 @@ static bool trans_BIOR_a(DisasContext ctx, arg_BIOR_a a)
1440	1457	temp = tcg_temp_new();
1441	1458	mask = tcg_temp_new();
1442	1459	mem = tcg_const_i32(0xffff00 \| a->abs);
1443		- tcg_gen_qemu_ld_i32(temp, mem, 0, MO_B \| MO_SIGN \| MO_TE);
	1460	+ tcg_gen_qemu_ld_i32(temp, mem, 0, MO_8 \| MO_SIGN \| MO_TE);
1444	1461	tcg_gen_not_i32(temp, temp);
1445	1462	tcg_gen_andi_i32(temp, temp, 1 << a->imm);
1446		- tcg_gen_shli_i32(mask, cpu_psw_c, a->imm);
	1463	+ tcg_gen_shli_i32(mask, cpu_ccr_c, a->imm);
1447	1464	tcg_gen_or_i32(mask, temp, mask);
1448		- tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, mask, 0);
	1465	+ tcg_gen_setcondi_i32(TCG_COND_NE, cpu_ccr_c, mask, 0);
1449	1466	tcg_temp_free(temp);
1450	1467	tcg_temp_free(mask);
1451	1468	tcg_temp_free(mem);

		@@ -1459,7 +1476,7 @@ static bool trans_BIST_r(DisasContext ctx, arg_BIST_r a)
1459	1476	mask = tcg_temp_new();
1460	1477	h8300_gen_reg_ldb(a->r, temp);
1461	1478	tcg_gen_andi_i32(temp, temp, ~1 << a->imm);
1462		- tcg_gen_not_i32(mask, cpu_psw_c);
	1479	+ tcg_gen_not_i32(mask, cpu_ccr_c);
1463	1480	tcg_gen_shli_i32(mask, mask, a->imm);
1464	1481	tcg_gen_or_i32(temp, temp, mask);
1465	1482	h8300_gen_reg_stb(a->r, temp);

		@@ -1473,13 +1490,13 @@ static bool trans_BIST_m(DisasContext ctx, arg_BIST_m a)
1473	1490	TCGv temp, mask;
1474	1491	temp = tcg_temp_new();
1475	1492	mask = tcg_temp_new();
1476		- tcg_gen_qemu_ld_i32(temp, cpu_regs[a->er], 0, MO_B \| MO_SIGN \| MO_TE);
	1493	+ tcg_gen_qemu_ld_i32(temp, cpu_regs[a->er], 0, MO_8 \| MO_SIGN \| MO_TE);
1477	1494	tcg_gen_not_i32(temp, temp);
1478	1495	tcg_gen_andi_i32(temp, temp, ~1 << a->imm);
1479		- tcg_gen_not_i32(mask, cpu_psw_c);
	1496	+ tcg_gen_not_i32(mask, cpu_ccr_c);
1480	1497	tcg_gen_shli_i32(mask, mask, a->imm);
1481	1498	tcg_gen_or_i32(temp, temp, mask);
1482		- tcg_gen_qemu_st_i32(temp, cpu_regs[a->er], 0, MO_B \| MO_SIGN \| MO_TE);
	1499	+ tcg_gen_qemu_st_i32(temp, cpu_regs[a->er], 0, MO_8 \| MO_SIGN \| MO_TE);
1483	1500	tcg_temp_free(temp);
1484	1501	tcg_temp_free(mask);
1485	1502	return true;

		@@ -1491,13 +1508,13 @@ static bool trans_BIST_a(DisasContext ctx, arg_BIST_a a)
1491	1508	temp = tcg_temp_new();
1492	1509	mask = tcg_temp_new();
1493	1510	mem = tcg_const_i32(0xffff00 \| a->abs);
1494		- tcg_gen_qemu_ld_i32(temp, mem, 0, MO_B \| MO_SIGN \| MO_TE);
	1511	+ tcg_gen_qemu_ld_i32(temp, mem, 0, MO_8 \| MO_SIGN \| MO_TE);
1495	1512	tcg_gen_not_i32(temp, temp);
1496	1513	tcg_gen_andi_i32(temp, temp, ~1 << a->imm);
1497		- tcg_gen_not_i32(mask, cpu_psw_c);
	1514	+ tcg_gen_not_i32(mask, cpu_ccr_c);
1498	1515	tcg_gen_shli_i32(mask, mask, a->imm);
1499	1516	tcg_gen_or_i32(temp, temp, mask);
1500		- tcg_gen_qemu_st_i32(temp, mem, 0, MO_B \| MO_SIGN \| MO_TE);
	1517	+ tcg_gen_qemu_st_i32(temp, mem, 0, MO_8 \| MO_SIGN \| MO_TE);
1501	1518	tcg_temp_free(temp);
1502	1519	tcg_temp_free(mask);
1503	1520	tcg_temp_free(mem);

		@@ -1512,9 +1529,9 @@ static bool trans_BIXOR_r(DisasContext ctx, arg_BIXOR_r a)
1512	1529	h8300_gen_reg_ldb(a->r, temp);
1513	1530	tcg_gen_not_i32(temp, temp);
1514	1531	tcg_gen_andi_i32(temp, temp, 1 << a->imm);
1515		- tcg_gen_shli_i32(mask, cpu_psw_c, a->imm);
	1532	+ tcg_gen_shli_i32(mask, cpu_ccr_c, a->imm);
1516	1533	tcg_gen_xor_i32(mask, temp, mask);
1517		- tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, mask, 0);
	1534	+ tcg_gen_setcondi_i32(TCG_COND_NE, cpu_ccr_c, mask, 0);
1518	1535	tcg_temp_free(temp);
1519	1536	tcg_temp_free(mask);
1520	1537	return true;

		@@ -1525,12 +1542,12 @@ static bool trans_BIXOR_m(DisasContext ctx, arg_BIXOR_m a)
1525	1542	TCGv temp, mask;
1526	1543	temp = tcg_temp_new();
1527	1544	mask = tcg_temp_new();
1528		- tcg_gen_qemu_ld_i32(temp, cpu_regs[a->er], 0, MO_B \| MO_SIGN \| MO_TE);
	1545	+ tcg_gen_qemu_ld_i32(temp, cpu_regs[a->er], 0, MO_8 \| MO_SIGN \| MO_TE);
1529	1546	tcg_gen_not_i32(temp, temp);
1530	1547	tcg_gen_andi_i32(temp, temp, 1 << a->imm);
1531		- tcg_gen_shli_i32(mask, cpu_psw_c, a->imm);
	1548	+ tcg_gen_shli_i32(mask, cpu_ccr_c, a->imm);
1532	1549	tcg_gen_xor_i32(mask, temp, mask);
1533		- tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, mask, 0);
	1550	+ tcg_gen_setcondi_i32(TCG_COND_NE, cpu_ccr_c, mask, 0);
1534	1551	tcg_temp_free(temp);
1535	1552	tcg_temp_free(mask);
1536	1553	return true;

		@@ -1542,12 +1559,12 @@ static bool trans_BIXOR_a(DisasContext ctx, arg_BIXOR_a a)
1542	1559	temp = tcg_temp_new();
1543	1560	mask = tcg_temp_new();
1544	1561	mem = tcg_const_i32(0xffff00 \| a->abs);
1545		- tcg_gen_qemu_ld_i32(temp, mem, 0, MO_B \| MO_SIGN \| MO_TE);
	1562	+ tcg_gen_qemu_ld_i32(temp, mem, 0, MO_8 \| MO_SIGN \| MO_TE);
1546	1563	tcg_gen_not_i32(temp, temp);
1547	1564	tcg_gen_andi_i32(temp, temp, 1 << a->imm);
1548		- tcg_gen_shli_i32(mask, cpu_psw_c, a->imm);
	1565	+ tcg_gen_shli_i32(mask, cpu_ccr_c, a->imm);
1549	1566	tcg_gen_xor_i32(mask, temp, mask);
1550		- tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, mask, 0);
	1567	+ tcg_gen_setcondi_i32(TCG_COND_NE, cpu_ccr_c, mask, 0);
1551	1568	tcg_temp_free(temp);
1552	1569	tcg_temp_free(mask);
1553	1570	tcg_temp_free(mem);

		@@ -1559,28 +1576,28 @@ static bool trans_BLD_r(DisasContext ctx, arg_BLD_r a)
1559	1576	TCGv temp;
1560	1577	temp = tcg_temp_new();
1561	1578	h8300_gen_reg_ldb(a->r, temp);
1562		- tcg_gen_extract_i32(cpu_psw_c, temp, a->imm, 1);
	1579	+ tcg_gen_extract_i32(cpu_ccr_c, temp, a->imm, 1);
1563	1580	tcg_temp_free(temp);
1564	1581	return true;
1565	1582	}
1566	1583
1567	1584	static bool trans_BLD_m(DisasContext ctx, arg_BLD_m a)
1568	1585	{
1569		- TCGv temp, mask;
	1586	+ TCGv temp;
1570	1587	temp = tcg_temp_new();
1571		- tcg_gen_qemu_ld_i32(temp, cpu_regs[a->er], 0, MO_B \| MO_SIGN \| MO_TE);
1572		- tcg_gen_extract_i32(cpu_psw_c, temp, a->imm, 1);
	1588	+ tcg_gen_qemu_ld_i32(temp, cpu_regs[a->er], 0, MO_8 \| MO_SIGN \| MO_TE);
	1589	+ tcg_gen_extract_i32(cpu_ccr_c, temp, a->imm, 1);
1573	1590	tcg_temp_free(temp);
1574	1591	return true;
1575	1592	}
1576	1593
1577	1594	static bool trans_BLD_a(DisasContext ctx, arg_BLD_a a)
1578	1595	{
1579		- TCGv temp, mask, mem;
	1596	+ TCGv temp, mem;
1580	1597	temp = tcg_temp_new();
1581	1598	mem = tcg_const_i32(0xffff00 \| a->abs);
1582		- tcg_gen_qemu_ld_i32(temp, mem, 0, MO_B \| MO_SIGN \| MO_TE);
1583		- tcg_gen_extract_i32(cpu_psw_c, temp, a->imm, 1);
	1599	+ tcg_gen_qemu_ld_i32(temp, mem, 0, MO_8 \| MO_SIGN \| MO_TE);
	1600	+ tcg_gen_extract_i32(cpu_ccr_c, temp, a->imm, 1);
1584	1601	tcg_temp_free(temp);
1585	1602	tcg_temp_free(mem);
1586	1603	return true;

		@@ -1593,9 +1610,9 @@ static bool trans_BOR_r(DisasContext ctx, arg_BOR_r a)
1593	1610	mask = tcg_temp_new();
1594	1611	h8300_gen_reg_ldb(a->r, temp);
1595	1612	tcg_gen_andi_i32(temp, temp, 1 << a->imm);
1596		- tcg_gen_shli_i32(mask, cpu_psw_c, a->imm);
	1613	+ tcg_gen_shli_i32(mask, cpu_ccr_c, a->imm);
1597	1614	tcg_gen_or_i32(mask, temp, mask);
1598		- tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, mask, 0);
	1615	+ tcg_gen_setcondi_i32(TCG_COND_NE, cpu_ccr_c, mask, 0);
1599	1616	tcg_temp_free(temp);
1600	1617	tcg_temp_free(mask);
1601	1618	return true;

		@@ -1606,11 +1623,11 @@ static bool trans_BOR_m(DisasContext ctx, arg_BOR_m a)
1606	1623	TCGv temp, mask;
1607	1624	temp = tcg_temp_new();
1608	1625	mask = tcg_temp_new();
1609		- tcg_gen_qemu_ld_i32(temp, cpu_regs[a->er], 0, MO_B \| MO_SIGN \| MO_TE);
	1626	+ tcg_gen_qemu_ld_i32(temp, cpu_regs[a->er], 0, MO_8 \| MO_SIGN \| MO_TE);
1610	1627	tcg_gen_andi_i32(temp, temp, 1 << a->imm);
1611		- tcg_gen_shli_i32(mask, cpu_psw_c, a->imm);
	1628	+ tcg_gen_shli_i32(mask, cpu_ccr_c, a->imm);
1612	1629	tcg_gen_or_i32(mask, temp, mask);
1613		- tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, mask, 0);
	1630	+ tcg_gen_setcondi_i32(TCG_COND_NE, cpu_ccr_c, mask, 0);
1614	1631	tcg_temp_free(temp);
1615	1632	tcg_temp_free(mask);
1616	1633	return true;

		@@ -1622,11 +1639,11 @@ static bool trans_BOR_a(DisasContext ctx, arg_BOR_a a)
1622	1639	temp = tcg_temp_new();
1623	1640	mask = tcg_temp_new();
1624	1641	mem = tcg_const_i32(0xffff00 \| a->abs);
1625		- tcg_gen_qemu_ld_i32(temp, mem, 0, MO_B \| MO_SIGN \| MO_TE);
	1642	+ tcg_gen_qemu_ld_i32(temp, mem, 0, MO_8 \| MO_SIGN \| MO_TE);
1626	1643	tcg_gen_andi_i32(temp, temp, 1 << a->imm);
1627		- tcg_gen_shli_i32(mask, cpu_psw_c, a->imm);
	1644	+ tcg_gen_shli_i32(mask, cpu_ccr_c, a->imm);
1628	1645	tcg_gen_or_i32(mask, temp, mask);
1629		- tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, mask, 0);
	1646	+ tcg_gen_setcondi_i32(TCG_COND_NE, cpu_ccr_c, mask, 0);
1630	1647	tcg_temp_free(temp);
1631	1648	tcg_temp_free(mask);
1632	1649	tcg_temp_free(mem);

		@@ -1640,7 +1657,7 @@ static bool trans_BST_r(DisasContext ctx, arg_BST_r a)
1640	1657	mask = tcg_temp_new();
1641	1658	h8300_gen_reg_ldb(a->r, temp);
1642	1659	tcg_gen_andi_i32(temp, temp, ~1 << a->imm);
1643		- tcg_gen_shli_i32(mask, cpu_psw_c, a->imm);
	1660	+ tcg_gen_shli_i32(mask, cpu_ccr_c, a->imm);
1644	1661	tcg_gen_or_i32(temp, temp, mask);
1645	1662	h8300_gen_reg_stb(a->r, temp);
1646	1663	tcg_temp_free(temp);

		@@ -1648,34 +1665,32 @@ static bool trans_BST_r(DisasContext ctx, arg_BST_r a)
1648	1665	return true;
1649	1666	}
1650	1667
1651		-static bool trans_BIST_m(DisasContext ctx, arg_BIST_m a)
	1668	+static bool trans_BST_m(DisasContext ctx, arg_BST_m a)
1652	1669	{
1653	1670	TCGv temp, mask;
1654	1671	temp = tcg_temp_new();
1655	1672	mask = tcg_temp_new();
1656		- tcg_gen_qemu_ld_i32(temp, cpu_regs[a->er], 0, MO_B \| MO_SIGN \| MO_TE);
1657		- tcg_gen_not_i32(temp, temp);
	1673	+ tcg_gen_qemu_ld_i32(temp, cpu_regs[a->er], 0, MO_8 \| MO_SIGN \| MO_TE);
1658	1674	tcg_gen_andi_i32(temp, temp, ~1 << a->imm);
1659		- tcg_gen_shli_i32(mask, cpu_psw_c, a->imm);
	1675	+ tcg_gen_shli_i32(mask, cpu_ccr_c, a->imm);
1660	1676	tcg_gen_or_i32(temp, temp, mask);
1661		- tcg_gen_qemu_st_i32(temp, cpu_regs[a->er], 0, MO_B \| MO_SIGN \| MO_TE);
	1677	+ tcg_gen_qemu_st_i32(temp, cpu_regs[a->er], 0, MO_8 \| MO_SIGN \| MO_TE);
1662	1678	tcg_temp_free(temp);
1663	1679	tcg_temp_free(mask);
1664	1680	return true;
1665	1681	}
1666	1682
1667		-static bool trans_BIST_a(DisasContext ctx, arg_BIST_a a)
	1683	+static bool trans_BST_a(DisasContext ctx, arg_BST_a a)
1668	1684	{
1669	1685	TCGv temp, mask, mem;
1670	1686	temp = tcg_temp_new();
1671	1687	mask = tcg_temp_new();
1672	1688	mem = tcg_const_i32(0xffff00 \| a->abs);
1673		- tcg_gen_qemu_ld_i32(temp, mem, 0, MO_B \| MO_SIGN \| MO_TE);
1674		- tcg_gen_not_i32(temp, temp);
	1689	+ tcg_gen_qemu_ld_i32(temp, mem, 0, MO_8 \| MO_SIGN \| MO_TE);
1675	1690	tcg_gen_andi_i32(temp, temp, ~1 << a->imm);
1676		- tcg_gen_shli_i32(mask, cpu_psw_c, a->imm);
	1691	+ tcg_gen_shli_i32(mask, cpu_ccr_c, a->imm);
1677	1692	tcg_gen_or_i32(temp, temp, mask);
1678		- tcg_gen_qemu_st_i32(temp, mem, 0, MO_B \| MO_SIGN \| MO_TE);
	1693	+ tcg_gen_qemu_st_i32(temp, mem, 0, MO_8 \| MO_SIGN \| MO_TE);
1679	1694	tcg_temp_free(temp);
1680	1695	tcg_temp_free(mask);
1681	1696	tcg_temp_free(mem);

		@@ -1689,9 +1704,9 @@ static bool trans_BXOR_r(DisasContext ctx, arg_BXOR_r a)
1689	1704	mask = tcg_temp_new();
1690	1705	h8300_gen_reg_ldb(a->r, temp);
1691	1706	tcg_gen_andi_i32(temp, temp, 1 << a->imm);
1692		- tcg_gen_shli_i32(mask, cpu_psw_c, a->imm);
	1707	+ tcg_gen_shli_i32(mask, cpu_ccr_c, a->imm);
1693	1708	tcg_gen_xor_i32(mask, temp, mask);
1694		- tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, mask, 0);
	1709	+ tcg_gen_setcondi_i32(TCG_COND_NE, cpu_ccr_c, mask, 0);
1695	1710	tcg_temp_free(temp);
1696	1711	tcg_temp_free(mask);
1697	1712	return true;

		@@ -1702,11 +1717,11 @@ static bool trans_BXOR_m(DisasContext ctx, arg_BXOR_m a)
1702	1717	TCGv temp, mask;
1703	1718	temp = tcg_temp_new();
1704	1719	mask = tcg_temp_new();
1705		- tcg_gen_qemu_ld_i32(temp, cpu_regs[a->er], 0, MO_B \| MO_SIGN \| MO_TE);
	1720	+ tcg_gen_qemu_ld_i32(temp, cpu_regs[a->er], 0, MO_8 \| MO_SIGN \| MO_TE);
1706	1721	tcg_gen_andi_i32(temp, temp, 1 << a->imm);
1707		- tcg_gen_shli_i32(mask, cpu_psw_c, a->imm);
	1722	+ tcg_gen_shli_i32(mask, cpu_ccr_c, a->imm);
1708	1723	tcg_gen_xor_i32(mask, temp, mask);
1709		- tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, mask, 0);
	1724	+ tcg_gen_setcondi_i32(TCG_COND_NE, cpu_ccr_c, mask, 0);
1710	1725	tcg_temp_free(temp);
1711	1726	tcg_temp_free(mask);
1712	1727	return true;

		@@ -1718,11 +1733,11 @@ static bool trans_BXOR_a(DisasContext ctx, arg_BXOR_a a)
1718	1733	temp = tcg_temp_new();
1719	1734	mask = tcg_temp_new();
1720	1735	mem = tcg_const_i32(0xffff00 \| a->abs);
1721		- tcg_gen_qemu_ld_i32(temp, mem, 0, MO_B \| MO_SIGN \| MO_TE);
	1736	+ tcg_gen_qemu_ld_i32(temp, mem, 0, MO_8 \| MO_SIGN \| MO_TE);
1722	1737	tcg_gen_andi_i32(temp, temp, 1 << a->imm);
1723		- tcg_gen_shli_i32(mask, cpu_psw_c, a->imm);
	1738	+ tcg_gen_shli_i32(mask, cpu_ccr_c, a->imm);
1724	1739	tcg_gen_xor_i32(mask, temp, mask);
1725		- tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, mask, 0);
	1740	+ tcg_gen_setcondi_i32(TCG_COND_NE, cpu_ccr_c, mask, 0);
1726	1741	tcg_temp_free(temp);
1727	1742	tcg_temp_free(mask);
1728	1743	tcg_temp_free(mem);

		@@ -1744,11 +1759,10 @@ static bool trans_BCLR_im(DisasContext ctx, arg_BCLR_im a)
1744	1759	{
1745	1760	TCGv temp;
1746	1761	temp = tcg_temp_new();
1747		- tcg_gen_qemu_ld_i32(temp, cpu_regs[a->er], 0, MO_B \| MO_SIGN \| MO_TE);
	1762	+ tcg_gen_qemu_ld_i32(temp, cpu_regs[a->er], 0, MO_8 \| MO_SIGN \| MO_TE);
1748	1763	tcg_gen_andi_i32(temp, temp, ~1 << a->imm);
1749		- tcg_gen_qemu_st_i32(temp, cpu_regs[a->er], 0, MO_B \| MO_SIGN \| MO_TE);
	1764	+ tcg_gen_qemu_st_i32(temp, cpu_regs[a->er], 0, MO_8 \| MO_SIGN \| MO_TE);
1750	1765	tcg_temp_free(temp);
1751		- tcg_temp_free(mask);
1752	1766	return true;
1753	1767	}
1754	1768

		@@ -1757,9 +1771,9 @@ static bool trans_BCLR_ia(DisasContext ctx, arg_BCLR_ia a)
1757	1771	TCGv temp, mem;
1758	1772	temp = tcg_temp_new();
1759	1773	mem = tcg_const_i32(0xffff00 \| a->abs);
1760		- tcg_gen_qemu_ld_i32(temp, mem, 0, MO_B \| MO_SIGN \| MO_TE);
	1774	+ tcg_gen_qemu_ld_i32(temp, mem, 0, MO_8 \| MO_SIGN \| MO_TE);
1761	1775	tcg_gen_andi_i32(temp, temp, ~1 << a->imm);
1762		- tcg_gen_qemu_st_i32(temp, mem, 0, MO_B \| MO_SIGN \| MO_TE);
	1776	+ tcg_gen_qemu_st_i32(temp, mem, 0, MO_8 \| MO_SIGN \| MO_TE);
1763	1777	tcg_temp_free(temp);
1764	1778	tcg_temp_free(mem);
1765	1779	return true;

		@@ -1767,51 +1781,60 @@ static bool trans_BCLR_ia(DisasContext ctx, arg_BCLR_ia a)
1767	1781
1768	1782	static bool trans_BCLR_rr(DisasContext ctx, arg_BCLR_rr a)
1769	1783	{
1770		- TCGv temp, mask;
	1784	+ TCGv temp, mask, shift;
1771	1785	temp = tcg_temp_new();
1772	1786	mask = tcg_temp_new();
	1787	+ shift = tcg_temp_new();
1773	1788	h8300_gen_reg_ldb(a->rd, temp);
	1789	+ h8300_gen_reg_ldb(a->rs, shift);
1774	1790	tcg_gen_movi_i32(mask, 1);
1775		- tcg_gen_shl_i32(mask, mask, a->rs);
	1791	+ tcg_gen_shl_i32(mask, mask, shift);
1776	1792	tcg_gen_not_i32(mask, mask);
1777	1793	tcg_gen_and_i32(temp, temp, mask);
1778		- h8300_gen_reg_stb(a->r, temp);
	1794	+ h8300_gen_reg_stb(a->rd, temp);
1779	1795	tcg_temp_free(temp);
1780	1796	tcg_temp_free(mask);
	1797	+ tcg_temp_free(shift);
1781	1798	return true;
1782	1799	}
1783	1800
1784	1801	static bool trans_BCLR_rm(DisasContext ctx, arg_BCLR_rm a)
1785	1802	{
1786		- TCGv temp, mask;
	1803	+ TCGv temp, mask, shift;
1787	1804	temp = tcg_temp_new();
1788	1805	mask = tcg_temp_new();
1789		- tcg_gen_qemu_ld_i32(temp, cpu_regs[a->er], 0, MO_B \| MO_SIGN \| MO_TE);
	1806	+ shift = tcg_temp_new();
	1807	+ tcg_gen_qemu_ld_i32(temp, cpu_regs[a->rd], 0, MO_8 \| MO_SIGN \| MO_TE);
	1808	+ h8300_gen_reg_ldb(a->rn, shift);
1790	1809	tcg_gen_movi_i32(mask, 1);
1791		- tcg_gen_shl_i32(mask, mask, a->rs);
	1810	+ tcg_gen_shl_i32(mask, mask, shift);
1792	1811	tcg_gen_not_i32(mask, mask);
1793	1812	tcg_gen_and_i32(temp, temp, mask);
1794		- tcg_gen_qemu_st_i32(temp, cpu_regs[a->er], 0, MO_B \| MO_SIGN \| MO_TE);
	1813	+ tcg_gen_qemu_st_i32(temp, cpu_regs[a->rd], 0, MO_8 \| MO_SIGN \| MO_TE);
1795	1814	tcg_temp_free(temp);
1796	1815	tcg_temp_free(mask);
	1816	+ tcg_temp_free(shift);
1797	1817	return true;
1798	1818	}
1799	1819
1800	1820	static bool trans_BCLR_ra(DisasContext ctx, arg_BCLR_ra a)
1801	1821	{
1802		- TCGv temp, mask, mem;
	1822	+ TCGv temp, mask, mem, shift;
1803	1823	temp = tcg_temp_new();
1804	1824	mask = tcg_temp_new();
1805	1825	mem = tcg_const_i32(0xffff00 \| a->abs);
1806		- tcg_gen_qemu_ld_i32(temp, mem, 0, MO_B \| MO_SIGN \| MO_TE);
	1826	+ shift = tcg_temp_new();
	1827	+ tcg_gen_qemu_ld_i32(temp, mem, 0, MO_8 \| MO_SIGN \| MO_TE);
	1828	+ h8300_gen_reg_ldb(a->rn, shift);
1807	1829	tcg_gen_movi_i32(mask, 1);
1808		- tcg_gen_shl_i32(mask, mask, a->rs);
	1830	+ tcg_gen_shl_i32(mask, mask, shift);
1809	1831	tcg_gen_not_i32(mask, mask);
1810	1832	tcg_gen_and_i32(temp, temp, mask);
1811		- tcg_gen_qemu_st_i32(temp, mem, 0, MO_B \| MO_SIGN \| MO_TE);
	1833	+ tcg_gen_qemu_st_i32(temp, mem, 0, MO_8 \| MO_SIGN \| MO_TE);
1812	1834	tcg_temp_free(temp);
1813	1835	tcg_temp_free(mask);
1814	1836	tcg_temp_free(mem);
	1837	+ tcg_temp_free(shift);
1815	1838	return true;
1816	1839	}
1817	1840

		@@ -1830,21 +1853,21 @@ static bool trans_BNOT_im(DisasContext ctx, arg_BNOT_im a)
1830	1853	{
1831	1854	TCGv temp;
1832	1855	temp = tcg_temp_new();
1833		- tcg_gen_qemu_ld_i32(temp, cpu_regs[a->er], 0, MO_B \| MO_SIGN \| MO_TE);
	1856	+ tcg_gen_qemu_ld_i32(temp, cpu_regs[a->er], 0, MO_8 \| MO_SIGN \| MO_TE);
1834	1857	tcg_gen_xori_i32(temp, temp, 1 << a->imm);
1835		- tcg_gen_qemu_st_i32(temp, cpu_regs[a->er], 0, MO_B \| MO_SIGN \| MO_TE);
	1858	+ tcg_gen_qemu_st_i32(temp, cpu_regs[a->er], 0, MO_8 \| MO_SIGN \| MO_TE);
1836	1859	tcg_temp_free(temp);
1837	1860	return true;
1838	1861	}
1839	1862
1840		-static bool trans_BNOT_ia(DisasContext ctx, arg_BNOT_ra a)
	1863	+static bool trans_BNOT_ia(DisasContext ctx, arg_BNOT_ia a)
1841	1864	{
1842	1865	TCGv temp, mem;
1843	1866	temp = tcg_temp_new();
1844	1867	mem = tcg_const_i32(0xffff00 \| a->abs);
1845		- tcg_gen_qemu_ld_i32(temp, mem, 0, MO_B \| MO_SIGN \| MO_TE);
	1868	+ tcg_gen_qemu_ld_i32(temp, mem, 0, MO_8 \| MO_SIGN \| MO_TE);
1846	1869	tcg_gen_xori_i32(temp, temp, 1 << a->imm);
1847		- tcg_gen_qemu_st_i32(temp, mem, 0, MO_B \| MO_SIGN \| MO_TE);
	1870	+ tcg_gen_qemu_st_i32(temp, mem, 0, MO_8 \| MO_SIGN \| MO_TE);
1848	1871	tcg_temp_free(temp);
1849	1872	tcg_temp_free(mem);
1850	1873	return true;

		@@ -1852,29 +1875,34 @@ static bool trans_BNOT_ia(DisasContext ctx, arg_BNOT_ra a)
1852	1875
1853	1876	static bool trans_BNOT_rr(DisasContext ctx, arg_BNOT_rr a)
1854	1877	{
1855		- TCGv temp, mask;
	1878	+ TCGv temp, mask, shift;
1856	1879	temp = tcg_temp_new();
1857	1880	mask = tcg_temp_new();
	1881	+ shift = tcg_temp_new();
1858	1882	h8300_gen_reg_ldb(a->rd, temp);
	1883	+ h8300_gen_reg_ldb(a->rs, shift);
1859	1884	tcg_gen_movi_i32(mask, 1);
1860		- tcg_gen_shl_i32(mask, mask, a->rs);
	1885	+ tcg_gen_shl_i32(mask, mask, shift);
1861	1886	tcg_gen_xor_i32(temp, temp, mask);
1862		- h8300_gen_reg_stb(a->r, temp);
	1887	+ h8300_gen_reg_stb(a->rd, temp);
1863	1888	tcg_temp_free(temp);
1864	1889	tcg_temp_free(mask);
	1890	+ tcg_temp_free(shift);
1865	1891	return true;
1866	1892	}
1867	1893
1868	1894	static bool trans_BNOT_rm(DisasContext ctx, arg_BNOT_rm a)
1869	1895	{
1870		- TCGv temp, mask;
	1896	+ TCGv temp, mask, shift;
1871	1897	temp = tcg_temp_new();
1872	1898	mask = tcg_temp_new();
1873		- tcg_gen_qemu_ld_i32(temp, cpu_regs[a->er], 0, MO_B \| MO_SIGN \| MO_TE);
	1899	+ shift = tcg_temp_new();
	1900	+ tcg_gen_qemu_ld_i32(temp, cpu_regs[a->rd], 0, MO_8 \| MO_SIGN \| MO_TE);
	1901	+ h8300_gen_reg_ldb(a->rn, shift);
1874	1902	tcg_gen_movi_i32(mask, 1);
1875		- tcg_gen_shl_i32(mask, mask, a->rs);
	1903	+ tcg_gen_shl_i32(mask, mask, shift);
1876	1904	tcg_gen_xor_i32(temp, temp, mask);
1877		- tcg_gen_qemu_st_i32(temp, cpu_regs[a->er], 0, MO_B \| MO_SIGN \| MO_TE);
	1905	+ tcg_gen_qemu_st_i32(temp, cpu_regs[a->rd], 0, MO_8 \| MO_SIGN \| MO_TE);
1878	1906	tcg_temp_free(temp);
1879	1907	tcg_temp_free(mask);
1880	1908	return true;

		@@ -1882,18 +1910,21 @@ static bool trans_BNOT_rm(DisasContext ctx, arg_BNOT_rm a)
1882	1910
1883	1911	static bool trans_BNOT_ra(DisasContext ctx, arg_BNOT_ra a)
1884	1912	{
1885		- TCGv temp, mask, mem;
	1913	+ TCGv temp, mask, mem, shift;
1886	1914	temp = tcg_temp_new();
1887	1915	mask = tcg_temp_new();
1888	1916	mem = tcg_const_i32(0xffff00 \| a->abs);
1889		- tcg_gen_qemu_ld_i32(temp, mem, 0, MO_B \| MO_SIGN \| MO_TE);
	1917	+ shift = tcg_temp_new();
	1918	+ tcg_gen_qemu_ld_i32(temp, mem, 0, MO_8 \| MO_SIGN \| MO_TE);
	1919	+ h8300_gen_reg_ldb(a->rn, shift);
1890	1920	tcg_gen_movi_i32(mask, 1);
1891		- tcg_gen_shl_i32(mask, mask, a->rs);
	1921	+ tcg_gen_shl_i32(mask, mask, shift);
1892	1922	tcg_gen_xor_i32(temp, temp, mask);
1893		- tcg_gen_qemu_st_i32(temp, mem, 0, MO_B \| MO_SIGN \| MO_TE);
	1923	+ tcg_gen_qemu_st_i32(temp, mem, 0, MO_8 \| MO_SIGN \| MO_TE);
1894	1924	tcg_temp_free(temp);
1895	1925	tcg_temp_free(mask);
1896	1926	tcg_temp_free(mem);
	1927	+ tcg_temp_free(shift);
1897	1928	return true;
1898	1929	}
1899	1930

		@@ -1912,21 +1943,21 @@ static bool trans_BSET_im(DisasContext ctx, arg_BSET_im a)
1912	1943	{
1913	1944	TCGv temp;
1914	1945	temp = tcg_temp_new();
1915		- tcg_gen_qemu_ld_i32(temp, cpu_regs[a->er], 0, MO_B \| MO_SIGN \| MO_TE);
	1946	+ tcg_gen_qemu_ld_i32(temp, cpu_regs[a->er], 0, MO_8 \| MO_SIGN \| MO_TE);
1916	1947	tcg_gen_ori_i32(temp, temp, 1 << a->imm);
1917		- tcg_gen_qemu_st_i32(temp, cpu_regs[a->er], 0, MO_B \| MO_SIGN \| MO_TE);
	1948	+ tcg_gen_qemu_st_i32(temp, cpu_regs[a->er], 0, MO_8 \| MO_SIGN \| MO_TE);
1918	1949	tcg_temp_free(temp);
1919	1950	return true;
1920	1951	}
1921	1952
1922		-static bool trans_BSET_ia(DisasContext ctx, arg_BSET_ra a)
	1953	+static bool trans_BSET_ia(DisasContext ctx, arg_BSET_ia a)
1923	1954	{
1924	1955	TCGv temp, mem;
1925	1956	temp = tcg_temp_new();
1926	1957	mem = tcg_const_i32(0xffff00 \| a->abs);
1927		- tcg_gen_qemu_ld_i32(temp, mem, 0, MO_B \| MO_SIGN \| MO_TE);
	1958	+ tcg_gen_qemu_ld_i32(temp, mem, 0, MO_8 \| MO_SIGN \| MO_TE);
1928	1959	tcg_gen_ori_i32(temp, temp, 1 << a->imm);
1929		- tcg_gen_qemu_st_i32(temp, mem, 0, MO_B \| MO_SIGN \| MO_TE);
	1960	+ tcg_gen_qemu_st_i32(temp, mem, 0, MO_8 \| MO_SIGN \| MO_TE);
1930	1961	tcg_temp_free(temp);
1931	1962	tcg_temp_free(mem);
1932	1963	return true;

		@@ -1934,48 +1965,57 @@ static bool trans_BSET_ia(DisasContext ctx, arg_BSET_ra a)
1934	1965
1935	1966	static bool trans_BSET_rr(DisasContext ctx, arg_BSET_rr a)
1936	1967	{
1937		- TCGv temp, mask;
	1968	+ TCGv temp, mask, shift;
1938	1969	temp = tcg_temp_new();
1939	1970	mask = tcg_temp_new();
	1971	+ shift = tcg_temp_new();
1940	1972	h8300_gen_reg_ldb(a->rd, temp);
	1973	+ h8300_gen_reg_ldb(a->rs, shift);
1941	1974	tcg_gen_movi_i32(mask, 1);
1942		- tcg_gen_shl_i32(mask, mask, a->rs);
	1975	+ tcg_gen_shl_i32(mask, mask, shift);
1943	1976	tcg_gen_or_i32(temp, temp, mask);
1944		- h8300_gen_reg_stb(a->r, temp);
	1977	+ h8300_gen_reg_stb(a->rd, temp);
1945	1978	tcg_temp_free(temp);
1946	1979	tcg_temp_free(mask);
	1980	+ tcg_temp_free(shift);
1947	1981	return true;
1948	1982	}
1949	1983
1950	1984	static bool trans_BSET_rm(DisasContext ctx, arg_BSET_rm a)
1951	1985	{
1952		- TCGv temp, mask;
	1986	+ TCGv temp, mask, shift;
1953	1987	temp = tcg_temp_new();
1954	1988	mask = tcg_temp_new();
1955		- tcg_gen_qemu_ld_i32(temp, cpu_regs[a->er], 0, MO_B \| MO_SIGN \| MO_TE);
	1989	+ shift = tcg_temp_new();
	1990	+ tcg_gen_qemu_ld_i32(temp, cpu_regs[a->rd], 0, MO_8 \| MO_SIGN \| MO_TE);
	1991	+ h8300_gen_reg_ldb(a->rn, shift);
1956	1992	tcg_gen_movi_i32(mask, 1);
1957		- tcg_gen_shl_i32(mask, mask, a->rs);
	1993	+ tcg_gen_shl_i32(mask, mask, shift);
1958	1994	tcg_gen_or_i32(temp, temp, mask);
1959		- tcg_gen_qemu_st_i32(temp, cpu_regs[a->er], 0, MO_B \| MO_SIGN \| MO_TE);
	1995	+ tcg_gen_qemu_st_i32(temp, cpu_regs[a->rd], 0, MO_8 \| MO_SIGN \| MO_TE);
1960	1996	tcg_temp_free(temp);
1961	1997	tcg_temp_free(mask);
	1998	+ tcg_temp_free(shift);
1962	1999	return true;
1963	2000	}
1964	2001
1965	2002	static bool trans_BSET_ra(DisasContext ctx, arg_BSET_ra a)
1966	2003	{
1967		- TCGv temp, mask, mem;
	2004	+ TCGv temp, mask, mem, shift;
1968	2005	temp = tcg_temp_new();
1969	2006	mask = tcg_temp_new();
1970	2007	mem = tcg_const_i32(0xffff00 \| a->abs);
1971		- tcg_gen_qemu_ld_i32(temp, mem, 0, MO_B \| MO_SIGN \| MO_TE);
	2008	+ shift = tcg_temp_new();
	2009	+ tcg_gen_qemu_ld_i32(temp, mem, 0, MO_8 \| MO_SIGN \| MO_TE);
	2010	+ h8300_gen_reg_ldb(a->rn, shift);
1972	2011	tcg_gen_movi_i32(mask, 1);
1973		- tcg_gen_shl_i32(mask, mask, a->rs);
	2012	+ tcg_gen_shl_i32(mask, mask, shift);
1974	2013	tcg_gen_or_i32(temp, temp, mask);
1975		- tcg_gen_qemu_st_i32(temp, mem, 0, MO_B \| MO_SIGN \| MO_TE);
	2014	+ tcg_gen_qemu_st_i32(temp, mem, 0, MO_8 \| MO_SIGN \| MO_TE);
1976	2015	tcg_temp_free(temp);
1977	2016	tcg_temp_free(mask);
1978	2017	tcg_temp_free(mem);
	2018	+ tcg_temp_free(shift);
1979	2019	return true;
1980	2020	}
1981	2021

		@@ -1984,7 +2024,7 @@ static bool trans_BTST_ir(DisasContext ctx, arg_BTST_ir a)
1984	2024	TCGv temp;
1985	2025	temp = tcg_temp_new();
1986	2026	h8300_gen_reg_ldb(a->r, temp);
1987		- tcg_gen_andi_i32(cpu_psw_z, temp, 1 << a->imm);
	2027	+ tcg_gen_andi_i32(cpu_ccr_z, temp, 1 << a->imm);
1988	2028	tcg_temp_free(temp);
1989	2029	return true;
1990	2030	}

		@@ -1993,19 +2033,19 @@ static bool trans_BTST_im(DisasContext ctx, arg_BTST_im a)
1993	2033	{
1994	2034	TCGv temp;
1995	2035	temp = tcg_temp_new();
1996		- tcg_gen_qemu_ld_i32(temp, cpu_regs[a->er], 0, MO_B \| MO_SIGN \| MO_TE);
1997		- tcg_gen_andi_i32(cpu_psw_z, temp, 1 << a->imm);
	2036	+ tcg_gen_qemu_ld_i32(temp, cpu_regs[a->er], 0, MO_8 \| MO_SIGN \| MO_TE);
	2037	+ tcg_gen_andi_i32(cpu_ccr_z, temp, 1 << a->imm);
1998	2038	tcg_temp_free(temp);
1999	2039	return true;
2000	2040	}
2001	2041
2002		-static bool trans_BTST_ia(DisasContext ctx, arg_BTST_ra a)
	2042	+static bool trans_BTST_ia(DisasContext ctx, arg_BTST_ia a)
2003	2043	{
2004	2044	TCGv temp, mem;
2005	2045	temp = tcg_temp_new();
2006	2046	mem = tcg_const_i32(0xffff00 \| a->abs);
2007		- tcg_gen_qemu_ld_i32(temp, mem, 0, MO_B \| MO_SIGN \| MO_TE);
2008		- tcg_gen_andi_i32(cpu_psw_z, temp, 1 << a->imm);
	2047	+ tcg_gen_qemu_ld_i32(temp, mem, 0, MO_8 \| MO_SIGN \| MO_TE);
	2048	+ tcg_gen_andi_i32(cpu_ccr_z, temp, 1 << a->imm);
2009	2049	tcg_temp_free(temp);
2010	2050	tcg_temp_free(mem);
2011	2051	return true;

		@@ -2013,45 +2053,54 @@ static bool trans_BTST_ia(DisasContext ctx, arg_BTST_ra a)
2013	2053
2014	2054	static bool trans_BTST_rr(DisasContext ctx, arg_BTST_rr a)
2015	2055	{
2016		- TCGv temp, mask;
	2056	+ TCGv temp, mask, shift;
2017	2057	temp = tcg_temp_new();
2018	2058	mask = tcg_temp_new();
	2059	+ shift = tcg_temp_new();
2019	2060	h8300_gen_reg_ldb(a->rd, temp);
	2061	+ h8300_gen_reg_ldb(a->rs, shift);
2020	2062	tcg_gen_movi_i32(mask, 1);
2021		- tcg_gen_shl_i32(mask, mask, a->rs);
2022		- tcg_gen_and_i32(cpu_psw_z, temp, mask);
	2063	+ tcg_gen_shl_i32(mask, mask, shift);
	2064	+ tcg_gen_and_i32(cpu_ccr_z, temp, mask);
2023	2065	tcg_temp_free(temp);
2024	2066	tcg_temp_free(mask);
	2067	+ tcg_temp_free(shift);
2025	2068	return true;
2026	2069	}
2027	2070
2028	2071	static bool trans_BTST_rm(DisasContext ctx, arg_BTST_rm a)
2029	2072	{
2030		- TCGv temp, mask;
	2073	+ TCGv temp, mask, shift;
2031	2074	temp = tcg_temp_new();
2032	2075	mask = tcg_temp_new();
2033		- tcg_gen_qemu_ld_i32(temp, cpu_regs[a->er], 0, MO_B \| MO_SIGN \| MO_TE);
	2076	+ shift = tcg_temp_new();
	2077	+ tcg_gen_qemu_ld_i32(temp, cpu_regs[a->rd], 0, MO_8 \| MO_SIGN \| MO_TE);
	2078	+ h8300_gen_reg_ldb(a->rn, shift);
2034	2079	tcg_gen_movi_i32(mask, 1);
2035		- tcg_gen_shl_i32(mask, mask, a->rs);
2036		- tcg_gen_and_i32(cpu_psw_z, temp, mask);
	2080	+ tcg_gen_shl_i32(mask, mask, shift);
	2081	+ tcg_gen_and_i32(cpu_ccr_z, temp, mask);
2037	2082	tcg_temp_free(temp);
2038	2083	tcg_temp_free(mask);
	2084	+ tcg_temp_free(shift);
2039	2085	return true;
2040	2086	}
2041	2087
2042	2088	static bool trans_BTST_ra(DisasContext ctx, arg_BTST_ra a)
2043	2089	{
2044		- TCGv temp, mask, mem;
	2090	+ TCGv temp, mask, mem, shift;
2045	2091	temp = tcg_temp_new();
2046	2092	mask = tcg_temp_new();
2047	2093	mem = tcg_const_i32(0xffff00 \| a->abs);
2048		- tcg_gen_qemu_ld_i32(temp, mem, 0, MO_B \| MO_SIGN \| MO_TE);
	2094	+ shift = tcg_temp_new();
	2095	+ tcg_gen_qemu_ld_i32(temp, mem, 0, MO_8 \| MO_SIGN \| MO_TE);
	2096	+ h8300_gen_reg_ldb(a->rn, shift);
2049	2097	tcg_gen_movi_i32(mask, 1);
2050		- tcg_gen_shl_i32(mask, mask, a->rs);
2051		- tcg_gen_and_i32(cpu_psw_z, temp, mask);
	2098	+ tcg_gen_shl_i32(mask, mask, shift);
	2099	+ tcg_gen_and_i32(cpu_ccr_z, temp, mask);
2052	2100	tcg_temp_free(temp);
2053	2101	tcg_temp_free(mask);
2054	2102	tcg_temp_free(mem);
	2103	+ tcg_temp_free(shift);
2055	2104	return true;
2056	2105	}
2057	2106

		@@ -2063,7 +2112,7 @@ static bool trans_Bcc(DisasContext ctx, arg_Bcc a)
2063	2112	switch (a->cd) {
2064	2113	case 0:
2065	2114	/* always true case */
2066		- gen_goto_tb(ctx, 0, ctx->pc + dst);
	2115	+ gen_goto_tb(ctx, 0, ctx->base.pc_next + a->dsp);
2067	2116	break;
2068	2117	case 1:
2069	2118	/* always false case */

		@@ -2071,30 +2120,24 @@ static bool trans_Bcc(DisasContext ctx, arg_Bcc a)
2071	2120	break;
2072	2121	case 2 ... 15:
2073	2122	dc.temp = tcg_temp_new();
2074		- ccr_cond(&dc, cd);
	2123	+ ccr_cond(&dc, a->cd);
2075	2124	t = gen_new_label();
2076	2125	done = gen_new_label();
2077	2126	tcg_gen_brcondi_i32(dc.cond, dc.value, 0, t);
2078	2127	gen_goto_tb(ctx, 0, ctx->base.pc_next);
2079	2128	tcg_gen_br(done);
2080	2129	gen_set_label(t);
2081		- gen_goto_tb(ctx, 1, ctx->pc + a->dst);
	2130	+ gen_goto_tb(ctx, 1, ctx->base.pc_next + a->dsp);
2082	2131	gen_set_label(done);
2083	2132	tcg_temp_free(dc.temp);
2084	2133	break;
2085	2134	}
2086		-}
2087		-
2088		-static bool trans_JMP_r(DisasContext ctx, arg_JMP_r a)
2089		-{
2090		- tcg_gen_and_i32(cpu_pc, cpu_regs[a->r], 0x00ffffff);
2091		- ctx->base.is_jmp = DISAS_JUMP;
2092	2135	return true;
2093	2136	}
2094	2137
2095	2138	static bool trans_JMP_r(DisasContext ctx, arg_JMP_r a)
2096	2139	{
2097		- tcg_gen_andi_i32(cpu_pc, cpu_regs[a->r], 0x00ffffff);
	2140	+ tcg_gen_andi_i32(cpu_pc, cpu_regs[a->rs], 0x00ffffff);
2098	2141	ctx->base.is_jmp = DISAS_JUMP;
2099	2142	return true;
2100	2143	}

		@@ -2115,9 +2158,9 @@ static bool trans_JMP_aa8(DisasContext ctx, arg_JMP_aa8 a)
2115	2158	return true;
2116	2159	}
2117	2160
2118		-static inline void save_pc(void)
	2161	+static inline void save_pc(DisasContext *ctx)
2119	2162	{
2120		- TCGv pc = tcg_const_i32(ctx->base.pc->next);
	2163	+ TCGv pc = tcg_const_i32(ctx->base.pc_next);
2121	2164	tcg_gen_subi_i32(cpu_sp, cpu_sp, 4);
2122	2165	tcg_gen_qemu_st_i32(pc, cpu_sp, 0, MO_32 \| MO_SIGN \| MO_TE);
2123	2166	tcg_temp_free(pc);

		@@ -2125,15 +2168,15 @@ static inline void save_pc(void)
2125	2168
2126	2169	static bool trans_JSR_r(DisasContext ctx, arg_JMP_r a)
2127	2170	{
2128		- save_pc();
2129		- tcg_gen_andi_i32(cpu_pc, cpu_regs[a->r], 0x00ffffff);
	2171	+ save_pc(ctx);
	2172	+ tcg_gen_andi_i32(cpu_pc, cpu_regs[a->rs], 0x00ffffff);
2130	2173	ctx->base.is_jmp = DISAS_JUMP;
2131	2174	return true;
2132	2175	}
2133	2176
2134	2177	static bool trans_JSR_a24(DisasContext ctx, arg_JSR_a24 a)
2135	2178	{
2136		- save_pc();
	2179	+ save_pc(ctx);
2137	2180	tcg_gen_movi_i32(cpu_pc, a->abs);
2138	2181	ctx->base.is_jmp = DISAS_JUMP;
2139	2182	return true;

		@@ -2142,16 +2185,27 @@ static bool trans_JSR_a24(DisasContext ctx, arg_JSR_a24 a)
2142	2185	static bool trans_JSR_aa8(DisasContext ctx, arg_JSR_aa8 a)
2143	2186	{
2144	2187	TCGv mem = tcg_const_i32(a->abs);
2145		- save_pc();
2146		- tcg_gen_qemu_ld_i32(cpu_pc, mem, 0, MO_32 \| MO_SIGN \| MO_TE);
2147		- ctx->base.is_jmp = DISAS_JUMP;
	2188	+ if (a->abs != 0xc7) {
	2189	+ save_pc(ctx);
	2190	+ tcg_gen_qemu_ld_i32(cpu_pc, mem, 0, MO_32 \| MO_SIGN \| MO_TE);
	2191	+ ctx->base.is_jmp = DISAS_JUMP;
	2192	+ } else {
	2193	+ gen_helper_sim_write(cpu_env);
	2194	+ }
2148	2195	tcg_temp_free(mem);
2149	2196	return true;
2150	2197	}
2151	2198
	2199	+static bool trans_BSR(DisasContext ctx, arg_BSR a)
	2200	+{
	2201	+ save_pc(ctx);
	2202	+ gen_goto_tb(ctx, 0, ctx->base.pc_next + a->dsp);
	2203	+ return true;
	2204	+}
	2205	+
2152	2206	static bool trans_RTS(DisasContext ctx, arg_RTS a)
2153	2207	{
2154		- tcg_gen_qemu_ld_i32(cpu_pc, cpu_sp, 0, MO_32 \| MO_SIGN \| MO_TE);
	2208	+ tcg_gen_qemu_ld_i32(cpu_pc, cpu_sp, 0, MO_32 \| MO_TE);
2155	2209	tcg_gen_addi_i32(cpu_sp, cpu_sp, 4);
2156	2210	ctx->base.is_jmp = DISAS_JUMP;
2157	2211	return true;

		@@ -2161,11 +2215,11 @@ static bool trans_RTE(DisasContext ctx, arg_RTE a)
2161	2215	{
2162	2216	TCGv ccr;
2163	2217	ccr = tcg_temp_new();
2164		- tcg_gen_qemu_ld_i32(ccr, cpu_sp, 0, MO_32 \| MO_SIGN \| MO_TE);
	2218	+ tcg_gen_qemu_ld_i32(ccr, cpu_sp, 0, MO_32 \| MO_TE);
2165	2219	tcg_gen_addi_i32(cpu_sp, cpu_sp, 4);
2166	2220	tcg_gen_extract_i32(cpu_pc, ccr, 0, 24);
2167	2221	tcg_gen_extract_i32(ccr, ccr, 24, 8);
2168		- gen_set_ccr(cpu_env, ccr);
	2222	+ gen_helper_set_ccr(cpu_env, ccr);
2169	2223	ctx->base.is_jmp = DISAS_EXIT;
2170	2224	tcg_temp_free(ccr);
2171	2225	return true;

		@@ -2186,8 +2240,8 @@ static bool trans_TRAPA(DisasContext ctx, arg_TRAPA a)
2186	2240
2187	2241	static bool trans_SLEEP(DisasContext ctx, arg_SLEEP a)
2188	2242	{
2189		- tcg_gen_movi_i32(cpu_pc, ctx->base.pc->next);
2190		- gen_helper_wait(cpu_env);
	2243	+ tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);
	2244	+ gen_helper_sleep(cpu_env);
2191	2245	return true;
2192	2246	}
2193	2247

		@@ -2195,7 +2249,7 @@ static bool trans_LDC_i(DisasContext ctx, arg_LDC_i a)
2195	2249	{
2196	2250	TCGv val;
2197	2251	val = tcg_const_i32(a->imm);
2198		- gen_set_ccr(cpu_env, val);
	2252	+ gen_helper_set_ccr(cpu_env, val);
2199	2253	ctx->base.is_jmp = DISAS_UPDATE;
2200	2254	tcg_temp_free(val);
2201	2255	return true;

		@@ -2206,7 +2260,7 @@ static bool trans_LDC_r(DisasContext ctx, arg_LDC_r a)
2206	2260	TCGv val;
2207	2261	val = tcg_temp_new();
2208	2262	h8300_gen_reg_ldb(a->r, val);
2209		- gen_set_ccr(cpu_env, val);
	2263	+ gen_helper_set_ccr(cpu_env, val);
2210	2264	ctx->base.is_jmp = DISAS_UPDATE;
2211	2265	tcg_temp_free(val);
2212	2266	return true;

		@@ -2217,10 +2271,10 @@ static bool trans_LDC_m(DisasContext ctx, arg_LDC_m a)
2217	2271	TCGv val, mem;
2218	2272	val = tcg_temp_new();
2219	2273	mem = tcg_temp_new();
2220		- tcg_gen_addi_i32(mem, cpu_regs[a->er], a->dsp);
2221		- tcg_gen_qemu_ldu_i32(val, mem, 0, MO_16 \| MO_SIGN \| MO_TE);
	2274	+ tcg_gen_addi_i32(mem, cpu_regs[a->r], a->dsp);
	2275	+ tcg_gen_qemu_ld_i32(val, mem, 0, MO_16 \| MO_TE);
2222	2276	tcg_gen_shri_i32(val, val, 8);
2223		- gen_set_ccr(cpu_env, val);
	2277	+ gen_helper_set_ccr(cpu_env, val);
2224	2278	ctx->base.is_jmp = DISAS_UPDATE;
2225	2279	tcg_temp_free(val);
2226	2280	tcg_temp_free(mem);

		@@ -2231,10 +2285,10 @@ static bool trans_LDC_mp(DisasContext ctx, arg_LDC_mp a)
2231	2285	{
2232	2286	TCGv val;
2233	2287	val = tcg_temp_new();
2234		- tcg_gen_qemu_ldu_i32(val, cpu_regs[a->er], 0, MO_16 \| MO_SIGN \| MO_TE);
2235		- tcg_gen_addi_i32(cpu_regs[a->er], cpu_regs[a->er], 4);
	2288	+ tcg_gen_qemu_ld_i32(val, cpu_regs[a->r], 0, MO_16 \| MO_TE);
	2289	+ tcg_gen_addi_i32(cpu_regs[a->r], cpu_regs[a->r], 4);
2236	2290	tcg_gen_shri_i32(val, val, 8);
2237		- gen_set_ccr(cpu_env, val);
	2291	+ gen_helper_set_ccr(cpu_env, val);
2238	2292	ctx->base.is_jmp = DISAS_UPDATE;
2239	2293	tcg_temp_free(val);
2240	2294	return true;

		@@ -2245,9 +2299,9 @@ static bool trans_LDC_a(DisasContext ctx, arg_LDC_a a)
2245	2299	TCGv val, mem;
2246	2300	val = tcg_temp_new();
2247	2301	mem = tcg_const_i32(a->abs & 0x00ffffff);
2248		- tcg_gen_qemu_ldu_i32(val, mem, 0, MO_16 \| MO_SIGN \| MO_TE);
	2302	+ tcg_gen_qemu_ld_i32(val, mem, 0, MO_16 \| MO_TE);
2249	2303	tcg_gen_shri_i32(val, val, 8);
2250		- gen_set_ccr(cpu_env, val);
	2304	+ gen_helper_set_ccr(cpu_env, val);
2251	2305	ctx->base.is_jmp = DISAS_UPDATE;
2252	2306	tcg_temp_free(val);
2253	2307	tcg_temp_free(mem);

		@@ -2259,17 +2313,17 @@ static bool trans_LDCSTC_m(DisasContext ctx, arg_LDCSTC_m a)
2259	2313	TCGv val, mem;
2260	2314	val = tcg_temp_new();
2261	2315	mem = tcg_temp_new();
2262		- tcg_gen_addi_i32(mem, cpu_regs[a->er], a->dsp);
	2316	+ tcg_gen_addi_i32(mem, cpu_regs[a->r], a->dsp);
2263	2317	tcg_gen_andi_i32(mem, mem, 0x00ffffff);
2264	2318	if (a->ldst == 2) {
2265		- tcg_gen_qemu_ldu_i32(val, mem, 0, MO_16 \| MO_SIGN \| MO_TE);
	2319	+ tcg_gen_qemu_ld_i32(val, mem, 0, MO_16 \| MO_TE);
2266	2320	tcg_gen_shri_i32(val, val, 8);
2267		- gen_set_ccr(cpu_env, val);
	2321	+ gen_helper_set_ccr(cpu_env, val);
2268	2322	ctx->base.is_jmp = DISAS_UPDATE;
2269	2323	} else {
2270		- gen_get_ccr(val, cpu_env);
	2324	+ gen_helper_get_ccr(val, cpu_env);
2271	2325	tcg_gen_shli_i32(val, val, 8);
2272		- tcg_gen_qemu_st_i32(val, mem, 0, MO_16 \| MO_SIGN \| MO_TE);
	2326	+ tcg_gen_qemu_st_i32(val, mem, 0, MO_16 \| MO_TE);
2273	2327	}
2274	2328	tcg_temp_free(val);
2275	2329	tcg_temp_free(mem);

		@@ -2280,7 +2334,7 @@ static bool trans_STC_r(DisasContext ctx, arg_STC_r a)
2280	2334	{
2281	2335	TCGv val;
2282	2336	val = tcg_temp_new();
2283		- gen_get_ccr(val, cpu_env);
	2337	+ gen_helper_get_ccr(val, cpu_env);
2284	2338	h8300_gen_reg_ldb(a->r, val);
2285	2339	tcg_temp_free(val);
2286	2340	return true;

		@@ -2291,10 +2345,10 @@ static bool trans_STC_m(DisasContext ctx, arg_STC_m a)
2291	2345	TCGv val, mem;
2292	2346	val = tcg_temp_new();
2293	2347	mem = tcg_temp_new();
2294		- tcg_gen_addi_i32(mem, cpu_regs[a->er], a->dsp);
2295		- gen_get_ccr(val, cpu_env);
	2348	+ tcg_gen_addi_i32(mem, cpu_regs[a->r], a->dsp);
	2349	+ gen_helper_get_ccr(val, cpu_env);
2296	2350	tcg_gen_shli_i32(val, val, 8);
2297		- tcg_gen_qemu_st_i32(val, mem, 0, MO_16 \| MO_SIGN \| MO_TE);
	2351	+ tcg_gen_qemu_st_i32(val, mem, 0, MO_16 \| MO_TE);
2298	2352	tcg_temp_free(val);
2299	2353	tcg_temp_free(mem);
2300	2354	return true;

		@@ -2304,10 +2358,10 @@ static bool trans_STC_mp(DisasContext ctx, arg_STC_mp a)
2304	2358	{
2305	2359	TCGv val;
2306	2360	val = tcg_temp_new();
2307		- gen_get_ccr(val, cpu_env);
	2361	+ gen_helper_get_ccr(val, cpu_env);
2308	2362	tcg_gen_shli_i32(val, val, 8);
2309		- tcg_gen_subi_i32(cpu_regs[a->er], cpu_regs[a->er], 4);
2310		- tcg_gen_qemu_st_i32(val, cpu_regs[a->er], 0, MO_16 \| MO_SIGN \| MO_TE);
	2363	+ tcg_gen_subi_i32(cpu_regs[a->r], cpu_regs[a->r], 4);
	2364	+ tcg_gen_qemu_st_i32(val, cpu_regs[a->r], 0, MO_16 \| MO_TE);
2311	2365	tcg_temp_free(val);
2312	2366	return true;
2313	2367	}

		@@ -2317,9 +2371,9 @@ static bool trans_STC_a(DisasContext ctx, arg_STC_a a)
2317	2371	TCGv val, mem;
2318	2372	val = tcg_temp_new();
2319	2373	mem = tcg_const_i32(a->abs & 0x00ffffff);
2320		- gen_get_ccr(val, cpu_env);
	2374	+ gen_helper_get_ccr(val, cpu_env);
2321	2375	tcg_gen_shli_i32(val, val, 8);
2322		- tcg_gen_qemu_st_i32(val, mem, 0, MO_16 \| MO_SIGN \| MO_TE);
	2376	+ tcg_gen_qemu_st_i32(val, mem, 0, MO_16 \| MO_TE);
2323	2377	tcg_temp_free(val);
2324	2378	tcg_temp_free(mem);
2325	2379	return true;

		@@ -2329,9 +2383,9 @@ static bool trans_ANDC(DisasContext ctx, arg_ANDC a)
2329	2383	{
2330	2384	TCGv val;
2331	2385	val = tcg_temp_new();
2332		- gen_get_ccr(val, cpu_env);
2333		- gen_andi_i32(val, val, a->imm);
2334		- gen_set_ccr(cpu_env, val);
	2386	+ gen_helper_get_ccr(val, cpu_env);
	2387	+ tcg_gen_andi_i32(val, val, a->imm);
	2388	+ gen_helper_set_ccr(cpu_env, val);
2335	2389	ctx->base.is_jmp = DISAS_UPDATE;
2336	2390	tcg_temp_free(val);
2337	2391	return true;

		@@ -2341,9 +2395,9 @@ static bool trans_ORC(DisasContext ctx, arg_ORC a)
2341	2395	{
2342	2396	TCGv val;
2343	2397	val = tcg_temp_new();
2344		- gen_get_ccr(val, cpu_env);
2345		- gen_ori_i32(val, val, a->imm);
2346		- gen_set_ccr(cpu_env, val);
	2398	+ gen_helper_get_ccr(val, cpu_env);
	2399	+ tcg_gen_ori_i32(val, val, a->imm);
	2400	+ gen_helper_set_ccr(cpu_env, val);
2347	2401	ctx->base.is_jmp = DISAS_UPDATE;
2348	2402	tcg_temp_free(val);
2349	2403	return true;

		@@ -2353,9 +2407,9 @@ static bool trans_XORC(DisasContext ctx, arg_XORC a)
2353	2407	{
2354	2408	TCGv val;
2355	2409	val = tcg_temp_new();
2356		- gen_get_ccr(val, cpu_env);
2357		- gen_xori_i32(val, val, a->imm);
2358		- gen_set_ccr(cpu_env, val);
	2410	+ gen_helper_get_ccr(val, cpu_env);
	2411	+ tcg_gen_xori_i32(val, val, a->imm);
	2412	+ gen_helper_set_ccr(cpu_env, val);
2359	2413	ctx->base.is_jmp = DISAS_UPDATE;
2360	2414	tcg_temp_free(val);
2361	2415	return true;

		@@ -2366,13 +2420,13 @@ static bool trans_NOP(DisasContext ctx, arg_NOP a)
2366	2420	return true;
2367	2421	}
2368	2422
2369		-static bool trans_EEPMOVB(DisasContext ctx, arg_EEPMOVB a)
	2423	+static bool trans_EEPMOV_B(DisasContext ctx, arg_EEPMOV_B a)
2370	2424	{
2371	2425	gen_helper_eepmovb(cpu_env);
2372	2426	return true;
2373	2427	}
2374	2428
2375		-static bool trans_EEPMOVW(DisasContext ctx, arg_EEPMOVW a)
	2429	+static bool trans_EEPMOV_W(DisasContext ctx, arg_EEPMOV_W a)
2376	2430	{
2377	2431	gen_helper_eepmovw(cpu_env);
2378	2432	return true;

		@@ -2417,7 +2471,8 @@ static void h8300_tr_translate_insn(DisasContextBase dcbase, CPUState cs)
2417	2471	ctx->pc = ctx->base.pc_next;
2418	2472	insn = decode_load(ctx);
2419	2473	if (!decode(ctx, insn)) {
2420		- gen_helper_raise_illegal_instruction(cpu_env);
	2474	+ qemu_log_mask(LOG_GUEST_ERROR,
	2475	+ "Unknwon instruction at 0x%06x", ctx->pc);
2421	2476	}
2422	2477	}
2423	2478

		@@ -2495,12 +2550,12 @@ void h8300_translate_init(void)
2495	2550	regnames[i]);
2496	2551	}
2497	2552	ALLOC_REGISTER(pc, "PC");
2498		- ALLOC_REGISTER(psw_v, "CCR(V)");
2499		- ALLOC_REGISTER(psw_n, "CCR(N)");
2500		- ALLOC_REGISTER(psw_z, "CCR(Z)");
2501		- ALLOC_REGISTER(psw_c, "CCR(C)");
2502		- ALLOC_REGISTER(psw_u, "CCR(U)");
2503		- ALLOC_REGISTER(psw_h, "CCR(H)");
2504		- ALLOC_REGISTER(psw_ui, "CCR(UI)");
2505		- ALLOC_REGISTER(psw_i, "CCR(I)");
	2553	+ ALLOC_REGISTER(ccr_v, "CCR(V)");
	2554	+ ALLOC_REGISTER(ccr_n, "CCR(N)");
	2555	+ ALLOC_REGISTER(ccr_z, "CCR(Z)");
	2556	+ ALLOC_REGISTER(ccr_c, "CCR(C)");
	2557	+ ALLOC_REGISTER(ccr_u, "CCR(U)");
	2558	+ ALLOC_REGISTER(ccr_h, "CCR(H)");
	2559	+ ALLOC_REGISTER(ccr_ui, "CCR(UI)");
	2560	+ ALLOC_REGISTER(ccr_i, "CCR(I)");
2506	2561	}

--- a/target/rx/translate.c

+++ b/target/rx/translate.c

		@@ -1087,6 +1087,7 @@ static void rx_sub(TCGv ret, TCGv arg1, TCGv arg2)
1087	1087	tcg_gen_mov_i32(ret, cpu_psw_s);
1088	1088	}
1089	1089	}
	1090	+
1090	1091	static void rx_cmp(TCGv dummy, TCGv arg1, TCGv arg2)
1091	1092	{
1092	1093	rx_sub(NULL, arg1, arg2);

qemu RX Fork