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Revision9c489ea6bed134fecfd556b439c68bba48fbe102 (tree)
Time2017-07-20 06:45:16
AuthorLluís Vilanova <vilanova@ac.u...>
CommiterRichard Henderson

Log Message

tcg: Pass generic CPUState to gen_intermediate_code()

Needed to implement a target-agnostic gen_intermediate_code()
in the future.

Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Alex Benneé <alex.benee@linaro.org>
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
Message-Id: <150002025498.22386.18051908483085660588.stgit@frigg.lan>
Signed-off-by: Richard Henderson <rth@twiddle.net>

Change Summary

Incremental Difference

--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -1280,7 +1280,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
12801280 tcg_func_start(&tcg_ctx);
12811281
12821282 tcg_ctx.cpu = ENV_GET_CPU(env);
1283- gen_intermediate_code(env, tb);
1283+ gen_intermediate_code(cpu, tb);
12841284 tcg_ctx.cpu = NULL;
12851285
12861286 trace_translate_block(tb, tb->pc, tb->tc_ptr);
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -66,7 +66,7 @@ typedef ram_addr_t tb_page_addr_t;
6666
6767 #include "qemu/log.h"
6868
69-void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb);
69+void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb);
7070 void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,
7171 target_ulong *data);
7272
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -2952,10 +2952,9 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
29522952 return ret;
29532953 }
29542954
2955-void gen_intermediate_code(CPUAlphaState *env, struct TranslationBlock *tb)
2955+void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
29562956 {
2957- AlphaCPU *cpu = alpha_env_get_cpu(env);
2958- CPUState *cs = CPU(cpu);
2957+ CPUAlphaState *env = cs->env_ptr;
29592958 DisasContext ctx, *ctxp = &ctx;
29602959 target_ulong pc_start;
29612960 target_ulong pc_mask;
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -11179,10 +11179,10 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s)
1117911179 free_tmp_a64(s);
1118011180 }
1118111181
11182-void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb)
11182+void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb)
1118311183 {
11184- CPUState *cs = CPU(cpu);
11185- CPUARMState *env = &cpu->env;
11184+ CPUARMState *env = cs->env_ptr;
11185+ ARMCPU *cpu = arm_env_get_cpu(env);
1118611186 DisasContext dc1, *dc = &dc1;
1118711187 target_ulong pc_start;
1118811188 target_ulong next_page_start;
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -11795,10 +11795,10 @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
1179511795 }
1179611796
1179711797 /* generate intermediate code for basic block 'tb'. */
11798-void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
11798+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
1179911799 {
11800+ CPUARMState *env = cs->env_ptr;
1180011801 ARMCPU *cpu = arm_env_get_cpu(env);
11801- CPUState *cs = CPU(cpu);
1180211802 DisasContext dc1, *dc = &dc1;
1180311803 target_ulong pc_start;
1180411804 target_ulong next_page_start;
@@ -11812,7 +11812,7 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
1181211812 * the A32/T32 complexity to do with conditional execution/IT blocks/etc.
1181311813 */
1181411814 if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {
11815- gen_intermediate_code_a64(cpu, tb);
11815+ gen_intermediate_code_a64(cs, tb);
1181611816 return;
1181711817 }
1181811818
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -149,7 +149,7 @@ static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
149149
150150 #ifdef TARGET_AARCH64
151151 void a64_translate_init(void);
152-void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb);
152+void gen_intermediate_code_a64(CPUState *cpu, TranslationBlock *tb);
153153 void gen_a64_set_pc_im(uint64_t val);
154154 void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
155155 fprintf_function cpu_fprintf, int flags);
@@ -158,7 +158,7 @@ static inline void a64_translate_init(void)
158158 {
159159 }
160160
161-static inline void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb)
161+static inline void gen_intermediate_code_a64(CPUState *cpu, TranslationBlock *tb)
162162 {
163163 }
164164
--- a/target/cris/translate.c
+++ b/target/cris/translate.c
@@ -3080,10 +3080,9 @@ static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc)
30803080 */
30813081
30823082 /* generate intermediate code for basic block 'tb'. */
3083-void gen_intermediate_code(CPUCRISState *env, struct TranslationBlock *tb)
3083+void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
30843084 {
3085- CRISCPU *cpu = cris_env_get_cpu(env);
3086- CPUState *cs = CPU(cpu);
3085+ CPUCRISState *env = cs->env_ptr;
30873086 uint32_t pc_start;
30883087 unsigned int insn_len;
30893088 struct DisasContext ctx;
@@ -3105,7 +3104,7 @@ void gen_intermediate_code(CPUCRISState *env, struct TranslationBlock *tb)
31053104 * delayslot, like in real hw.
31063105 */
31073106 pc_start = tb->pc & ~1;
3108- dc->cpu = cpu;
3107+ dc->cpu = cris_env_get_cpu(env);
31093108 dc->tb = tb;
31103109
31113110 dc->is_jmp = DISAS_NEXT;
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -3740,10 +3740,9 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
37403740 return gen_illegal(ctx);
37413741 }
37423742
3743-void gen_intermediate_code(CPUHPPAState *env, struct TranslationBlock *tb)
3743+void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
37443744 {
3745- HPPACPU *cpu = hppa_env_get_cpu(env);
3746- CPUState *cs = CPU(cpu);
3745+ CPUHPPAState *env = cs->env_ptr;
37473746 DisasContext ctx;
37483747 ExitStatus ret;
37493748 int num_insns, max_insns, i;
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -8378,10 +8378,9 @@ void tcg_x86_init(void)
83788378 }
83798379
83808380 /* generate intermediate code for basic block 'tb'. */
8381-void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb)
8381+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
83828382 {
8383- X86CPU *cpu = x86_env_get_cpu(env);
8384- CPUState *cs = CPU(cpu);
8383+ CPUX86State *env = cs->env_ptr;
83858384 DisasContext dc1, *dc = &dc1;
83868385 target_ulong pc_ptr;
83878386 uint32_t flags;
--- a/target/lm32/translate.c
+++ b/target/lm32/translate.c
@@ -1044,10 +1044,10 @@ static inline void decode(DisasContext *dc, uint32_t ir)
10441044 }
10451045
10461046 /* generate intermediate code for basic block 'tb'. */
1047-void gen_intermediate_code(CPULM32State *env, struct TranslationBlock *tb)
1047+void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
10481048 {
1049+ CPULM32State *env = cs->env_ptr;
10491050 LM32CPU *cpu = lm32_env_get_cpu(env);
1050- CPUState *cs = CPU(cpu);
10511051 struct DisasContext ctx, *dc = &ctx;
10521052 uint32_t pc_start;
10531053 uint32_t next_page_start;
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -5518,10 +5518,9 @@ static void disas_m68k_insn(CPUM68KState * env, DisasContext *s)
55185518 }
55195519
55205520 /* generate intermediate code for basic block 'tb'. */
5521-void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb)
5521+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
55225522 {
5523- M68kCPU *cpu = m68k_env_get_cpu(env);
5524- CPUState *cs = CPU(cpu);
5523+ CPUM68KState *env = cs->env_ptr;
55255524 DisasContext dc1, *dc = &dc1;
55265525 target_ulong pc_start;
55275526 int pc_offset;
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1625,10 +1625,10 @@ static inline void decode(DisasContext *dc, uint32_t ir)
16251625 }
16261626
16271627 /* generate intermediate code for basic block 'tb'. */
1628-void gen_intermediate_code(CPUMBState *env, struct TranslationBlock *tb)
1628+void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
16291629 {
1630+ CPUMBState *env = cs->env_ptr;
16301631 MicroBlazeCPU *cpu = mb_env_get_cpu(env);
1631- CPUState *cs = CPU(cpu);
16321632 uint32_t pc_start;
16331633 struct DisasContext ctx;
16341634 struct DisasContext *dc = &ctx;
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -19888,10 +19888,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
1988819888 }
1988919889 }
1989019890
19891-void gen_intermediate_code(CPUMIPSState *env, struct TranslationBlock *tb)
19891+void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
1989219892 {
19893- MIPSCPU *cpu = mips_env_get_cpu(env);
19894- CPUState *cs = CPU(cpu);
19893+ CPUMIPSState *env = cs->env_ptr;
1989519894 DisasContext ctx;
1989619895 target_ulong pc_start;
1989719896 target_ulong next_page_start;
--- a/target/moxie/translate.c
+++ b/target/moxie/translate.c
@@ -822,10 +822,10 @@ static int decode_opc(MoxieCPU *cpu, DisasContext *ctx)
822822 }
823823
824824 /* generate intermediate code for basic block 'tb'. */
825-void gen_intermediate_code(CPUMoxieState *env, struct TranslationBlock *tb)
825+void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
826826 {
827+ CPUMoxieState *env = cs->env_ptr;
827828 MoxieCPU *cpu = moxie_env_get_cpu(env);
828- CPUState *cs = CPU(cpu);
829829 DisasContext ctx;
830830 target_ulong pc_start;
831831 int num_insns, max_insns;
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -799,10 +799,9 @@ static void gen_exception(DisasContext *dc, uint32_t excp)
799799 }
800800
801801 /* generate intermediate code for basic block 'tb'. */
802-void gen_intermediate_code(CPUNios2State *env, TranslationBlock *tb)
802+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
803803 {
804- Nios2CPU *cpu = nios2_env_get_cpu(env);
805- CPUState *cs = CPU(cpu);
804+ CPUNios2State *env = cs->env_ptr;
806805 DisasContext dc1, *dc = &dc1;
807806 int num_insns;
808807 int max_insns;
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -1518,10 +1518,10 @@ static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu)
15181518 }
15191519 }
15201520
1521-void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb)
1521+void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
15221522 {
1523+ CPUOpenRISCState *env = cs->env_ptr;
15231524 OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
1524- CPUState *cs = CPU(cpu);
15251525 struct DisasContext ctx, *dc = &ctx;
15261526 uint32_t pc_start;
15271527 uint32_t next_page_start;
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7196,10 +7196,9 @@ void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
71967196 }
71977197
71987198 /*****************************************************************************/
7199-void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
7199+void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
72007200 {
7201- PowerPCCPU *cpu = ppc_env_get_cpu(env);
7202- CPUState *cs = CPU(cpu);
7201+ CPUPPCState *env = cs->env_ptr;
72037202 DisasContext ctx, *ctxp = &ctx;
72047203 opc_handler_t **table, *handler;
72057204 target_ulong pc_start;
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -5853,10 +5853,9 @@ static ExitStatus translate_one(CPUS390XState *env, DisasContext *s)
58535853 return ret;
58545854 }
58555855
5856-void gen_intermediate_code(CPUS390XState *env, struct TranslationBlock *tb)
5856+void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
58575857 {
5858- S390CPU *cpu = s390_env_get_cpu(env);
5859- CPUState *cs = CPU(cpu);
5858+ CPUS390XState *env = cs->env_ptr;
58605859 DisasContext dc;
58615860 target_ulong pc_start;
58625861 uint64_t next_page_start;
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -2230,10 +2230,9 @@ static int decode_gusa(DisasContext *ctx, CPUSH4State *env, int *pmax_insns)
22302230 }
22312231 #endif
22322232
2233-void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb)
2233+void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
22342234 {
2235- SuperHCPU *cpu = sh_env_get_cpu(env);
2236- CPUState *cs = CPU(cpu);
2235+ CPUSH4State *env = cs->env_ptr;
22372236 DisasContext ctx;
22382237 target_ulong pc_start;
22392238 int num_insns;
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -5739,10 +5739,9 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
57395739 }
57405740 }
57415741
5742-void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
5742+void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
57435743 {
5744- SPARCCPU *cpu = sparc_env_get_cpu(env);
5745- CPUState *cs = CPU(cpu);
5744+ CPUSPARCState *env = cs->env_ptr;
57465745 target_ulong pc_start, last_pc;
57475746 DisasContext dc1, *dc = &dc1;
57485747 int num_insns;
--- a/target/tilegx/translate.c
+++ b/target/tilegx/translate.c
@@ -2370,12 +2370,11 @@ static void translate_one_bundle(DisasContext *dc, uint64_t bundle)
23702370 }
23712371 }
23722372
2373-void gen_intermediate_code(CPUTLGState *env, struct TranslationBlock *tb)
2373+void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
23742374 {
2375- TileGXCPU *cpu = tilegx_env_get_cpu(env);
2375+ CPUTLGState *env = cs->env_ptr;
23762376 DisasContext ctx;
23772377 DisasContext *dc = &ctx;
2378- CPUState *cs = CPU(cpu);
23792378 uint64_t pc_start = tb->pc;
23802379 uint64_t next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
23812380 int num_insns = 0;
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -8782,10 +8782,9 @@ static void decode_opc(CPUTriCoreState *env, DisasContext *ctx, int *is_branch)
87828782 }
87838783 }
87848784
8785-void gen_intermediate_code(CPUTriCoreState *env, struct TranslationBlock *tb)
8785+void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
87868786 {
8787- TriCoreCPU *cpu = tricore_env_get_cpu(env);
8788- CPUState *cs = CPU(cpu);
8787+ CPUTriCoreState *env = cs->env_ptr;
87898788 DisasContext ctx;
87908789 target_ulong pc_start;
87918790 int num_insns, max_insns;
--- a/target/unicore32/translate.c
+++ b/target/unicore32/translate.c
@@ -1869,10 +1869,9 @@ static void disas_uc32_insn(CPUUniCore32State *env, DisasContext *s)
18691869 }
18701870
18711871 /* generate intermediate code for basic block 'tb'. */
1872-void gen_intermediate_code(CPUUniCore32State *env, TranslationBlock *tb)
1872+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
18731873 {
1874- UniCore32CPU *cpu = uc32_env_get_cpu(env);
1875- CPUState *cs = CPU(cpu);
1874+ CPUUniCore32State *env = cs->env_ptr;
18761875 DisasContext dc1, *dc = &dc1;
18771876 target_ulong pc_start;
18781877 uint32_t next_page_start;
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -3117,10 +3117,9 @@ static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc)
31173117 }
31183118 }
31193119
3120-void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb)
3120+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
31213121 {
3122- XtensaCPU *cpu = xtensa_env_get_cpu(env);
3123- CPUState *cs = CPU(cpu);
3122+ CPUXtensaState *env = cs->env_ptr;
31243123 DisasContext dc;
31253124 int insn_count = 0;
31263125 int max_insns = tb->cflags & CF_COUNT_MASK;