Commit: f2f1dde75160cac6ede330f3db50dc817d01a2d6 - qemu (git)

Commit MetaInfo

• Revision: f2f1dde75160cac6ede330f3db50dc817d01a2d6 (tree)
• Time: 2018-03-28 13:45:16
• Author: Richard Henderson <richard.henderson@lina...>
• Commiter: Richard Henderson

Log Message

tcg: Mark muluh_i64 and mulsh_i64 as 64-bit ops

Failure to do so results in the tcg optimizer sign-extending
any constant fold from 32-bits. This turns out to be visible
in the RISC-V testsuite using a host that emits these opcodes
(e.g. any non-x86_64).

Reported-by: Michael Clark <[e-mail]>
Reviewed-by: Emilio G. Cota <[e-mail]>
Reviewed-by: Philippe Mathieu-Daudé <[e-mail]>
Signed-off-by: Richard Henderson <[e-mail]>

Change Summary

• modified: tcg/tcg-opc.h

Incremental Difference

--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -182,8 +182,8 @@ DEF(add2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_add2_i64))
 DEF(sub2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_sub2_i64))
 DEF(mulu2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulu2_i64))
 DEF(muls2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muls2_i64))
-DEF(muluh_i64, 1, 2, 0, IMPL(TCG_TARGET_HAS_muluh_i64))
-DEF(mulsh_i64, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i64))
+DEF(muluh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muluh_i64))
+DEF(mulsh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulsh_i64))
 
 #define TLADDR_ARGS  (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? 1 : 2)
 #define DATA64_ARGS  (TCG_TARGET_REG_BITS == 64 ? 1 : 2)