Revision | 8de13a8b174d53904ba76a81499caf66f328ddac (tree) |
---|---|
Time | 2016-06-01 00:07:11 |
Author | Yoshinori Sato <ysato@user...> |
Commiter | Yoshinori Sato |
sh: TAC T-SH7706LSR MMC support
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
@@ -12,9 +12,14 @@ | ||
12 | 12 | */ |
13 | 13 | |
14 | 14 | #include <common.h> |
15 | +#include <mmc.h> | |
16 | +#include <spi.h> | |
15 | 17 | #include <asm/io.h> |
16 | 18 | #include <asm/processor.h> |
17 | 19 | |
20 | +#define SCPCR (0xa4000116) | |
21 | +#define SCPDR (0xa4000136) | |
22 | + | |
18 | 23 | int board_early_init_f(void) |
19 | 24 | { |
20 | 25 | writew(0x2980, BCR2); |
@@ -29,3 +34,25 @@ int dram_init(void) | ||
29 | 34 | gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; |
30 | 35 | return 0; |
31 | 36 | } |
37 | + | |
38 | +int board_mmc_init(bd_t *bis) | |
39 | +{ | |
40 | + writeb(readb(SCPDR) | 0x02, SCPDR); | |
41 | + writew((readw(SCPCR) & ~0x0c) | 0x04, SCPCR); | |
42 | + return 0; | |
43 | +} | |
44 | + | |
45 | +int spi_cs_is_valid(unsigned int bus, unsigned int cs) | |
46 | +{ | |
47 | + return bus == 0 && cs == 0; | |
48 | +} | |
49 | + | |
50 | +void spi_cs_activate(struct spi_slave *slave) | |
51 | +{ | |
52 | + writeb(readb(SCPDR) & ~0x02, SCPDR); | |
53 | +} | |
54 | + | |
55 | +void spi_cs_deactivate(struct spi_slave *slave) | |
56 | +{ | |
57 | + writeb(readb(SCPDR) | 0x02, SCPDR); | |
58 | +} |
@@ -43,6 +43,7 @@ obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o | ||
43 | 43 | obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o |
44 | 44 | obj-$(CONFIG_SH_SPI) += sh_spi.o |
45 | 45 | obj-$(CONFIG_SH_QSPI) += sh_qspi.o |
46 | +obj-$(CONFIG_TAC_SSU) += tac_ssu.o | |
46 | 47 | obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o |
47 | 48 | obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o |
48 | 49 | obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o |
@@ -0,0 +1,81 @@ | ||
1 | +/* | |
2 | + * Copyright (c) 2016 Yoshinori Sato <ysato@users.sourceforge.jp> | |
3 | + * | |
4 | + * SPDX-License-Identifier: GPL-2.0+ | |
5 | + */ | |
6 | + | |
7 | +#include <common.h> | |
8 | +#include <errno.h> | |
9 | +#include <spi.h> | |
10 | +#include <asm/io.h> | |
11 | + | |
12 | +#define DR (0xb0008000) | |
13 | +#define BR (0xb0008004) | |
14 | +#define SR (0xb0008002) | |
15 | + | |
16 | +DECLARE_GLOBAL_DATA_PTR; | |
17 | + | |
18 | +struct ssu_spi_slave { | |
19 | + struct spi_slave slave; | |
20 | +}; | |
21 | + | |
22 | +void spi_set_speed(struct spi_slave *slave, uint hz) | |
23 | +{ | |
24 | +} | |
25 | + | |
26 | +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, | |
27 | + const void *dout, void *din, unsigned long flags) | |
28 | +{ | |
29 | + const char *out = dout; | |
30 | + char *in = din; | |
31 | + unsigned int j; | |
32 | + | |
33 | + if (flags & SPI_XFER_BEGIN) | |
34 | + spi_cs_activate(slave); | |
35 | + | |
36 | + for (j = bitlen / 8; j > 0; j--) { | |
37 | + if (out) { | |
38 | + writeb(*out++, DR); | |
39 | + while(!(readb(SR) & 0x80)); | |
40 | + } | |
41 | + if (in) { | |
42 | + while(!(readb(SR) & 0x80)); | |
43 | + *in++ = readb(BR); | |
44 | + } | |
45 | + } | |
46 | + if (out) | |
47 | + readb(BR); | |
48 | + | |
49 | + if (flags & SPI_XFER_END) | |
50 | + spi_cs_deactivate(slave); | |
51 | + | |
52 | + return 0; | |
53 | +} | |
54 | + | |
55 | +void spi_init(void) | |
56 | +{ | |
57 | +} | |
58 | + | |
59 | +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, | |
60 | + unsigned int max_hz, unsigned int mode) | |
61 | +{ | |
62 | + struct ssu_spi_slave *ss; | |
63 | + ss = spi_alloc_slave(struct ssu_spi_slave, bus, cs); | |
64 | + if (!ss) | |
65 | + return NULL; | |
66 | + return &ss->slave; | |
67 | +} | |
68 | + | |
69 | +void spi_free_slave(struct spi_slave *slave) | |
70 | +{ | |
71 | +} | |
72 | + | |
73 | +int spi_claim_bus(struct spi_slave *slave) | |
74 | +{ | |
75 | + return 0; | |
76 | +} | |
77 | + | |
78 | +void spi_release_bus(struct spi_slave *slave) | |
79 | +{ | |
80 | + /* Nothing to do */ | |
81 | +} |
@@ -89,4 +89,11 @@ | ||
89 | 89 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 |
90 | 90 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 |
91 | 91 | |
92 | +#define CONFIG_MMC | |
93 | +#define CONFIG_MMC_SPI | |
94 | +#define CONFIG_CMD_MMC_SPI | |
95 | +#define CONFIG_GENERIC_MMC | |
96 | +#define CONFIG_DOS_PARTITION | |
97 | +#define CONFIG_TAC_SSU | |
98 | + | |
92 | 99 | #endif /* __SHMIN_H */ |