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Revisiona7069ddfa9b369e8bed449806a4422ad751246ab (tree)
Time2014-02-07 22:14:33
AuthorAlexey Brodkin <Alexey.Brodkin@syno...>
CommiterTom Rini

Log Message

arc: add AXS101 board support

AXS101 is a new generation of devlopment boards from Synopsys that houses
ASIC with ARC700 and lots of DesignWare peripherals:

  • DW APB UART
  • DW Mobile Storage (MMC/SD)
  • DW I2C
  • DW GMAC

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Francois Bedard <fbedard@synopsys.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>

Change Summary

Incremental Difference

--- /dev/null
+++ b/board/synopsys/axs101/Makefile
@@ -0,0 +1,8 @@
1+#
2+# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
3+#
4+# SPDX-License-Identifier: GPL-2.0+
5+#
6+
7+obj-y += axs101.o
8+obj-$(CONFIG_CMD_NAND) += nand.o
--- /dev/null
+++ b/board/synopsys/axs101/axs101.c
@@ -0,0 +1,44 @@
1+/*
2+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
3+ *
4+ * SPDX-License-Identifier: GPL-2.0+
5+ */
6+
7+#include <common.h>
8+#include <dwmmc.h>
9+#include <malloc.h>
10+#include <netdev.h>
11+#include <phy.h>
12+
13+DECLARE_GLOBAL_DATA_PTR;
14+
15+int board_mmc_init(bd_t *bis)
16+{
17+ struct dwmci_host *host = NULL;
18+
19+ host = malloc(sizeof(struct dwmci_host));
20+ if (!host) {
21+ printf("dwmci_host malloc fail!\n");
22+ return 1;
23+ }
24+
25+ memset(host, 0, sizeof(struct dwmci_host));
26+ host->name = "Synopsys Mobile storage";
27+ host->ioaddr = (void *)ARC_DWMMC_BASE;
28+ host->buswidth = 4;
29+ host->dev_index = 0;
30+ host->bus_hz = 25000000;
31+
32+ add_dwmci(host, 52000000, 400000);
33+
34+ return 0;
35+}
36+
37+int board_eth_init(bd_t *bis)
38+{
39+ if (designware_initialize(0, ARC_DWGMAC_BASE, 0,
40+ PHY_INTERFACE_MODE_RGMII) >= 0)
41+ return 1;
42+
43+ return 0;
44+}
--- /dev/null
+++ b/board/synopsys/axs101/nand.c
@@ -0,0 +1,226 @@
1+/*
2+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
3+ *
4+ * SPDX-License-Identifier: GPL-2.0+
5+ */
6+
7+#include <bouncebuf.h>
8+#include <common.h>
9+#include <malloc.h>
10+#include <nand.h>
11+#include <asm/io.h>
12+
13+#define BUS_WIDTH 8 /* AXI data bus width in bytes */
14+
15+/* DMA buffer descriptor bits & masks */
16+#define BD_STAT_OWN (1 << 31)
17+#define BD_STAT_BD_FIRST (1 << 3)
18+#define BD_STAT_BD_LAST (1 << 2)
19+#define BD_SIZES_BUFFER1_MASK 0xfff
20+
21+#define BD_STAT_BD_COMPLETE (BD_STAT_BD_FIRST | BD_STAT_BD_LAST)
22+
23+/* Controller command flags */
24+#define B_WFR (1 << 19) /* 1b - Wait for ready */
25+#define B_LC (1 << 18) /* 1b - Last cycle */
26+#define B_IWC (1 << 13) /* 1b - Interrupt when complete */
27+
28+/* NAND cycle types */
29+#define B_CT_ADDRESS (0x0 << 16) /* Address operation */
30+#define B_CT_COMMAND (0x1 << 16) /* Command operation */
31+#define B_CT_WRITE (0x2 << 16) /* Write operation */
32+#define B_CT_READ (0x3 << 16) /* Write operation */
33+
34+enum nand_isr_t {
35+ NAND_ISR_DATAREQUIRED = 0,
36+ NAND_ISR_TXUNDERFLOW,
37+ NAND_ISR_TXOVERFLOW,
38+ NAND_ISR_DATAAVAILABLE,
39+ NAND_ISR_RXUNDERFLOW,
40+ NAND_ISR_RXOVERFLOW,
41+ NAND_ISR_TXDMACOMPLETE,
42+ NAND_ISR_RXDMACOMPLETE,
43+ NAND_ISR_DESCRIPTORUNAVAILABLE,
44+ NAND_ISR_CMDDONE,
45+ NAND_ISR_CMDAVAILABLE,
46+ NAND_ISR_CMDERROR,
47+ NAND_ISR_DATATRANSFEROVER,
48+ NAND_ISR_NONE
49+};
50+
51+enum nand_regs_t {
52+ AC_FIFO = 0, /* address and command fifo */
53+ IDMAC_BDADDR = 0x18, /* idmac descriptor list base address */
54+ INT_STATUS = 0x118, /* interrupt status register */
55+ INT_CLR_STATUS = 0x120, /* interrupt clear status register */
56+};
57+
58+struct nand_bd {
59+ uint32_t status; /* DES0 */
60+ uint32_t sizes; /* DES1 */
61+ uint32_t buffer_ptr0; /* DES2 */
62+ uint32_t buffer_ptr1; /* DES3 */
63+};
64+
65+#define NAND_REG_WRITE(r, v) writel(v, CONFIG_SYS_NAND_BASE + r)
66+#define NAND_REG_READ(r) readl(CONFIG_SYS_NAND_BASE + r)
67+
68+static struct nand_bd *bd; /* DMA buffer descriptors */
69+
70+/**
71+ * axs101_nand_write_buf - write buffer to chip
72+ * @mtd: MTD device structure
73+ * @buf: data buffer
74+ * @len: number of bytes to write
75+ */
76+static uint32_t nand_flag_is_set(uint32_t flag)
77+{
78+ uint32_t reg = NAND_REG_READ(INT_STATUS);
79+
80+ if (reg & (1 << NAND_ISR_CMDERROR))
81+ return 0;
82+
83+ if (reg & (1 << flag)) {
84+ NAND_REG_WRITE(INT_CLR_STATUS, 1 << flag);
85+ return 1;
86+ }
87+
88+ return 0;
89+}
90+
91+/**
92+ * axs101_nand_write_buf - write buffer to chip
93+ * @mtd: MTD device structure
94+ * @buf: data buffer
95+ * @len: number of bytes to write
96+ */
97+static void axs101_nand_write_buf(struct mtd_info *mtd, const u_char *buf,
98+ int len)
99+{
100+ struct bounce_buffer bbstate;
101+
102+ bounce_buffer_start(&bbstate, (void *)buf, len, GEN_BB_READ);
103+
104+ /* Setup buffer descriptor */
105+ writel(BD_STAT_OWN | BD_STAT_BD_COMPLETE, &bd->status);
106+ writel(ALIGN(len, BUS_WIDTH) & BD_SIZES_BUFFER1_MASK, &bd->sizes);
107+ writel(bbstate.bounce_buffer, &bd->buffer_ptr0);
108+ writel(0, &bd->buffer_ptr1);
109+
110+ /* Issue "write" command */
111+ NAND_REG_WRITE(AC_FIFO, B_CT_WRITE | B_WFR | B_IWC | B_LC | (len-1));
112+
113+ /* Wait for NAND command and DMA to complete */
114+ while (!nand_flag_is_set(NAND_ISR_CMDDONE))
115+ ;
116+ while (!nand_flag_is_set(NAND_ISR_TXDMACOMPLETE))
117+ ;
118+
119+ bounce_buffer_stop(&bbstate);
120+}
121+
122+/**
123+ * axs101_nand_read_buf - read chip data into buffer
124+ * @mtd: MTD device structure
125+ * @buf: buffer to store data
126+ * @len: number of bytes to read
127+ */
128+static void axs101_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
129+{
130+ struct bounce_buffer bbstate;
131+
132+ bounce_buffer_start(&bbstate, buf, len, GEN_BB_WRITE);
133+
134+ /* Setup buffer descriptor */
135+ writel(BD_STAT_OWN | BD_STAT_BD_COMPLETE, &bd->status);
136+ writel(ALIGN(len, BUS_WIDTH) & BD_SIZES_BUFFER1_MASK, &bd->sizes);
137+ writel(bbstate.bounce_buffer, &bd->buffer_ptr0);
138+ writel(0, &bd->buffer_ptr1);
139+
140+ /* Issue "read" command */
141+ NAND_REG_WRITE(AC_FIFO, B_CT_READ | B_WFR | B_IWC | B_LC | (len - 1));
142+
143+ /* Wait for NAND command and DMA to complete */
144+ while (!nand_flag_is_set(NAND_ISR_CMDDONE))
145+ ;
146+ while (!nand_flag_is_set(NAND_ISR_RXDMACOMPLETE))
147+ ;
148+
149+ bounce_buffer_stop(&bbstate);
150+}
151+
152+/**
153+ * axs101_nand_read_byte - read one byte from the chip
154+ * @mtd: MTD device structure
155+ */
156+static u_char axs101_nand_read_byte(struct mtd_info *mtd)
157+{
158+ u8 byte;
159+
160+ axs101_nand_read_buf(mtd, (uchar *)&byte, sizeof(byte));
161+ return byte;
162+}
163+
164+/**
165+ * axs101_nand_read_word - read one word from the chip
166+ * @mtd: MTD device structure
167+ */
168+static u16 axs101_nand_read_word(struct mtd_info *mtd)
169+{
170+ u16 word;
171+
172+ axs101_nand_read_buf(mtd, (uchar *)&word, sizeof(word));
173+ return word;
174+}
175+
176+/**
177+ * axs101_nand_hwcontrol - NAND control functions wrapper.
178+ * @mtd: MTD device structure
179+ * @cmd: Command
180+ */
181+static void axs101_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd,
182+ unsigned int ctrl)
183+{
184+ if (cmd == NAND_CMD_NONE)
185+ return;
186+
187+ cmd = cmd & 0xff;
188+
189+ switch (ctrl & (NAND_ALE | NAND_CLE)) {
190+ /* Address */
191+ case NAND_ALE:
192+ cmd |= B_CT_ADDRESS;
193+ break;
194+
195+ /* Command */
196+ case NAND_CLE:
197+ cmd |= B_CT_COMMAND | B_WFR;
198+
199+ break;
200+
201+ default:
202+ debug("%s: unknown ctrl %#x\n", __func__, ctrl);
203+ }
204+
205+ NAND_REG_WRITE(AC_FIFO, cmd | B_LC);
206+ while (!nand_flag_is_set(NAND_ISR_CMDDONE))
207+ ;
208+}
209+
210+int board_nand_init(struct nand_chip *nand)
211+{
212+ bd = (struct nand_bd *)memalign(ARCH_DMA_MINALIGN,
213+ sizeof(struct nand_bd));
214+
215+ /* Set buffer descriptor address in IDMAC */
216+ NAND_REG_WRITE(IDMAC_BDADDR, bd);
217+
218+ nand->ecc.mode = NAND_ECC_SOFT;
219+ nand->cmd_ctrl = axs101_nand_hwcontrol;
220+ nand->read_byte = axs101_nand_read_byte;
221+ nand->read_word = axs101_nand_read_word;
222+ nand->write_buf = axs101_nand_write_buf;
223+ nand->read_buf = axs101_nand_read_buf;
224+
225+ return 0;
226+}
--- a/boards.cfg
+++ b/boards.cfg
@@ -1230,6 +1230,7 @@ Active sparc leon3 - gaisler -
12301230 Active sparc leon3 - gaisler - gr_xc3s_1500 - -
12311231 Active sparc leon3 - gaisler - grsim - -
12321232 Active x86 x86 coreboot chromebook-x86 coreboot coreboot-x86 coreboot:SYS_TEXT_BASE=0x01110000 -
1233+Active arc arc700 - synopsys - axs101 - Alexey Brodkin <abrodkin@synopsys.com>
12331234 Active arc arc700 - synopsys - arcangel4 - Alexey Brodkin <abrodkin@synopsys.com>
12341235 Active arc arc700 - synopsys arcangel4 arcangel4-be - Alexey Brodkin <abrodkin@synopsys.com>
12351236 Orphan arm arm1136 mx31 - imx31_phycore imx31_phycore_eet imx31_phycore:IMX31_PHYCORE_EET (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
--- /dev/null
+++ b/include/configs/axs101.h
@@ -0,0 +1,181 @@
1+/*
2+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
3+ *
4+ * SPDX-License-Identifier: GPL-2.0+
5+ */
6+
7+#ifndef _CONFIG_AXS101_H_
8+#define _CONFIG_AXS101_H_
9+
10+/*
11+ * CPU configuration
12+ */
13+#define CONFIG_ARC700
14+#define CONFIG_ARC_MMU_VER 3
15+#define CONFIG_SYS_CACHELINE_SIZE 32
16+#define CONFIG_SYS_CLK_FREQ 750000000
17+#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
18+
19+/* dwgmac doesn't work with D$ enabled now */
20+#define CONFIG_SYS_DCACHE_OFF
21+
22+/*
23+ * Board configuration
24+ */
25+#define CONFIG_SYS_GENERIC_BOARD
26+#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */
27+
28+#define CONFIG_ARCH_EARLY_INIT_R
29+
30+#define ARC_FPGA_PERIPHERAL_BASE 0xE0000000
31+#define ARC_APB_PERIPHERAL_BASE 0xF0000000
32+#define ARC_DWMMC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x15000)
33+#define ARC_DWGMAC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x18000)
34+
35+/*
36+ * Memory configuration
37+ */
38+#define CONFIG_SYS_TEXT_BASE 0x81000000
39+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
40+
41+#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
42+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
43+#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 Mb */
44+
45+#define CONFIG_SYS_INIT_SP_ADDR \
46+ (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
47+
48+#define CONFIG_SYS_MALLOC_LEN 0x200000 /* 2 MB */
49+#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */
50+#define CONFIG_SYS_LOAD_ADDR 0x82000000
51+
52+/*
53+ * NAND Flash configuration
54+ */
55+#define CONFIG_SYS_NO_FLASH
56+#define CONFIG_SYS_NAND_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x16000)
57+#define CONFIG_SYS_MAX_NAND_DEVICE 1
58+
59+/*
60+ * UART configuration
61+ *
62+ * CONFIG_CONS_INDEX = 1 - Debug UART
63+ * CONFIG_CONS_INDEX = 4 - FPGA UART connected to FTDI/USB
64+ */
65+#define CONFIG_CONS_INDEX 4
66+#define CONFIG_SYS_NS16550
67+#define CONFIG_SYS_NS16550_SERIAL
68+#define CONFIG_SYS_NS16550_REG_SIZE -4
69+#if (CONFIG_CONS_INDEX == 1)
70+ /* Debug UART */
71+# define CONFIG_SYS_NS16550_CLK 33333000
72+#else
73+ /* FPGA UARTs use different clock */
74+# define CONFIG_SYS_NS16550_CLK 33333333
75+#endif
76+#define CONFIG_SYS_NS16550_COM1 (ARC_APB_PERIPHERAL_BASE + 0x5000)
77+#define CONFIG_SYS_NS16550_COM2 (ARC_FPGA_PERIPHERAL_BASE + 0x20000)
78+#define CONFIG_SYS_NS16550_COM3 (ARC_FPGA_PERIPHERAL_BASE + 0x21000)
79+#define CONFIG_SYS_NS16550_COM4 (ARC_FPGA_PERIPHERAL_BASE + 0x22000)
80+#define CONFIG_SYS_NS16550_MEM32
81+
82+#define CONFIG_BAUDRATE 115200
83+/*
84+ * I2C configuration
85+ */
86+#define CONFIG_HARD_I2C
87+#define CONFIG_DW_I2C
88+#define CONFIG_I2C_MULTI_BUS
89+#define CONFIG_I2C_ENV_EEPROM_BUS 2
90+#define CONFIG_SYS_I2C_SPEED 100000
91+#define CONFIG_SYS_I2C_SLAVE 0
92+#define CONFIG_SYS_I2C_BASE 0xE001D000
93+#define CONFIG_SYS_I2C_BASE1 0xE001E000
94+#define CONFIG_SYS_I2C_BASE2 0xE001F000
95+#define CONFIG_SYS_I2C_BUS_MAX 3
96+#define IC_CLK 50
97+
98+/*
99+ * EEPROM configuration
100+ */
101+#define CONFIG_SYS_I2C_MULTI_EEPROMS
102+#define CONFIG_SYS_I2C_EEPROM_ADDR (0xA8 >> 1)
103+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
104+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1
105+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
106+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 32
107+
108+/*
109+ * SD/MMC configuration
110+ */
111+#define CONFIG_MMC
112+#define CONFIG_GENERIC_MMC
113+#define CONFIG_DWMMC
114+#define CONFIG_DOS_PARTITION
115+
116+/*
117+ * Ethernet PHY configuration
118+ */
119+#define CONFIG_PHYLIB
120+#define CONFIG_MII
121+#define CONFIG_PHY_GIGE
122+
123+/*
124+ * Ethernet configuration
125+ */
126+#define CONFIG_DESIGNWARE_ETH
127+#define CONFIG_DW_AUTONEG
128+#define CONFIG_DW_SEARCH_PHY
129+#define CONFIG_NET_MULTI
130+
131+/*
132+ * Command line configuration
133+ */
134+#include <config_cmd_default.h>
135+
136+#define CONFIG_CMD_DHCP
137+#define CONFIG_CMD_EEPROM
138+#define CONFIG_CMD_ELF
139+#define CONFIG_CMD_FAT
140+#define CONFIG_CMD_I2C
141+#define CONFIG_CMD_MMC
142+#define CONFIG_CMD_NAND
143+#define CONFIG_CMD_PING
144+#define CONFIG_CMD_RARP
145+
146+#define CONFIG_OF_LIBFDT
147+
148+#define CONFIG_AUTO_COMPLETE
149+#define CONFIG_SYS_MAXARGS 16
150+
151+/*
152+ * Environment settings
153+ */
154+#define CONFIG_ENV_IS_IN_EEPROM
155+#define CONFIG_ENV_SIZE 0x00200 /* 512 bytes */
156+#define CONFIG_ENV_OFFSET 0
157+
158+/*
159+ * Environment configuration
160+ */
161+#define CONFIG_BOOTDELAY 3
162+#define CONFIG_BOOTFILE "uImage"
163+#define CONFIG_BOOTARGS "console=ttyS3,115200n8"
164+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
165+
166+/*
167+ * Console configuration
168+ */
169+#define CONFIG_SYS_LONGHELP
170+#define CONFIG_SYS_PROMPT "axs# "
171+#define CONFIG_SYS_CBSIZE 256
172+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
173+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
174+ sizeof(CONFIG_SYS_PROMPT) + 16)
175+
176+/*
177+ * Misc utility configuration
178+ */
179+#define CONFIG_BOUNCE_BUFFER
180+
181+#endif /* _CONFIG_AXS101_H_ */