Commit: eafc727f106e09a9ded921f5dc23daa2015cad3c - uboot (git)

Commit MetaInfo

• Revision: eafc727f106e09a9ded921f5dc23daa2015cad3c (tree)
• Time: 2020-07-26 17:58:23
• Author: Yoshinori Sato <ysato@user...>
• Commiter: Yoshinori Sato

Log Message

Add RX62N CPG

Change Summary

• modified: drivers/clk/Kconfig
• modified: drivers/clk/Makefile
• add: drivers/clk/rx62n-cpg.c

Incremental Difference

--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -187,4 +187,10 @@ config SANDBOX_CLK_CCF
 	  Enable this option if you want to test the Linux kernel's Common
 	  Clock Framework [CCF] code in U-Boot's Sandbox clock driver.
 
+config CLK_RX62N
+        bool "Enable clock driver support for Renesas RX62N"
+	depends on CLK && RX
+	help
+	  Enable this to support the clocks on Renesas RX62N MCU.
+
 endmenu

--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -47,3 +47,4 @@ obj-$(CONFIG_STM32H7) += clk_stm32h7.o
 obj-$(CONFIG_CLK_TI_SCI) += clk-ti-sci.o
 obj-$(CONFIG_CLK_VERSAL) += clk_versal.o
 obj-$(CONFIG_CLK_CDCE9XX) += clk-cdce9xx.o
+obj-$(CONFIG_CLK_RX62N) += rx62n-cpg.o

--- /dev/null
+++ b/drivers/clk/rx62n-cpg.c
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2020 Yoshinori Sato <[e-mail]>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <div64.h>
+#include <dm.h>
+#include <linux/err.h>
+#include <asm/io.h>
+
+struct rx62n_cpg_priv {
+	struct clk parent;
+	void *base;
+	int out;
+};
+
+static ulong rx62n_cpg_get_rate(struct clk *clk)
+{
+	struct rx62n_cpg_priv *priv = dev_get_priv(clk->dev);
+	u64 rate;
+	int shift;
+	int divrate;
+
+	rate = clk_get_rate(&priv->parent);
+	if (IS_ERR_VALUE(rate))
+		return rate;
+	shift = 8 * (priv->out + 1);
+	divrate = readl(priv->base);
+	divrate = (divrate >> shift) & 0x0f;
+	divrate = 1 << divrate;
+
+	do_div(rate, divrate);
+	return rate;
+}
+
+static ulong rx62n_cpg_set_rate(struct clk *clk, ulong rate)
+{
+	struct rx62n_cpg_priv *priv = dev_get_priv(clk->dev);
+	u32 sckcr;
+	int shift;
+	u64 divrate;
+	int i;
+	
+	divrate = clk_get_rate(&priv->parent);
+	if (IS_ERR_VALUE(divrate))
+		return divrate;
+
+	shift = 8 * (priv->out + 1);
+        do_div(divrate, rate);
+	for (i = 0; i < 4; i++) {
+		if (divrate == 1) {
+			sckcr = readl(priv->base);
+			sckcr &= ~(0x0f << shift);
+			sckcr |= i << shift;
+			writel(sckcr, priv->base);
+			return 0;
+		}
+		divrate >>= 1;
+	}
+	return -EINVAL;
+}
+
+const struct clk_ops rx62n_cpg_ops = {
+	.get_rate = rx62n_cpg_get_rate,
+	.set_rate = rx62n_cpg_set_rate,
+};
+
+
+static int rx62n_cpg_probe(struct udevice *dev)
+{
+	struct rx62n_cpg_priv *priv = dev_get_priv(dev);
+	int err;
+	fdt_addr_t addr;
+	static char *names[] = {"pck", "bck", "ick"};
+	int id;
+
+	addr = dev_read_addr(dev);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+	priv->base = (void *)addr;
+        err = clk_get_by_index(dev, 0, &priv->parent);
+        if (err)
+                return err;
+	for (id = 0; id < 3; id++) {
+		if (strcmp(dev->name, names[id]) == 0) {
+			priv->out = id;
+			break;
+		}
+	}
+	return 0;
+}
+
+static const struct udevice_id rx62n_cpg_ids[] = {
+	{
+		.compatible = "renesas,rx62n-cpg",
+	},
+	{ }
+};
+
+U_BOOT_DRIVER(rx62n_cpg) = {
+	.name = "rx62n_cpg",
+	.id = UCLASS_CLK,
+	.of_match = rx62n_cpg_ids,
+	.ops = &rx62n_cpg_ops,
+	.probe = rx62n_cpg_probe,
+	.priv_auto_alloc_size = sizeof(struct rx62n_cpg_priv),
+};