Revision | fb2b88567d3b06095b089e70f75160a107710ea8 (tree) |
---|---|
Time | 2022-07-26 15:42:16 |
Author | Oleksandr Suvorov <oleksandr.suvorov@foun...> |
Commiter | Michal Simek |
fpga: add option for loading FPGA secure bitstreams
It allows using this feature without enabling the "fpga loads"
command.
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Co-developed-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com>
Signed-off-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com>
Tested-by: Ricardo Salveti <ricardo@foundries.io>
Tested-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com>
Link: https://lore.kernel.org/r/20220722141614.297383-2-oleksandr.suvorov@foundries.io
Signed-off-by: Michal Simek <michal.simek@amd.com>
@@ -1038,8 +1038,9 @@ config CMD_FPGA_LOADP | ||
1038 | 1038 | a partial bitstream. |
1039 | 1039 | |
1040 | 1040 | config CMD_FPGA_LOAD_SECURE |
1041 | - bool "fpga loads - loads secure bitstreams (Xilinx only)" | |
1041 | + bool "fpga loads - loads secure bitstreams" | |
1042 | 1042 | depends on CMD_FPGA |
1043 | + select FPGA_LOAD_SECURE | |
1043 | 1044 | help |
1044 | 1045 | Enables the fpga loads command which is used to load secure |
1045 | 1046 | (authenticated or encrypted or both) bitstreams on to FPGA. |
@@ -104,4 +104,18 @@ config SYS_FPGA_PROG_FEEDBACK | ||
104 | 104 | help |
105 | 105 | Enable printing of hash marks during FPGA configuration. |
106 | 106 | |
107 | +config FPGA_LOAD_SECURE | |
108 | + bool "Enable loading secure bitstreams" | |
109 | + depends on FPGA | |
110 | + help | |
111 | + Enables the fpga loads() functions that are used to load secure | |
112 | + (authenticated or encrypted or both) bitstreams on to FPGA. | |
113 | + | |
114 | +config SPL_FPGA_LOAD_SECURE | |
115 | + bool "Enable loading secure bitstreams for SPL" | |
116 | + depends on SPL_FPGA | |
117 | + help | |
118 | + Enables the fpga loads() functions that are used to load secure | |
119 | + (authenticated or encrypted or both) bitstreams on to FPGA. | |
120 | + | |
107 | 121 | endmenu |
@@ -220,7 +220,7 @@ int fpga_fsload(int devnum, const void *buf, size_t size, | ||
220 | 220 | } |
221 | 221 | #endif |
222 | 222 | |
223 | -#if defined(CONFIG_CMD_FPGA_LOAD_SECURE) | |
223 | +#if CONFIG_IS_ENABLED(FPGA_LOAD_SECURE) | |
224 | 224 | int fpga_loads(int devnum, const void *buf, size_t size, |
225 | 225 | struct fpga_secure_info *fpga_sec_info) |
226 | 226 | { |
@@ -172,7 +172,7 @@ int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize, | ||
172 | 172 | } |
173 | 173 | #endif |
174 | 174 | |
175 | -#if defined(CONFIG_CMD_FPGA_LOAD_SECURE) | |
175 | +#if CONFIG_IS_ENABLED(FPGA_LOAD_SECURE) | |
176 | 176 | int xilinx_loads(xilinx_desc *desc, const void *buf, size_t bsize, |
177 | 177 | struct fpga_secure_info *fpga_sec_info) |
178 | 178 | { |
@@ -245,7 +245,7 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize, | ||
245 | 245 | return ret; |
246 | 246 | } |
247 | 247 | |
248 | -#if defined(CONFIG_CMD_FPGA_LOAD_SECURE) && !defined(CONFIG_SPL_BUILD) | |
248 | +#if CONFIG_IS_ENABLED(FPGA_LOAD_SECURE) | |
249 | 249 | static int zynqmp_loads(xilinx_desc *desc, const void *buf, size_t bsize, |
250 | 250 | struct fpga_secure_info *fpga_sec_info) |
251 | 251 | { |
@@ -306,7 +306,7 @@ static int zynqmp_pcap_info(xilinx_desc *desc) | ||
306 | 306 | |
307 | 307 | struct xilinx_fpga_op zynqmp_op = { |
308 | 308 | .load = zynqmp_load, |
309 | -#if defined(CONFIG_CMD_FPGA_LOAD_SECURE) && !defined(CONFIG_SPL_BUILD) | |
309 | +#if CONFIG_IS_ENABLED(FPGA_LOAD_SECURE) | |
310 | 310 | .loads = zynqmp_loads, |
311 | 311 | #endif |
312 | 312 | .info = zynqmp_pcap_info, |